2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/component.h>
31 #include <linux/reset.h>
32 #include <linux/delay.h>
34 #include "rockchip_drm_drv.h"
35 #include "rockchip_drm_gem.h"
36 #include "rockchip_drm_fb.h"
37 #include "rockchip_drm_vop.h"
39 #define VOP_REG(off, _mask, s) \
44 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
45 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
46 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
47 vop_mask_write(x, off, (mask) << shift, (v) << shift)
49 #define REG_SET(x, base, reg, v, mode) \
50 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
51 #define REG_SET_MASK(x, base, reg, v, mode) \
52 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
54 #define VOP_WIN_SET(x, win, name, v) \
55 REG_SET(x, win->base, win->phy->name, v, RELAXED)
56 #define VOP_SCL_SET(x, win, name, v) \
57 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
58 #define VOP_CTRL_SET(x, name, v) \
59 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
61 #define VOP_INTR_GET(vop, name) \
62 vop_read_reg(vop, 0, &vop->data->ctrl->name)
64 #define VOP_INTR_SET(vop, name, v) \
65 REG_SET(vop, 0, vop->data->intr->name, v, NORMAL)
66 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
69 for (i = 0; i < vop->data->intr->nintrs; i++) { \
70 if (vop->data->intr->intrs[i] & type) \
73 VOP_INTR_SET(vop, name, reg); \
75 #define VOP_INTR_GET_TYPE(vop, name, type) \
76 vop_get_intr_type(vop, &vop->data->intr->name, type)
78 #define VOP_WIN_GET(x, win, name) \
79 vop_read_reg(x, win->base, &win->phy->name)
81 #define VOP_WIN_GET_YRGBADDR(vop, win) \
82 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
84 #define to_vop(x) container_of(x, struct vop, crtc)
85 #define to_vop_win(x) container_of(x, struct vop_win, base)
86 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
88 struct vop_plane_state {
89 struct drm_plane_state base;
98 struct drm_plane base;
99 const struct vop_win_data *data;
102 struct vop_plane_state state;
106 struct drm_crtc crtc;
108 struct drm_device *drm_dev;
111 /* mutex vsync_ work */
112 struct mutex vsync_mutex;
113 bool vsync_work_pending;
114 struct completion dsp_hold_completion;
115 struct completion wait_update_complete;
116 struct drm_pending_vblank_event *event;
118 const struct vop_data *data;
123 /* physical map length of vop register */
126 /* one time only one process allowed to config the register */
128 /* lock vop irq reg */
137 /* vop share memory frequency */
141 struct reset_control *dclk_rst;
143 struct vop_win win[];
146 enum vop_data_format {
147 VOP_FMT_ARGB8888 = 0,
150 VOP_FMT_YUV420SP = 4,
155 struct vop_reg_data {
167 struct vop_reg standby;
168 struct vop_reg data_blank;
169 struct vop_reg gate_en;
170 struct vop_reg mmu_en;
171 struct vop_reg rgb_en;
172 struct vop_reg edp_en;
173 struct vop_reg hdmi_en;
174 struct vop_reg mipi_en;
175 struct vop_reg out_mode;
176 struct vop_reg dither_down;
177 struct vop_reg dither_up;
178 struct vop_reg pin_pol;
180 struct vop_reg htotal_pw;
181 struct vop_reg hact_st_end;
182 struct vop_reg vtotal_pw;
183 struct vop_reg vact_st_end;
184 struct vop_reg hpost_st_end;
185 struct vop_reg vpost_st_end;
187 struct vop_reg cfg_done;
193 struct vop_reg enable;
194 struct vop_reg clear;
195 struct vop_reg status;
197 struct vop_scl_regs {
198 struct vop_reg cbcr_vsd_mode;
199 struct vop_reg cbcr_vsu_mode;
200 struct vop_reg cbcr_hsd_mode;
201 struct vop_reg cbcr_ver_scl_mode;
202 struct vop_reg cbcr_hor_scl_mode;
203 struct vop_reg yrgb_vsd_mode;
204 struct vop_reg yrgb_vsu_mode;
205 struct vop_reg yrgb_hsd_mode;
206 struct vop_reg yrgb_ver_scl_mode;
207 struct vop_reg yrgb_hor_scl_mode;
208 struct vop_reg line_load_mode;
209 struct vop_reg cbcr_axi_gather_num;
210 struct vop_reg yrgb_axi_gather_num;
211 struct vop_reg vsd_cbcr_gt2;
212 struct vop_reg vsd_cbcr_gt4;
213 struct vop_reg vsd_yrgb_gt2;
214 struct vop_reg vsd_yrgb_gt4;
215 struct vop_reg bic_coe_sel;
216 struct vop_reg cbcr_axi_gather_en;
217 struct vop_reg yrgb_axi_gather_en;
219 struct vop_reg lb_mode;
220 struct vop_reg scale_yrgb_x;
221 struct vop_reg scale_yrgb_y;
222 struct vop_reg scale_cbcr_x;
223 struct vop_reg scale_cbcr_y;
227 const struct vop_scl_regs *scl;
228 const uint32_t *data_formats;
231 struct vop_reg enable;
232 struct vop_reg format;
233 struct vop_reg rb_swap;
234 struct vop_reg act_info;
235 struct vop_reg dsp_info;
236 struct vop_reg dsp_st;
237 struct vop_reg yrgb_mst;
238 struct vop_reg uv_mst;
239 struct vop_reg yrgb_vir;
240 struct vop_reg uv_vir;
242 struct vop_reg dst_alpha_ctl;
243 struct vop_reg src_alpha_ctl;
246 struct vop_win_data {
248 const struct vop_win_phy *phy;
249 enum drm_plane_type type;
253 const struct vop_reg_data *init_table;
254 unsigned int table_size;
255 const struct vop_ctrl *ctrl;
256 const struct vop_intr *intr;
257 const struct vop_win_data *win;
258 unsigned int win_size;
261 static const uint32_t formats_01[] = {
275 static const uint32_t formats_234[] = {
286 static const struct vop_scl_regs win_full_scl = {
287 .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
288 .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
289 .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
290 .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
291 .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
292 .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
293 .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
294 .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
295 .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
296 .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
297 .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
298 .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
299 .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
300 .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
301 .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
302 .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
303 .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
304 .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
305 .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
306 .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
307 .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
308 .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
309 .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
310 .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
311 .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
314 static const struct vop_win_phy win01_data = {
315 .scl = &win_full_scl,
316 .data_formats = formats_01,
317 .nformats = ARRAY_SIZE(formats_01),
318 .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
319 .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
320 .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
321 .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
322 .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
323 .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
324 .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
325 .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
326 .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
327 .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
328 .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
329 .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
332 static const struct vop_win_phy win23_data = {
333 .data_formats = formats_234,
334 .nformats = ARRAY_SIZE(formats_234),
335 .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
336 .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
337 .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
338 .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
339 .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
340 .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
341 .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
342 .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
343 .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
346 static const struct vop_ctrl ctrl_data = {
347 .standby = VOP_REG(SYS_CTRL, 0x1, 22),
348 .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
349 .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
350 .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
351 .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
352 .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
353 .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
354 .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
355 .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
356 .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
357 .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
358 .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
359 .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
360 .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
361 .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
362 .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
363 .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
364 .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
365 .cfg_done = VOP_REG(REG_CFG_DONE, 0x1, 0),
368 static const struct vop_reg_data vop_init_reg_table[] = {
369 {SYS_CTRL, 0x00c00000},
370 {DSP_CTRL0, 0x00000000},
371 {WIN0_CTRL0, 0x00000080},
372 {WIN1_CTRL0, 0x00000080},
373 /* TODO: Win2/3 support multiple area function, but we haven't found
374 * a suitable way to use it yet, so let's just use them as other windows
375 * with only area 0 enabled.
377 {WIN2_CTRL0, 0x00000010},
378 {WIN3_CTRL0, 0x00000010},
382 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
383 * special support to get alpha blending working. For now, just use overlay
384 * window 3 for the drm cursor.
387 static const struct vop_win_data rk3288_vop_win_data[] = {
388 { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
389 { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
390 { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
391 { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
394 static const int rk3288_vop_intrs[] = {
401 static const struct vop_intr rk3288_vop_intr = {
402 .intrs = rk3288_vop_intrs,
403 .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
404 .status = VOP_REG(INTR_CTRL0, 0xf, 0),
405 .enable = VOP_REG(INTR_CTRL0, 0xf, 4),
406 .clear = VOP_REG(INTR_CTRL0, 0xf, 8),
409 static const struct vop_data rk3288_vop = {
410 .init_table = vop_init_reg_table,
411 .intr = &rk3288_vop_intr,
412 .table_size = ARRAY_SIZE(vop_init_reg_table),
414 .win = rk3288_vop_win_data,
415 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
418 static const struct of_device_id vop_driver_dt_match[] = {
419 { .compatible = "rockchip,rk3288-vop",
420 .data = &rk3288_vop },
423 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
425 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
427 writel(v, vop->regs + offset);
428 vop->regsbak[offset >> 2] = v;
431 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
433 return readl(vop->regs + offset);
436 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
437 const struct vop_reg *reg)
439 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
442 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
443 uint32_t mask, uint32_t v)
446 uint32_t cached_val = vop->regsbak[offset >> 2];
448 cached_val = (cached_val & ~mask) | v;
449 writel(cached_val, vop->regs + offset);
450 vop->regsbak[offset >> 2] = cached_val;
454 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
455 uint32_t mask, uint32_t v)
458 uint32_t cached_val = vop->regsbak[offset >> 2];
460 cached_val = (cached_val & ~mask) | v;
461 writel_relaxed(cached_val, vop->regs + offset);
462 vop->regsbak[offset >> 2] = cached_val;
466 static inline uint32_t vop_get_intr_type(struct vop *vop,
467 const struct vop_reg *reg, int type)
470 uint32_t regs = vop_read_reg(vop, 0, reg);
472 for (i = 0; i < vop->data->intr->nintrs; i++) {
473 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
474 ret |= vop->data->intr->intrs[i];
480 static inline void vop_cfg_done(struct vop *vop)
482 VOP_CTRL_SET(vop, cfg_done, 1);
485 static bool has_rb_swapped(uint32_t format)
488 case DRM_FORMAT_XBGR8888:
489 case DRM_FORMAT_ABGR8888:
490 case DRM_FORMAT_BGR888:
491 case DRM_FORMAT_BGR565:
498 static enum vop_data_format vop_convert_format(uint32_t format)
501 case DRM_FORMAT_XRGB8888:
502 case DRM_FORMAT_ARGB8888:
503 case DRM_FORMAT_XBGR8888:
504 case DRM_FORMAT_ABGR8888:
505 return VOP_FMT_ARGB8888;
506 case DRM_FORMAT_RGB888:
507 case DRM_FORMAT_BGR888:
508 return VOP_FMT_RGB888;
509 case DRM_FORMAT_RGB565:
510 case DRM_FORMAT_BGR565:
511 return VOP_FMT_RGB565;
512 case DRM_FORMAT_NV12:
513 return VOP_FMT_YUV420SP;
514 case DRM_FORMAT_NV16:
515 return VOP_FMT_YUV422SP;
516 case DRM_FORMAT_NV24:
517 return VOP_FMT_YUV444SP;
519 DRM_ERROR("unsupport format[%08x]\n", format);
524 static bool is_yuv_support(uint32_t format)
527 case DRM_FORMAT_NV12:
528 case DRM_FORMAT_NV16:
529 case DRM_FORMAT_NV24:
536 static bool is_alpha_support(uint32_t format)
539 case DRM_FORMAT_ARGB8888:
540 case DRM_FORMAT_ABGR8888:
547 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
548 uint32_t dst, bool is_horizontal,
549 int vsu_mode, int *vskiplines)
551 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
554 if (mode == SCALE_UP)
555 val = GET_SCL_FT_BIC(src, dst);
556 else if (mode == SCALE_DOWN)
557 val = GET_SCL_FT_BILI_DN(src, dst);
559 if (mode == SCALE_UP) {
560 if (vsu_mode == SCALE_UP_BIL)
561 val = GET_SCL_FT_BILI_UP(src, dst);
563 val = GET_SCL_FT_BIC(src, dst);
564 } else if (mode == SCALE_DOWN) {
566 *vskiplines = scl_get_vskiplines(src, dst);
567 val = scl_get_bili_dn_vskip(src, dst,
570 val = GET_SCL_FT_BILI_DN(src, dst);
578 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
579 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
580 uint32_t dst_h, uint32_t pixel_format)
582 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
583 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
584 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
585 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
586 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
587 bool is_yuv = is_yuv_support(pixel_format);
588 uint16_t cbcr_src_w = src_w / hsub;
589 uint16_t cbcr_src_h = src_h / vsub;
596 DRM_ERROR("Maximum destination width (3840) exceeded\n");
600 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
601 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
604 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
605 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
606 if (cbcr_hor_scl_mode == SCALE_DOWN)
607 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
609 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
611 if (yrgb_hor_scl_mode == SCALE_DOWN)
612 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
614 lb_mode = scl_vop_cal_lb_mode(src_w, false);
617 VOP_SCL_SET(vop, win, lb_mode, lb_mode);
618 if (lb_mode == LB_RGB_3840X2) {
619 if (yrgb_ver_scl_mode != SCALE_NONE) {
620 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
623 if (cbcr_ver_scl_mode != SCALE_NONE) {
624 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
627 vsu_mode = SCALE_UP_BIL;
628 } else if (lb_mode == LB_RGB_2560X4) {
629 vsu_mode = SCALE_UP_BIL;
631 vsu_mode = SCALE_UP_BIC;
634 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
636 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
637 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
638 false, vsu_mode, &vskiplines);
639 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
641 VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4);
642 VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2);
644 VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
645 VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
646 VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
647 VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
648 VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode);
650 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
651 dst_w, true, 0, NULL);
652 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
653 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
654 dst_h, false, vsu_mode, &vskiplines);
655 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
657 VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4);
658 VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2);
659 VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
660 VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
661 VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
662 VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
663 VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode);
667 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
671 if (WARN_ON(!vop->is_enabled))
674 spin_lock_irqsave(&vop->irq_lock, flags);
676 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
678 spin_unlock_irqrestore(&vop->irq_lock, flags);
681 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
685 if (WARN_ON(!vop->is_enabled))
688 spin_lock_irqsave(&vop->irq_lock, flags);
690 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
692 spin_unlock_irqrestore(&vop->irq_lock, flags);
695 static void vop_enable(struct drm_crtc *crtc)
697 struct vop *vop = to_vop(crtc);
703 ret = pm_runtime_get_sync(vop->dev);
705 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
709 ret = clk_enable(vop->hclk);
711 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
715 ret = clk_enable(vop->dclk);
717 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
718 goto err_disable_hclk;
721 ret = clk_enable(vop->aclk);
723 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
724 goto err_disable_dclk;
728 * Slave iommu shares power, irq and clock with vop. It was associated
729 * automatically with this master device via common driver code.
730 * Now that we have enabled the clock we attach it to the shared drm
733 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
735 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
736 goto err_disable_aclk;
739 memcpy(vop->regs, vop->regsbak, vop->len);
741 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
743 vop->is_enabled = true;
745 spin_lock(&vop->reg_lock);
747 VOP_CTRL_SET(vop, standby, 0);
749 spin_unlock(&vop->reg_lock);
751 enable_irq(vop->irq);
753 drm_crtc_vblank_on(crtc);
758 clk_disable(vop->aclk);
760 clk_disable(vop->dclk);
762 clk_disable(vop->hclk);
765 static void vop_crtc_disable(struct drm_crtc *crtc)
767 struct vop *vop = to_vop(crtc);
769 if (!vop->is_enabled)
772 drm_crtc_vblank_off(crtc);
775 * Vop standby will take effect at end of current frame,
776 * if dsp hold valid irq happen, it means standby complete.
778 * we must wait standby complete when we want to disable aclk,
779 * if not, memory bus maybe dead.
781 reinit_completion(&vop->dsp_hold_completion);
782 vop_dsp_hold_valid_irq_enable(vop);
784 spin_lock(&vop->reg_lock);
786 VOP_CTRL_SET(vop, standby, 1);
788 spin_unlock(&vop->reg_lock);
790 wait_for_completion(&vop->dsp_hold_completion);
792 vop_dsp_hold_valid_irq_disable(vop);
794 disable_irq(vop->irq);
796 vop->is_enabled = false;
799 * vop standby complete, so iommu detach is safe.
801 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
803 clk_disable(vop->dclk);
804 clk_disable(vop->aclk);
805 clk_disable(vop->hclk);
806 pm_runtime_put(vop->dev);
809 static void vop_plane_destroy(struct drm_plane *plane)
811 drm_plane_cleanup(plane);
814 static int vop_plane_atomic_check(struct drm_plane *plane,
815 struct drm_plane_state *state)
817 struct drm_crtc *crtc = state->crtc;
818 struct drm_framebuffer *fb = state->fb;
819 struct vop_win *vop_win = to_vop_win(plane);
820 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
821 const struct vop_win_data *win = vop_win->data;
824 struct drm_rect *dest = &vop_plane_state->dest;
825 struct drm_rect *src = &vop_plane_state->src;
826 struct drm_rect clip;
827 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
828 DRM_PLANE_HELPER_NO_SCALING;
829 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
830 DRM_PLANE_HELPER_NO_SCALING;
832 crtc = crtc ? crtc : plane->state->crtc;
834 * Both crtc or plane->state->crtc can be null.
838 src->x1 = state->src_x;
839 src->y1 = state->src_y;
840 src->x2 = state->src_x + state->src_w;
841 src->y2 = state->src_y + state->src_h;
842 dest->x1 = state->crtc_x;
843 dest->y1 = state->crtc_y;
844 dest->x2 = state->crtc_x + state->crtc_w;
845 dest->y2 = state->crtc_y + state->crtc_h;
849 clip.x2 = crtc->mode.hdisplay;
850 clip.y2 = crtc->mode.vdisplay;
852 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
856 true, true, &visible);
863 vop_plane_state->format = vop_convert_format(fb->pixel_format);
864 if (vop_plane_state->format < 0)
865 return vop_plane_state->format;
868 * Src.x1 can be odd when do clip, but yuv plane start point
869 * need align with 2 pixel.
871 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
874 vop_plane_state->enable = true;
879 vop_plane_state->enable = false;
883 static void vop_plane_atomic_disable(struct drm_plane *plane,
884 struct drm_plane_state *old_state)
886 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
887 struct vop_win *vop_win = to_vop_win(plane);
888 const struct vop_win_data *win = vop_win->data;
889 struct vop *vop = to_vop(old_state->crtc);
891 if (!old_state->crtc)
894 spin_lock(&vop->reg_lock);
896 VOP_WIN_SET(vop, win, enable, 0);
898 spin_unlock(&vop->reg_lock);
900 vop_plane_state->enable = false;
903 static void vop_plane_atomic_update(struct drm_plane *plane,
904 struct drm_plane_state *old_state)
906 struct drm_plane_state *state = plane->state;
907 struct drm_crtc *crtc = state->crtc;
908 struct vop_win *vop_win = to_vop_win(plane);
909 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
910 const struct vop_win_data *win = vop_win->data;
911 struct vop *vop = to_vop(state->crtc);
912 struct drm_framebuffer *fb = state->fb;
913 unsigned int actual_w, actual_h;
914 unsigned int dsp_stx, dsp_sty;
915 uint32_t act_info, dsp_info, dsp_st;
916 struct drm_rect *src = &vop_plane_state->src;
917 struct drm_rect *dest = &vop_plane_state->dest;
918 struct drm_gem_object *obj, *uv_obj;
919 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
920 unsigned long offset;
926 * can't update plane when vop is disabled.
931 if (WARN_ON(!vop->is_enabled))
934 if (!vop_plane_state->enable) {
935 vop_plane_atomic_disable(plane, old_state);
939 obj = rockchip_fb_get_gem_obj(fb, 0);
940 rk_obj = to_rockchip_obj(obj);
942 actual_w = drm_rect_width(src) >> 16;
943 actual_h = drm_rect_height(src) >> 16;
944 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
946 dsp_info = (drm_rect_height(dest) - 1) << 16;
947 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
949 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
950 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
951 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
953 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
954 offset += (src->y1 >> 16) * fb->pitches[0];
955 vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
957 spin_lock(&vop->reg_lock);
959 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
960 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
961 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
962 if (is_yuv_support(fb->pixel_format)) {
963 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
964 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
965 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
967 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
968 rk_uv_obj = to_rockchip_obj(uv_obj);
970 offset = (src->x1 >> 16) * bpp / hsub;
971 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
973 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
974 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
975 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
979 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
980 drm_rect_width(dest), drm_rect_height(dest),
983 VOP_WIN_SET(vop, win, act_info, act_info);
984 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
985 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
987 rb_swap = has_rb_swapped(fb->pixel_format);
988 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
990 if (is_alpha_support(fb->pixel_format)) {
991 VOP_WIN_SET(vop, win, dst_alpha_ctl,
992 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
993 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
994 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
995 SRC_BLEND_M0(ALPHA_PER_PIX) |
996 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
997 SRC_FACTOR_M0(ALPHA_ONE);
998 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1000 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1003 VOP_WIN_SET(vop, win, enable, 1);
1004 spin_unlock(&vop->reg_lock);
1007 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1008 .atomic_check = vop_plane_atomic_check,
1009 .atomic_update = vop_plane_atomic_update,
1010 .atomic_disable = vop_plane_atomic_disable,
1013 void vop_atomic_plane_reset(struct drm_plane *plane)
1015 struct vop_plane_state *vop_plane_state =
1016 to_vop_plane_state(plane->state);
1018 if (plane->state && plane->state->fb)
1019 drm_framebuffer_unreference(plane->state->fb);
1021 kfree(vop_plane_state);
1022 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1023 if (!vop_plane_state)
1026 plane->state = &vop_plane_state->base;
1027 plane->state->plane = plane;
1030 struct drm_plane_state *
1031 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1033 struct vop_plane_state *old_vop_plane_state;
1034 struct vop_plane_state *vop_plane_state;
1036 if (WARN_ON(!plane->state))
1039 old_vop_plane_state = to_vop_plane_state(plane->state);
1040 vop_plane_state = kmemdup(old_vop_plane_state,
1041 sizeof(*vop_plane_state), GFP_KERNEL);
1042 if (!vop_plane_state)
1045 __drm_atomic_helper_plane_duplicate_state(plane,
1046 &vop_plane_state->base);
1048 return &vop_plane_state->base;
1051 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1052 struct drm_plane_state *state)
1054 struct vop_plane_state *vop_state = to_vop_plane_state(state);
1056 __drm_atomic_helper_plane_destroy_state(plane, state);
1061 static const struct drm_plane_funcs vop_plane_funcs = {
1062 .update_plane = drm_atomic_helper_update_plane,
1063 .disable_plane = drm_atomic_helper_disable_plane,
1064 .destroy = vop_plane_destroy,
1065 .reset = vop_atomic_plane_reset,
1066 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1067 .atomic_destroy_state = vop_atomic_plane_destroy_state,
1070 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
1074 struct vop *vop = to_vop(crtc);
1076 if (WARN_ON(!vop->is_enabled))
1079 switch (connector_type) {
1080 case DRM_MODE_CONNECTOR_LVDS:
1081 VOP_CTRL_SET(vop, rgb_en, 1);
1083 case DRM_MODE_CONNECTOR_eDP:
1084 VOP_CTRL_SET(vop, edp_en, 1);
1086 case DRM_MODE_CONNECTOR_HDMIA:
1087 VOP_CTRL_SET(vop, hdmi_en, 1);
1090 DRM_ERROR("unsupport connector_type[%d]\n", connector_type);
1093 VOP_CTRL_SET(vop, out_mode, out_mode);
1097 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
1099 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1101 struct vop *vop = to_vop(crtc);
1102 unsigned long flags;
1104 if (WARN_ON(!vop->is_enabled))
1107 spin_lock_irqsave(&vop->irq_lock, flags);
1109 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1111 spin_unlock_irqrestore(&vop->irq_lock, flags);
1116 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1118 struct vop *vop = to_vop(crtc);
1119 unsigned long flags;
1121 if (WARN_ON(!vop->is_enabled))
1124 spin_lock_irqsave(&vop->irq_lock, flags);
1126 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1128 spin_unlock_irqrestore(&vop->irq_lock, flags);
1131 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1133 struct vop *vop = to_vop(crtc);
1135 reinit_completion(&vop->wait_update_complete);
1136 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1139 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1140 .enable_vblank = vop_crtc_enable_vblank,
1141 .disable_vblank = vop_crtc_disable_vblank,
1142 .wait_for_update = vop_crtc_wait_for_update,
1145 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1146 const struct drm_display_mode *mode,
1147 struct drm_display_mode *adjusted_mode)
1149 if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
1155 static void vop_crtc_enable(struct drm_crtc *crtc)
1157 struct vop *vop = to_vop(crtc);
1158 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1159 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1160 u16 hdisplay = adjusted_mode->hdisplay;
1161 u16 htotal = adjusted_mode->htotal;
1162 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1163 u16 hact_end = hact_st + hdisplay;
1164 u16 vdisplay = adjusted_mode->vdisplay;
1165 u16 vtotal = adjusted_mode->vtotal;
1166 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1167 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1168 u16 vact_end = vact_st + vdisplay;
1173 * If dclk rate is zero, mean that scanout is stop,
1174 * we don't need wait any more.
1176 if (clk_get_rate(vop->dclk)) {
1178 * Rk3288 vop timing register is immediately, when configure
1179 * display timing on display time, may cause tearing.
1181 * Vop standby will take effect at end of current frame,
1182 * if dsp hold valid irq happen, it means standby complete.
1185 * standby and wait complete --> |----
1188 * |---> dsp hold irq
1189 * configure display timing --> |
1191 * | new frame start.
1194 reinit_completion(&vop->dsp_hold_completion);
1195 vop_dsp_hold_valid_irq_enable(vop);
1197 spin_lock(&vop->reg_lock);
1199 VOP_CTRL_SET(vop, standby, 1);
1201 spin_unlock(&vop->reg_lock);
1203 wait_for_completion(&vop->dsp_hold_completion);
1205 vop_dsp_hold_valid_irq_disable(vop);
1209 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1210 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1211 VOP_CTRL_SET(vop, pin_pol, val);
1213 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1214 val = hact_st << 16;
1216 VOP_CTRL_SET(vop, hact_st_end, val);
1217 VOP_CTRL_SET(vop, hpost_st_end, val);
1219 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1220 val = vact_st << 16;
1222 VOP_CTRL_SET(vop, vact_st_end, val);
1223 VOP_CTRL_SET(vop, vpost_st_end, val);
1225 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1227 VOP_CTRL_SET(vop, standby, 0);
1230 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1231 struct drm_crtc_state *old_crtc_state)
1233 struct vop *vop = to_vop(crtc);
1235 if (WARN_ON(!vop->is_enabled))
1238 spin_lock(&vop->reg_lock);
1242 spin_unlock(&vop->reg_lock);
1245 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1246 struct drm_crtc_state *old_crtc_state)
1248 struct vop *vop = to_vop(crtc);
1250 if (crtc->state->event) {
1251 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1253 vop->event = crtc->state->event;
1254 crtc->state->event = NULL;
1258 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1259 .enable = vop_crtc_enable,
1260 .disable = vop_crtc_disable,
1261 .mode_fixup = vop_crtc_mode_fixup,
1262 .atomic_flush = vop_crtc_atomic_flush,
1263 .atomic_begin = vop_crtc_atomic_begin,
1266 static void vop_crtc_destroy(struct drm_crtc *crtc)
1268 drm_crtc_cleanup(crtc);
1271 static const struct drm_crtc_funcs vop_crtc_funcs = {
1272 .set_config = drm_atomic_helper_set_config,
1273 .page_flip = drm_atomic_helper_page_flip,
1274 .destroy = vop_crtc_destroy,
1275 .reset = drm_atomic_helper_crtc_reset,
1276 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1277 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1280 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1282 struct drm_plane *plane = &vop_win->base;
1283 struct vop_plane_state *state = to_vop_plane_state(plane->state);
1284 dma_addr_t yrgb_mst;
1287 return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0;
1289 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1291 return yrgb_mst == state->yrgb_mst;
1294 static void vop_handle_vblank(struct vop *vop)
1296 struct drm_device *drm = vop->drm_dev;
1297 struct drm_crtc *crtc = &vop->crtc;
1298 unsigned long flags;
1301 for (i = 0; i < vop->data->win_size; i++) {
1302 if (!vop_win_pending_is_complete(&vop->win[i]))
1307 spin_lock_irqsave(&drm->event_lock, flags);
1309 drm_crtc_send_vblank_event(crtc, vop->event);
1310 drm_crtc_vblank_put(crtc);
1313 spin_unlock_irqrestore(&drm->event_lock, flags);
1315 if (!completion_done(&vop->wait_update_complete))
1316 complete(&vop->wait_update_complete);
1319 static irqreturn_t vop_isr(int irq, void *data)
1321 struct vop *vop = data;
1322 struct drm_crtc *crtc = &vop->crtc;
1323 uint32_t active_irqs;
1324 unsigned long flags;
1328 * interrupt register has interrupt status, enable and clear bits, we
1329 * must hold irq_lock to avoid a race with enable/disable_vblank().
1331 spin_lock_irqsave(&vop->irq_lock, flags);
1333 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1334 /* Clear all active interrupt sources */
1336 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1338 spin_unlock_irqrestore(&vop->irq_lock, flags);
1340 /* This is expected for vop iommu irqs, since the irq is shared */
1344 if (active_irqs & DSP_HOLD_VALID_INTR) {
1345 complete(&vop->dsp_hold_completion);
1346 active_irqs &= ~DSP_HOLD_VALID_INTR;
1350 if (active_irqs & FS_INTR) {
1351 drm_crtc_handle_vblank(crtc);
1352 vop_handle_vblank(vop);
1353 active_irqs &= ~FS_INTR;
1357 /* Unhandled irqs are spurious. */
1359 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1364 static int vop_create_crtc(struct vop *vop)
1366 const struct vop_data *vop_data = vop->data;
1367 struct device *dev = vop->dev;
1368 struct drm_device *drm_dev = vop->drm_dev;
1369 struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1370 struct drm_crtc *crtc = &vop->crtc;
1371 struct device_node *port;
1376 * Create drm_plane for primary and cursor planes first, since we need
1377 * to pass them to drm_crtc_init_with_planes, which sets the
1378 * "possible_crtcs" to the newly initialized crtc.
1380 for (i = 0; i < vop_data->win_size; i++) {
1381 struct vop_win *vop_win = &vop->win[i];
1382 const struct vop_win_data *win_data = vop_win->data;
1384 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1385 win_data->type != DRM_PLANE_TYPE_CURSOR)
1388 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1389 0, &vop_plane_funcs,
1390 win_data->phy->data_formats,
1391 win_data->phy->nformats,
1392 win_data->type, NULL);
1394 DRM_ERROR("failed to initialize plane\n");
1395 goto err_cleanup_planes;
1398 plane = &vop_win->base;
1399 drm_plane_helper_add(plane, &plane_helper_funcs);
1400 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1402 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1406 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1407 &vop_crtc_funcs, NULL);
1411 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1414 * Create drm_planes for overlay windows with possible_crtcs restricted
1415 * to the newly created crtc.
1417 for (i = 0; i < vop_data->win_size; i++) {
1418 struct vop_win *vop_win = &vop->win[i];
1419 const struct vop_win_data *win_data = vop_win->data;
1420 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1422 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1425 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1428 win_data->phy->data_formats,
1429 win_data->phy->nformats,
1430 win_data->type, NULL);
1432 DRM_ERROR("failed to initialize overlay plane\n");
1433 goto err_cleanup_crtc;
1435 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1438 port = of_get_child_by_name(dev->of_node, "port");
1440 DRM_ERROR("no port node found in %s\n",
1441 dev->of_node->full_name);
1442 goto err_cleanup_crtc;
1445 init_completion(&vop->dsp_hold_completion);
1446 init_completion(&vop->wait_update_complete);
1448 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1453 drm_crtc_cleanup(crtc);
1455 list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1456 drm_plane_cleanup(plane);
1460 static void vop_destroy_crtc(struct vop *vop)
1462 struct drm_crtc *crtc = &vop->crtc;
1464 rockchip_unregister_crtc_funcs(crtc);
1465 of_node_put(crtc->port);
1466 drm_crtc_cleanup(crtc);
1469 static int vop_initial(struct vop *vop)
1471 const struct vop_data *vop_data = vop->data;
1472 const struct vop_reg_data *init_table = vop_data->init_table;
1473 struct reset_control *ahb_rst;
1476 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1477 if (IS_ERR(vop->hclk)) {
1478 dev_err(vop->dev, "failed to get hclk source\n");
1479 return PTR_ERR(vop->hclk);
1481 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1482 if (IS_ERR(vop->aclk)) {
1483 dev_err(vop->dev, "failed to get aclk source\n");
1484 return PTR_ERR(vop->aclk);
1486 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1487 if (IS_ERR(vop->dclk)) {
1488 dev_err(vop->dev, "failed to get dclk source\n");
1489 return PTR_ERR(vop->dclk);
1492 ret = clk_prepare(vop->dclk);
1494 dev_err(vop->dev, "failed to prepare dclk\n");
1498 /* Enable both the hclk and aclk to setup the vop */
1499 ret = clk_prepare_enable(vop->hclk);
1501 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1502 goto err_unprepare_dclk;
1505 ret = clk_prepare_enable(vop->aclk);
1507 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1508 goto err_disable_hclk;
1512 * do hclk_reset, reset all vop registers.
1514 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1515 if (IS_ERR(ahb_rst)) {
1516 dev_err(vop->dev, "failed to get ahb reset\n");
1517 ret = PTR_ERR(ahb_rst);
1518 goto err_disable_aclk;
1520 reset_control_assert(ahb_rst);
1521 usleep_range(10, 20);
1522 reset_control_deassert(ahb_rst);
1524 memcpy(vop->regsbak, vop->regs, vop->len);
1526 for (i = 0; i < vop_data->table_size; i++)
1527 vop_writel(vop, init_table[i].offset, init_table[i].value);
1529 for (i = 0; i < vop_data->win_size; i++) {
1530 const struct vop_win_data *win = &vop_data->win[i];
1532 VOP_WIN_SET(vop, win, enable, 0);
1538 * do dclk_reset, let all config take affect.
1540 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1541 if (IS_ERR(vop->dclk_rst)) {
1542 dev_err(vop->dev, "failed to get dclk reset\n");
1543 ret = PTR_ERR(vop->dclk_rst);
1544 goto err_disable_aclk;
1546 reset_control_assert(vop->dclk_rst);
1547 usleep_range(10, 20);
1548 reset_control_deassert(vop->dclk_rst);
1550 clk_disable(vop->hclk);
1551 clk_disable(vop->aclk);
1553 vop->is_enabled = false;
1558 clk_disable_unprepare(vop->aclk);
1560 clk_disable_unprepare(vop->hclk);
1562 clk_unprepare(vop->dclk);
1567 * Initialize the vop->win array elements.
1569 static void vop_win_init(struct vop *vop)
1571 const struct vop_data *vop_data = vop->data;
1574 for (i = 0; i < vop_data->win_size; i++) {
1575 struct vop_win *vop_win = &vop->win[i];
1576 const struct vop_win_data *win_data = &vop_data->win[i];
1578 vop_win->data = win_data;
1583 static int vop_bind(struct device *dev, struct device *master, void *data)
1585 struct platform_device *pdev = to_platform_device(dev);
1586 const struct of_device_id *of_id;
1587 const struct vop_data *vop_data;
1588 struct drm_device *drm_dev = data;
1590 struct resource *res;
1594 of_id = of_match_device(vop_driver_dt_match, dev);
1595 vop_data = of_id->data;
1599 /* Allocate vop struct and its vop_win array */
1600 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1601 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1606 vop->data = vop_data;
1607 vop->drm_dev = drm_dev;
1608 dev_set_drvdata(dev, vop);
1612 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1613 vop->len = resource_size(res);
1614 vop->regs = devm_ioremap_resource(dev, res);
1615 if (IS_ERR(vop->regs))
1616 return PTR_ERR(vop->regs);
1618 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1622 ret = vop_initial(vop);
1624 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1628 irq = platform_get_irq(pdev, 0);
1630 dev_err(dev, "cannot find irq for vop\n");
1633 vop->irq = (unsigned int)irq;
1635 spin_lock_init(&vop->reg_lock);
1636 spin_lock_init(&vop->irq_lock);
1638 mutex_init(&vop->vsync_mutex);
1640 ret = devm_request_irq(dev, vop->irq, vop_isr,
1641 IRQF_SHARED, dev_name(dev), vop);
1645 /* IRQ is initially disabled; it gets enabled in power_on */
1646 disable_irq(vop->irq);
1648 ret = vop_create_crtc(vop);
1652 pm_runtime_enable(&pdev->dev);
1656 static void vop_unbind(struct device *dev, struct device *master, void *data)
1658 struct vop *vop = dev_get_drvdata(dev);
1660 pm_runtime_disable(dev);
1661 vop_destroy_crtc(vop);
1664 static const struct component_ops vop_component_ops = {
1666 .unbind = vop_unbind,
1669 static int vop_probe(struct platform_device *pdev)
1671 struct device *dev = &pdev->dev;
1673 if (!dev->of_node) {
1674 dev_err(dev, "can't find vop devices\n");
1678 return component_add(dev, &vop_component_ops);
1681 static int vop_remove(struct platform_device *pdev)
1683 component_del(&pdev->dev, &vop_component_ops);
1688 struct platform_driver vop_platform_driver = {
1690 .remove = vop_remove,
1692 .name = "rockchip-vop",
1693 .owner = THIS_MODULE,
1694 .of_match_table = of_match_ptr(vop_driver_dt_match),
1698 module_platform_driver(vop_platform_driver);
1700 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1701 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1702 MODULE_LICENSE("GPL v2");