2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/component.h>
31 #include <linux/reset.h>
32 #include <linux/delay.h>
34 #include "rockchip_drm_drv.h"
35 #include "rockchip_drm_gem.h"
36 #include "rockchip_drm_fb.h"
37 #include "rockchip_drm_vop.h"
39 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
40 vop_mask_write(x, off, mask, shift, v, write_mask, true)
42 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
43 vop_mask_write(x, off, mask, shift, v, write_mask, false)
45 #define REG_SET(x, base, reg, v, mode) \
46 __REG_SET_##mode(x, base + reg.offset, \
47 reg.mask, reg.shift, v, reg.write_mask)
48 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
49 __REG_SET_##mode(x, base + reg.offset, \
50 mask, reg.shift, v, reg.write_mask)
52 #define VOP_WIN_SET(x, win, name, v) \
53 REG_SET(x, win->base, win->phy->name, v, RELAXED)
54 #define VOP_SCL_SET(x, win, name, v) \
55 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
56 #define VOP_SCL_SET_EXT(x, win, name, v) \
57 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
58 #define VOP_CTRL_SET(x, name, v) \
59 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
61 #define VOP_INTR_GET(vop, name) \
62 vop_read_reg(vop, 0, &vop->data->ctrl->name)
64 #define VOP_INTR_SET(vop, name, mask, v) \
65 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
66 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
68 int i, reg = 0, mask = 0; \
69 for (i = 0; i < vop->data->intr->nintrs; i++) { \
70 if (vop->data->intr->intrs[i] & type) { \
75 VOP_INTR_SET(vop, name, mask, reg); \
77 #define VOP_INTR_GET_TYPE(vop, name, type) \
78 vop_get_intr_type(vop, &vop->data->intr->name, type)
80 #define VOP_WIN_GET(x, win, name) \
81 vop_read_reg(x, win->base, &win->phy->name)
83 #define VOP_WIN_GET_YRGBADDR(vop, win) \
84 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
86 #define to_vop(x) container_of(x, struct vop, crtc)
87 #define to_vop_win(x) container_of(x, struct vop_win, base)
88 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
90 struct vop_plane_state {
91 struct drm_plane_state base;
100 struct drm_plane base;
101 const struct vop_win_data *data;
104 struct vop_plane_state state;
108 struct drm_crtc crtc;
110 struct drm_device *drm_dev;
113 /* mutex vsync_ work */
114 struct mutex vsync_mutex;
115 bool vsync_work_pending;
116 struct completion dsp_hold_completion;
117 struct completion wait_update_complete;
118 struct drm_pending_vblank_event *event;
120 const struct vop_data *data;
125 /* physical map length of vop register */
128 /* one time only one process allowed to config the register */
130 /* lock vop irq reg */
139 /* vop share memory frequency */
143 struct reset_control *dclk_rst;
145 struct vop_win win[];
148 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
150 writel(v, vop->regs + offset);
151 vop->regsbak[offset >> 2] = v;
154 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
156 return readl(vop->regs + offset);
159 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
160 const struct vop_reg *reg)
162 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
165 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
166 uint32_t mask, uint32_t shift, uint32_t v,
167 bool write_mask, bool relaxed)
173 v = (v << shift) | (mask << (shift + 16));
175 uint32_t cached_val = vop->regsbak[offset >> 2];
177 v = (cached_val & ~(mask << shift)) | (v << shift);
178 vop->regsbak[offset >> 2] = v;
182 writel_relaxed(v, vop->regs + offset);
184 writel(v, vop->regs + offset);
187 static inline uint32_t vop_get_intr_type(struct vop *vop,
188 const struct vop_reg *reg, int type)
191 uint32_t regs = vop_read_reg(vop, 0, reg);
193 for (i = 0; i < vop->data->intr->nintrs; i++) {
194 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
195 ret |= vop->data->intr->intrs[i];
201 static inline void vop_cfg_done(struct vop *vop)
203 VOP_CTRL_SET(vop, cfg_done, 1);
206 static bool has_rb_swapped(uint32_t format)
209 case DRM_FORMAT_XBGR8888:
210 case DRM_FORMAT_ABGR8888:
211 case DRM_FORMAT_BGR888:
212 case DRM_FORMAT_BGR565:
219 static enum vop_data_format vop_convert_format(uint32_t format)
222 case DRM_FORMAT_XRGB8888:
223 case DRM_FORMAT_ARGB8888:
224 case DRM_FORMAT_XBGR8888:
225 case DRM_FORMAT_ABGR8888:
226 return VOP_FMT_ARGB8888;
227 case DRM_FORMAT_RGB888:
228 case DRM_FORMAT_BGR888:
229 return VOP_FMT_RGB888;
230 case DRM_FORMAT_RGB565:
231 case DRM_FORMAT_BGR565:
232 return VOP_FMT_RGB565;
233 case DRM_FORMAT_NV12:
234 return VOP_FMT_YUV420SP;
235 case DRM_FORMAT_NV16:
236 return VOP_FMT_YUV422SP;
237 case DRM_FORMAT_NV24:
238 return VOP_FMT_YUV444SP;
240 DRM_ERROR("unsupport format[%08x]\n", format);
245 static bool is_yuv_support(uint32_t format)
248 case DRM_FORMAT_NV12:
249 case DRM_FORMAT_NV16:
250 case DRM_FORMAT_NV24:
257 static bool is_alpha_support(uint32_t format)
260 case DRM_FORMAT_ARGB8888:
261 case DRM_FORMAT_ABGR8888:
268 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
269 uint32_t dst, bool is_horizontal,
270 int vsu_mode, int *vskiplines)
272 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
275 if (mode == SCALE_UP)
276 val = GET_SCL_FT_BIC(src, dst);
277 else if (mode == SCALE_DOWN)
278 val = GET_SCL_FT_BILI_DN(src, dst);
280 if (mode == SCALE_UP) {
281 if (vsu_mode == SCALE_UP_BIL)
282 val = GET_SCL_FT_BILI_UP(src, dst);
284 val = GET_SCL_FT_BIC(src, dst);
285 } else if (mode == SCALE_DOWN) {
287 *vskiplines = scl_get_vskiplines(src, dst);
288 val = scl_get_bili_dn_vskip(src, dst,
291 val = GET_SCL_FT_BILI_DN(src, dst);
299 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
300 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
301 uint32_t dst_h, uint32_t pixel_format)
303 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
304 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
305 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
306 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
307 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
308 bool is_yuv = is_yuv_support(pixel_format);
309 uint16_t cbcr_src_w = src_w / hsub;
310 uint16_t cbcr_src_h = src_h / vsub;
317 DRM_ERROR("Maximum destination width (3840) exceeded\n");
321 if (!win->phy->scl->ext) {
322 VOP_SCL_SET(vop, win, scale_yrgb_x,
323 scl_cal_scale2(src_w, dst_w));
324 VOP_SCL_SET(vop, win, scale_yrgb_y,
325 scl_cal_scale2(src_h, dst_h));
327 VOP_SCL_SET(vop, win, scale_cbcr_x,
328 scl_cal_scale2(src_w, dst_w));
329 VOP_SCL_SET(vop, win, scale_cbcr_y,
330 scl_cal_scale2(src_h, dst_h));
335 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
336 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
339 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
340 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
341 if (cbcr_hor_scl_mode == SCALE_DOWN)
342 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
344 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
346 if (yrgb_hor_scl_mode == SCALE_DOWN)
347 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
349 lb_mode = scl_vop_cal_lb_mode(src_w, false);
352 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
353 if (lb_mode == LB_RGB_3840X2) {
354 if (yrgb_ver_scl_mode != SCALE_NONE) {
355 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
358 if (cbcr_ver_scl_mode != SCALE_NONE) {
359 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
362 vsu_mode = SCALE_UP_BIL;
363 } else if (lb_mode == LB_RGB_2560X4) {
364 vsu_mode = SCALE_UP_BIL;
366 vsu_mode = SCALE_UP_BIC;
369 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
371 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
372 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
373 false, vsu_mode, &vskiplines);
374 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
376 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
377 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
379 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
380 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
381 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
382 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
383 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
385 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
386 dst_w, true, 0, NULL);
387 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
388 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
389 dst_h, false, vsu_mode, &vskiplines);
390 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
392 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
393 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
394 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
395 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
396 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
397 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
398 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
402 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
406 if (WARN_ON(!vop->is_enabled))
409 spin_lock_irqsave(&vop->irq_lock, flags);
411 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
413 spin_unlock_irqrestore(&vop->irq_lock, flags);
416 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
420 if (WARN_ON(!vop->is_enabled))
423 spin_lock_irqsave(&vop->irq_lock, flags);
425 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
427 spin_unlock_irqrestore(&vop->irq_lock, flags);
430 static void vop_enable(struct drm_crtc *crtc)
432 struct vop *vop = to_vop(crtc);
438 ret = pm_runtime_get_sync(vop->dev);
440 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
444 ret = clk_enable(vop->hclk);
446 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
450 ret = clk_enable(vop->dclk);
452 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
453 goto err_disable_hclk;
456 ret = clk_enable(vop->aclk);
458 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
459 goto err_disable_dclk;
463 * Slave iommu shares power, irq and clock with vop. It was associated
464 * automatically with this master device via common driver code.
465 * Now that we have enabled the clock we attach it to the shared drm
468 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
470 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
471 goto err_disable_aclk;
474 memcpy(vop->regs, vop->regsbak, vop->len);
476 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
478 vop->is_enabled = true;
480 spin_lock(&vop->reg_lock);
482 VOP_CTRL_SET(vop, standby, 0);
484 spin_unlock(&vop->reg_lock);
486 enable_irq(vop->irq);
488 drm_crtc_vblank_on(crtc);
493 clk_disable(vop->aclk);
495 clk_disable(vop->dclk);
497 clk_disable(vop->hclk);
500 static void vop_crtc_disable(struct drm_crtc *crtc)
502 struct vop *vop = to_vop(crtc);
505 if (!vop->is_enabled)
509 * We need to make sure that all windows are disabled before we
510 * disable that crtc. Otherwise we might try to scan from a destroyed
513 for (i = 0; i < vop->data->win_size; i++) {
514 struct vop_win *vop_win = &vop->win[i];
515 const struct vop_win_data *win = vop_win->data;
517 spin_lock(&vop->reg_lock);
518 VOP_WIN_SET(vop, win, enable, 0);
519 spin_unlock(&vop->reg_lock);
522 drm_crtc_vblank_off(crtc);
525 * Vop standby will take effect at end of current frame,
526 * if dsp hold valid irq happen, it means standby complete.
528 * we must wait standby complete when we want to disable aclk,
529 * if not, memory bus maybe dead.
531 reinit_completion(&vop->dsp_hold_completion);
532 vop_dsp_hold_valid_irq_enable(vop);
534 spin_lock(&vop->reg_lock);
536 VOP_CTRL_SET(vop, standby, 1);
538 spin_unlock(&vop->reg_lock);
540 wait_for_completion(&vop->dsp_hold_completion);
542 vop_dsp_hold_valid_irq_disable(vop);
544 disable_irq(vop->irq);
546 vop->is_enabled = false;
549 * vop standby complete, so iommu detach is safe.
551 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
553 clk_disable(vop->dclk);
554 clk_disable(vop->aclk);
555 clk_disable(vop->hclk);
556 pm_runtime_put(vop->dev);
559 static void vop_plane_destroy(struct drm_plane *plane)
561 drm_plane_cleanup(plane);
564 static int vop_plane_atomic_check(struct drm_plane *plane,
565 struct drm_plane_state *state)
567 struct drm_crtc *crtc = state->crtc;
568 struct drm_framebuffer *fb = state->fb;
569 struct vop_win *vop_win = to_vop_win(plane);
570 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
571 const struct vop_win_data *win = vop_win->data;
574 struct drm_rect *dest = &vop_plane_state->dest;
575 struct drm_rect *src = &vop_plane_state->src;
576 struct drm_rect clip;
577 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
578 DRM_PLANE_HELPER_NO_SCALING;
579 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
580 DRM_PLANE_HELPER_NO_SCALING;
582 crtc = crtc ? crtc : plane->state->crtc;
584 * Both crtc or plane->state->crtc can be null.
588 src->x1 = state->src_x;
589 src->y1 = state->src_y;
590 src->x2 = state->src_x + state->src_w;
591 src->y2 = state->src_y + state->src_h;
592 dest->x1 = state->crtc_x;
593 dest->y1 = state->crtc_y;
594 dest->x2 = state->crtc_x + state->crtc_w;
595 dest->y2 = state->crtc_y + state->crtc_h;
599 clip.x2 = crtc->mode.hdisplay;
600 clip.y2 = crtc->mode.vdisplay;
602 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
606 true, true, &visible);
613 vop_plane_state->format = vop_convert_format(fb->pixel_format);
614 if (vop_plane_state->format < 0)
615 return vop_plane_state->format;
618 * Src.x1 can be odd when do clip, but yuv plane start point
619 * need align with 2 pixel.
621 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
624 vop_plane_state->enable = true;
629 vop_plane_state->enable = false;
633 static void vop_plane_atomic_disable(struct drm_plane *plane,
634 struct drm_plane_state *old_state)
636 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
637 struct vop_win *vop_win = to_vop_win(plane);
638 const struct vop_win_data *win = vop_win->data;
639 struct vop *vop = to_vop(old_state->crtc);
641 if (!old_state->crtc)
644 spin_lock(&vop->reg_lock);
646 VOP_WIN_SET(vop, win, enable, 0);
648 spin_unlock(&vop->reg_lock);
650 vop_plane_state->enable = false;
653 static void vop_plane_atomic_update(struct drm_plane *plane,
654 struct drm_plane_state *old_state)
656 struct drm_plane_state *state = plane->state;
657 struct drm_crtc *crtc = state->crtc;
658 struct vop_win *vop_win = to_vop_win(plane);
659 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
660 const struct vop_win_data *win = vop_win->data;
661 struct vop *vop = to_vop(state->crtc);
662 struct drm_framebuffer *fb = state->fb;
663 unsigned int actual_w, actual_h;
664 unsigned int dsp_stx, dsp_sty;
665 uint32_t act_info, dsp_info, dsp_st;
666 struct drm_rect *src = &vop_plane_state->src;
667 struct drm_rect *dest = &vop_plane_state->dest;
668 struct drm_gem_object *obj, *uv_obj;
669 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
670 unsigned long offset;
676 * can't update plane when vop is disabled.
681 if (WARN_ON(!vop->is_enabled))
684 if (!vop_plane_state->enable) {
685 vop_plane_atomic_disable(plane, old_state);
689 obj = rockchip_fb_get_gem_obj(fb, 0);
690 rk_obj = to_rockchip_obj(obj);
692 actual_w = drm_rect_width(src) >> 16;
693 actual_h = drm_rect_height(src) >> 16;
694 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
696 dsp_info = (drm_rect_height(dest) - 1) << 16;
697 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
699 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
700 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
701 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
703 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
704 offset += (src->y1 >> 16) * fb->pitches[0];
705 vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
707 spin_lock(&vop->reg_lock);
709 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
710 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
711 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
712 if (is_yuv_support(fb->pixel_format)) {
713 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
714 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
715 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
717 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
718 rk_uv_obj = to_rockchip_obj(uv_obj);
720 offset = (src->x1 >> 16) * bpp / hsub;
721 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
723 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
724 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
725 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
729 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
730 drm_rect_width(dest), drm_rect_height(dest),
733 VOP_WIN_SET(vop, win, act_info, act_info);
734 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
735 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
737 rb_swap = has_rb_swapped(fb->pixel_format);
738 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
740 if (is_alpha_support(fb->pixel_format)) {
741 VOP_WIN_SET(vop, win, dst_alpha_ctl,
742 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
743 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
744 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
745 SRC_BLEND_M0(ALPHA_PER_PIX) |
746 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
747 SRC_FACTOR_M0(ALPHA_ONE);
748 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
750 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
753 VOP_WIN_SET(vop, win, enable, 1);
754 spin_unlock(&vop->reg_lock);
757 static const struct drm_plane_helper_funcs plane_helper_funcs = {
758 .atomic_check = vop_plane_atomic_check,
759 .atomic_update = vop_plane_atomic_update,
760 .atomic_disable = vop_plane_atomic_disable,
763 void vop_atomic_plane_reset(struct drm_plane *plane)
765 struct vop_plane_state *vop_plane_state =
766 to_vop_plane_state(plane->state);
768 if (plane->state && plane->state->fb)
769 drm_framebuffer_unreference(plane->state->fb);
771 kfree(vop_plane_state);
772 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
773 if (!vop_plane_state)
776 plane->state = &vop_plane_state->base;
777 plane->state->plane = plane;
780 struct drm_plane_state *
781 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
783 struct vop_plane_state *old_vop_plane_state;
784 struct vop_plane_state *vop_plane_state;
786 if (WARN_ON(!plane->state))
789 old_vop_plane_state = to_vop_plane_state(plane->state);
790 vop_plane_state = kmemdup(old_vop_plane_state,
791 sizeof(*vop_plane_state), GFP_KERNEL);
792 if (!vop_plane_state)
795 __drm_atomic_helper_plane_duplicate_state(plane,
796 &vop_plane_state->base);
798 return &vop_plane_state->base;
801 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
802 struct drm_plane_state *state)
804 struct vop_plane_state *vop_state = to_vop_plane_state(state);
806 __drm_atomic_helper_plane_destroy_state(plane, state);
811 static const struct drm_plane_funcs vop_plane_funcs = {
812 .update_plane = drm_atomic_helper_update_plane,
813 .disable_plane = drm_atomic_helper_disable_plane,
814 .destroy = vop_plane_destroy,
815 .reset = vop_atomic_plane_reset,
816 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
817 .atomic_destroy_state = vop_atomic_plane_destroy_state,
820 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
822 struct vop *vop = to_vop(crtc);
825 if (WARN_ON(!vop->is_enabled))
828 spin_lock_irqsave(&vop->irq_lock, flags);
830 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
832 spin_unlock_irqrestore(&vop->irq_lock, flags);
837 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
839 struct vop *vop = to_vop(crtc);
842 if (WARN_ON(!vop->is_enabled))
845 spin_lock_irqsave(&vop->irq_lock, flags);
847 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
849 spin_unlock_irqrestore(&vop->irq_lock, flags);
852 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
854 struct vop *vop = to_vop(crtc);
856 reinit_completion(&vop->wait_update_complete);
857 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
860 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
861 struct drm_file *file_priv)
863 struct drm_device *drm = crtc->dev;
864 struct vop *vop = to_vop(crtc);
865 struct drm_pending_vblank_event *e;
868 spin_lock_irqsave(&drm->event_lock, flags);
870 if (e && e->base.file_priv == file_priv) {
873 e->base.destroy(&e->base);
874 file_priv->event_space += sizeof(e->event);
876 spin_unlock_irqrestore(&drm->event_lock, flags);
879 static const struct rockchip_crtc_funcs private_crtc_funcs = {
880 .enable_vblank = vop_crtc_enable_vblank,
881 .disable_vblank = vop_crtc_disable_vblank,
882 .wait_for_update = vop_crtc_wait_for_update,
883 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
886 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
887 const struct drm_display_mode *mode,
888 struct drm_display_mode *adjusted_mode)
890 struct vop *vop = to_vop(crtc);
892 adjusted_mode->clock =
893 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
898 static void vop_crtc_enable(struct drm_crtc *crtc)
900 struct vop *vop = to_vop(crtc);
901 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
902 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
903 u16 hdisplay = adjusted_mode->hdisplay;
904 u16 htotal = adjusted_mode->htotal;
905 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
906 u16 hact_end = hact_st + hdisplay;
907 u16 vdisplay = adjusted_mode->vdisplay;
908 u16 vtotal = adjusted_mode->vtotal;
909 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
910 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
911 u16 vact_end = vact_st + vdisplay;
912 uint32_t pin_pol, val;
913 int type = ROCKCHIP_OUT_MODE_TYPE(adjusted_mode->private_flags);
914 int out_mode = ROCKCHIP_OUT_MODE(adjusted_mode->private_flags);
918 * If dclk rate is zero, mean that scanout is stop,
919 * we don't need wait any more.
921 if (clk_get_rate(vop->dclk)) {
923 * Rk3288 vop timing register is immediately, when configure
924 * display timing on display time, may cause tearing.
926 * Vop standby will take effect at end of current frame,
927 * if dsp hold valid irq happen, it means standby complete.
930 * standby and wait complete --> |----
934 * configure display timing --> |
939 reinit_completion(&vop->dsp_hold_completion);
940 vop_dsp_hold_valid_irq_enable(vop);
942 spin_lock(&vop->reg_lock);
944 VOP_CTRL_SET(vop, standby, 1);
946 spin_unlock(&vop->reg_lock);
948 wait_for_completion(&vop->dsp_hold_completion);
950 vop_dsp_hold_valid_irq_disable(vop);
954 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
955 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
956 VOP_CTRL_SET(vop, pin_pol, pin_pol);
959 case DRM_MODE_CONNECTOR_LVDS:
960 VOP_CTRL_SET(vop, rgb_en, 1);
961 VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol);
963 case DRM_MODE_CONNECTOR_eDP:
964 VOP_CTRL_SET(vop, edp_pin_pol, pin_pol);
965 VOP_CTRL_SET(vop, edp_en, 1);
967 case DRM_MODE_CONNECTOR_HDMIA:
968 VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol);
969 VOP_CTRL_SET(vop, hdmi_en, 1);
971 case DRM_MODE_CONNECTOR_DSI:
972 VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol);
973 VOP_CTRL_SET(vop, mipi_en, 1);
976 DRM_ERROR("unsupport connector_type[%d]\n", type);
978 VOP_CTRL_SET(vop, out_mode, out_mode);
980 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
983 VOP_CTRL_SET(vop, hact_st_end, val);
984 VOP_CTRL_SET(vop, hpost_st_end, val);
986 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
989 VOP_CTRL_SET(vop, vact_st_end, val);
990 VOP_CTRL_SET(vop, vpost_st_end, val);
992 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
994 VOP_CTRL_SET(vop, standby, 0);
997 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
998 struct drm_crtc_state *old_crtc_state)
1000 struct vop *vop = to_vop(crtc);
1002 if (WARN_ON(!vop->is_enabled))
1005 spin_lock(&vop->reg_lock);
1009 spin_unlock(&vop->reg_lock);
1012 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1013 struct drm_crtc_state *old_crtc_state)
1015 struct vop *vop = to_vop(crtc);
1017 if (crtc->state->event) {
1018 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1020 vop->event = crtc->state->event;
1021 crtc->state->event = NULL;
1025 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1026 .enable = vop_crtc_enable,
1027 .disable = vop_crtc_disable,
1028 .mode_fixup = vop_crtc_mode_fixup,
1029 .atomic_flush = vop_crtc_atomic_flush,
1030 .atomic_begin = vop_crtc_atomic_begin,
1033 static void vop_crtc_destroy(struct drm_crtc *crtc)
1035 drm_crtc_cleanup(crtc);
1038 static const struct drm_crtc_funcs vop_crtc_funcs = {
1039 .set_config = drm_atomic_helper_set_config,
1040 .page_flip = drm_atomic_helper_page_flip,
1041 .destroy = vop_crtc_destroy,
1042 .reset = drm_atomic_helper_crtc_reset,
1043 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1044 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1047 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1049 struct drm_plane *plane = &vop_win->base;
1050 struct vop_plane_state *state = to_vop_plane_state(plane->state);
1051 dma_addr_t yrgb_mst;
1054 return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0;
1056 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1058 return yrgb_mst == state->yrgb_mst;
1061 static void vop_handle_vblank(struct vop *vop)
1063 struct drm_device *drm = vop->drm_dev;
1064 struct drm_crtc *crtc = &vop->crtc;
1065 unsigned long flags;
1068 for (i = 0; i < vop->data->win_size; i++) {
1069 if (!vop_win_pending_is_complete(&vop->win[i]))
1074 spin_lock_irqsave(&drm->event_lock, flags);
1076 drm_crtc_send_vblank_event(crtc, vop->event);
1077 drm_crtc_vblank_put(crtc);
1080 spin_unlock_irqrestore(&drm->event_lock, flags);
1082 if (!completion_done(&vop->wait_update_complete))
1083 complete(&vop->wait_update_complete);
1086 static irqreturn_t vop_isr(int irq, void *data)
1088 struct vop *vop = data;
1089 struct drm_crtc *crtc = &vop->crtc;
1090 uint32_t active_irqs;
1091 unsigned long flags;
1095 * interrupt register has interrupt status, enable and clear bits, we
1096 * must hold irq_lock to avoid a race with enable/disable_vblank().
1098 spin_lock_irqsave(&vop->irq_lock, flags);
1100 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1101 /* Clear all active interrupt sources */
1103 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1105 spin_unlock_irqrestore(&vop->irq_lock, flags);
1107 /* This is expected for vop iommu irqs, since the irq is shared */
1111 if (active_irqs & DSP_HOLD_VALID_INTR) {
1112 complete(&vop->dsp_hold_completion);
1113 active_irqs &= ~DSP_HOLD_VALID_INTR;
1117 if (active_irqs & FS_INTR) {
1118 drm_crtc_handle_vblank(crtc);
1119 vop_handle_vblank(vop);
1120 active_irqs &= ~FS_INTR;
1124 /* Unhandled irqs are spurious. */
1126 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1131 static int vop_create_crtc(struct vop *vop)
1133 const struct vop_data *vop_data = vop->data;
1134 struct device *dev = vop->dev;
1135 struct drm_device *drm_dev = vop->drm_dev;
1136 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1137 struct drm_crtc *crtc = &vop->crtc;
1138 struct device_node *port;
1143 * Create drm_plane for primary and cursor planes first, since we need
1144 * to pass them to drm_crtc_init_with_planes, which sets the
1145 * "possible_crtcs" to the newly initialized crtc.
1147 for (i = 0; i < vop_data->win_size; i++) {
1148 struct vop_win *vop_win = &vop->win[i];
1149 const struct vop_win_data *win_data = vop_win->data;
1151 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1152 win_data->type != DRM_PLANE_TYPE_CURSOR)
1155 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1156 0, &vop_plane_funcs,
1157 win_data->phy->data_formats,
1158 win_data->phy->nformats,
1159 win_data->type, NULL);
1161 DRM_ERROR("failed to initialize plane\n");
1162 goto err_cleanup_planes;
1165 plane = &vop_win->base;
1166 drm_plane_helper_add(plane, &plane_helper_funcs);
1167 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1169 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1173 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1174 &vop_crtc_funcs, NULL);
1176 goto err_cleanup_planes;
1178 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1181 * Create drm_planes for overlay windows with possible_crtcs restricted
1182 * to the newly created crtc.
1184 for (i = 0; i < vop_data->win_size; i++) {
1185 struct vop_win *vop_win = &vop->win[i];
1186 const struct vop_win_data *win_data = vop_win->data;
1187 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1189 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1192 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1195 win_data->phy->data_formats,
1196 win_data->phy->nformats,
1197 win_data->type, NULL);
1199 DRM_ERROR("failed to initialize overlay plane\n");
1200 goto err_cleanup_crtc;
1202 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1205 port = of_get_child_by_name(dev->of_node, "port");
1207 DRM_ERROR("no port node found in %s\n",
1208 dev->of_node->full_name);
1210 goto err_cleanup_crtc;
1213 init_completion(&vop->dsp_hold_completion);
1214 init_completion(&vop->wait_update_complete);
1216 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1221 drm_crtc_cleanup(crtc);
1223 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1225 drm_plane_cleanup(plane);
1229 static void vop_destroy_crtc(struct vop *vop)
1231 struct drm_crtc *crtc = &vop->crtc;
1232 struct drm_device *drm_dev = vop->drm_dev;
1233 struct drm_plane *plane, *tmp;
1235 rockchip_unregister_crtc_funcs(crtc);
1236 of_node_put(crtc->port);
1239 * We need to cleanup the planes now. Why?
1241 * The planes are "&vop->win[i].base". That means the memory is
1242 * all part of the big "struct vop" chunk of memory. That memory
1243 * was devm allocated and associated with this component. We need to
1244 * free it ourselves before vop_unbind() finishes.
1246 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1248 vop_plane_destroy(plane);
1251 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1252 * references the CRTC.
1254 drm_crtc_cleanup(crtc);
1257 static int vop_initial(struct vop *vop)
1259 const struct vop_data *vop_data = vop->data;
1260 const struct vop_reg_data *init_table = vop_data->init_table;
1261 struct reset_control *ahb_rst;
1264 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1265 if (IS_ERR(vop->hclk)) {
1266 dev_err(vop->dev, "failed to get hclk source\n");
1267 return PTR_ERR(vop->hclk);
1269 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1270 if (IS_ERR(vop->aclk)) {
1271 dev_err(vop->dev, "failed to get aclk source\n");
1272 return PTR_ERR(vop->aclk);
1274 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1275 if (IS_ERR(vop->dclk)) {
1276 dev_err(vop->dev, "failed to get dclk source\n");
1277 return PTR_ERR(vop->dclk);
1280 ret = clk_prepare(vop->dclk);
1282 dev_err(vop->dev, "failed to prepare dclk\n");
1286 /* Enable both the hclk and aclk to setup the vop */
1287 ret = clk_prepare_enable(vop->hclk);
1289 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1290 goto err_unprepare_dclk;
1293 ret = clk_prepare_enable(vop->aclk);
1295 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1296 goto err_disable_hclk;
1300 * do hclk_reset, reset all vop registers.
1302 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1303 if (IS_ERR(ahb_rst)) {
1304 dev_err(vop->dev, "failed to get ahb reset\n");
1305 ret = PTR_ERR(ahb_rst);
1306 goto err_disable_aclk;
1308 reset_control_assert(ahb_rst);
1309 usleep_range(10, 20);
1310 reset_control_deassert(ahb_rst);
1312 memcpy(vop->regsbak, vop->regs, vop->len);
1314 for (i = 0; i < vop_data->table_size; i++)
1315 vop_writel(vop, init_table[i].offset, init_table[i].value);
1317 for (i = 0; i < vop_data->win_size; i++) {
1318 const struct vop_win_data *win = &vop_data->win[i];
1320 VOP_WIN_SET(vop, win, enable, 0);
1326 * do dclk_reset, let all config take affect.
1328 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1329 if (IS_ERR(vop->dclk_rst)) {
1330 dev_err(vop->dev, "failed to get dclk reset\n");
1331 ret = PTR_ERR(vop->dclk_rst);
1332 goto err_disable_aclk;
1334 reset_control_assert(vop->dclk_rst);
1335 usleep_range(10, 20);
1336 reset_control_deassert(vop->dclk_rst);
1338 clk_disable(vop->hclk);
1339 clk_disable(vop->aclk);
1341 vop->is_enabled = false;
1346 clk_disable_unprepare(vop->aclk);
1348 clk_disable_unprepare(vop->hclk);
1350 clk_unprepare(vop->dclk);
1355 * Initialize the vop->win array elements.
1357 static void vop_win_init(struct vop *vop)
1359 const struct vop_data *vop_data = vop->data;
1362 for (i = 0; i < vop_data->win_size; i++) {
1363 struct vop_win *vop_win = &vop->win[i];
1364 const struct vop_win_data *win_data = &vop_data->win[i];
1366 vop_win->data = win_data;
1371 static int vop_bind(struct device *dev, struct device *master, void *data)
1373 struct platform_device *pdev = to_platform_device(dev);
1374 const struct vop_data *vop_data;
1375 struct drm_device *drm_dev = data;
1377 struct resource *res;
1381 vop_data = of_device_get_match_data(dev);
1385 /* Allocate vop struct and its vop_win array */
1386 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1387 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1392 vop->data = vop_data;
1393 vop->drm_dev = drm_dev;
1394 dev_set_drvdata(dev, vop);
1398 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1399 vop->len = resource_size(res);
1400 vop->regs = devm_ioremap_resource(dev, res);
1401 if (IS_ERR(vop->regs))
1402 return PTR_ERR(vop->regs);
1404 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1408 ret = vop_initial(vop);
1410 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1414 irq = platform_get_irq(pdev, 0);
1416 dev_err(dev, "cannot find irq for vop\n");
1419 vop->irq = (unsigned int)irq;
1421 spin_lock_init(&vop->reg_lock);
1422 spin_lock_init(&vop->irq_lock);
1424 mutex_init(&vop->vsync_mutex);
1426 ret = devm_request_irq(dev, vop->irq, vop_isr,
1427 IRQF_SHARED, dev_name(dev), vop);
1431 /* IRQ is initially disabled; it gets enabled in power_on */
1432 disable_irq(vop->irq);
1434 ret = vop_create_crtc(vop);
1438 pm_runtime_enable(&pdev->dev);
1442 static void vop_unbind(struct device *dev, struct device *master, void *data)
1444 struct vop *vop = dev_get_drvdata(dev);
1446 pm_runtime_disable(dev);
1447 vop_destroy_crtc(vop);
1450 const struct component_ops vop_component_ops = {
1452 .unbind = vop_unbind,
1454 EXPORT_SYMBOL_GPL(vop_component_ops);