2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/component.h>
31 #include <linux/reset.h>
32 #include <linux/delay.h>
34 #include "rockchip_drm_drv.h"
35 #include "rockchip_drm_gem.h"
36 #include "rockchip_drm_fb.h"
37 #include "rockchip_drm_vop.h"
39 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
40 vop_mask_write(x, off, mask, shift, v, write_mask, true)
42 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
43 vop_mask_write(x, off, mask, shift, v, write_mask, false)
45 #define REG_SET(x, off, reg, v, mode) \
46 __REG_SET_##mode(x, off + reg.offset, \
47 reg.mask, reg.shift, v, reg.write_mask)
48 #define REG_SET_MASK(x, off, reg, mask, v, mode) \
49 __REG_SET_##mode(x, off + reg.offset, \
50 mask, reg.shift, v, reg.write_mask)
52 #define VOP_WIN_SET(x, win, name, v) \
53 REG_SET(x, win->offset, VOP_WIN_NAME(win, name), v, RELAXED)
54 #define VOP_SCL_SET(x, win, name, v) \
55 REG_SET(x, win->offset, win->phy->scl->name, v, RELAXED)
56 #define VOP_SCL_SET_EXT(x, win, name, v) \
57 REG_SET(x, win->offset, win->phy->scl->ext->name, v, RELAXED)
59 #define VOP_CTRL_SET(x, name, v) \
60 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
62 #define VOP_INTR_GET(vop, name) \
63 vop_read_reg(vop, 0, &vop->data->ctrl->name)
65 #define VOP_INTR_SET(vop, name, mask, v) \
66 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
67 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
69 int i, reg = 0, mask = 0; \
70 for (i = 0; i < vop->data->intr->nintrs; i++) { \
71 if (vop->data->intr->intrs[i] & type) { \
76 VOP_INTR_SET(vop, name, mask, reg); \
78 #define VOP_INTR_GET_TYPE(vop, name, type) \
79 vop_get_intr_type(vop, &vop->data->intr->name, type)
81 #define VOP_WIN_GET(x, win, name) \
82 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
84 #define VOP_WIN_NAME(win, name) \
85 (vop_get_win_phy(win, &win->phy->name)->name)
87 #define VOP_WIN_GET_YRGBADDR(vop, win) \
88 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
90 #define to_vop(x) container_of(x, struct vop, crtc)
91 #define to_vop_win(x) container_of(x, struct vop_win, base)
92 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
94 struct vop_plane_state {
95 struct drm_plane_state base;
104 struct vop_win *parent;
105 struct drm_plane base;
108 enum drm_plane_type type;
109 const struct vop_win_phy *phy;
110 const uint32_t *data_formats;
114 struct vop_plane_state state;
118 struct drm_crtc crtc;
120 struct drm_device *drm_dev;
123 /* mutex vsync_ work */
124 struct mutex vsync_mutex;
125 bool vsync_work_pending;
126 struct completion dsp_hold_completion;
127 struct completion wait_update_complete;
128 struct drm_pending_vblank_event *event;
130 const struct vop_data *data;
136 /* physical map length of vop register */
139 /* one time only one process allowed to config the register */
141 /* lock vop irq reg */
150 /* vop share memory frequency */
154 struct reset_control *dclk_rst;
156 struct vop_win win[];
159 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
161 writel(v, vop->regs + offset);
162 vop->regsbak[offset >> 2] = v;
165 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
167 return readl(vop->regs + offset);
170 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
171 const struct vop_reg *reg)
173 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
176 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
177 uint32_t mask, uint32_t shift, uint32_t v,
178 bool write_mask, bool relaxed)
184 v = (v << shift) | (mask << (shift + 16));
186 uint32_t cached_val = vop->regsbak[offset >> 2];
188 v = (cached_val & ~(mask << shift)) | (v << shift);
189 vop->regsbak[offset >> 2] = v;
193 writel_relaxed(v, vop->regs + offset);
195 writel(v, vop->regs + offset);
198 static inline const struct vop_win_phy *
199 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
201 if (!reg->mask && win->parent)
202 return win->parent->phy;
207 static inline uint32_t vop_get_intr_type(struct vop *vop,
208 const struct vop_reg *reg, int type)
211 uint32_t regs = vop_read_reg(vop, 0, reg);
213 for (i = 0; i < vop->data->intr->nintrs; i++) {
214 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
215 ret |= vop->data->intr->intrs[i];
221 static inline void vop_cfg_done(struct vop *vop)
223 VOP_CTRL_SET(vop, cfg_done, 1);
226 static bool has_rb_swapped(uint32_t format)
229 case DRM_FORMAT_XBGR8888:
230 case DRM_FORMAT_ABGR8888:
231 case DRM_FORMAT_BGR888:
232 case DRM_FORMAT_BGR565:
239 static enum vop_data_format vop_convert_format(uint32_t format)
242 case DRM_FORMAT_XRGB8888:
243 case DRM_FORMAT_ARGB8888:
244 case DRM_FORMAT_XBGR8888:
245 case DRM_FORMAT_ABGR8888:
246 return VOP_FMT_ARGB8888;
247 case DRM_FORMAT_RGB888:
248 case DRM_FORMAT_BGR888:
249 return VOP_FMT_RGB888;
250 case DRM_FORMAT_RGB565:
251 case DRM_FORMAT_BGR565:
252 return VOP_FMT_RGB565;
253 case DRM_FORMAT_NV12:
254 return VOP_FMT_YUV420SP;
255 case DRM_FORMAT_NV16:
256 return VOP_FMT_YUV422SP;
257 case DRM_FORMAT_NV24:
258 return VOP_FMT_YUV444SP;
260 DRM_ERROR("unsupport format[%08x]\n", format);
265 static bool is_yuv_support(uint32_t format)
268 case DRM_FORMAT_NV12:
269 case DRM_FORMAT_NV16:
270 case DRM_FORMAT_NV24:
277 static bool is_alpha_support(uint32_t format)
280 case DRM_FORMAT_ARGB8888:
281 case DRM_FORMAT_ABGR8888:
288 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
289 uint32_t dst, bool is_horizontal,
290 int vsu_mode, int *vskiplines)
292 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
295 if (mode == SCALE_UP)
296 val = GET_SCL_FT_BIC(src, dst);
297 else if (mode == SCALE_DOWN)
298 val = GET_SCL_FT_BILI_DN(src, dst);
300 if (mode == SCALE_UP) {
301 if (vsu_mode == SCALE_UP_BIL)
302 val = GET_SCL_FT_BILI_UP(src, dst);
304 val = GET_SCL_FT_BIC(src, dst);
305 } else if (mode == SCALE_DOWN) {
307 *vskiplines = scl_get_vskiplines(src, dst);
308 val = scl_get_bili_dn_vskip(src, dst,
311 val = GET_SCL_FT_BILI_DN(src, dst);
319 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
320 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
321 uint32_t dst_h, uint32_t pixel_format)
323 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
324 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
325 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
326 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
327 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
328 bool is_yuv = is_yuv_support(pixel_format);
329 uint16_t cbcr_src_w = src_w / hsub;
330 uint16_t cbcr_src_h = src_h / vsub;
340 DRM_ERROR("Maximum destination width (3840) exceeded\n");
344 if (!win->phy->scl->ext) {
345 VOP_SCL_SET(vop, win, scale_yrgb_x,
346 scl_cal_scale2(src_w, dst_w));
347 VOP_SCL_SET(vop, win, scale_yrgb_y,
348 scl_cal_scale2(src_h, dst_h));
350 VOP_SCL_SET(vop, win, scale_cbcr_x,
351 scl_cal_scale2(src_w, dst_w));
352 VOP_SCL_SET(vop, win, scale_cbcr_y,
353 scl_cal_scale2(src_h, dst_h));
358 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
359 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
362 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
363 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
364 if (cbcr_hor_scl_mode == SCALE_DOWN)
365 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
367 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
369 if (yrgb_hor_scl_mode == SCALE_DOWN)
370 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
372 lb_mode = scl_vop_cal_lb_mode(src_w, false);
375 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
376 if (lb_mode == LB_RGB_3840X2) {
377 if (yrgb_ver_scl_mode != SCALE_NONE) {
378 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
381 if (cbcr_ver_scl_mode != SCALE_NONE) {
382 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
385 vsu_mode = SCALE_UP_BIL;
386 } else if (lb_mode == LB_RGB_2560X4) {
387 vsu_mode = SCALE_UP_BIL;
389 vsu_mode = SCALE_UP_BIC;
392 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
394 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
395 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
396 false, vsu_mode, &vskiplines);
397 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
399 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
400 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
402 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
403 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
404 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
405 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
406 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
408 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
409 dst_w, true, 0, NULL);
410 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
411 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
412 dst_h, false, vsu_mode, &vskiplines);
413 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
415 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
416 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
417 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
418 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
419 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
420 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
421 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
425 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
429 if (WARN_ON(!vop->is_enabled))
432 spin_lock_irqsave(&vop->irq_lock, flags);
434 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
436 spin_unlock_irqrestore(&vop->irq_lock, flags);
439 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
443 if (WARN_ON(!vop->is_enabled))
446 spin_lock_irqsave(&vop->irq_lock, flags);
448 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
450 spin_unlock_irqrestore(&vop->irq_lock, flags);
453 static void vop_enable(struct drm_crtc *crtc)
455 struct vop *vop = to_vop(crtc);
461 ret = pm_runtime_get_sync(vop->dev);
463 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
467 ret = clk_enable(vop->hclk);
469 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
473 ret = clk_enable(vop->dclk);
475 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
476 goto err_disable_hclk;
479 ret = clk_enable(vop->aclk);
481 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
482 goto err_disable_dclk;
486 * Slave iommu shares power, irq and clock with vop. It was associated
487 * automatically with this master device via common driver code.
488 * Now that we have enabled the clock we attach it to the shared drm
491 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
493 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
494 goto err_disable_aclk;
497 memcpy(vop->regs, vop->regsbak, vop->len);
499 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
501 vop->is_enabled = true;
503 spin_lock(&vop->reg_lock);
505 VOP_CTRL_SET(vop, standby, 0);
507 spin_unlock(&vop->reg_lock);
509 enable_irq(vop->irq);
511 drm_crtc_vblank_on(crtc);
516 clk_disable(vop->aclk);
518 clk_disable(vop->dclk);
520 clk_disable(vop->hclk);
523 static void vop_crtc_disable(struct drm_crtc *crtc)
525 struct vop *vop = to_vop(crtc);
528 if (!vop->is_enabled)
532 * We need to make sure that all windows are disabled before we
533 * disable that crtc. Otherwise we might try to scan from a destroyed
536 for (i = 0; i < vop->num_wins; i++) {
537 struct vop_win *win = &vop->win[i];
539 spin_lock(&vop->reg_lock);
540 VOP_WIN_SET(vop, win, enable, 0);
541 spin_unlock(&vop->reg_lock);
544 drm_crtc_vblank_off(crtc);
547 * Vop standby will take effect at end of current frame,
548 * if dsp hold valid irq happen, it means standby complete.
550 * we must wait standby complete when we want to disable aclk,
551 * if not, memory bus maybe dead.
553 reinit_completion(&vop->dsp_hold_completion);
554 vop_dsp_hold_valid_irq_enable(vop);
556 spin_lock(&vop->reg_lock);
558 VOP_CTRL_SET(vop, standby, 1);
560 spin_unlock(&vop->reg_lock);
562 wait_for_completion(&vop->dsp_hold_completion);
564 vop_dsp_hold_valid_irq_disable(vop);
566 disable_irq(vop->irq);
568 vop->is_enabled = false;
571 * vop standby complete, so iommu detach is safe.
573 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
575 clk_disable(vop->dclk);
576 clk_disable(vop->aclk);
577 clk_disable(vop->hclk);
578 pm_runtime_put(vop->dev);
581 static void vop_plane_destroy(struct drm_plane *plane)
583 drm_plane_cleanup(plane);
586 static int vop_plane_atomic_check(struct drm_plane *plane,
587 struct drm_plane_state *state)
589 struct drm_crtc *crtc = state->crtc;
590 struct drm_framebuffer *fb = state->fb;
591 struct vop_win *win = to_vop_win(plane);
592 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
595 struct drm_rect *dest = &vop_plane_state->dest;
596 struct drm_rect *src = &vop_plane_state->src;
597 struct drm_rect clip;
598 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
599 DRM_PLANE_HELPER_NO_SCALING;
600 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
601 DRM_PLANE_HELPER_NO_SCALING;
603 crtc = crtc ? crtc : plane->state->crtc;
605 * Both crtc or plane->state->crtc can be null.
609 src->x1 = state->src_x;
610 src->y1 = state->src_y;
611 src->x2 = state->src_x + state->src_w;
612 src->y2 = state->src_y + state->src_h;
613 dest->x1 = state->crtc_x;
614 dest->y1 = state->crtc_y;
615 dest->x2 = state->crtc_x + state->crtc_w;
616 dest->y2 = state->crtc_y + state->crtc_h;
620 clip.x2 = crtc->mode.hdisplay;
621 clip.y2 = crtc->mode.vdisplay;
623 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
627 true, true, &visible);
634 vop_plane_state->format = vop_convert_format(fb->pixel_format);
635 if (vop_plane_state->format < 0)
636 return vop_plane_state->format;
639 * Src.x1 can be odd when do clip, but yuv plane start point
640 * need align with 2 pixel.
642 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
645 vop_plane_state->enable = true;
650 vop_plane_state->enable = false;
654 static void vop_plane_atomic_disable(struct drm_plane *plane,
655 struct drm_plane_state *old_state)
657 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
658 struct vop_win *win = to_vop_win(plane);
659 struct vop *vop = to_vop(old_state->crtc);
661 if (!old_state->crtc)
664 spin_lock(&vop->reg_lock);
666 VOP_WIN_SET(vop, win, enable, 0);
668 spin_unlock(&vop->reg_lock);
670 vop_plane_state->enable = false;
673 static void vop_plane_atomic_update(struct drm_plane *plane,
674 struct drm_plane_state *old_state)
676 struct drm_plane_state *state = plane->state;
677 struct drm_crtc *crtc = state->crtc;
678 struct vop_win *win = to_vop_win(plane);
679 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
680 struct vop *vop = to_vop(state->crtc);
681 struct drm_framebuffer *fb = state->fb;
682 unsigned int actual_w, actual_h;
683 unsigned int dsp_stx, dsp_sty;
684 uint32_t act_info, dsp_info, dsp_st;
685 struct drm_rect *src = &vop_plane_state->src;
686 struct drm_rect *dest = &vop_plane_state->dest;
687 struct drm_gem_object *obj, *uv_obj;
688 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
689 unsigned long offset;
695 * can't update plane when vop is disabled.
700 if (WARN_ON(!vop->is_enabled))
703 if (!vop_plane_state->enable) {
704 vop_plane_atomic_disable(plane, old_state);
708 obj = rockchip_fb_get_gem_obj(fb, 0);
709 rk_obj = to_rockchip_obj(obj);
711 actual_w = drm_rect_width(src) >> 16;
712 actual_h = drm_rect_height(src) >> 16;
713 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
715 dsp_info = (drm_rect_height(dest) - 1) << 16;
716 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
718 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
719 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
720 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
722 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
723 offset += (src->y1 >> 16) * fb->pitches[0];
724 vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
726 spin_lock(&vop->reg_lock);
728 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
729 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
730 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
731 if (is_yuv_support(fb->pixel_format)) {
732 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
733 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
734 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
736 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
737 rk_uv_obj = to_rockchip_obj(uv_obj);
739 offset = (src->x1 >> 16) * bpp / hsub;
740 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
742 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
743 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
744 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
747 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
748 drm_rect_width(dest), drm_rect_height(dest),
751 VOP_WIN_SET(vop, win, act_info, act_info);
752 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
753 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
755 rb_swap = has_rb_swapped(fb->pixel_format);
756 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
758 if (is_alpha_support(fb->pixel_format)) {
759 VOP_WIN_SET(vop, win, dst_alpha_ctl,
760 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
761 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
762 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
763 SRC_BLEND_M0(ALPHA_PER_PIX) |
764 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
765 SRC_FACTOR_M0(ALPHA_ONE);
766 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
768 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
771 VOP_WIN_SET(vop, win, enable, 1);
772 spin_unlock(&vop->reg_lock);
775 static const struct drm_plane_helper_funcs plane_helper_funcs = {
776 .atomic_check = vop_plane_atomic_check,
777 .atomic_update = vop_plane_atomic_update,
778 .atomic_disable = vop_plane_atomic_disable,
781 void vop_atomic_plane_reset(struct drm_plane *plane)
783 struct vop_plane_state *vop_plane_state =
784 to_vop_plane_state(plane->state);
786 if (plane->state && plane->state->fb)
787 drm_framebuffer_unreference(plane->state->fb);
789 kfree(vop_plane_state);
790 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
791 if (!vop_plane_state)
794 plane->state = &vop_plane_state->base;
795 plane->state->plane = plane;
798 struct drm_plane_state *
799 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
801 struct vop_plane_state *old_vop_plane_state;
802 struct vop_plane_state *vop_plane_state;
804 if (WARN_ON(!plane->state))
807 old_vop_plane_state = to_vop_plane_state(plane->state);
808 vop_plane_state = kmemdup(old_vop_plane_state,
809 sizeof(*vop_plane_state), GFP_KERNEL);
810 if (!vop_plane_state)
813 __drm_atomic_helper_plane_duplicate_state(plane,
814 &vop_plane_state->base);
816 return &vop_plane_state->base;
819 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
820 struct drm_plane_state *state)
822 struct vop_plane_state *vop_state = to_vop_plane_state(state);
824 __drm_atomic_helper_plane_destroy_state(plane, state);
829 static const struct drm_plane_funcs vop_plane_funcs = {
830 .update_plane = drm_atomic_helper_update_plane,
831 .disable_plane = drm_atomic_helper_disable_plane,
832 .destroy = vop_plane_destroy,
833 .reset = vop_atomic_plane_reset,
834 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
835 .atomic_destroy_state = vop_atomic_plane_destroy_state,
838 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
840 struct vop *vop = to_vop(crtc);
843 if (WARN_ON(!vop->is_enabled))
846 spin_lock_irqsave(&vop->irq_lock, flags);
848 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
850 spin_unlock_irqrestore(&vop->irq_lock, flags);
855 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
857 struct vop *vop = to_vop(crtc);
860 if (WARN_ON(!vop->is_enabled))
863 spin_lock_irqsave(&vop->irq_lock, flags);
865 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
867 spin_unlock_irqrestore(&vop->irq_lock, flags);
870 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
872 struct vop *vop = to_vop(crtc);
874 reinit_completion(&vop->wait_update_complete);
875 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
878 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
879 struct drm_file *file_priv)
881 struct drm_device *drm = crtc->dev;
882 struct vop *vop = to_vop(crtc);
883 struct drm_pending_vblank_event *e;
886 spin_lock_irqsave(&drm->event_lock, flags);
888 if (e && e->base.file_priv == file_priv) {
891 e->base.destroy(&e->base);
892 file_priv->event_space += sizeof(e->event);
894 spin_unlock_irqrestore(&drm->event_lock, flags);
897 static const struct rockchip_crtc_funcs private_crtc_funcs = {
898 .enable_vblank = vop_crtc_enable_vblank,
899 .disable_vblank = vop_crtc_disable_vblank,
900 .wait_for_update = vop_crtc_wait_for_update,
901 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
904 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
905 const struct drm_display_mode *mode,
906 struct drm_display_mode *adjusted_mode)
908 struct vop *vop = to_vop(crtc);
910 adjusted_mode->clock =
911 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
916 static void vop_crtc_enable(struct drm_crtc *crtc)
918 struct vop *vop = to_vop(crtc);
919 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
920 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
921 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
922 u16 hdisplay = adjusted_mode->hdisplay;
923 u16 htotal = adjusted_mode->htotal;
924 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
925 u16 hact_end = hact_st + hdisplay;
926 u16 vdisplay = adjusted_mode->vdisplay;
927 u16 vtotal = adjusted_mode->vtotal;
928 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
929 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
930 u16 vact_end = vact_st + vdisplay;
935 * If dclk rate is zero, mean that scanout is stop,
936 * we don't need wait any more.
938 if (clk_get_rate(vop->dclk)) {
940 * Rk3288 vop timing register is immediately, when configure
941 * display timing on display time, may cause tearing.
943 * Vop standby will take effect at end of current frame,
944 * if dsp hold valid irq happen, it means standby complete.
947 * standby and wait complete --> |----
951 * configure display timing --> |
956 reinit_completion(&vop->dsp_hold_completion);
957 vop_dsp_hold_valid_irq_enable(vop);
959 spin_lock(&vop->reg_lock);
961 VOP_CTRL_SET(vop, standby, 1);
963 spin_unlock(&vop->reg_lock);
965 wait_for_completion(&vop->dsp_hold_completion);
967 vop_dsp_hold_valid_irq_disable(vop);
971 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
972 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
973 VOP_CTRL_SET(vop, pin_pol, val);
974 switch (s->output_type) {
975 case DRM_MODE_CONNECTOR_LVDS:
976 VOP_CTRL_SET(vop, rgb_en, 1);
978 case DRM_MODE_CONNECTOR_eDP:
979 VOP_CTRL_SET(vop, edp_en, 1);
981 case DRM_MODE_CONNECTOR_HDMIA:
982 VOP_CTRL_SET(vop, hdmi_en, 1);
984 case DRM_MODE_CONNECTOR_DSI:
985 VOP_CTRL_SET(vop, mipi_en, 1);
988 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
990 VOP_CTRL_SET(vop, out_mode, s->output_mode);
992 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
995 VOP_CTRL_SET(vop, hact_st_end, val);
996 VOP_CTRL_SET(vop, hpost_st_end, val);
998 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1001 VOP_CTRL_SET(vop, vact_st_end, val);
1002 VOP_CTRL_SET(vop, vpost_st_end, val);
1004 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1006 VOP_CTRL_SET(vop, standby, 0);
1009 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1010 struct drm_crtc_state *old_crtc_state)
1012 struct vop *vop = to_vop(crtc);
1014 if (WARN_ON(!vop->is_enabled))
1017 spin_lock(&vop->reg_lock);
1021 spin_unlock(&vop->reg_lock);
1024 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1025 struct drm_crtc_state *old_crtc_state)
1027 struct vop *vop = to_vop(crtc);
1029 if (crtc->state->event) {
1030 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1032 vop->event = crtc->state->event;
1033 crtc->state->event = NULL;
1037 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1038 .enable = vop_crtc_enable,
1039 .disable = vop_crtc_disable,
1040 .mode_fixup = vop_crtc_mode_fixup,
1041 .atomic_flush = vop_crtc_atomic_flush,
1042 .atomic_begin = vop_crtc_atomic_begin,
1045 static void vop_crtc_destroy(struct drm_crtc *crtc)
1047 drm_crtc_cleanup(crtc);
1050 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1052 struct rockchip_crtc_state *rockchip_state;
1054 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1055 if (!rockchip_state)
1058 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1059 return &rockchip_state->base;
1062 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1063 struct drm_crtc_state *state)
1065 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1067 __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1071 static const struct drm_crtc_funcs vop_crtc_funcs = {
1072 .set_config = drm_atomic_helper_set_config,
1073 .page_flip = drm_atomic_helper_page_flip,
1074 .destroy = vop_crtc_destroy,
1075 .reset = drm_atomic_helper_crtc_reset,
1076 .atomic_duplicate_state = vop_crtc_duplicate_state,
1077 .atomic_destroy_state = vop_crtc_destroy_state,
1080 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1082 struct drm_plane *plane = &vop_win->base;
1083 struct vop_plane_state *state = to_vop_plane_state(plane->state);
1084 dma_addr_t yrgb_mst;
1087 return VOP_WIN_GET(vop_win->vop, vop_win, enable) == 0;
1089 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win);
1091 return yrgb_mst == state->yrgb_mst;
1094 static void vop_handle_vblank(struct vop *vop)
1096 struct drm_device *drm = vop->drm_dev;
1097 struct drm_crtc *crtc = &vop->crtc;
1098 unsigned long flags;
1101 for (i = 0; i < vop->num_wins; i++) {
1102 if (!vop_win_pending_is_complete(&vop->win[i]))
1107 spin_lock_irqsave(&drm->event_lock, flags);
1109 drm_crtc_send_vblank_event(crtc, vop->event);
1110 drm_crtc_vblank_put(crtc);
1113 spin_unlock_irqrestore(&drm->event_lock, flags);
1115 if (!completion_done(&vop->wait_update_complete))
1116 complete(&vop->wait_update_complete);
1119 static irqreturn_t vop_isr(int irq, void *data)
1121 struct vop *vop = data;
1122 struct drm_crtc *crtc = &vop->crtc;
1123 uint32_t active_irqs;
1124 unsigned long flags;
1128 * interrupt register has interrupt status, enable and clear bits, we
1129 * must hold irq_lock to avoid a race with enable/disable_vblank().
1131 spin_lock_irqsave(&vop->irq_lock, flags);
1133 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1134 /* Clear all active interrupt sources */
1136 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1138 spin_unlock_irqrestore(&vop->irq_lock, flags);
1140 /* This is expected for vop iommu irqs, since the irq is shared */
1144 if (active_irqs & DSP_HOLD_VALID_INTR) {
1145 complete(&vop->dsp_hold_completion);
1146 active_irqs &= ~DSP_HOLD_VALID_INTR;
1150 if (active_irqs & FS_INTR) {
1151 drm_crtc_handle_vblank(crtc);
1152 vop_handle_vblank(vop);
1153 active_irqs &= ~FS_INTR;
1157 /* Unhandled irqs are spurious. */
1159 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1164 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1165 unsigned long possible_crtcs)
1167 struct drm_plane *share = NULL;
1171 share = &win->parent->base;
1173 ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1174 possible_crtcs, &vop_plane_funcs,
1175 win->data_formats, win->nformats, win->type);
1177 DRM_ERROR("failed to initialize plane\n");
1180 drm_plane_helper_add(&win->base, &plane_helper_funcs);
1185 static int vop_create_crtc(struct vop *vop)
1187 struct device *dev = vop->dev;
1188 struct drm_device *drm_dev = vop->drm_dev;
1189 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1190 struct drm_crtc *crtc = &vop->crtc;
1191 struct device_node *port;
1196 * Create drm_plane for primary and cursor planes first, since we need
1197 * to pass them to drm_crtc_init_with_planes, which sets the
1198 * "possible_crtcs" to the newly initialized crtc.
1200 for (i = 0; i < vop->num_wins; i++) {
1201 struct vop_win *win = &vop->win[i];
1203 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1204 win->type != DRM_PLANE_TYPE_CURSOR)
1207 if (vop_plane_init(vop, win, 0))
1208 goto err_cleanup_planes;
1211 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1213 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1218 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1219 &vop_crtc_funcs, NULL);
1221 goto err_cleanup_planes;
1223 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1226 * Create drm_planes for overlay windows with possible_crtcs restricted
1227 * to the newly created crtc.
1229 for (i = 0; i < vop->num_wins; i++) {
1230 struct vop_win *win = &vop->win[i];
1231 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1233 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1236 if (vop_plane_init(vop, win, possible_crtcs))
1237 goto err_cleanup_crtc;
1240 port = of_get_child_by_name(dev->of_node, "port");
1242 DRM_ERROR("no port node found in %s\n",
1243 dev->of_node->full_name);
1245 goto err_cleanup_crtc;
1248 init_completion(&vop->dsp_hold_completion);
1249 init_completion(&vop->wait_update_complete);
1251 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1256 drm_crtc_cleanup(crtc);
1258 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1260 drm_plane_cleanup(plane);
1264 static void vop_destroy_crtc(struct vop *vop)
1266 struct drm_crtc *crtc = &vop->crtc;
1267 struct drm_device *drm_dev = vop->drm_dev;
1268 struct drm_plane *plane, *tmp;
1270 rockchip_unregister_crtc_funcs(crtc);
1271 of_node_put(crtc->port);
1274 * We need to cleanup the planes now. Why?
1276 * The planes are "&vop->win[i].base". That means the memory is
1277 * all part of the big "struct vop" chunk of memory. That memory
1278 * was devm allocated and associated with this component. We need to
1279 * free it ourselves before vop_unbind() finishes.
1281 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1283 vop_plane_destroy(plane);
1286 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1287 * references the CRTC.
1289 drm_crtc_cleanup(crtc);
1292 static int vop_initial(struct vop *vop)
1294 const struct vop_data *vop_data = vop->data;
1295 const struct vop_reg_data *init_table = vop_data->init_table;
1296 struct reset_control *ahb_rst;
1299 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1300 if (IS_ERR(vop->hclk)) {
1301 dev_err(vop->dev, "failed to get hclk source\n");
1302 return PTR_ERR(vop->hclk);
1304 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1305 if (IS_ERR(vop->aclk)) {
1306 dev_err(vop->dev, "failed to get aclk source\n");
1307 return PTR_ERR(vop->aclk);
1309 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1310 if (IS_ERR(vop->dclk)) {
1311 dev_err(vop->dev, "failed to get dclk source\n");
1312 return PTR_ERR(vop->dclk);
1315 ret = clk_prepare(vop->dclk);
1317 dev_err(vop->dev, "failed to prepare dclk\n");
1321 /* Enable both the hclk and aclk to setup the vop */
1322 ret = clk_prepare_enable(vop->hclk);
1324 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1325 goto err_unprepare_dclk;
1328 ret = clk_prepare_enable(vop->aclk);
1330 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1331 goto err_disable_hclk;
1335 * do hclk_reset, reset all vop registers.
1337 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1338 if (IS_ERR(ahb_rst)) {
1339 dev_err(vop->dev, "failed to get ahb reset\n");
1340 ret = PTR_ERR(ahb_rst);
1341 goto err_disable_aclk;
1343 reset_control_assert(ahb_rst);
1344 usleep_range(10, 20);
1345 reset_control_deassert(ahb_rst);
1347 memcpy(vop->regsbak, vop->regs, vop->len);
1349 for (i = 0; i < vop_data->table_size; i++)
1350 vop_writel(vop, init_table[i].offset, init_table[i].value);
1352 for (i = 0; i < vop->num_wins; i++) {
1353 struct vop_win *win = &vop->win[i];
1355 VOP_WIN_SET(vop, win, enable, 0);
1361 * do dclk_reset, let all config take affect.
1363 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1364 if (IS_ERR(vop->dclk_rst)) {
1365 dev_err(vop->dev, "failed to get dclk reset\n");
1366 ret = PTR_ERR(vop->dclk_rst);
1367 goto err_disable_aclk;
1369 reset_control_assert(vop->dclk_rst);
1370 usleep_range(10, 20);
1371 reset_control_deassert(vop->dclk_rst);
1373 clk_disable(vop->hclk);
1374 clk_disable(vop->aclk);
1376 vop->is_enabled = false;
1381 clk_disable_unprepare(vop->aclk);
1383 clk_disable_unprepare(vop->hclk);
1385 clk_unprepare(vop->dclk);
1390 * Initialize the vop->win array elements.
1392 static void vop_win_init(struct vop *vop)
1394 const struct vop_data *vop_data = vop->data;
1396 unsigned int num_wins = 0;
1398 for (i = 0; i < vop_data->win_size; i++) {
1399 struct vop_win *vop_win = &vop->win[num_wins];
1400 const struct vop_win_data *win_data = &vop_data->win[i];
1402 vop_win->phy = win_data->phy;
1403 vop_win->offset = win_data->base;
1404 vop_win->type = win_data->type;
1405 vop_win->data_formats = win_data->phy->data_formats;
1406 vop_win->nformats = win_data->phy->nformats;
1410 for (j = 0; j < win_data->area_size; j++) {
1411 struct vop_win *vop_area = &vop->win[num_wins];
1412 const struct vop_win_phy *area = win_data->area[j];
1414 vop_area->parent = vop_win;
1415 vop_area->offset = vop_win->offset;
1416 vop_area->phy = area;
1417 vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1418 vop_area->data_formats = vop_win->data_formats;
1419 vop_area->nformats = vop_win->nformats;
1420 vop_area->vop = vop;
1426 static int vop_bind(struct device *dev, struct device *master, void *data)
1428 struct platform_device *pdev = to_platform_device(dev);
1429 const struct vop_data *vop_data;
1430 struct drm_device *drm_dev = data;
1432 struct resource *res;
1437 vop_data = of_device_get_match_data(dev);
1441 for (i = 0; i < vop_data->win_size; i++) {
1442 const struct vop_win_data *win_data = &vop_data->win[i];
1444 num_wins += win_data->area_size + 1;
1447 /* Allocate vop struct and its vop_win array */
1448 alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1449 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1454 vop->data = vop_data;
1455 vop->drm_dev = drm_dev;
1456 vop->num_wins = num_wins;
1457 dev_set_drvdata(dev, vop);
1461 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1462 vop->len = resource_size(res);
1463 vop->regs = devm_ioremap_resource(dev, res);
1464 if (IS_ERR(vop->regs))
1465 return PTR_ERR(vop->regs);
1467 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1471 ret = vop_initial(vop);
1473 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1477 irq = platform_get_irq(pdev, 0);
1479 dev_err(dev, "cannot find irq for vop\n");
1482 vop->irq = (unsigned int)irq;
1484 spin_lock_init(&vop->reg_lock);
1485 spin_lock_init(&vop->irq_lock);
1487 mutex_init(&vop->vsync_mutex);
1489 ret = devm_request_irq(dev, vop->irq, vop_isr,
1490 IRQF_SHARED, dev_name(dev), vop);
1494 /* IRQ is initially disabled; it gets enabled in power_on */
1495 disable_irq(vop->irq);
1497 ret = vop_create_crtc(vop);
1501 pm_runtime_enable(&pdev->dev);
1505 static void vop_unbind(struct device *dev, struct device *master, void *data)
1507 struct vop *vop = dev_get_drvdata(dev);
1509 pm_runtime_disable(dev);
1510 vop_destroy_crtc(vop);
1513 const struct component_ops vop_component_ops = {
1515 .unbind = vop_unbind,
1517 EXPORT_SYMBOL_GPL(vop_component_ops);