drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34 #include <uapi/drm/rockchip_drm.h>
  35
  36 #include "rockchip_drm_drv.h"
  37 #include "rockchip_drm_gem.h"
  38 #include "rockchip_drm_fb.h"
  39 #include "rockchip_drm_vop.h"
  40
  41 #define VOP_REG_SUPPORT(vop, reg) \
  42                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  43                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  44                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  45                 reg.mask))
  46
  47 #define VOP_WIN_SUPPORT(vop, win, name) \
  48                 VOP_REG_SUPPORT(vop, win->phy->name)
  49
  50 #define VOP_CTRL_SUPPORT(vop, win, name) \
  51                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  52
  53 #define VOP_INTR_SUPPORT(vop, win, name) \
  54                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  55
  56 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  57                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  58
  59 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  60         do { \
  61                 if (VOP_REG_SUPPORT(vop, reg)) \
  62                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  63                                   v, reg.write_mask, relaxed); \
  64                 else \
  65                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  66         } while(0)
  67
  68 #define REG_SET(x, name, off, reg, v, relaxed) \
  69                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  70 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  71                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  72
  73 #define VOP_WIN_SET(x, win, name, v) \
  74                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  75 #define VOP_SCL_SET(x, win, name, v) \
  76                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  77 #define VOP_SCL_SET_EXT(x, win, name, v) \
  78                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  79
  80 #define VOP_CTRL_SET(x, name, v) \
  81                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  82
  83 #define VOP_INTR_GET(vop, name) \
  84                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  85
  86 #define VOP_INTR_SET(vop, name, mask, v) \
  87                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  88                              mask, v, false)
  89
  90 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  91         do { \
  92                 int i, reg = 0, mask = 0; \
  93                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  94                         if (vop->data->intr->intrs[i] & type) { \
  95                                 reg |= (v) << i; \
  96                                 mask |= 1 << i; \
  97                         } \
  98                 } \
  99                 VOP_INTR_SET(vop, name, mask, reg); \
 100         } while (0)
 101 #define VOP_INTR_GET_TYPE(vop, name, type) \
 102                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 103
 104 #define VOP_CTRL_GET(x, name) \
 105                 vop_read_reg(x, 0, vop->data->ctrl->name)
 106
 107 #define VOP_WIN_GET(x, win, name) \
 108                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 109
 110 #define VOP_WIN_NAME(win, name) \
 111                 (vop_get_win_phy(win, &win->phy->name)->name)
 112
 113 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 114                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 115
 116 #define to_vop(x) container_of(x, struct vop, crtc)
 117 #define to_vop_win(x) container_of(x, struct vop_win, base)
 118 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 119
 120 struct vop_zpos {
 121         int win_id;
 122         int zpos;
 123 };
 124
 125 struct vop_plane_state {
 126         struct drm_plane_state base;
 127         int format;
 128         int zpos;
 129         struct drm_rect src;
 130         struct drm_rect dest;
 131         dma_addr_t yrgb_mst;
 132         dma_addr_t uv_mst;
 133         bool enable;
 134 };
 135
 136 struct vop_win {
 137         struct vop_win *parent;
 138         struct drm_plane base;
 139
 140         int win_id;
 141         int area_id;
 142         uint32_t offset;
 143         enum drm_plane_type type;
 144         const struct vop_win_phy *phy;
 145         const uint32_t *data_formats;
 146         uint32_t nformats;
 147         struct vop *vop;
 148
 149         struct drm_property *rotation_prop;
 150         struct vop_plane_state state;
 151 };
 152
 153 struct vop {
 154         struct drm_crtc crtc;
 155         struct device *dev;
 156         struct drm_device *drm_dev;
 157         struct drm_property *plane_zpos_prop;
 158         struct drm_property *plane_feature_prop;
 159         bool is_iommu_enabled;
 160         bool is_iommu_needed;
 161         bool is_enabled;
 162
 163         /* mutex vsync_ work */
 164         struct mutex vsync_mutex;
 165         bool vsync_work_pending;
 166         struct completion dsp_hold_completion;
 167         struct completion wait_update_complete;
 168         struct drm_pending_vblank_event *event;
 169
 170         const struct vop_data *data;
 171         int num_wins;
 172
 173         uint32_t *regsbak;
 174         void __iomem *regs;
 175
 176         /* physical map length of vop register */
 177         uint32_t len;
 178
 179         /* one time only one process allowed to config the register */
 180         spinlock_t reg_lock;
 181         /* lock vop irq reg */
 182         spinlock_t irq_lock;
 183
 184         unsigned int irq;
 185
 186         /* vop AHP clk */
 187         struct clk *hclk;
 188         /* vop dclk */
 189         struct clk *dclk;
 190         /* vop share memory frequency */
 191         struct clk *aclk;
 192
 193         /* vop dclk reset */
 194         struct reset_control *dclk_rst;
 195
 196         struct vop_win win[];
 197 };
 198
 199 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 200 {
 201         writel(v, vop->regs + offset);
 202         vop->regsbak[offset >> 2] = v;
 203 }
 204
 205 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 206 {
 207         return readl(vop->regs + offset);
 208 }
 209
 210 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 211                                     const struct vop_reg *reg)
 212 {
 213         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 214 }
 215
 216 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 217                                   uint32_t mask, uint32_t shift, uint32_t v,
 218                                   bool write_mask, bool relaxed)
 219 {
 220         if (!mask)
 221                 return;
 222
 223         if (write_mask) {
 224                 v = ((v & mask) << shift) | (mask << (shift + 16));
 225         } else {
 226                 uint32_t cached_val = vop->regsbak[offset >> 2];
 227
 228                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 229                 vop->regsbak[offset >> 2] = v;
 230         }
 231
 232         if (relaxed)
 233                 writel_relaxed(v, vop->regs + offset);
 234         else
 235                 writel(v, vop->regs + offset);
 236 }
 237
 238 static inline const struct vop_win_phy *
 239 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 240 {
 241         if (!reg->mask && win->parent)
 242                 return win->parent->phy;
 243
 244         return win->phy;
 245 }
 246
 247 static inline uint32_t vop_get_intr_type(struct vop *vop,
 248                                          const struct vop_reg *reg, int type)
 249 {
 250         uint32_t i, ret = 0;
 251         uint32_t regs = vop_read_reg(vop, 0, reg);
 252
 253         for (i = 0; i < vop->data->intr->nintrs; i++) {
 254                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 255                         ret |= vop->data->intr->intrs[i];
 256         }
 257
 258         return ret;
 259 }
 260
 261 static inline void vop_cfg_done(struct vop *vop)
 262 {
 263         VOP_CTRL_SET(vop, cfg_done, 1);
 264 }
 265
 266 static bool vop_is_allwin_disabled(struct vop *vop)
 267 {
 268         int i;
 269
 270         for (i = 0; i < vop->num_wins; i++) {
 271                 struct vop_win *win = &vop->win[i];
 272
 273                 if (VOP_WIN_GET(vop, win, enable) != 0)
 274                         return false;
 275         }
 276
 277         return true;
 278 }
 279
 280 static bool vop_win_pending_is_complete(struct vop *vop)
 281 {
 282         dma_addr_t yrgb_mst;
 283         int i;
 284
 285         for (i = 0; i < vop->num_wins; i++) {
 286                 struct vop_win *win = &vop->win[i];
 287                 struct drm_plane *plane = &win->base;
 288                 struct vop_plane_state *state =
 289                                 to_vop_plane_state(plane->state);
 290                 if (!state->enable) {
 291                         if (VOP_WIN_GET(vop, win, enable) != 0)
 292                                 return false;
 293                         continue;
 294                 }
 295                 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop, win);
 296                 if (yrgb_mst != state->yrgb_mst)
 297                         return false;
 298         }
 299
 300         return true;
 301 }
 302
 303 static bool has_rb_swapped(uint32_t format)
 304 {
 305         switch (format) {
 306         case DRM_FORMAT_XBGR8888:
 307         case DRM_FORMAT_ABGR8888:
 308         case DRM_FORMAT_BGR888:
 309         case DRM_FORMAT_BGR565:
 310                 return true;
 311         default:
 312                 return false;
 313         }
 314 }
 315
 316 static enum vop_data_format vop_convert_format(uint32_t format)
 317 {
 318         switch (format) {
 319         case DRM_FORMAT_XRGB8888:
 320         case DRM_FORMAT_ARGB8888:
 321         case DRM_FORMAT_XBGR8888:
 322         case DRM_FORMAT_ABGR8888:
 323                 return VOP_FMT_ARGB8888;
 324         case DRM_FORMAT_RGB888:
 325         case DRM_FORMAT_BGR888:
 326                 return VOP_FMT_RGB888;
 327         case DRM_FORMAT_RGB565:
 328         case DRM_FORMAT_BGR565:
 329                 return VOP_FMT_RGB565;
 330         case DRM_FORMAT_NV12:
 331                 return VOP_FMT_YUV420SP;
 332         case DRM_FORMAT_NV16:
 333                 return VOP_FMT_YUV422SP;
 334         case DRM_FORMAT_NV24:
 335                 return VOP_FMT_YUV444SP;
 336         default:
 337                 DRM_ERROR("unsupport format[%08x]\n", format);
 338                 return -EINVAL;
 339         }
 340 }
 341
 342 static bool is_yuv_support(uint32_t format)
 343 {
 344         switch (format) {
 345         case DRM_FORMAT_NV12:
 346         case DRM_FORMAT_NV16:
 347         case DRM_FORMAT_NV24:
 348                 return true;
 349         default:
 350                 return false;
 351         }
 352 }
 353
 354 static bool is_alpha_support(uint32_t format)
 355 {
 356         switch (format) {
 357         case DRM_FORMAT_ARGB8888:
 358         case DRM_FORMAT_ABGR8888:
 359                 return true;
 360         default:
 361                 return false;
 362         }
 363 }
 364
 365 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 366                                   uint32_t dst, bool is_horizontal,
 367                                   int vsu_mode, int *vskiplines)
 368 {
 369         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 370
 371         if (is_horizontal) {
 372                 if (mode == SCALE_UP)
 373                         val = GET_SCL_FT_BIC(src, dst);
 374                 else if (mode == SCALE_DOWN)
 375                         val = GET_SCL_FT_BILI_DN(src, dst);
 376         } else {
 377                 if (mode == SCALE_UP) {
 378                         if (vsu_mode == SCALE_UP_BIL)
 379                                 val = GET_SCL_FT_BILI_UP(src, dst);
 380                         else
 381                                 val = GET_SCL_FT_BIC(src, dst);
 382                 } else if (mode == SCALE_DOWN) {
 383                         if (vskiplines) {
 384                                 *vskiplines = scl_get_vskiplines(src, dst);
 385                                 val = scl_get_bili_dn_vskip(src, dst,
 386                                                             *vskiplines);
 387                         } else {
 388                                 val = GET_SCL_FT_BILI_DN(src, dst);
 389                         }
 390                 }
 391         }
 392
 393         return val;
 394 }
 395
 396 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 397                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 398                                 uint32_t dst_h, uint32_t pixel_format)
 399 {
 400         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 401         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 402         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 403         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 404         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 405         bool is_yuv = is_yuv_support(pixel_format);
 406         uint16_t cbcr_src_w = src_w / hsub;
 407         uint16_t cbcr_src_h = src_h / vsub;
 408         uint16_t vsu_mode;
 409         uint16_t lb_mode;
 410         uint32_t val;
 411         int vskiplines = 0;
 412
 413         if (!win->phy->scl)
 414                 return;
 415
 416         if (dst_w > 3840) {
 417                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 418                 return;
 419         }
 420
 421         if (!win->phy->scl->ext) {
 422                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 423                             scl_cal_scale2(src_w, dst_w));
 424                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 425                             scl_cal_scale2(src_h, dst_h));
 426                 if (is_yuv) {
 427                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 428                                     scl_cal_scale2(cbcr_src_w, dst_w));
 429                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 430                                     scl_cal_scale2(cbcr_src_h, dst_h));
 431                 }
 432                 return;
 433         }
 434
 435         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 436         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 437
 438         if (is_yuv) {
 439                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 440                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 441                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 442                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 443                 else
 444                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 445         } else {
 446                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 447                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 448                 else
 449                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 450         }
 451
 452         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 453         if (lb_mode == LB_RGB_3840X2) {
 454                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 455                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 456                         return;
 457                 }
 458                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 459                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 460                         return;
 461                 }
 462                 vsu_mode = SCALE_UP_BIL;
 463         } else if (lb_mode == LB_RGB_2560X4) {
 464                 vsu_mode = SCALE_UP_BIL;
 465         } else {
 466                 vsu_mode = SCALE_UP_BIC;
 467         }
 468
 469         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 470                                 true, 0, NULL);
 471         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 472         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 473                                 false, vsu_mode, &vskiplines);
 474         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 475
 476         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 477         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 478
 479         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 480         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 481         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 482         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 483         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 484         if (is_yuv) {
 485                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 486                                         dst_w, true, 0, NULL);
 487                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 488                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 489                                         dst_h, false, vsu_mode, &vskiplines);
 490                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 491
 492                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 493                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 494                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 495                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 496                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 497                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 498                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 499         }
 500 }
 501
 502 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 503 {
 504         unsigned long flags;
 505
 506         spin_lock_irqsave(&vop->irq_lock, flags);
 507
 508         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 509
 510         spin_unlock_irqrestore(&vop->irq_lock, flags);
 511 }
 512
 513 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 514 {
 515         unsigned long flags;
 516
 517         spin_lock_irqsave(&vop->irq_lock, flags);
 518
 519         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 520
 521         spin_unlock_irqrestore(&vop->irq_lock, flags);
 522 }
 523
 524 static void vop_enable(struct drm_crtc *crtc)
 525 {
 526         struct vop *vop = to_vop(crtc);
 527         int ret, i;
 528
 529         ret = clk_prepare_enable(vop->hclk);
 530         if (ret < 0) {
 531                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 532                 return;
 533         }
 534
 535         ret = clk_prepare_enable(vop->dclk);
 536         if (ret < 0) {
 537                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 538                 goto err_disable_hclk;
 539         }
 540
 541         ret = clk_prepare_enable(vop->aclk);
 542         if (ret < 0) {
 543                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 544                 goto err_disable_dclk;
 545         }
 546
 547         ret = pm_runtime_get_sync(vop->dev);
 548         if (ret < 0) {
 549                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 550                 return;
 551         }
 552
 553         memcpy(vop->regsbak, vop->regs, vop->len);
 554
 555         VOP_CTRL_SET(vop, global_regdone_en, 1);
 556
 557         for (i = 0; i < vop->num_wins; i++) {
 558                 struct vop_win *win = &vop->win[i];
 559
 560                 VOP_WIN_SET(vop, win, gate, 1);
 561         }
 562         vop->is_enabled = true;
 563
 564         spin_lock(&vop->reg_lock);
 565
 566         VOP_CTRL_SET(vop, standby, 0);
 567
 568         spin_unlock(&vop->reg_lock);
 569
 570         enable_irq(vop->irq);
 571
 572         drm_crtc_vblank_on(crtc);
 573
 574         return;
 575
 576 err_disable_dclk:
 577         clk_disable_unprepare(vop->dclk);
 578 err_disable_hclk:
 579         clk_disable_unprepare(vop->hclk);
 580 }
 581
 582 static void vop_crtc_disable(struct drm_crtc *crtc)
 583 {
 584         struct vop *vop = to_vop(crtc);
 585         int i;
 586
 587         /*
 588          * We need to make sure that all windows are disabled before we
 589          * disable that crtc. Otherwise we might try to scan from a destroyed
 590          * buffer later.
 591          */
 592         for (i = 0; i < vop->num_wins; i++) {
 593                 struct vop_win *win = &vop->win[i];
 594
 595                 spin_lock(&vop->reg_lock);
 596                 VOP_WIN_SET(vop, win, enable, 0);
 597                 spin_unlock(&vop->reg_lock);
 598         }
 599         vop_cfg_done(vop);
 600
 601         drm_crtc_vblank_off(crtc);
 602
 603         /*
 604          * Vop standby will take effect at end of current frame,
 605          * if dsp hold valid irq happen, it means standby complete.
 606          *
 607          * we must wait standby complete when we want to disable aclk,
 608          * if not, memory bus maybe dead.
 609          */
 610         reinit_completion(&vop->dsp_hold_completion);
 611         vop_dsp_hold_valid_irq_enable(vop);
 612
 613         spin_lock(&vop->reg_lock);
 614
 615         VOP_CTRL_SET(vop, standby, 1);
 616
 617         spin_unlock(&vop->reg_lock);
 618
 619         wait_for_completion(&vop->dsp_hold_completion);
 620
 621         vop_dsp_hold_valid_irq_disable(vop);
 622
 623         disable_irq(vop->irq);
 624
 625         vop->is_enabled = false;
 626         if (vop->is_iommu_enabled) {
 627                 /*
 628                  * vop standby complete, so iommu detach is safe.
 629                  */
 630                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 631                 vop->is_iommu_enabled = false;
 632         }
 633
 634         pm_runtime_put(vop->dev);
 635         clk_disable_unprepare(vop->dclk);
 636         clk_disable_unprepare(vop->aclk);
 637         clk_disable_unprepare(vop->hclk);
 638 }
 639
 640 static void vop_plane_destroy(struct drm_plane *plane)
 641 {
 642         drm_plane_cleanup(plane);
 643 }
 644
 645 static int vop_plane_prepare_fb(struct drm_plane *plane,
 646                                 const struct drm_plane_state *new_state)
 647 {
 648         if (plane->state->fb)
 649                 drm_framebuffer_reference(plane->state->fb);
 650
 651         return 0;
 652 }
 653
 654 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 655                                  const struct drm_plane_state *old_state)
 656 {
 657         if (old_state->fb)
 658                 drm_framebuffer_unreference(old_state->fb);
 659 }
 660
 661 static int vop_plane_atomic_check(struct drm_plane *plane,
 662                            struct drm_plane_state *state)
 663 {
 664         struct drm_crtc *crtc = state->crtc;
 665         struct drm_framebuffer *fb = state->fb;
 666         struct vop_win *win = to_vop_win(plane);
 667         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 668         struct drm_crtc_state *crtc_state;
 669         bool visible;
 670         int ret;
 671         struct drm_rect *dest = &vop_plane_state->dest;
 672         struct drm_rect *src = &vop_plane_state->src;
 673         struct drm_rect clip;
 674         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 675                                         DRM_PLANE_HELPER_NO_SCALING;
 676         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 677                                         DRM_PLANE_HELPER_NO_SCALING;
 678         unsigned long offset;
 679         dma_addr_t dma_addr;
 680
 681         crtc = crtc ? crtc : plane->state->crtc;
 682         /*
 683          * Both crtc or plane->state->crtc can be null.
 684          */
 685         if (!crtc || !fb)
 686                 goto out_disable;
 687
 688         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 689         if (IS_ERR(crtc_state))
 690                 return PTR_ERR(crtc_state);
 691
 692         src->x1 = state->src_x;
 693         src->y1 = state->src_y;
 694         src->x2 = state->src_x + state->src_w;
 695         src->y2 = state->src_y + state->src_h;
 696         dest->x1 = state->crtc_x;
 697         dest->y1 = state->crtc_y;
 698         dest->x2 = state->crtc_x + state->crtc_w;
 699         dest->y2 = state->crtc_y + state->crtc_h;
 700
 701         clip.x1 = 0;
 702         clip.y1 = 0;
 703         clip.x2 = crtc_state->mode.hdisplay;
 704         clip.y2 = crtc_state->mode.vdisplay;
 705
 706         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 707                                             src, dest, &clip,
 708                                             min_scale,
 709                                             max_scale,
 710                                             true, true, &visible);
 711         if (ret)
 712                 return ret;
 713
 714         if (!visible)
 715                 goto out_disable;
 716
 717         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 718         if (vop_plane_state->format < 0)
 719                 return vop_plane_state->format;
 720
 721         /*
 722          * Src.x1 can be odd when do clip, but yuv plane start point
 723          * need align with 2 pixel.
 724          */
 725         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 726                 return -EINVAL;
 727
 728         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 729         if (state->rotation & BIT(DRM_REFLECT_Y))
 730                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 731         else
 732                 offset += (src->y1 >> 16) * fb->pitches[0];
 733
 734         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
 735         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
 736         if (is_yuv_support(fb->pixel_format)) {
 737                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 738                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 739                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 740
 741                 offset = (src->x1 >> 16) * bpp / hsub;
 742                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 743
 744                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
 745                 dma_addr += offset + fb->offsets[1];
 746                 vop_plane_state->uv_mst = dma_addr;
 747         }
 748
 749         vop_plane_state->enable = true;
 750
 751         return 0;
 752
 753 out_disable:
 754         vop_plane_state->enable = false;
 755         return 0;
 756 }
 757
 758 static void vop_plane_atomic_disable(struct drm_plane *plane,
 759                                      struct drm_plane_state *old_state)
 760 {
 761         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 762         struct vop_win *win = to_vop_win(plane);
 763         struct vop *vop = to_vop(old_state->crtc);
 764
 765         if (!old_state->crtc)
 766                 return;
 767
 768         spin_lock(&vop->reg_lock);
 769
 770         VOP_WIN_SET(vop, win, enable, 0);
 771
 772         spin_unlock(&vop->reg_lock);
 773
 774         vop_plane_state->enable = false;
 775 }
 776
 777 static void vop_plane_atomic_update(struct drm_plane *plane,
 778                 struct drm_plane_state *old_state)
 779 {
 780         struct drm_plane_state *state = plane->state;
 781         struct drm_crtc *crtc = state->crtc;
 782         struct vop_win *win = to_vop_win(plane);
 783         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 784         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 785         struct vop *vop = to_vop(state->crtc);
 786         struct drm_framebuffer *fb = state->fb;
 787         unsigned int actual_w, actual_h;
 788         unsigned int dsp_stx, dsp_sty;
 789         uint32_t act_info, dsp_info, dsp_st;
 790         struct drm_rect *src = &vop_plane_state->src;
 791         struct drm_rect *dest = &vop_plane_state->dest;
 792         int ymirror, xmirror;
 793         uint32_t val;
 794         bool rb_swap;
 795
 796         /*
 797          * can't update plane when vop is disabled.
 798          */
 799         if (!crtc)
 800                 return;
 801
 802         if (!vop_plane_state->enable) {
 803                 vop_plane_atomic_disable(plane, old_state);
 804                 return;
 805         }
 806
 807         actual_w = drm_rect_width(src) >> 16;
 808         actual_h = drm_rect_height(src) >> 16;
 809         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 810
 811         dsp_info = (drm_rect_height(dest) - 1) << 16;
 812         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 813
 814         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 815         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 816         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 817
 818         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
 819         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
 820
 821         spin_lock(&vop->reg_lock);
 822
 823         VOP_WIN_SET(vop, win, xmirror, xmirror);
 824         VOP_WIN_SET(vop, win, ymirror, ymirror);
 825         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 826         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 827         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 828         if (is_yuv_support(fb->pixel_format)) {
 829                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 830                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
 831         }
 832
 833         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 834                             drm_rect_width(dest), drm_rect_height(dest),
 835                             fb->pixel_format);
 836
 837         VOP_WIN_SET(vop, win, act_info, act_info);
 838         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 839         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 840
 841         rb_swap = has_rb_swapped(fb->pixel_format);
 842         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 843
 844         if (is_alpha_support(fb->pixel_format) &&
 845             (s->dsp_layer_sel & 0x3) != win->win_id) {
 846                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 847                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 848                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 849                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 850                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 851                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 852                         SRC_FACTOR_M0(ALPHA_ONE);
 853                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 854                 VOP_WIN_SET(vop, win, alpha_mode, 1);
 855                 VOP_WIN_SET(vop, win, alpha_en, 1);
 856         } else {
 857                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 858                 VOP_WIN_SET(vop, win, alpha_en, 0);
 859         }
 860
 861         VOP_WIN_SET(vop, win, enable, 1);
 862         spin_unlock(&vop->reg_lock);
 863         vop->is_iommu_needed = true;
 864 }
 865
 866 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 867         .prepare_fb = vop_plane_prepare_fb,
 868         .cleanup_fb = vop_plane_cleanup_fb,
 869         .atomic_check = vop_plane_atomic_check,
 870         .atomic_update = vop_plane_atomic_update,
 871         .atomic_disable = vop_plane_atomic_disable,
 872 };
 873
 874 void vop_atomic_plane_reset(struct drm_plane *plane)
 875 {
 876         struct vop_win *win = to_vop_win(plane);
 877         struct vop_plane_state *vop_plane_state =
 878                                         to_vop_plane_state(plane->state);
 879
 880         if (plane->state && plane->state->fb)
 881                 drm_framebuffer_unreference(plane->state->fb);
 882
 883         kfree(vop_plane_state);
 884         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 885         if (!vop_plane_state)
 886                 return;
 887
 888         vop_plane_state->zpos = win->win_id;
 889         plane->state = &vop_plane_state->base;
 890         plane->state->plane = plane;
 891 }
 892
 893 struct drm_plane_state *
 894 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 895 {
 896         struct vop_plane_state *old_vop_plane_state;
 897         struct vop_plane_state *vop_plane_state;
 898
 899         if (WARN_ON(!plane->state))
 900                 return NULL;
 901
 902         old_vop_plane_state = to_vop_plane_state(plane->state);
 903         vop_plane_state = kmemdup(old_vop_plane_state,
 904                                   sizeof(*vop_plane_state), GFP_KERNEL);
 905         if (!vop_plane_state)
 906                 return NULL;
 907
 908         __drm_atomic_helper_plane_duplicate_state(plane,
 909                                                   &vop_plane_state->base);
 910
 911         return &vop_plane_state->base;
 912 }
 913
 914 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 915                                            struct drm_plane_state *state)
 916 {
 917         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 918
 919         __drm_atomic_helper_plane_destroy_state(plane, state);
 920
 921         kfree(vop_state);
 922 }
 923
 924 static int vop_atomic_plane_set_property(struct drm_plane *plane,
 925                                          struct drm_plane_state *state,
 926                                          struct drm_property *property,
 927                                          uint64_t val)
 928 {
 929         struct vop_win *win = to_vop_win(plane);
 930         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 931
 932         if (property == win->vop->plane_zpos_prop) {
 933                 plane_state->zpos = val;
 934                 return 0;
 935         }
 936
 937         if (property == win->rotation_prop) {
 938                 state->rotation = val;
 939                 return 0;
 940         }
 941
 942         DRM_ERROR("failed to set vop plane property\n");
 943         return -EINVAL;
 944 }
 945
 946 static int vop_atomic_plane_get_property(struct drm_plane *plane,
 947                                          const struct drm_plane_state *state,
 948                                          struct drm_property *property,
 949                                          uint64_t *val)
 950 {
 951         struct vop_win *win = to_vop_win(plane);
 952         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 953
 954         if (property == win->vop->plane_zpos_prop) {
 955                 *val = plane_state->zpos;
 956                 return 0;
 957         }
 958
 959         if (property == win->rotation_prop) {
 960                 *val = state->rotation;
 961                 return 0;
 962         }
 963
 964         DRM_ERROR("failed to get vop plane property\n");
 965         return -EINVAL;
 966 }
 967
 968 static const struct drm_plane_funcs vop_plane_funcs = {
 969         .update_plane   = drm_atomic_helper_update_plane,
 970         .disable_plane  = drm_atomic_helper_disable_plane,
 971         .destroy = vop_plane_destroy,
 972         .reset = vop_atomic_plane_reset,
 973         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
 974         .atomic_destroy_state = vop_atomic_plane_destroy_state,
 975         .atomic_set_property = vop_atomic_plane_set_property,
 976         .atomic_get_property = vop_atomic_plane_get_property,
 977 };
 978
 979 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 980 {
 981         struct vop *vop = to_vop(crtc);
 982         unsigned long flags;
 983
 984         if (!vop->is_enabled)
 985                 return -EPERM;
 986
 987         spin_lock_irqsave(&vop->irq_lock, flags);
 988
 989         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 990
 991         spin_unlock_irqrestore(&vop->irq_lock, flags);
 992
 993         return 0;
 994 }
 995
 996 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 997 {
 998         struct vop *vop = to_vop(crtc);
 999         unsigned long flags;
1000
1001         if (!vop->is_enabled)
1002                 return;
1003
1004         spin_lock_irqsave(&vop->irq_lock, flags);
1005
1006         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1007
1008         spin_unlock_irqrestore(&vop->irq_lock, flags);
1009 }
1010
1011 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1012 {
1013         struct vop *vop = to_vop(crtc);
1014
1015         reinit_completion(&vop->wait_update_complete);
1016         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1017 }
1018
1019 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1020                                            struct drm_file *file_priv)
1021 {
1022         struct drm_device *drm = crtc->dev;
1023         struct vop *vop = to_vop(crtc);
1024         struct drm_pending_vblank_event *e;
1025         unsigned long flags;
1026
1027         spin_lock_irqsave(&drm->event_lock, flags);
1028         e = vop->event;
1029         if (e && e->base.file_priv == file_priv) {
1030                 vop->event = NULL;
1031
1032                 e->base.destroy(&e->base);
1033                 file_priv->event_space += sizeof(e->event);
1034         }
1035         spin_unlock_irqrestore(&drm->event_lock, flags);
1036 }
1037
1038 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1039         .enable_vblank = vop_crtc_enable_vblank,
1040         .disable_vblank = vop_crtc_disable_vblank,
1041         .wait_for_update = vop_crtc_wait_for_update,
1042         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1043 };
1044
1045 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1046                                 const struct drm_display_mode *mode,
1047                                 struct drm_display_mode *adjusted_mode)
1048 {
1049         struct vop *vop = to_vop(crtc);
1050
1051         adjusted_mode->clock =
1052                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1053
1054         return true;
1055 }
1056
1057 static void vop_crtc_enable(struct drm_crtc *crtc)
1058 {
1059         struct vop *vop = to_vop(crtc);
1060         const struct vop_data *vop_data = vop->data;
1061         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1062         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1063         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1064         u16 hdisplay = adjusted_mode->hdisplay;
1065         u16 htotal = adjusted_mode->htotal;
1066         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1067         u16 hact_end = hact_st + hdisplay;
1068         u16 vdisplay = adjusted_mode->vdisplay;
1069         u16 vtotal = adjusted_mode->vtotal;
1070         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1071         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1072         u16 vact_end = vact_st + vdisplay;
1073         uint32_t val;
1074
1075         vop_enable(crtc);
1076         /*
1077          * If dclk rate is zero, mean that scanout is stop,
1078          * we don't need wait any more.
1079          */
1080         if (clk_get_rate(vop->dclk)) {
1081                 /*
1082                  * Rk3288 vop timing register is immediately, when configure
1083                  * display timing on display time, may cause tearing.
1084                  *
1085                  * Vop standby will take effect at end of current frame,
1086                  * if dsp hold valid irq happen, it means standby complete.
1087                  *
1088                  * mode set:
1089                  *    standby and wait complete --> |----
1090                  *                                  | display time
1091                  *                                  |----
1092                  *                                  |---> dsp hold irq
1093                  *     configure display timing --> |
1094                  *         standby exit             |
1095                  *                                  | new frame start.
1096                  */
1097
1098                 reinit_completion(&vop->dsp_hold_completion);
1099                 vop_dsp_hold_valid_irq_enable(vop);
1100
1101                 spin_lock(&vop->reg_lock);
1102
1103                 VOP_CTRL_SET(vop, standby, 1);
1104
1105                 spin_unlock(&vop->reg_lock);
1106
1107                 wait_for_completion(&vop->dsp_hold_completion);
1108
1109                 vop_dsp_hold_valid_irq_disable(vop);
1110         }
1111
1112         val = 0x8;
1113         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1114         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1115         VOP_CTRL_SET(vop, pin_pol, val);
1116         switch (s->output_type) {
1117         case DRM_MODE_CONNECTOR_LVDS:
1118                 VOP_CTRL_SET(vop, rgb_en, 1);
1119                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1120                 break;
1121         case DRM_MODE_CONNECTOR_eDP:
1122                 VOP_CTRL_SET(vop, edp_en, 1);
1123                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1124                 break;
1125         case DRM_MODE_CONNECTOR_HDMIA:
1126                 VOP_CTRL_SET(vop, hdmi_en, 1);
1127                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1128                 break;
1129         case DRM_MODE_CONNECTOR_DSI:
1130                 VOP_CTRL_SET(vop, mipi_en, 1);
1131                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1132                 break;
1133         default:
1134                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1135         }
1136
1137         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1138             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1139                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1140
1141         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1142
1143         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1144         val = hact_st << 16;
1145         val |= hact_end;
1146         VOP_CTRL_SET(vop, hact_st_end, val);
1147         VOP_CTRL_SET(vop, hpost_st_end, val);
1148
1149         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1150         val = vact_st << 16;
1151         val |= vact_end;
1152         VOP_CTRL_SET(vop, vact_st_end, val);
1153         VOP_CTRL_SET(vop, vpost_st_end, val);
1154
1155         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1156
1157         VOP_CTRL_SET(vop, standby, 0);
1158 }
1159
1160 static int vop_zpos_cmp(const void *a, const void *b)
1161 {
1162         struct vop_zpos *pa = (struct vop_zpos *)a;
1163         struct vop_zpos *pb = (struct vop_zpos *)b;
1164
1165         return pa->zpos - pb->zpos;
1166 }
1167
1168 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1169                                  struct drm_crtc_state *crtc_state)
1170 {
1171         struct drm_atomic_state *state = crtc_state->state;
1172         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1173         struct vop *vop = to_vop(crtc);
1174         const struct vop_data *vop_data = vop->data;
1175         struct drm_plane *plane;
1176         struct drm_plane_state *pstate;
1177         struct vop_plane_state *plane_state;
1178         struct vop_zpos *pzpos;
1179         int dsp_layer_sel = 0;
1180         int i, j, cnt = 0, ret = 0;
1181
1182         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1183         if (!pzpos)
1184                 return -ENOMEM;
1185
1186         for (i = 0; i < vop_data->win_size; i++) {
1187                 const struct vop_win_data *win_data = &vop_data->win[i];
1188                 struct vop_win *win;
1189
1190                 if (!win_data->phy)
1191                         continue;
1192
1193                 for (j = 0; j < vop->num_wins; j++) {
1194                         win = &vop->win[j];
1195
1196                         if (win->win_id == i && !win->area_id)
1197                                 break;
1198                 }
1199                 if (WARN_ON(j >= vop->num_wins)) {
1200                         ret = -EINVAL;
1201                         goto err_free_pzpos;
1202                 }
1203
1204                 plane = &win->base;
1205                 pstate = state->plane_states[drm_plane_index(plane)];
1206                 /*
1207                  * plane might not have changed, in which case take
1208                  * current state:
1209                  */
1210                 if (!pstate)
1211                         pstate = plane->state;
1212                 plane_state = to_vop_plane_state(pstate);
1213                 pzpos[cnt].zpos = plane_state->zpos;
1214                 pzpos[cnt++].win_id = win->win_id;
1215         }
1216
1217         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1218
1219         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1220                 const struct vop_win_data *win_data = &vop_data->win[i];
1221                 int shift = i * 2;
1222
1223                 if (win_data->phy) {
1224                         struct vop_zpos *zpos = &pzpos[cnt++];
1225
1226                         dsp_layer_sel |= zpos->win_id << shift;
1227                 } else {
1228                         dsp_layer_sel |= i << shift;
1229                 }
1230         }
1231
1232         s->dsp_layer_sel = dsp_layer_sel;
1233
1234 err_free_pzpos:
1235         kfree(pzpos);
1236         return ret;
1237 }
1238
1239 static void vop_cfg_update(struct drm_crtc *crtc,
1240                            struct drm_crtc_state *old_crtc_state)
1241 {
1242         struct rockchip_crtc_state *s =
1243                         to_rockchip_crtc_state(crtc->state);
1244         struct vop *vop = to_vop(crtc);
1245
1246         spin_lock(&vop->reg_lock);
1247
1248         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1249         vop_cfg_done(vop);
1250
1251         spin_unlock(&vop->reg_lock);
1252 }
1253
1254 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1255                                   struct drm_crtc_state *old_crtc_state)
1256 {
1257         struct vop *vop = to_vop(crtc);
1258
1259         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1260                 int ret;
1261                 if (!vop_is_allwin_disabled(vop)) {
1262                         vop_cfg_update(crtc, old_crtc_state);
1263                         while(!vop_win_pending_is_complete(vop));
1264                 }
1265                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1266                 if (ret) {
1267                         dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
1268                 }
1269                 vop->is_iommu_enabled = true;
1270         }
1271
1272         vop_cfg_update(crtc, old_crtc_state);
1273 }
1274
1275 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1276                                   struct drm_crtc_state *old_crtc_state)
1277 {
1278         struct vop *vop = to_vop(crtc);
1279
1280         if (crtc->state->event) {
1281                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1282
1283                 vop->event = crtc->state->event;
1284                 crtc->state->event = NULL;
1285         }
1286 }
1287
1288 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1289         .enable = vop_crtc_enable,
1290         .disable = vop_crtc_disable,
1291         .mode_fixup = vop_crtc_mode_fixup,
1292         .atomic_check = vop_crtc_atomic_check,
1293         .atomic_flush = vop_crtc_atomic_flush,
1294         .atomic_begin = vop_crtc_atomic_begin,
1295 };
1296
1297 static void vop_crtc_destroy(struct drm_crtc *crtc)
1298 {
1299         drm_crtc_cleanup(crtc);
1300 }
1301
1302 static void vop_crtc_reset(struct drm_crtc *crtc)
1303 {
1304         if (crtc->state)
1305                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1306         kfree(crtc->state);
1307
1308         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1309         if (crtc->state)
1310                 crtc->state->crtc = crtc;
1311 }
1312
1313 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1314 {
1315         struct rockchip_crtc_state *rockchip_state;
1316
1317         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1318         if (!rockchip_state)
1319                 return NULL;
1320
1321         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1322         return &rockchip_state->base;
1323 }
1324
1325 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1326                                    struct drm_crtc_state *state)
1327 {
1328         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1329
1330         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1331         kfree(s);
1332 }
1333
1334 static const struct drm_crtc_funcs vop_crtc_funcs = {
1335         .set_config = drm_atomic_helper_set_config,
1336         .page_flip = drm_atomic_helper_page_flip,
1337         .destroy = vop_crtc_destroy,
1338         .reset = vop_crtc_reset,
1339         .atomic_duplicate_state = vop_crtc_duplicate_state,
1340         .atomic_destroy_state = vop_crtc_destroy_state,
1341 };
1342
1343 static void vop_handle_vblank(struct vop *vop)
1344 {
1345         struct drm_device *drm = vop->drm_dev;
1346         struct drm_crtc *crtc = &vop->crtc;
1347         unsigned long flags;
1348
1349         if (!vop_win_pending_is_complete(vop))
1350                 return;
1351
1352         if (vop->event) {
1353                 spin_lock_irqsave(&drm->event_lock, flags);
1354
1355                 drm_crtc_send_vblank_event(crtc, vop->event);
1356                 drm_crtc_vblank_put(crtc);
1357                 vop->event = NULL;
1358
1359                 spin_unlock_irqrestore(&drm->event_lock, flags);
1360         }
1361         if (!completion_done(&vop->wait_update_complete))
1362                 complete(&vop->wait_update_complete);
1363 }
1364
1365 static irqreturn_t vop_isr(int irq, void *data)
1366 {
1367         struct vop *vop = data;
1368         struct drm_crtc *crtc = &vop->crtc;
1369         uint32_t active_irqs;
1370         unsigned long flags;
1371         int ret = IRQ_NONE;
1372
1373         /*
1374          * interrupt register has interrupt status, enable and clear bits, we
1375          * must hold irq_lock to avoid a race with enable/disable_vblank().
1376         */
1377         spin_lock_irqsave(&vop->irq_lock, flags);
1378
1379         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1380         /* Clear all active interrupt sources */
1381         if (active_irqs)
1382                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1383
1384         spin_unlock_irqrestore(&vop->irq_lock, flags);
1385
1386         /* This is expected for vop iommu irqs, since the irq is shared */
1387         if (!active_irqs)
1388                 return IRQ_NONE;
1389
1390         if (active_irqs & DSP_HOLD_VALID_INTR) {
1391                 complete(&vop->dsp_hold_completion);
1392                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1393                 ret = IRQ_HANDLED;
1394         }
1395
1396         if (active_irqs & FS_INTR) {
1397                 drm_crtc_handle_vblank(crtc);
1398                 vop_handle_vblank(vop);
1399                 active_irqs &= ~FS_INTR;
1400                 ret = IRQ_HANDLED;
1401         }
1402
1403         /* Unhandled irqs are spurious. */
1404         if (active_irqs)
1405                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1406
1407         return ret;
1408 }
1409
1410 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1411                           unsigned long possible_crtcs)
1412 {
1413         struct drm_plane *share = NULL;
1414         unsigned int rotations = 0;
1415         struct drm_property *prop;
1416         uint64_t feature = 0;
1417         int ret;
1418
1419         if (win->parent)
1420                 share = &win->parent->base;
1421
1422         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1423                                    possible_crtcs, &vop_plane_funcs,
1424                                    win->data_formats, win->nformats, win->type);
1425         if (ret) {
1426                 DRM_ERROR("failed to initialize plane\n");
1427                 return ret;
1428         }
1429         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1430         drm_object_attach_property(&win->base.base,
1431                                    vop->plane_zpos_prop, win->win_id);
1432
1433         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1434                 rotations |= BIT(DRM_REFLECT_X);
1435
1436         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1437                 rotations |= BIT(DRM_REFLECT_Y);
1438
1439         if (rotations) {
1440                 rotations |= BIT(DRM_ROTATE_0);
1441                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1442                                                          rotations);
1443                 if (!prop) {
1444                         DRM_ERROR("failed to create zpos property\n");
1445                         return -EINVAL;
1446                 }
1447                 drm_object_attach_property(&win->base.base, prop,
1448                                            BIT(DRM_ROTATE_0));
1449                 win->rotation_prop = prop;
1450         }
1451         if (win->phy->scl)
1452                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
1453         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
1454             VOP_WIN_SUPPORT(vop, win, alpha_en))
1455                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
1456
1457         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
1458                                    feature);
1459
1460         return 0;
1461 }
1462
1463 static int vop_create_crtc(struct vop *vop)
1464 {
1465         struct device *dev = vop->dev;
1466         struct drm_device *drm_dev = vop->drm_dev;
1467         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1468         struct drm_crtc *crtc = &vop->crtc;
1469         struct device_node *port;
1470         int ret;
1471         int i;
1472
1473         /*
1474          * Create drm_plane for primary and cursor planes first, since we need
1475          * to pass them to drm_crtc_init_with_planes, which sets the
1476          * "possible_crtcs" to the newly initialized crtc.
1477          */
1478         for (i = 0; i < vop->num_wins; i++) {
1479                 struct vop_win *win = &vop->win[i];
1480
1481                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1482                     win->type != DRM_PLANE_TYPE_CURSOR)
1483                         continue;
1484
1485                 ret = vop_plane_init(vop, win, 0);
1486                 if (ret)
1487                         goto err_cleanup_planes;
1488
1489                 plane = &win->base;
1490                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1491                         primary = plane;
1492                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1493                         cursor = plane;
1494
1495         }
1496
1497         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1498                                         &vop_crtc_funcs, NULL);
1499         if (ret)
1500                 goto err_cleanup_planes;
1501
1502         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1503
1504         /*
1505          * Create drm_planes for overlay windows with possible_crtcs restricted
1506          * to the newly created crtc.
1507          */
1508         for (i = 0; i < vop->num_wins; i++) {
1509                 struct vop_win *win = &vop->win[i];
1510                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1511
1512                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1513                         continue;
1514
1515                 ret = vop_plane_init(vop, win, possible_crtcs);
1516                 if (ret)
1517                         goto err_cleanup_crtc;
1518         }
1519
1520         port = of_get_child_by_name(dev->of_node, "port");
1521         if (!port) {
1522                 DRM_ERROR("no port node found in %s\n",
1523                           dev->of_node->full_name);
1524                 ret = -ENOENT;
1525                 goto err_cleanup_crtc;
1526         }
1527
1528         init_completion(&vop->dsp_hold_completion);
1529         init_completion(&vop->wait_update_complete);
1530         crtc->port = port;
1531         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1532
1533         return 0;
1534
1535 err_cleanup_crtc:
1536         drm_crtc_cleanup(crtc);
1537 err_cleanup_planes:
1538         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1539                                  head)
1540                 drm_plane_cleanup(plane);
1541         return ret;
1542 }
1543
1544 static void vop_destroy_crtc(struct vop *vop)
1545 {
1546         struct drm_crtc *crtc = &vop->crtc;
1547         struct drm_device *drm_dev = vop->drm_dev;
1548         struct drm_plane *plane, *tmp;
1549
1550         rockchip_unregister_crtc_funcs(crtc);
1551         of_node_put(crtc->port);
1552
1553         /*
1554          * We need to cleanup the planes now.  Why?
1555          *
1556          * The planes are "&vop->win[i].base".  That means the memory is
1557          * all part of the big "struct vop" chunk of memory.  That memory
1558          * was devm allocated and associated with this component.  We need to
1559          * free it ourselves before vop_unbind() finishes.
1560          */
1561         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1562                                  head)
1563                 vop_plane_destroy(plane);
1564
1565         /*
1566          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1567          * references the CRTC.
1568          */
1569         drm_crtc_cleanup(crtc);
1570 }
1571
1572 /*
1573  * Initialize the vop->win array elements.
1574  */
1575 static int vop_win_init(struct vop *vop)
1576 {
1577         const struct vop_data *vop_data = vop->data;
1578         unsigned int i, j;
1579         unsigned int num_wins = 0;
1580         struct drm_property *prop;
1581         static const struct drm_prop_enum_list props[] = {
1582                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
1583                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
1584         };
1585
1586         for (i = 0; i < vop_data->win_size; i++) {
1587                 struct vop_win *vop_win = &vop->win[num_wins];
1588                 const struct vop_win_data *win_data = &vop_data->win[i];
1589
1590                 if (!win_data->phy)
1591                         continue;
1592
1593                 vop_win->phy = win_data->phy;
1594                 vop_win->offset = win_data->base;
1595                 vop_win->type = win_data->type;
1596                 vop_win->data_formats = win_data->phy->data_formats;
1597                 vop_win->nformats = win_data->phy->nformats;
1598                 vop_win->vop = vop;
1599                 vop_win->win_id = i;
1600                 vop_win->area_id = 0;
1601                 num_wins++;
1602
1603                 for (j = 0; j < win_data->area_size; j++) {
1604                         struct vop_win *vop_area = &vop->win[num_wins];
1605                         const struct vop_win_phy *area = win_data->area[j];
1606
1607                         vop_area->parent = vop_win;
1608                         vop_area->offset = vop_win->offset;
1609                         vop_area->phy = area;
1610                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1611                         vop_area->data_formats = vop_win->data_formats;
1612                         vop_area->nformats = vop_win->nformats;
1613                         vop_area->vop = vop;
1614                         vop_area->win_id = i;
1615                         vop_area->area_id = j;
1616                         num_wins++;
1617                 }
1618         }
1619
1620         vop->num_wins = num_wins;
1621
1622         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1623                                          "ZPOS", 0, vop->data->win_size);
1624         if (!prop) {
1625                 DRM_ERROR("failed to create zpos property\n");
1626                 return -EINVAL;
1627         }
1628         vop->plane_zpos_prop = prop;
1629
1630         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
1631                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
1632                                 props, ARRAY_SIZE(props),
1633                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
1634                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
1635         if (!vop->plane_feature_prop) {
1636                 DRM_ERROR("failed to create feature property\n");
1637                 return -EINVAL;
1638         }
1639
1640         return 0;
1641 }
1642
1643 static int vop_bind(struct device *dev, struct device *master, void *data)
1644 {
1645         struct platform_device *pdev = to_platform_device(dev);
1646         const struct vop_data *vop_data;
1647         struct drm_device *drm_dev = data;
1648         struct vop *vop;
1649         struct resource *res;
1650         size_t alloc_size;
1651         int ret, irq, i;
1652         int num_wins = 0;
1653
1654         vop_data = of_device_get_match_data(dev);
1655         if (!vop_data)
1656                 return -ENODEV;
1657
1658         for (i = 0; i < vop_data->win_size; i++) {
1659                 const struct vop_win_data *win_data = &vop_data->win[i];
1660
1661                 num_wins += win_data->area_size + 1;
1662         }
1663
1664         /* Allocate vop struct and its vop_win array */
1665         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1666         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1667         if (!vop)
1668                 return -ENOMEM;
1669
1670         vop->dev = dev;
1671         vop->data = vop_data;
1672         vop->drm_dev = drm_dev;
1673         vop->num_wins = num_wins;
1674         dev_set_drvdata(dev, vop);
1675
1676         ret = vop_win_init(vop);
1677         if (ret)
1678                 return ret;
1679
1680         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1681         vop->len = resource_size(res);
1682         vop->regs = devm_ioremap_resource(dev, res);
1683         if (IS_ERR(vop->regs))
1684                 return PTR_ERR(vop->regs);
1685
1686         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1687         if (!vop->regsbak)
1688                 return -ENOMEM;
1689
1690         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1691         if (IS_ERR(vop->hclk)) {
1692                 dev_err(vop->dev, "failed to get hclk source\n");
1693                 return PTR_ERR(vop->hclk);
1694         }
1695         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1696         if (IS_ERR(vop->aclk)) {
1697                 dev_err(vop->dev, "failed to get aclk source\n");
1698                 return PTR_ERR(vop->aclk);
1699         }
1700         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1701         if (IS_ERR(vop->dclk)) {
1702                 dev_err(vop->dev, "failed to get dclk source\n");
1703                 return PTR_ERR(vop->dclk);
1704         }
1705
1706         irq = platform_get_irq(pdev, 0);
1707         if (irq < 0) {
1708                 dev_err(dev, "cannot find irq for vop\n");
1709                 return irq;
1710         }
1711         vop->irq = (unsigned int)irq;
1712
1713         spin_lock_init(&vop->reg_lock);
1714         spin_lock_init(&vop->irq_lock);
1715
1716         mutex_init(&vop->vsync_mutex);
1717
1718         ret = devm_request_irq(dev, vop->irq, vop_isr,
1719                                IRQF_SHARED, dev_name(dev), vop);
1720         if (ret)
1721                 return ret;
1722
1723         /* IRQ is initially disabled; it gets enabled in power_on */
1724         disable_irq(vop->irq);
1725
1726         ret = vop_create_crtc(vop);
1727         if (ret)
1728                 return ret;
1729
1730         pm_runtime_enable(&pdev->dev);
1731         return 0;
1732 }
1733
1734 static void vop_unbind(struct device *dev, struct device *master, void *data)
1735 {
1736         struct vop *vop = dev_get_drvdata(dev);
1737
1738         pm_runtime_disable(dev);
1739         vop_destroy_crtc(vop);
1740 }
1741
1742 const struct component_ops vop_component_ops = {
1743         .bind = vop_bind,
1744         .unbind = vop_unbind,
1745 };
1746 EXPORT_SYMBOL_GPL(vop_component_ops);