drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/iopoll.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/clk.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/component.h>
  31
  32 #include <linux/reset.h>
  33 #include <linux/delay.h>
  34 #include <linux/sort.h>
  35 #include <uapi/drm/rockchip_drm.h>
  36
  37 #include "rockchip_drm_drv.h"
  38 #include "rockchip_drm_gem.h"
  39 #include "rockchip_drm_fb.h"
  40 #include "rockchip_drm_vop.h"
  41
  42 #define VOP_REG_SUPPORT(vop, reg) \
  43                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  44                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  45                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  46                 reg.mask))
  47
  48 #define VOP_WIN_SUPPORT(vop, win, name) \
  49                 VOP_REG_SUPPORT(vop, win->phy->name)
  50
  51 #define VOP_CTRL_SUPPORT(vop, name) \
  52                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  53
  54 #define VOP_INTR_SUPPORT(vop, name) \
  55                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  56
  57 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  58                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  59
  60 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  61         do { \
  62                 if (VOP_REG_SUPPORT(vop, reg)) \
  63                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  64                                   v, reg.write_mask, relaxed); \
  65                 else \
  66                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  67         } while(0)
  68
  69 #define REG_SET(x, name, off, reg, v, relaxed) \
  70                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  71 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  72                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  73
  74 #define VOP_WIN_SET(x, win, name, v) \
  75                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  76 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  77                 REG_SET(x, name, win->offset, win->ext->name, v, true)
  78 #define VOP_SCL_SET(x, win, name, v) \
  79                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  80 #define VOP_SCL_SET_EXT(x, win, name, v) \
  81                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  82
  83 #define VOP_CTRL_SET(x, name, v) \
  84                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  85
  86 #define VOP_INTR_GET(vop, name) \
  87                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  88
  89 #define VOP_INTR_SET(vop, name, v) \
  90                 REG_SET(vop, name, 0, vop->data->intr->name, \
  91                         v, false)
  92 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  93                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  94                              mask, v, false)
  95
  96 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  97         do { \
  98                 int i, reg = 0, mask = 0; \
  99                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 100                         if (vop->data->intr->intrs[i] & type) { \
 101                                 reg |= (v) << i; \
 102                                 mask |= 1 << i; \
 103                         } \
 104                 } \
 105                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 106         } while (0)
 107 #define VOP_INTR_GET_TYPE(vop, name, type) \
 108                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 109
 110 #define VOP_CTRL_GET(x, name) \
 111                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 112
 113 #define VOP_WIN_GET(x, win, name) \
 114                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 115
 116 #define VOP_WIN_NAME(win, name) \
 117                 (vop_get_win_phy(win, &win->phy->name)->name)
 118
 119 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 120                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 121
 122 #define to_vop(x) container_of(x, struct vop, crtc)
 123 #define to_vop_win(x) container_of(x, struct vop_win, base)
 124 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 125
 126 struct vop_zpos {
 127         int win_id;
 128         int zpos;
 129 };
 130
 131 struct vop_plane_state {
 132         struct drm_plane_state base;
 133         int format;
 134         int zpos;
 135         struct drm_rect src;
 136         struct drm_rect dest;
 137         dma_addr_t yrgb_mst;
 138         dma_addr_t uv_mst;
 139         const uint32_t *y2r_table;
 140         const uint32_t *r2r_table;
 141         const uint32_t *r2y_table;
 142         bool enable;
 143 };
 144
 145 struct vop_win {
 146         struct vop_win *parent;
 147         struct drm_plane base;
 148
 149         int win_id;
 150         int area_id;
 151         uint32_t offset;
 152         enum drm_plane_type type;
 153         const struct vop_win_phy *phy;
 154         const struct vop_csc *csc;
 155         const uint32_t *data_formats;
 156         uint32_t nformats;
 157         struct vop *vop;
 158
 159         struct drm_property *rotation_prop;
 160         struct vop_plane_state state;
 161 };
 162
 163 struct vop {
 164         struct drm_crtc crtc;
 165         struct device *dev;
 166         struct drm_device *drm_dev;
 167         struct drm_property *plane_zpos_prop;
 168         struct drm_property *plane_feature_prop;
 169         struct drm_property *feature_prop;
 170         bool is_iommu_enabled;
 171         bool is_iommu_needed;
 172         bool is_enabled;
 173
 174         /* mutex vsync_ work */
 175         struct mutex vsync_mutex;
 176         bool vsync_work_pending;
 177         struct completion dsp_hold_completion;
 178         struct completion wait_update_complete;
 179         struct drm_pending_vblank_event *event;
 180
 181         struct completion line_flag_completion;
 182
 183         const struct vop_data *data;
 184         int num_wins;
 185
 186         uint32_t *regsbak;
 187         void __iomem *regs;
 188
 189         /* physical map length of vop register */
 190         uint32_t len;
 191
 192         /* one time only one process allowed to config the register */
 193         spinlock_t reg_lock;
 194         /* lock vop irq reg */
 195         spinlock_t irq_lock;
 196
 197         unsigned int irq;
 198
 199         /* vop AHP clk */
 200         struct clk *hclk;
 201         /* vop dclk */
 202         struct clk *dclk;
 203         /* vop share memory frequency */
 204         struct clk *aclk;
 205
 206         /* vop dclk reset */
 207         struct reset_control *dclk_rst;
 208
 209         struct vop_win win[];
 210 };
 211
 212 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 213 {
 214         writel(v, vop->regs + offset);
 215         vop->regsbak[offset >> 2] = v;
 216 }
 217
 218 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 219 {
 220         return readl(vop->regs + offset);
 221 }
 222
 223 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 224                                     const struct vop_reg *reg)
 225 {
 226         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 227 }
 228
 229 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 230                                   uint32_t mask, uint32_t shift, uint32_t v,
 231                                   bool write_mask, bool relaxed)
 232 {
 233         if (!mask)
 234                 return;
 235
 236         if (write_mask) {
 237                 v = ((v & mask) << shift) | (mask << (shift + 16));
 238         } else {
 239                 uint32_t cached_val = vop->regsbak[offset >> 2];
 240
 241                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 242                 vop->regsbak[offset >> 2] = v;
 243         }
 244
 245         if (relaxed)
 246                 writel_relaxed(v, vop->regs + offset);
 247         else
 248                 writel(v, vop->regs + offset);
 249 }
 250
 251 static inline const struct vop_win_phy *
 252 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 253 {
 254         if (!reg->mask && win->parent)
 255                 return win->parent->phy;
 256
 257         return win->phy;
 258 }
 259
 260 static inline uint32_t vop_get_intr_type(struct vop *vop,
 261                                          const struct vop_reg *reg, int type)
 262 {
 263         uint32_t i, ret = 0;
 264         uint32_t regs = vop_read_reg(vop, 0, reg);
 265
 266         for (i = 0; i < vop->data->intr->nintrs; i++) {
 267                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 268                         ret |= vop->data->intr->intrs[i];
 269         }
 270
 271         return ret;
 272 }
 273
 274 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 275 {
 276         int i;
 277
 278         if (!table)
 279                 return;
 280
 281         for (i = 0; i < 8; i++)
 282                 vop_writel(vop, offset + i * 4, table[i]);
 283 }
 284
 285 static inline void vop_cfg_done(struct vop *vop)
 286 {
 287         VOP_CTRL_SET(vop, cfg_done, 1);
 288 }
 289
 290 static bool vop_is_allwin_disabled(struct vop *vop)
 291 {
 292         int i;
 293
 294         for (i = 0; i < vop->num_wins; i++) {
 295                 struct vop_win *win = &vop->win[i];
 296
 297                 if (VOP_WIN_GET(vop, win, enable) != 0)
 298                         return false;
 299         }
 300
 301         return true;
 302 }
 303
 304 static bool vop_is_cfg_done_complete(struct vop *vop)
 305 {
 306         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 307 }
 308
 309 static bool vop_fs_irq_is_active(struct vop *vop)
 310 {
 311         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 312 }
 313
 314 static bool vop_line_flag_is_active(struct vop *vop)
 315 {
 316         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 317 }
 318
 319 static bool has_rb_swapped(uint32_t format)
 320 {
 321         switch (format) {
 322         case DRM_FORMAT_XBGR8888:
 323         case DRM_FORMAT_ABGR8888:
 324         case DRM_FORMAT_BGR888:
 325         case DRM_FORMAT_BGR565:
 326                 return true;
 327         default:
 328                 return false;
 329         }
 330 }
 331
 332 static enum vop_data_format vop_convert_format(uint32_t format)
 333 {
 334         switch (format) {
 335         case DRM_FORMAT_XRGB8888:
 336         case DRM_FORMAT_ARGB8888:
 337         case DRM_FORMAT_XBGR8888:
 338         case DRM_FORMAT_ABGR8888:
 339                 return VOP_FMT_ARGB8888;
 340         case DRM_FORMAT_RGB888:
 341         case DRM_FORMAT_BGR888:
 342                 return VOP_FMT_RGB888;
 343         case DRM_FORMAT_RGB565:
 344         case DRM_FORMAT_BGR565:
 345                 return VOP_FMT_RGB565;
 346         case DRM_FORMAT_NV12:
 347         case DRM_FORMAT_NV12_10:
 348                 return VOP_FMT_YUV420SP;
 349         case DRM_FORMAT_NV16:
 350         case DRM_FORMAT_NV16_10:
 351                 return VOP_FMT_YUV422SP;
 352         case DRM_FORMAT_NV24:
 353         case DRM_FORMAT_NV24_10:
 354                 return VOP_FMT_YUV444SP;
 355         default:
 356                 DRM_ERROR("unsupport format[%08x]\n", format);
 357                 return -EINVAL;
 358         }
 359 }
 360
 361 static bool is_yuv_support(uint32_t format)
 362 {
 363         switch (format) {
 364         case DRM_FORMAT_NV12:
 365         case DRM_FORMAT_NV12_10:
 366         case DRM_FORMAT_NV16:
 367         case DRM_FORMAT_NV16_10:
 368         case DRM_FORMAT_NV24:
 369         case DRM_FORMAT_NV24_10:
 370                 return true;
 371         default:
 372                 return false;
 373         }
 374 }
 375
 376 static bool is_yuv_10bit(uint32_t format)
 377 {
 378         switch (format) {
 379         case DRM_FORMAT_NV12_10:
 380         case DRM_FORMAT_NV16_10:
 381         case DRM_FORMAT_NV24_10:
 382                 return true;
 383         default:
 384                 return false;
 385         }
 386 }
 387
 388 static bool is_alpha_support(uint32_t format)
 389 {
 390         switch (format) {
 391         case DRM_FORMAT_ARGB8888:
 392         case DRM_FORMAT_ABGR8888:
 393                 return true;
 394         default:
 395                 return false;
 396         }
 397 }
 398
 399 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 400                                   uint32_t dst, bool is_horizontal,
 401                                   int vsu_mode, int *vskiplines)
 402 {
 403         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 404
 405         if (is_horizontal) {
 406                 if (mode == SCALE_UP)
 407                         val = GET_SCL_FT_BIC(src, dst);
 408                 else if (mode == SCALE_DOWN)
 409                         val = GET_SCL_FT_BILI_DN(src, dst);
 410         } else {
 411                 if (mode == SCALE_UP) {
 412                         if (vsu_mode == SCALE_UP_BIL)
 413                                 val = GET_SCL_FT_BILI_UP(src, dst);
 414                         else
 415                                 val = GET_SCL_FT_BIC(src, dst);
 416                 } else if (mode == SCALE_DOWN) {
 417                         if (vskiplines) {
 418                                 *vskiplines = scl_get_vskiplines(src, dst);
 419                                 val = scl_get_bili_dn_vskip(src, dst,
 420                                                             *vskiplines);
 421                         } else {
 422                                 val = GET_SCL_FT_BILI_DN(src, dst);
 423                         }
 424                 }
 425         }
 426
 427         return val;
 428 }
 429
 430 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 431                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 432                                 uint32_t dst_h, uint32_t pixel_format)
 433 {
 434         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 435         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 436         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 437         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 438         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 439         bool is_yuv = is_yuv_support(pixel_format);
 440         uint16_t cbcr_src_w = src_w / hsub;
 441         uint16_t cbcr_src_h = src_h / vsub;
 442         uint16_t vsu_mode;
 443         uint16_t lb_mode;
 444         uint32_t val;
 445         int vskiplines = 0;
 446
 447         if (!win->phy->scl)
 448                 return;
 449
 450         if (dst_w > 3840) {
 451                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 452                 return;
 453         }
 454
 455         if (!win->phy->scl->ext) {
 456                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 457                             scl_cal_scale2(src_w, dst_w));
 458                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 459                             scl_cal_scale2(src_h, dst_h));
 460                 if (is_yuv) {
 461                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 462                                     scl_cal_scale2(cbcr_src_w, dst_w));
 463                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 464                                     scl_cal_scale2(cbcr_src_h, dst_h));
 465                 }
 466                 return;
 467         }
 468
 469         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 470         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 471
 472         if (is_yuv) {
 473                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 474                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 475                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 476                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 477                 else
 478                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 479         } else {
 480                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 481                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 482                 else
 483                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 484         }
 485
 486         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 487         if (lb_mode == LB_RGB_3840X2) {
 488                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 489                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 490                         return;
 491                 }
 492                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 493                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 494                         return;
 495                 }
 496                 vsu_mode = SCALE_UP_BIL;
 497         } else if (lb_mode == LB_RGB_2560X4) {
 498                 vsu_mode = SCALE_UP_BIL;
 499         } else {
 500                 vsu_mode = SCALE_UP_BIC;
 501         }
 502
 503         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 504                                 true, 0, NULL);
 505         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 506         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 507                                 false, vsu_mode, &vskiplines);
 508         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 509
 510         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 511         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 512
 513         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 514         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 515         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 516         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 517         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 518         if (is_yuv) {
 519                 vskiplines = 0;
 520
 521                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 522                                         dst_w, true, 0, NULL);
 523                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 524                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 525                                         dst_h, false, vsu_mode, &vskiplines);
 526                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 527
 528                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 529                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 530                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 531                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 532                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 533                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 534                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 535         }
 536 }
 537
 538 /*
 539  * rk3399 colorspace path:
 540  *      Input        Win csc                     Output
 541  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 542  *    RGB        --> R2Y                  __/
 543  *
 544  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 545  *    RGB        --> 709To2020->R2Y       __/
 546  *
 547  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 548  *    RGB        --> R2Y                  __/
 549  *
 550  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 551  *    RGB        --> 709To2020->R2Y       __/
 552  *
 553  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 554  *    RGB        --> R2Y                  __/
 555  *
 556  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 557  *    RGB        --> R2Y(601)             __/
 558  *
 559  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 560  *    RGB        --> bypass               __/
 561  *
 562  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 563  *
 564  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 565  *
 566  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 567  *
 568  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 569  */
 570 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 571                          bool is_input_yuv, bool is_output_yuv,
 572                          int input_csc, int output_csc,
 573                          const uint32_t **y2r_table,
 574                          const uint32_t **r2r_table,
 575                          const uint32_t **r2y_table)
 576 {
 577         *y2r_table = NULL;
 578         *r2r_table = NULL;
 579         *r2y_table = NULL;
 580
 581         if (is_output_yuv) {
 582                 if (output_csc == CSC_BT2020) {
 583                         if (is_input_yuv) {
 584                                 if (input_csc == CSC_BT2020)
 585                                         return 0;
 586                                 *y2r_table = csc_table->y2r_bt709;
 587                         }
 588                         if (input_csc != CSC_BT2020)
 589                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 590                         *r2y_table = csc_table->r2y_bt2020;
 591                 } else {
 592                         if (is_input_yuv && input_csc == CSC_BT2020)
 593                                 *y2r_table = csc_table->y2r_bt2020;
 594                         if (input_csc == CSC_BT2020)
 595                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 596                         if (!is_input_yuv || y2r_table) {
 597                                 if (output_csc == CSC_BT709)
 598                                         *r2y_table = csc_table->r2y_bt709;
 599                                 else
 600                                         *r2y_table = csc_table->r2y_bt601;
 601                         }
 602                 }
 603
 604         } else {
 605                 if (!is_input_yuv)
 606                         return 0;
 607
 608                 /*
 609                  * is possible use bt2020 on rgb mode?
 610                  */
 611                 if (WARN_ON(output_csc == CSC_BT2020))
 612                         return -EINVAL;
 613
 614                 if (input_csc == CSC_BT2020)
 615                         *y2r_table = csc_table->y2r_bt2020;
 616                 else if (input_csc == CSC_BT709)
 617                         *y2r_table = csc_table->y2r_bt709;
 618                 else
 619                         *y2r_table = csc_table->y2r_bt601;
 620
 621                 if (input_csc == CSC_BT2020)
 622                         /*
 623                          * We don't have bt601 to bt709 table, force use bt709.
 624                          */
 625                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 626         }
 627
 628         return 0;
 629 }
 630
 631 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 632                                 struct drm_crtc_state *crtc_state)
 633 {
 634         struct vop *vop = to_vop(crtc);
 635         struct drm_atomic_state *state = crtc_state->state;
 636         const struct vop_csc_table *csc_table = vop->data->csc_table;
 637         struct drm_plane_state *pstate;
 638         struct drm_plane *plane;
 639         bool is_yuv;
 640         int ret;
 641
 642         if (!csc_table)
 643                 return 0;
 644
 645         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 646                 struct vop_plane_state *vop_plane_state;
 647
 648                 pstate = drm_atomic_get_plane_state(state, plane);
 649                 if (IS_ERR(pstate))
 650                         return PTR_ERR(pstate);
 651                 vop_plane_state = to_vop_plane_state(pstate);
 652
 653                 if (!pstate->fb)
 654                         continue;
 655                 is_yuv = is_yuv_support(pstate->fb->pixel_format);
 656
 657                 /*
 658                  * TODO: force set input and output csc mode.
 659                  */
 660                 ret = vop_csc_setup(csc_table, is_yuv, false,
 661                                     CSC_BT709, CSC_BT709,
 662                                     &vop_plane_state->y2r_table,
 663                                     &vop_plane_state->r2r_table,
 664                                     &vop_plane_state->r2y_table);
 665                 if (ret)
 666                         return ret;
 667         }
 668
 669         return 0;
 670 }
 671
 672 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 673 {
 674         unsigned long flags;
 675
 676         spin_lock_irqsave(&vop->irq_lock, flags);
 677
 678         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 679         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 680
 681         spin_unlock_irqrestore(&vop->irq_lock, flags);
 682 }
 683
 684 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 685 {
 686         unsigned long flags;
 687
 688         spin_lock_irqsave(&vop->irq_lock, flags);
 689
 690         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 691
 692         spin_unlock_irqrestore(&vop->irq_lock, flags);
 693 }
 694
 695 /*
 696  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 697  *     the "FRAME_SYNC" interrupt.
 698  * (2) the active data region of each frame ends at dsp_vact_end
 699  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 700  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 701  *
 702  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 703  * Interrupts
 704  * LINE_FLAG -------------------------------+
 705  * FRAME_SYNC ----+                         |
 706  *                |                         |
 707  *                v                         v
 708  *                | Vsync | Vbp |  Vactive  | Vfp |
 709  *                        ^     ^           ^     ^
 710  *                        |     |           |     |
 711  *                        |     |           |     |
 712  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 713  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 714  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 715  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 716  */
 717 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 718 {
 719         uint32_t line_flag_irq;
 720         unsigned long flags;
 721
 722         spin_lock_irqsave(&vop->irq_lock, flags);
 723
 724         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 725
 726         spin_unlock_irqrestore(&vop->irq_lock, flags);
 727
 728         return !!line_flag_irq;
 729 }
 730
 731 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 732 {
 733         unsigned long flags;
 734
 735         if (WARN_ON(!vop->is_enabled))
 736                 return;
 737
 738         spin_lock_irqsave(&vop->irq_lock, flags);
 739
 740         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 741         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 742         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 743
 744         spin_unlock_irqrestore(&vop->irq_lock, flags);
 745 }
 746
 747 static void vop_line_flag_irq_disable(struct vop *vop)
 748 {
 749         unsigned long flags;
 750
 751         if (WARN_ON(!vop->is_enabled))
 752                 return;
 753
 754         spin_lock_irqsave(&vop->irq_lock, flags);
 755
 756         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 757
 758         spin_unlock_irqrestore(&vop->irq_lock, flags);
 759 }
 760
 761 static void vop_enable(struct drm_crtc *crtc)
 762 {
 763         struct vop *vop = to_vop(crtc);
 764         int ret, i;
 765
 766         ret = clk_prepare_enable(vop->hclk);
 767         if (ret < 0) {
 768                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 769                 return;
 770         }
 771
 772         ret = clk_prepare_enable(vop->dclk);
 773         if (ret < 0) {
 774                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 775                 goto err_disable_hclk;
 776         }
 777
 778         ret = clk_prepare_enable(vop->aclk);
 779         if (ret < 0) {
 780                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 781                 goto err_disable_dclk;
 782         }
 783
 784         ret = pm_runtime_get_sync(vop->dev);
 785         if (ret < 0) {
 786                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 787                 return;
 788         }
 789
 790         memcpy(vop->regsbak, vop->regs, vop->len);
 791
 792         VOP_CTRL_SET(vop, global_regdone_en, 1);
 793         VOP_CTRL_SET(vop, dsp_blank, 0);
 794
 795         for (i = 0; i < vop->num_wins; i++) {
 796                 struct vop_win *win = &vop->win[i];
 797
 798                 VOP_WIN_SET(vop, win, gate, 1);
 799         }
 800         vop->is_enabled = true;
 801
 802         spin_lock(&vop->reg_lock);
 803
 804         VOP_CTRL_SET(vop, standby, 0);
 805
 806         spin_unlock(&vop->reg_lock);
 807
 808         enable_irq(vop->irq);
 809
 810         drm_crtc_vblank_on(crtc);
 811
 812         return;
 813
 814 err_disable_dclk:
 815         clk_disable_unprepare(vop->dclk);
 816 err_disable_hclk:
 817         clk_disable_unprepare(vop->hclk);
 818 }
 819
 820 static void vop_crtc_disable(struct drm_crtc *crtc)
 821 {
 822         struct vop *vop = to_vop(crtc);
 823         int i;
 824
 825         /*
 826          * We need to make sure that all windows are disabled before we
 827          * disable that crtc. Otherwise we might try to scan from a destroyed
 828          * buffer later.
 829          */
 830         for (i = 0; i < vop->num_wins; i++) {
 831                 struct vop_win *win = &vop->win[i];
 832
 833                 spin_lock(&vop->reg_lock);
 834                 if (win->phy->scl && win->phy->scl->ext) {
 835                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 836                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 837                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 838                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 839                 }
 840                 VOP_WIN_SET(vop, win, enable, 0);
 841                 spin_unlock(&vop->reg_lock);
 842         }
 843         VOP_CTRL_SET(vop, afbdc_en, 0);
 844         vop_cfg_done(vop);
 845
 846         drm_crtc_vblank_off(crtc);
 847
 848         /*
 849          * Vop standby will take effect at end of current frame,
 850          * if dsp hold valid irq happen, it means standby complete.
 851          *
 852          * we must wait standby complete when we want to disable aclk,
 853          * if not, memory bus maybe dead.
 854          */
 855         reinit_completion(&vop->dsp_hold_completion);
 856         vop_dsp_hold_valid_irq_enable(vop);
 857
 858         spin_lock(&vop->reg_lock);
 859
 860         VOP_CTRL_SET(vop, standby, 1);
 861
 862         spin_unlock(&vop->reg_lock);
 863
 864         wait_for_completion(&vop->dsp_hold_completion);
 865
 866         vop_dsp_hold_valid_irq_disable(vop);
 867
 868         disable_irq(vop->irq);
 869
 870         vop->is_enabled = false;
 871         if (vop->is_iommu_enabled) {
 872                 /*
 873                  * vop standby complete, so iommu detach is safe.
 874                  */
 875                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 876                 vop->is_iommu_enabled = false;
 877         }
 878
 879         pm_runtime_put(vop->dev);
 880         clk_disable_unprepare(vop->dclk);
 881         clk_disable_unprepare(vop->aclk);
 882         clk_disable_unprepare(vop->hclk);
 883 }
 884
 885 static void vop_plane_destroy(struct drm_plane *plane)
 886 {
 887         drm_plane_cleanup(plane);
 888 }
 889
 890 static int vop_plane_prepare_fb(struct drm_plane *plane,
 891                                 const struct drm_plane_state *new_state)
 892 {
 893         if (plane->state->fb)
 894                 drm_framebuffer_reference(plane->state->fb);
 895
 896         return 0;
 897 }
 898
 899 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 900                                  const struct drm_plane_state *old_state)
 901 {
 902         if (old_state->fb)
 903                 drm_framebuffer_unreference(old_state->fb);
 904 }
 905
 906 static int vop_plane_atomic_check(struct drm_plane *plane,
 907                            struct drm_plane_state *state)
 908 {
 909         struct drm_crtc *crtc = state->crtc;
 910         struct drm_framebuffer *fb = state->fb;
 911         struct vop_win *win = to_vop_win(plane);
 912         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 913         struct drm_crtc_state *crtc_state;
 914         bool visible;
 915         int ret;
 916         struct drm_rect *dest = &vop_plane_state->dest;
 917         struct drm_rect *src = &vop_plane_state->src;
 918         struct drm_rect clip;
 919         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 920                                         DRM_PLANE_HELPER_NO_SCALING;
 921         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 922                                         DRM_PLANE_HELPER_NO_SCALING;
 923         unsigned long offset;
 924         dma_addr_t dma_addr;
 925
 926         crtc = crtc ? crtc : plane->state->crtc;
 927         /*
 928          * Both crtc or plane->state->crtc can be null.
 929          */
 930         if (!crtc || !fb)
 931                 goto out_disable;
 932
 933         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 934         if (IS_ERR(crtc_state))
 935                 return PTR_ERR(crtc_state);
 936
 937         src->x1 = state->src_x;
 938         src->y1 = state->src_y;
 939         src->x2 = state->src_x + state->src_w;
 940         src->y2 = state->src_y + state->src_h;
 941         dest->x1 = state->crtc_x;
 942         dest->y1 = state->crtc_y;
 943         dest->x2 = state->crtc_x + state->crtc_w;
 944         dest->y2 = state->crtc_y + state->crtc_h;
 945
 946         clip.x1 = 0;
 947         clip.y1 = 0;
 948         clip.x2 = crtc_state->mode.hdisplay;
 949         clip.y2 = crtc_state->mode.vdisplay;
 950
 951         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 952                                             src, dest, &clip,
 953                                             min_scale,
 954                                             max_scale,
 955                                             true, true, &visible);
 956         if (ret)
 957                 return ret;
 958
 959         if (!visible)
 960                 goto out_disable;
 961
 962         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 963         if (vop_plane_state->format < 0)
 964                 return vop_plane_state->format;
 965
 966         /*
 967          * Src.x1 can be odd when do clip, but yuv plane start point
 968          * need align with 2 pixel.
 969          */
 970         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 971                 return -EINVAL;
 972
 973         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
 974         if (state->rotation & BIT(DRM_REFLECT_Y))
 975                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 976         else
 977                 offset += (src->y1 >> 16) * fb->pitches[0];
 978
 979         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
 980         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
 981         if (is_yuv_support(fb->pixel_format)) {
 982                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 983                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 984                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
 985
 986                 offset = (src->x1 >> 16) * bpp / hsub / 8;
 987                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 988
 989                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
 990                 dma_addr += offset + fb->offsets[1];
 991                 vop_plane_state->uv_mst = dma_addr;
 992         }
 993
 994         vop_plane_state->enable = true;
 995
 996         return 0;
 997
 998 out_disable:
 999         vop_plane_state->enable = false;
1000         return 0;
1001 }
1002
1003 static void vop_plane_atomic_disable(struct drm_plane *plane,
1004                                      struct drm_plane_state *old_state)
1005 {
1006         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1007         struct vop_win *win = to_vop_win(plane);
1008         struct vop *vop = to_vop(old_state->crtc);
1009
1010         if (!old_state->crtc)
1011                 return;
1012
1013         spin_lock(&vop->reg_lock);
1014
1015         /*
1016          * FIXUP: some of the vop scale would be abnormal after windows power
1017          * on/off so deinit scale to scale_none mode.
1018          */
1019         if (win->phy->scl && win->phy->scl->ext) {
1020                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1021                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1022                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1023                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1024         }
1025         VOP_WIN_SET(vop, win, enable, 0);
1026
1027         spin_unlock(&vop->reg_lock);
1028
1029         vop_plane_state->enable = false;
1030 }
1031
1032 static void vop_plane_atomic_update(struct drm_plane *plane,
1033                 struct drm_plane_state *old_state)
1034 {
1035         struct drm_plane_state *state = plane->state;
1036         struct drm_crtc *crtc = state->crtc;
1037         struct vop_win *win = to_vop_win(plane);
1038         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1039         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1040         struct vop *vop = to_vop(state->crtc);
1041         struct drm_framebuffer *fb = state->fb;
1042         unsigned int actual_w, actual_h;
1043         unsigned int dsp_stx, dsp_sty;
1044         uint32_t act_info, dsp_info, dsp_st;
1045         struct drm_rect *src = &vop_plane_state->src;
1046         struct drm_rect *dest = &vop_plane_state->dest;
1047         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1048         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1049         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1050         int ymirror, xmirror;
1051         uint32_t val;
1052         bool rb_swap;
1053
1054         /*
1055          * can't update plane when vop is disabled.
1056          */
1057         if (!crtc)
1058                 return;
1059
1060         if (!vop_plane_state->enable) {
1061                 vop_plane_atomic_disable(plane, old_state);
1062                 return;
1063         }
1064
1065         actual_w = drm_rect_width(src) >> 16;
1066         actual_h = drm_rect_height(src) >> 16;
1067         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1068
1069         dsp_info = (drm_rect_height(dest) - 1) << 16;
1070         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1071
1072         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1073         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1074         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1075
1076         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
1077         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1078
1079         spin_lock(&vop->reg_lock);
1080
1081         VOP_WIN_SET(vop, win, xmirror, xmirror);
1082         VOP_WIN_SET(vop, win, ymirror, ymirror);
1083         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1084         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1085         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1086         if (is_yuv_support(fb->pixel_format)) {
1087                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1088                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1089         }
1090         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1091
1092         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1093                             drm_rect_width(dest), drm_rect_height(dest),
1094                             fb->pixel_format);
1095
1096         VOP_WIN_SET(vop, win, act_info, act_info);
1097         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1098         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1099
1100         rb_swap = has_rb_swapped(fb->pixel_format);
1101         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1102
1103         if (is_alpha_support(fb->pixel_format) &&
1104             (s->dsp_layer_sel & 0x3) != win->win_id) {
1105                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1106                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1107                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1108                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1109                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1110                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1111                         SRC_FACTOR_M0(ALPHA_ONE);
1112                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1113                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1114                 VOP_WIN_SET(vop, win, alpha_en, 1);
1115         } else {
1116                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1117                 VOP_WIN_SET(vop, win, alpha_en, 0);
1118         }
1119
1120         if (win->csc) {
1121                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1122                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1123                 vop_load_csc_table(vop, win->csc->r2r_offset, r2y_table);
1124                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1125                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1126                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1127         }
1128         VOP_WIN_SET(vop, win, enable, 1);
1129         spin_unlock(&vop->reg_lock);
1130         vop->is_iommu_needed = true;
1131 }
1132
1133 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1134         .prepare_fb = vop_plane_prepare_fb,
1135         .cleanup_fb = vop_plane_cleanup_fb,
1136         .atomic_check = vop_plane_atomic_check,
1137         .atomic_update = vop_plane_atomic_update,
1138         .atomic_disable = vop_plane_atomic_disable,
1139 };
1140
1141 void vop_atomic_plane_reset(struct drm_plane *plane)
1142 {
1143         struct vop_win *win = to_vop_win(plane);
1144         struct vop_plane_state *vop_plane_state =
1145                                         to_vop_plane_state(plane->state);
1146
1147         if (plane->state && plane->state->fb)
1148                 drm_framebuffer_unreference(plane->state->fb);
1149
1150         kfree(vop_plane_state);
1151         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1152         if (!vop_plane_state)
1153                 return;
1154
1155         vop_plane_state->zpos = win->win_id;
1156         plane->state = &vop_plane_state->base;
1157         plane->state->plane = plane;
1158 }
1159
1160 struct drm_plane_state *
1161 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1162 {
1163         struct vop_plane_state *old_vop_plane_state;
1164         struct vop_plane_state *vop_plane_state;
1165
1166         if (WARN_ON(!plane->state))
1167                 return NULL;
1168
1169         old_vop_plane_state = to_vop_plane_state(plane->state);
1170         vop_plane_state = kmemdup(old_vop_plane_state,
1171                                   sizeof(*vop_plane_state), GFP_KERNEL);
1172         if (!vop_plane_state)
1173                 return NULL;
1174
1175         __drm_atomic_helper_plane_duplicate_state(plane,
1176                                                   &vop_plane_state->base);
1177
1178         return &vop_plane_state->base;
1179 }
1180
1181 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1182                                            struct drm_plane_state *state)
1183 {
1184         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1185
1186         __drm_atomic_helper_plane_destroy_state(plane, state);
1187
1188         kfree(vop_state);
1189 }
1190
1191 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1192                                          struct drm_plane_state *state,
1193                                          struct drm_property *property,
1194                                          uint64_t val)
1195 {
1196         struct vop_win *win = to_vop_win(plane);
1197         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1198
1199         if (property == win->vop->plane_zpos_prop) {
1200                 plane_state->zpos = val;
1201                 return 0;
1202         }
1203
1204         if (property == win->rotation_prop) {
1205                 state->rotation = val;
1206                 return 0;
1207         }
1208
1209         DRM_ERROR("failed to set vop plane property\n");
1210         return -EINVAL;
1211 }
1212
1213 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1214                                          const struct drm_plane_state *state,
1215                                          struct drm_property *property,
1216                                          uint64_t *val)
1217 {
1218         struct vop_win *win = to_vop_win(plane);
1219         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1220
1221         if (property == win->vop->plane_zpos_prop) {
1222                 *val = plane_state->zpos;
1223                 return 0;
1224         }
1225
1226         if (property == win->rotation_prop) {
1227                 *val = state->rotation;
1228                 return 0;
1229         }
1230
1231         DRM_ERROR("failed to get vop plane property\n");
1232         return -EINVAL;
1233 }
1234
1235 static const struct drm_plane_funcs vop_plane_funcs = {
1236         .update_plane   = drm_atomic_helper_update_plane,
1237         .disable_plane  = drm_atomic_helper_disable_plane,
1238         .destroy = vop_plane_destroy,
1239         .reset = vop_atomic_plane_reset,
1240         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1241         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1242         .atomic_set_property = vop_atomic_plane_set_property,
1243         .atomic_get_property = vop_atomic_plane_get_property,
1244 };
1245
1246 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1247 {
1248         struct vop *vop = to_vop(crtc);
1249         unsigned long flags;
1250
1251         if (!vop->is_enabled)
1252                 return -EPERM;
1253
1254         spin_lock_irqsave(&vop->irq_lock, flags);
1255
1256         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1257         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1258
1259         spin_unlock_irqrestore(&vop->irq_lock, flags);
1260
1261         return 0;
1262 }
1263
1264 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1265 {
1266         struct vop *vop = to_vop(crtc);
1267         unsigned long flags;
1268
1269         if (!vop->is_enabled)
1270                 return;
1271
1272         spin_lock_irqsave(&vop->irq_lock, flags);
1273
1274         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1275
1276         spin_unlock_irqrestore(&vop->irq_lock, flags);
1277 }
1278
1279 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1280 {
1281         struct vop *vop = to_vop(crtc);
1282
1283         reinit_completion(&vop->wait_update_complete);
1284         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1285 }
1286
1287 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1288                                            struct drm_file *file_priv)
1289 {
1290         struct drm_device *drm = crtc->dev;
1291         struct vop *vop = to_vop(crtc);
1292         struct drm_pending_vblank_event *e;
1293         unsigned long flags;
1294
1295         spin_lock_irqsave(&drm->event_lock, flags);
1296         e = vop->event;
1297         if (e && e->base.file_priv == file_priv) {
1298                 vop->event = NULL;
1299
1300                 e->base.destroy(&e->base);
1301                 file_priv->event_space += sizeof(e->event);
1302         }
1303         spin_unlock_irqrestore(&drm->event_lock, flags);
1304 }
1305
1306 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1307         .enable_vblank = vop_crtc_enable_vblank,
1308         .disable_vblank = vop_crtc_disable_vblank,
1309         .wait_for_update = vop_crtc_wait_for_update,
1310         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1311 };
1312
1313 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1314                                 const struct drm_display_mode *mode,
1315                                 struct drm_display_mode *adjusted_mode)
1316 {
1317         struct vop *vop = to_vop(crtc);
1318
1319         adjusted_mode->clock =
1320                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1321
1322         return true;
1323 }
1324
1325 static void vop_crtc_enable(struct drm_crtc *crtc)
1326 {
1327         struct vop *vop = to_vop(crtc);
1328         const struct vop_data *vop_data = vop->data;
1329         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1330         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1331         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1332         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1333         u16 htotal = adjusted_mode->crtc_htotal;
1334         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1335         u16 hact_end = hact_st + hdisplay;
1336         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1337         u16 vtotal = adjusted_mode->crtc_vtotal;
1338         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1339         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1340         u16 vact_end = vact_st + vdisplay;
1341         uint32_t version = vop->data->version;
1342         uint32_t val;
1343
1344         vop_enable(crtc);
1345         /*
1346          * If dclk rate is zero, mean that scanout is stop,
1347          * we don't need wait any more.
1348          *
1349          * Since vop version(3,4), vop timing is frame effect, not need config
1350          * timing register on vblank.
1351          */
1352         if (clk_get_rate(vop->dclk) &&
1353             !(VOP_MAJOR(version) == 3 && VOP_MINOR(version) >= 4)) {
1354                 /*
1355                  * Rk3288 vop timing register is immediately, when configure
1356                  * display timing on display time, may cause tearing.
1357                  *
1358                  * Vop standby will take effect at end of current frame,
1359                  * if dsp hold valid irq happen, it means standby complete.
1360                  *
1361                  * mode set:
1362                  *    standby and wait complete --> |----
1363                  *                                  | display time
1364                  *                                  |----
1365                  *                                  |---> dsp hold irq
1366                  *     configure display timing --> |
1367                  *         standby exit             |
1368                  *                                  | new frame start.
1369                  */
1370
1371                 reinit_completion(&vop->dsp_hold_completion);
1372                 vop_dsp_hold_valid_irq_enable(vop);
1373
1374                 spin_lock(&vop->reg_lock);
1375
1376                 VOP_CTRL_SET(vop, standby, 1);
1377
1378                 spin_unlock(&vop->reg_lock);
1379
1380                 wait_for_completion(&vop->dsp_hold_completion);
1381
1382                 vop_dsp_hold_valid_irq_disable(vop);
1383         }
1384
1385         val = 0x8;
1386         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1387         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1388         VOP_CTRL_SET(vop, pin_pol, val);
1389         switch (s->output_type) {
1390         case DRM_MODE_CONNECTOR_LVDS:
1391                 VOP_CTRL_SET(vop, rgb_en, 1);
1392                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1393                 break;
1394         case DRM_MODE_CONNECTOR_eDP:
1395                 VOP_CTRL_SET(vop, edp_en, 1);
1396                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1397                 break;
1398         case DRM_MODE_CONNECTOR_HDMIA:
1399                 VOP_CTRL_SET(vop, hdmi_en, 1);
1400                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1401                 break;
1402         case DRM_MODE_CONNECTOR_DSI:
1403                 VOP_CTRL_SET(vop, mipi_en, 1);
1404                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1405                 break;
1406         default:
1407                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1408         }
1409
1410         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1411             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1412                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1413
1414         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1415
1416         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1417         val = hact_st << 16;
1418         val |= hact_end;
1419         VOP_CTRL_SET(vop, hact_st_end, val);
1420         VOP_CTRL_SET(vop, hpost_st_end, val);
1421
1422         VOP_CTRL_SET(vop, vtotal_pw, (adjusted_mode->vtotal << 16) | vsync_len);
1423         val = vact_st << 16;
1424         val |= vact_end;
1425         VOP_CTRL_SET(vop, vact_st_end, val);
1426         VOP_CTRL_SET(vop, vpost_st_end, val);
1427         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1428                 u16 vact_st_f1 = vtotal + vact_st + 1;
1429                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1430
1431                 val = vact_st_f1 << 16 | vact_end_f1;
1432                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1433                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1434
1435                 val = vtotal << 16 | (vtotal + vsync_len);
1436                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1437                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1438                 VOP_CTRL_SET(vop, p2i_en, 1);
1439         } else {
1440                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1441                 VOP_CTRL_SET(vop, p2i_en, 0);
1442         }
1443
1444         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1445
1446         VOP_CTRL_SET(vop, standby, 0);
1447 }
1448
1449 static int vop_zpos_cmp(const void *a, const void *b)
1450 {
1451         struct vop_zpos *pa = (struct vop_zpos *)a;
1452         struct vop_zpos *pb = (struct vop_zpos *)b;
1453
1454         return pa->zpos - pb->zpos;
1455 }
1456
1457 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1458                                   struct drm_crtc_state *crtc_state)
1459 {
1460         struct vop *vop = to_vop(crtc);
1461         const struct vop_data *vop_data = vop->data;
1462         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1463         struct drm_atomic_state *state = crtc_state->state;
1464         struct drm_plane *plane;
1465         struct drm_plane_state *pstate;
1466         struct vop_plane_state *plane_state;
1467         struct vop_win *win;
1468         int afbdc_format;
1469         int i;
1470
1471         s->afbdc_en = 0;
1472
1473         for_each_plane_in_state(state, plane, pstate, i) {
1474                 struct drm_framebuffer *fb = pstate->fb;
1475                 struct drm_rect *src;
1476
1477                 win = to_vop_win(plane);
1478                 plane_state = to_vop_plane_state(pstate);
1479
1480                 if (pstate->crtc != crtc || !fb)
1481                         continue;
1482
1483                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1484                         continue;
1485
1486                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1487                         DRM_ERROR("not support afbdc\n");
1488                         return -EINVAL;
1489                 }
1490
1491                 switch (plane_state->format) {
1492                 case VOP_FMT_ARGB8888:
1493                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1494                         break;
1495                 case VOP_FMT_RGB888:
1496                         afbdc_format = AFBDC_FMT_U8U8U8;
1497                         break;
1498                 case VOP_FMT_RGB565:
1499                         afbdc_format = AFBDC_FMT_RGB565;
1500                         break;
1501                 default:
1502                         return -EINVAL;
1503                 }
1504
1505                 if (s->afbdc_en) {
1506                         DRM_ERROR("vop only support one afbc layer\n");
1507                         return -EINVAL;
1508                 }
1509
1510                 src = &plane_state->src;
1511                 if (src->x1 || src->y1 || fb->offsets[0]) {
1512                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1513                                   win->win_id);
1514                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1515                                   src->x1, src->y1, fb->offsets[0]);
1516                         return -EINVAL;
1517                 }
1518                 s->afbdc_win_format = afbdc_format;
1519                 s->afbdc_win_width = pstate->fb->width - 1;
1520                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1521                 s->afbdc_win_id = win->win_id;
1522                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1523                 s->afbdc_en = 1;
1524         }
1525
1526         return 0;
1527 }
1528
1529 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1530                                  struct drm_crtc_state *crtc_state)
1531 {
1532         struct drm_atomic_state *state = crtc_state->state;
1533         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1534         struct vop *vop = to_vop(crtc);
1535         const struct vop_data *vop_data = vop->data;
1536         struct drm_plane *plane;
1537         struct drm_plane_state *pstate;
1538         struct vop_plane_state *plane_state;
1539         struct vop_zpos *pzpos;
1540         int dsp_layer_sel = 0;
1541         int i, j, cnt = 0, ret = 0;
1542
1543         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1544         if (ret)
1545                 return ret;
1546
1547         ret = vop_csc_atomic_check(crtc, crtc_state);
1548         if (ret)
1549                 return ret;
1550
1551         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1552         if (!pzpos)
1553                 return -ENOMEM;
1554
1555         for (i = 0; i < vop_data->win_size; i++) {
1556                 const struct vop_win_data *win_data = &vop_data->win[i];
1557                 struct vop_win *win;
1558
1559                 if (!win_data->phy)
1560                         continue;
1561
1562                 for (j = 0; j < vop->num_wins; j++) {
1563                         win = &vop->win[j];
1564
1565                         if (win->win_id == i && !win->area_id)
1566                                 break;
1567                 }
1568                 if (WARN_ON(j >= vop->num_wins)) {
1569                         ret = -EINVAL;
1570                         goto err_free_pzpos;
1571                 }
1572
1573                 plane = &win->base;
1574                 pstate = state->plane_states[drm_plane_index(plane)];
1575                 /*
1576                  * plane might not have changed, in which case take
1577                  * current state:
1578                  */
1579                 if (!pstate)
1580                         pstate = plane->state;
1581                 plane_state = to_vop_plane_state(pstate);
1582                 pzpos[cnt].zpos = plane_state->zpos;
1583                 pzpos[cnt++].win_id = win->win_id;
1584         }
1585
1586         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1587
1588         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1589                 const struct vop_win_data *win_data = &vop_data->win[i];
1590                 int shift = i * 2;
1591
1592                 if (win_data->phy) {
1593                         struct vop_zpos *zpos = &pzpos[cnt++];
1594
1595                         dsp_layer_sel |= zpos->win_id << shift;
1596                 } else {
1597                         dsp_layer_sel |= i << shift;
1598                 }
1599         }
1600
1601         s->dsp_layer_sel = dsp_layer_sel;
1602
1603 err_free_pzpos:
1604         kfree(pzpos);
1605         return ret;
1606 }
1607
1608 static void vop_cfg_update(struct drm_crtc *crtc,
1609                            struct drm_crtc_state *old_crtc_state)
1610 {
1611         struct rockchip_crtc_state *s =
1612                         to_rockchip_crtc_state(crtc->state);
1613         struct vop *vop = to_vop(crtc);
1614
1615         spin_lock(&vop->reg_lock);
1616
1617         if (s->afbdc_en) {
1618                 uint32_t pic_size;
1619
1620                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1621                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1622                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1623                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1624                 pic_size = (s->afbdc_win_width & 0xffff);
1625                 pic_size |= s->afbdc_win_height << 16;
1626                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1627         }
1628
1629         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1630         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1631
1632         spin_unlock(&vop->reg_lock);
1633 }
1634
1635 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1636                                   struct drm_crtc_state *old_crtc_state)
1637 {
1638         struct vop *vop = to_vop(crtc);
1639
1640         vop_cfg_update(crtc, old_crtc_state);
1641
1642         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1643                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
1644                 int ret;
1645
1646                 if (need_wait_vblank) {
1647                         bool active;
1648
1649                         disable_irq(vop->irq);
1650                         drm_crtc_vblank_get(crtc);
1651                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
1652
1653                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
1654                                                         vop, active, active,
1655                                                         0, 50 * 1000);
1656                         if (ret)
1657                                 dev_err(vop->dev, "wait fs irq timeout\n");
1658
1659                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
1660                         vop_cfg_done(vop);
1661
1662                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
1663                                                         vop, active, active,
1664                                                         0, 50 * 1000);
1665                         if (ret)
1666                                 dev_err(vop->dev, "wait line flag timeout\n");
1667
1668                         enable_irq(vop->irq);
1669                 }
1670                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1671                 if (ret)
1672                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
1673                                 ret);
1674
1675                 if (need_wait_vblank) {
1676                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
1677                         drm_crtc_vblank_put(crtc);
1678                 }
1679
1680                 vop->is_iommu_enabled = true;
1681         }
1682
1683         vop_cfg_done(vop);
1684 }
1685
1686 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1687                                   struct drm_crtc_state *old_crtc_state)
1688 {
1689         struct vop *vop = to_vop(crtc);
1690
1691         if (crtc->state->event) {
1692                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1693
1694                 vop->event = crtc->state->event;
1695                 crtc->state->event = NULL;
1696         }
1697 }
1698
1699 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1700         .enable = vop_crtc_enable,
1701         .disable = vop_crtc_disable,
1702         .mode_fixup = vop_crtc_mode_fixup,
1703         .atomic_check = vop_crtc_atomic_check,
1704         .atomic_flush = vop_crtc_atomic_flush,
1705         .atomic_begin = vop_crtc_atomic_begin,
1706 };
1707
1708 static void vop_crtc_destroy(struct drm_crtc *crtc)
1709 {
1710         drm_crtc_cleanup(crtc);
1711 }
1712
1713 static void vop_crtc_reset(struct drm_crtc *crtc)
1714 {
1715         if (crtc->state)
1716                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1717         kfree(crtc->state);
1718
1719         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1720         if (crtc->state)
1721                 crtc->state->crtc = crtc;
1722 }
1723
1724 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1725 {
1726         struct rockchip_crtc_state *rockchip_state;
1727
1728         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1729         if (!rockchip_state)
1730                 return NULL;
1731
1732         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1733         return &rockchip_state->base;
1734 }
1735
1736 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1737                                    struct drm_crtc_state *state)
1738 {
1739         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1740
1741         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1742         kfree(s);
1743 }
1744
1745 static const struct drm_crtc_funcs vop_crtc_funcs = {
1746         .set_config = drm_atomic_helper_set_config,
1747         .page_flip = drm_atomic_helper_page_flip,
1748         .destroy = vop_crtc_destroy,
1749         .reset = vop_crtc_reset,
1750         .atomic_duplicate_state = vop_crtc_duplicate_state,
1751         .atomic_destroy_state = vop_crtc_destroy_state,
1752 };
1753
1754 static void vop_handle_vblank(struct vop *vop)
1755 {
1756         struct drm_device *drm = vop->drm_dev;
1757         struct drm_crtc *crtc = &vop->crtc;
1758         unsigned long flags;
1759
1760         if (!vop_is_cfg_done_complete(vop))
1761                 return;
1762
1763         if (vop->event) {
1764                 spin_lock_irqsave(&drm->event_lock, flags);
1765
1766                 drm_crtc_send_vblank_event(crtc, vop->event);
1767                 drm_crtc_vblank_put(crtc);
1768                 vop->event = NULL;
1769
1770                 spin_unlock_irqrestore(&drm->event_lock, flags);
1771         }
1772         if (!completion_done(&vop->wait_update_complete))
1773                 complete(&vop->wait_update_complete);
1774 }
1775
1776 static irqreturn_t vop_isr(int irq, void *data)
1777 {
1778         struct vop *vop = data;
1779         struct drm_crtc *crtc = &vop->crtc;
1780         uint32_t active_irqs;
1781         unsigned long flags;
1782         int ret = IRQ_NONE;
1783
1784         /*
1785          * interrupt register has interrupt status, enable and clear bits, we
1786          * must hold irq_lock to avoid a race with enable/disable_vblank().
1787         */
1788         spin_lock_irqsave(&vop->irq_lock, flags);
1789
1790         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1791         /* Clear all active interrupt sources */
1792         if (active_irqs)
1793                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1794
1795         spin_unlock_irqrestore(&vop->irq_lock, flags);
1796
1797         /* This is expected for vop iommu irqs, since the irq is shared */
1798         if (!active_irqs)
1799                 return IRQ_NONE;
1800
1801         if (active_irqs & DSP_HOLD_VALID_INTR) {
1802                 complete(&vop->dsp_hold_completion);
1803                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1804                 ret = IRQ_HANDLED;
1805         }
1806
1807         if (active_irqs & LINE_FLAG_INTR) {
1808                 complete(&vop->line_flag_completion);
1809                 active_irqs &= ~LINE_FLAG_INTR;
1810                 ret = IRQ_HANDLED;
1811         }
1812
1813         if (active_irqs & FS_INTR) {
1814                 drm_crtc_handle_vblank(crtc);
1815                 vop_handle_vblank(vop);
1816                 active_irqs &= ~FS_INTR;
1817                 ret = IRQ_HANDLED;
1818         }
1819
1820         /* Unhandled irqs are spurious. */
1821         if (active_irqs)
1822                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1823
1824         return ret;
1825 }
1826
1827 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1828                           unsigned long possible_crtcs)
1829 {
1830         struct drm_plane *share = NULL;
1831         unsigned int rotations = 0;
1832         struct drm_property *prop;
1833         uint64_t feature = 0;
1834         int ret;
1835
1836         if (win->parent)
1837                 share = &win->parent->base;
1838
1839         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1840                                    possible_crtcs, &vop_plane_funcs,
1841                                    win->data_formats, win->nformats, win->type);
1842         if (ret) {
1843                 DRM_ERROR("failed to initialize plane\n");
1844                 return ret;
1845         }
1846         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1847         drm_object_attach_property(&win->base.base,
1848                                    vop->plane_zpos_prop, win->win_id);
1849
1850         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1851                 rotations |= BIT(DRM_REFLECT_X);
1852
1853         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1854                 rotations |= BIT(DRM_REFLECT_Y);
1855
1856         if (rotations) {
1857                 rotations |= BIT(DRM_ROTATE_0);
1858                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1859                                                          rotations);
1860                 if (!prop) {
1861                         DRM_ERROR("failed to create zpos property\n");
1862                         return -EINVAL;
1863                 }
1864                 drm_object_attach_property(&win->base.base, prop,
1865                                            BIT(DRM_ROTATE_0));
1866                 win->rotation_prop = prop;
1867         }
1868         if (win->phy->scl)
1869                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
1870         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
1871             VOP_WIN_SUPPORT(vop, win, alpha_en))
1872                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
1873
1874         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
1875                                    feature);
1876
1877         return 0;
1878 }
1879
1880 static int vop_create_crtc(struct vop *vop)
1881 {
1882         struct device *dev = vop->dev;
1883         struct drm_device *drm_dev = vop->drm_dev;
1884         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1885         struct drm_crtc *crtc = &vop->crtc;
1886         struct device_node *port;
1887         uint64_t feature = 0;
1888         int ret;
1889         int i;
1890
1891         /*
1892          * Create drm_plane for primary and cursor planes first, since we need
1893          * to pass them to drm_crtc_init_with_planes, which sets the
1894          * "possible_crtcs" to the newly initialized crtc.
1895          */
1896         for (i = 0; i < vop->num_wins; i++) {
1897                 struct vop_win *win = &vop->win[i];
1898
1899                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1900                     win->type != DRM_PLANE_TYPE_CURSOR)
1901                         continue;
1902
1903                 ret = vop_plane_init(vop, win, 0);
1904                 if (ret)
1905                         goto err_cleanup_planes;
1906
1907                 plane = &win->base;
1908                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1909                         primary = plane;
1910                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1911                         cursor = plane;
1912
1913         }
1914
1915         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1916                                         &vop_crtc_funcs, NULL);
1917         if (ret)
1918                 goto err_cleanup_planes;
1919
1920         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1921
1922         /*
1923          * Create drm_planes for overlay windows with possible_crtcs restricted
1924          * to the newly created crtc.
1925          */
1926         for (i = 0; i < vop->num_wins; i++) {
1927                 struct vop_win *win = &vop->win[i];
1928                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1929
1930                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1931                         continue;
1932
1933                 ret = vop_plane_init(vop, win, possible_crtcs);
1934                 if (ret)
1935                         goto err_cleanup_crtc;
1936         }
1937
1938         port = of_get_child_by_name(dev->of_node, "port");
1939         if (!port) {
1940                 DRM_ERROR("no port node found in %s\n",
1941                           dev->of_node->full_name);
1942                 ret = -ENOENT;
1943                 goto err_cleanup_crtc;
1944         }
1945
1946         init_completion(&vop->dsp_hold_completion);
1947         init_completion(&vop->wait_update_complete);
1948         init_completion(&vop->line_flag_completion);
1949         crtc->port = port;
1950         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1951
1952         if (VOP_CTRL_SUPPORT(vop, afbdc_en))
1953                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
1954         drm_object_attach_property(&crtc->base, vop->feature_prop,
1955                                    feature);
1956
1957         return 0;
1958
1959 err_cleanup_crtc:
1960         drm_crtc_cleanup(crtc);
1961 err_cleanup_planes:
1962         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1963                                  head)
1964                 drm_plane_cleanup(plane);
1965         return ret;
1966 }
1967
1968 static void vop_destroy_crtc(struct vop *vop)
1969 {
1970         struct drm_crtc *crtc = &vop->crtc;
1971         struct drm_device *drm_dev = vop->drm_dev;
1972         struct drm_plane *plane, *tmp;
1973
1974         rockchip_unregister_crtc_funcs(crtc);
1975         of_node_put(crtc->port);
1976
1977         /*
1978          * We need to cleanup the planes now.  Why?
1979          *
1980          * The planes are "&vop->win[i].base".  That means the memory is
1981          * all part of the big "struct vop" chunk of memory.  That memory
1982          * was devm allocated and associated with this component.  We need to
1983          * free it ourselves before vop_unbind() finishes.
1984          */
1985         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1986                                  head)
1987                 vop_plane_destroy(plane);
1988
1989         /*
1990          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1991          * references the CRTC.
1992          */
1993         drm_crtc_cleanup(crtc);
1994 }
1995
1996 /*
1997  * Initialize the vop->win array elements.
1998  */
1999 static int vop_win_init(struct vop *vop)
2000 {
2001         const struct vop_data *vop_data = vop->data;
2002         unsigned int i, j;
2003         unsigned int num_wins = 0;
2004         struct drm_property *prop;
2005         static const struct drm_prop_enum_list props[] = {
2006                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2007                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2008         };
2009         static const struct drm_prop_enum_list crtc_props[] = {
2010                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2011         };
2012
2013         for (i = 0; i < vop_data->win_size; i++) {
2014                 struct vop_win *vop_win = &vop->win[num_wins];
2015                 const struct vop_win_data *win_data = &vop_data->win[i];
2016
2017                 if (!win_data->phy)
2018                         continue;
2019
2020                 vop_win->phy = win_data->phy;
2021                 vop_win->csc = win_data->csc;
2022                 vop_win->offset = win_data->base;
2023                 vop_win->type = win_data->type;
2024                 vop_win->data_formats = win_data->phy->data_formats;
2025                 vop_win->nformats = win_data->phy->nformats;
2026                 vop_win->vop = vop;
2027                 vop_win->win_id = i;
2028                 vop_win->area_id = 0;
2029                 num_wins++;
2030
2031                 for (j = 0; j < win_data->area_size; j++) {
2032                         struct vop_win *vop_area = &vop->win[num_wins];
2033                         const struct vop_win_phy *area = win_data->area[j];
2034
2035                         vop_area->parent = vop_win;
2036                         vop_area->offset = vop_win->offset;
2037                         vop_area->phy = area;
2038                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2039                         vop_area->data_formats = vop_win->data_formats;
2040                         vop_area->nformats = vop_win->nformats;
2041                         vop_area->vop = vop;
2042                         vop_area->win_id = i;
2043                         vop_area->area_id = j;
2044                         num_wins++;
2045                 }
2046         }
2047
2048         vop->num_wins = num_wins;
2049
2050         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2051                                          "ZPOS", 0, vop->data->win_size);
2052         if (!prop) {
2053                 DRM_ERROR("failed to create zpos property\n");
2054                 return -EINVAL;
2055         }
2056         vop->plane_zpos_prop = prop;
2057
2058         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2059                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2060                                 props, ARRAY_SIZE(props),
2061                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2062                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2063         if (!vop->plane_feature_prop) {
2064                 DRM_ERROR("failed to create feature property\n");
2065                 return -EINVAL;
2066         }
2067
2068         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2069                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2070                                 props, ARRAY_SIZE(crtc_props),
2071                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2072         if (!vop->feature_prop) {
2073                 DRM_ERROR("failed to create vop feature property\n");
2074                 return -EINVAL;
2075         }
2076
2077         return 0;
2078 }
2079
2080 /**
2081  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2082  * @crtc: CRTC to enable line flag
2083  * @line_num: interested line number
2084  * @mstimeout: millisecond for timeout
2085  *
2086  * Driver would hold here until the interested line flag interrupt have
2087  * happened or timeout to wait.
2088  *
2089  * Returns:
2090  * Zero on success, negative errno on failure.
2091  */
2092 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2093                                 unsigned int mstimeout)
2094 {
2095         struct vop *vop = to_vop(crtc);
2096         unsigned long jiffies_left;
2097
2098         if (!crtc || !vop->is_enabled)
2099                 return -ENODEV;
2100
2101         if (line_num > crtc->mode.vtotal || mstimeout <= 0)
2102                 return -EINVAL;
2103
2104         if (vop_line_flag_irq_is_enabled(vop))
2105                 return -EBUSY;
2106
2107         reinit_completion(&vop->line_flag_completion);
2108         vop_line_flag_irq_enable(vop, line_num);
2109
2110         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2111                                                    msecs_to_jiffies(mstimeout));
2112         vop_line_flag_irq_disable(vop);
2113
2114         if (jiffies_left == 0) {
2115                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2116                 return -ETIMEDOUT;
2117         }
2118
2119         return 0;
2120 }
2121 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2122
2123 static int vop_bind(struct device *dev, struct device *master, void *data)
2124 {
2125         struct platform_device *pdev = to_platform_device(dev);
2126         const struct vop_data *vop_data;
2127         struct drm_device *drm_dev = data;
2128         struct vop *vop;
2129         struct resource *res;
2130         size_t alloc_size;
2131         int ret, irq, i;
2132         int num_wins = 0;
2133
2134         vop_data = of_device_get_match_data(dev);
2135         if (!vop_data)
2136                 return -ENODEV;
2137
2138         for (i = 0; i < vop_data->win_size; i++) {
2139                 const struct vop_win_data *win_data = &vop_data->win[i];
2140
2141                 num_wins += win_data->area_size + 1;
2142         }
2143
2144         /* Allocate vop struct and its vop_win array */
2145         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2146         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2147         if (!vop)
2148                 return -ENOMEM;
2149
2150         vop->dev = dev;
2151         vop->data = vop_data;
2152         vop->drm_dev = drm_dev;
2153         vop->num_wins = num_wins;
2154         dev_set_drvdata(dev, vop);
2155
2156         ret = vop_win_init(vop);
2157         if (ret)
2158                 return ret;
2159
2160         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2161         vop->len = resource_size(res);
2162         vop->regs = devm_ioremap_resource(dev, res);
2163         if (IS_ERR(vop->regs))
2164                 return PTR_ERR(vop->regs);
2165
2166         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2167         if (!vop->regsbak)
2168                 return -ENOMEM;
2169
2170         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2171         if (IS_ERR(vop->hclk)) {
2172                 dev_err(vop->dev, "failed to get hclk source\n");
2173                 return PTR_ERR(vop->hclk);
2174         }
2175         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2176         if (IS_ERR(vop->aclk)) {
2177                 dev_err(vop->dev, "failed to get aclk source\n");
2178                 return PTR_ERR(vop->aclk);
2179         }
2180         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2181         if (IS_ERR(vop->dclk)) {
2182                 dev_err(vop->dev, "failed to get dclk source\n");
2183                 return PTR_ERR(vop->dclk);
2184         }
2185
2186         irq = platform_get_irq(pdev, 0);
2187         if (irq < 0) {
2188                 dev_err(dev, "cannot find irq for vop\n");
2189                 return irq;
2190         }
2191         vop->irq = (unsigned int)irq;
2192
2193         spin_lock_init(&vop->reg_lock);
2194         spin_lock_init(&vop->irq_lock);
2195
2196         mutex_init(&vop->vsync_mutex);
2197
2198         ret = devm_request_irq(dev, vop->irq, vop_isr,
2199                                IRQF_SHARED, dev_name(dev), vop);
2200         if (ret)
2201                 return ret;
2202
2203         /* IRQ is initially disabled; it gets enabled in power_on */
2204         disable_irq(vop->irq);
2205
2206         ret = vop_create_crtc(vop);
2207         if (ret)
2208                 return ret;
2209
2210         pm_runtime_enable(&pdev->dev);
2211         return 0;
2212 }
2213
2214 static void vop_unbind(struct device *dev, struct device *master, void *data)
2215 {
2216         struct vop *vop = dev_get_drvdata(dev);
2217
2218         pm_runtime_disable(dev);
2219         vop_destroy_crtc(vop);
2220 }
2221
2222 const struct component_ops vop_component_ops = {
2223         .bind = vop_bind,
2224         .unbind = vop_unbind,
2225 };
2226 EXPORT_SYMBOL_GPL(vop_component_ops);