2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/component.h>
31 #include <linux/reset.h>
32 #include <linux/delay.h>
33 #include <linux/sort.h>
35 #include "rockchip_drm_drv.h"
36 #include "rockchip_drm_gem.h"
37 #include "rockchip_drm_fb.h"
38 #include "rockchip_drm_vop.h"
40 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
41 vop_mask_write(x, off, mask, shift, v, write_mask, true)
43 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
44 vop_mask_write(x, off, mask, shift, v, write_mask, false)
46 #define REG_SET(x, off, reg, v, mode) \
47 __REG_SET_##mode(x, off + reg.offset, \
48 reg.mask, reg.shift, v, reg.write_mask)
49 #define REG_SET_MASK(x, off, reg, mask, v, mode) \
50 __REG_SET_##mode(x, off + reg.offset, \
51 mask, reg.shift, v, reg.write_mask)
53 #define VOP_WIN_SET(x, win, name, v) \
54 REG_SET(x, win->offset, VOP_WIN_NAME(win, name), v, RELAXED)
55 #define VOP_SCL_SET(x, win, name, v) \
56 REG_SET(x, win->offset, win->phy->scl->name, v, RELAXED)
57 #define VOP_SCL_SET_EXT(x, win, name, v) \
58 REG_SET(x, win->offset, win->phy->scl->ext->name, v, RELAXED)
60 #define VOP_CTRL_SET(x, name, v) \
61 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
63 #define VOP_INTR_GET(vop, name) \
64 vop_read_reg(vop, 0, &vop->data->ctrl->name)
66 #define VOP_INTR_SET(vop, name, mask, v) \
67 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
68 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
70 int i, reg = 0, mask = 0; \
71 for (i = 0; i < vop->data->intr->nintrs; i++) { \
72 if (vop->data->intr->intrs[i] & type) { \
77 VOP_INTR_SET(vop, name, mask, reg); \
79 #define VOP_INTR_GET_TYPE(vop, name, type) \
80 vop_get_intr_type(vop, &vop->data->intr->name, type)
82 #define VOP_WIN_GET(x, win, name) \
83 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
85 #define VOP_WIN_NAME(win, name) \
86 (vop_get_win_phy(win, &win->phy->name)->name)
88 #define VOP_WIN_GET_YRGBADDR(vop, win) \
89 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
91 #define to_vop(x) container_of(x, struct vop, crtc)
92 #define to_vop_win(x) container_of(x, struct vop_win, base)
93 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
100 struct vop_plane_state {
101 struct drm_plane_state base;
105 struct drm_rect dest;
111 struct vop_win *parent;
112 struct drm_plane base;
117 enum drm_plane_type type;
118 const struct vop_win_phy *phy;
119 const uint32_t *data_formats;
123 struct vop_plane_state state;
127 struct drm_crtc crtc;
129 struct drm_device *drm_dev;
130 struct drm_property *plane_zpos_prop;
133 /* mutex vsync_ work */
134 struct mutex vsync_mutex;
135 bool vsync_work_pending;
136 struct completion dsp_hold_completion;
137 struct completion wait_update_complete;
138 struct drm_pending_vblank_event *event;
140 const struct vop_data *data;
146 /* physical map length of vop register */
149 /* one time only one process allowed to config the register */
151 /* lock vop irq reg */
160 /* vop share memory frequency */
164 struct reset_control *dclk_rst;
166 struct vop_win win[];
169 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
171 writel(v, vop->regs + offset);
172 vop->regsbak[offset >> 2] = v;
175 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
177 return readl(vop->regs + offset);
180 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
181 const struct vop_reg *reg)
183 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
186 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
187 uint32_t mask, uint32_t shift, uint32_t v,
188 bool write_mask, bool relaxed)
194 v = ((v & mask) << shift) | (mask << (shift + 16));
196 uint32_t cached_val = vop->regsbak[offset >> 2];
198 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
199 vop->regsbak[offset >> 2] = v;
203 writel_relaxed(v, vop->regs + offset);
205 writel(v, vop->regs + offset);
208 static inline const struct vop_win_phy *
209 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
211 if (!reg->mask && win->parent)
212 return win->parent->phy;
217 static inline uint32_t vop_get_intr_type(struct vop *vop,
218 const struct vop_reg *reg, int type)
221 uint32_t regs = vop_read_reg(vop, 0, reg);
223 for (i = 0; i < vop->data->intr->nintrs; i++) {
224 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
225 ret |= vop->data->intr->intrs[i];
231 static inline void vop_cfg_done(struct vop *vop)
233 VOP_CTRL_SET(vop, cfg_done, 1);
236 static bool has_rb_swapped(uint32_t format)
239 case DRM_FORMAT_XBGR8888:
240 case DRM_FORMAT_ABGR8888:
241 case DRM_FORMAT_BGR888:
242 case DRM_FORMAT_BGR565:
249 static enum vop_data_format vop_convert_format(uint32_t format)
252 case DRM_FORMAT_XRGB8888:
253 case DRM_FORMAT_ARGB8888:
254 case DRM_FORMAT_XBGR8888:
255 case DRM_FORMAT_ABGR8888:
256 return VOP_FMT_ARGB8888;
257 case DRM_FORMAT_RGB888:
258 case DRM_FORMAT_BGR888:
259 return VOP_FMT_RGB888;
260 case DRM_FORMAT_RGB565:
261 case DRM_FORMAT_BGR565:
262 return VOP_FMT_RGB565;
263 case DRM_FORMAT_NV12:
264 return VOP_FMT_YUV420SP;
265 case DRM_FORMAT_NV16:
266 return VOP_FMT_YUV422SP;
267 case DRM_FORMAT_NV24:
268 return VOP_FMT_YUV444SP;
270 DRM_ERROR("unsupport format[%08x]\n", format);
275 static bool is_yuv_support(uint32_t format)
278 case DRM_FORMAT_NV12:
279 case DRM_FORMAT_NV16:
280 case DRM_FORMAT_NV24:
287 static bool is_alpha_support(uint32_t format)
290 case DRM_FORMAT_ARGB8888:
291 case DRM_FORMAT_ABGR8888:
298 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
299 uint32_t dst, bool is_horizontal,
300 int vsu_mode, int *vskiplines)
302 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
305 if (mode == SCALE_UP)
306 val = GET_SCL_FT_BIC(src, dst);
307 else if (mode == SCALE_DOWN)
308 val = GET_SCL_FT_BILI_DN(src, dst);
310 if (mode == SCALE_UP) {
311 if (vsu_mode == SCALE_UP_BIL)
312 val = GET_SCL_FT_BILI_UP(src, dst);
314 val = GET_SCL_FT_BIC(src, dst);
315 } else if (mode == SCALE_DOWN) {
317 *vskiplines = scl_get_vskiplines(src, dst);
318 val = scl_get_bili_dn_vskip(src, dst,
321 val = GET_SCL_FT_BILI_DN(src, dst);
329 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
330 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
331 uint32_t dst_h, uint32_t pixel_format)
333 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
334 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
335 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
336 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
337 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
338 bool is_yuv = is_yuv_support(pixel_format);
339 uint16_t cbcr_src_w = src_w / hsub;
340 uint16_t cbcr_src_h = src_h / vsub;
350 DRM_ERROR("Maximum destination width (3840) exceeded\n");
354 if (!win->phy->scl->ext) {
355 VOP_SCL_SET(vop, win, scale_yrgb_x,
356 scl_cal_scale2(src_w, dst_w));
357 VOP_SCL_SET(vop, win, scale_yrgb_y,
358 scl_cal_scale2(src_h, dst_h));
360 VOP_SCL_SET(vop, win, scale_cbcr_x,
361 scl_cal_scale2(cbcr_src_w, dst_w));
362 VOP_SCL_SET(vop, win, scale_cbcr_y,
363 scl_cal_scale2(cbcr_src_h, dst_h));
368 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
369 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
372 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
373 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
374 if (cbcr_hor_scl_mode == SCALE_DOWN)
375 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
377 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
379 if (yrgb_hor_scl_mode == SCALE_DOWN)
380 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
382 lb_mode = scl_vop_cal_lb_mode(src_w, false);
385 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
386 if (lb_mode == LB_RGB_3840X2) {
387 if (yrgb_ver_scl_mode != SCALE_NONE) {
388 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
391 if (cbcr_ver_scl_mode != SCALE_NONE) {
392 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
395 vsu_mode = SCALE_UP_BIL;
396 } else if (lb_mode == LB_RGB_2560X4) {
397 vsu_mode = SCALE_UP_BIL;
399 vsu_mode = SCALE_UP_BIC;
402 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
404 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
405 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
406 false, vsu_mode, &vskiplines);
407 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
409 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
410 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
412 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
413 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
414 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
415 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
416 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
418 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
419 dst_w, true, 0, NULL);
420 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
421 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
422 dst_h, false, vsu_mode, &vskiplines);
423 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
425 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
426 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
427 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
428 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
429 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
430 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
431 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
435 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
439 if (WARN_ON(!vop->is_enabled))
442 spin_lock_irqsave(&vop->irq_lock, flags);
444 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
446 spin_unlock_irqrestore(&vop->irq_lock, flags);
449 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
453 if (WARN_ON(!vop->is_enabled))
456 spin_lock_irqsave(&vop->irq_lock, flags);
458 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
460 spin_unlock_irqrestore(&vop->irq_lock, flags);
463 static void vop_enable(struct drm_crtc *crtc)
465 struct vop *vop = to_vop(crtc);
471 ret = clk_enable(vop->hclk);
473 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
477 ret = clk_enable(vop->dclk);
479 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
480 goto err_disable_hclk;
483 ret = clk_enable(vop->aclk);
485 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
486 goto err_disable_dclk;
489 ret = pm_runtime_get_sync(vop->dev);
491 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
496 * Slave iommu shares power, irq and clock with vop. It was associated
497 * automatically with this master device via common driver code.
498 * Now that we have enabled the clock we attach it to the shared drm
501 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
503 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
504 goto err_disable_aclk;
507 memcpy(vop->regs, vop->regsbak, vop->len);
509 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
511 vop->is_enabled = true;
513 spin_lock(&vop->reg_lock);
515 VOP_CTRL_SET(vop, standby, 0);
517 spin_unlock(&vop->reg_lock);
519 enable_irq(vop->irq);
521 drm_crtc_vblank_on(crtc);
526 clk_disable(vop->aclk);
528 clk_disable(vop->dclk);
530 clk_disable(vop->hclk);
533 static void vop_crtc_disable(struct drm_crtc *crtc)
535 struct vop *vop = to_vop(crtc);
538 if (!vop->is_enabled)
542 * We need to make sure that all windows are disabled before we
543 * disable that crtc. Otherwise we might try to scan from a destroyed
546 for (i = 0; i < vop->num_wins; i++) {
547 struct vop_win *win = &vop->win[i];
549 spin_lock(&vop->reg_lock);
550 VOP_WIN_SET(vop, win, enable, 0);
551 spin_unlock(&vop->reg_lock);
554 drm_crtc_vblank_off(crtc);
557 * Vop standby will take effect at end of current frame,
558 * if dsp hold valid irq happen, it means standby complete.
560 * we must wait standby complete when we want to disable aclk,
561 * if not, memory bus maybe dead.
563 reinit_completion(&vop->dsp_hold_completion);
564 vop_dsp_hold_valid_irq_enable(vop);
566 spin_lock(&vop->reg_lock);
568 VOP_CTRL_SET(vop, standby, 1);
570 spin_unlock(&vop->reg_lock);
572 wait_for_completion(&vop->dsp_hold_completion);
574 vop_dsp_hold_valid_irq_disable(vop);
576 disable_irq(vop->irq);
578 vop->is_enabled = false;
581 * vop standby complete, so iommu detach is safe.
583 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
585 pm_runtime_put(vop->dev);
586 clk_disable(vop->dclk);
587 clk_disable(vop->aclk);
588 clk_disable(vop->hclk);
591 static void vop_plane_destroy(struct drm_plane *plane)
593 drm_plane_cleanup(plane);
596 static int vop_plane_prepare_fb(struct drm_plane *plane,
597 const struct drm_plane_state *new_state)
599 if (plane->state->fb)
600 drm_framebuffer_reference(plane->state->fb);
605 static void vop_plane_cleanup_fb(struct drm_plane *plane,
606 const struct drm_plane_state *old_state)
609 drm_framebuffer_unreference(old_state->fb);
612 static int vop_plane_atomic_check(struct drm_plane *plane,
613 struct drm_plane_state *state)
615 struct drm_crtc *crtc = state->crtc;
616 struct drm_framebuffer *fb = state->fb;
617 struct vop_win *win = to_vop_win(plane);
618 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
619 struct drm_crtc_state *crtc_state;
622 struct drm_rect *dest = &vop_plane_state->dest;
623 struct drm_rect *src = &vop_plane_state->src;
624 struct drm_rect clip;
625 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
626 DRM_PLANE_HELPER_NO_SCALING;
627 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
628 DRM_PLANE_HELPER_NO_SCALING;
630 crtc = crtc ? crtc : plane->state->crtc;
632 * Both crtc or plane->state->crtc can be null.
637 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
638 if (IS_ERR(crtc_state))
639 return PTR_ERR(crtc_state);
641 src->x1 = state->src_x;
642 src->y1 = state->src_y;
643 src->x2 = state->src_x + state->src_w;
644 src->y2 = state->src_y + state->src_h;
645 dest->x1 = state->crtc_x;
646 dest->y1 = state->crtc_y;
647 dest->x2 = state->crtc_x + state->crtc_w;
648 dest->y2 = state->crtc_y + state->crtc_h;
652 clip.x2 = crtc_state->mode.hdisplay;
653 clip.y2 = crtc_state->mode.vdisplay;
655 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
659 true, true, &visible);
666 vop_plane_state->format = vop_convert_format(fb->pixel_format);
667 if (vop_plane_state->format < 0)
668 return vop_plane_state->format;
671 * Src.x1 can be odd when do clip, but yuv plane start point
672 * need align with 2 pixel.
674 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
677 vop_plane_state->enable = true;
682 vop_plane_state->enable = false;
686 static void vop_plane_atomic_disable(struct drm_plane *plane,
687 struct drm_plane_state *old_state)
689 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
690 struct vop_win *win = to_vop_win(plane);
691 struct vop *vop = to_vop(old_state->crtc);
693 if (!old_state->crtc)
696 spin_lock(&vop->reg_lock);
698 VOP_WIN_SET(vop, win, enable, 0);
700 spin_unlock(&vop->reg_lock);
702 vop_plane_state->enable = false;
705 static void vop_plane_atomic_update(struct drm_plane *plane,
706 struct drm_plane_state *old_state)
708 struct drm_plane_state *state = plane->state;
709 struct drm_crtc *crtc = state->crtc;
710 struct vop_win *win = to_vop_win(plane);
711 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
712 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
713 struct vop *vop = to_vop(state->crtc);
714 struct drm_framebuffer *fb = state->fb;
715 unsigned int actual_w, actual_h;
716 unsigned int dsp_stx, dsp_sty;
717 uint32_t act_info, dsp_info, dsp_st;
718 struct drm_rect *src = &vop_plane_state->src;
719 struct drm_rect *dest = &vop_plane_state->dest;
720 struct drm_gem_object *obj, *uv_obj;
721 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
722 unsigned long offset;
728 * can't update plane when vop is disabled.
733 if (WARN_ON(!vop->is_enabled))
736 if (!vop_plane_state->enable) {
737 vop_plane_atomic_disable(plane, old_state);
741 obj = rockchip_fb_get_gem_obj(fb, 0);
742 rk_obj = to_rockchip_obj(obj);
744 actual_w = drm_rect_width(src) >> 16;
745 actual_h = drm_rect_height(src) >> 16;
746 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
748 dsp_info = (drm_rect_height(dest) - 1) << 16;
749 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
751 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
752 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
753 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
755 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
756 offset += (src->y1 >> 16) * fb->pitches[0];
757 vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
759 spin_lock(&vop->reg_lock);
761 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
762 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
763 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
764 if (is_yuv_support(fb->pixel_format)) {
765 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
766 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
767 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
769 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
770 rk_uv_obj = to_rockchip_obj(uv_obj);
772 offset = (src->x1 >> 16) * bpp / hsub;
773 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
775 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
776 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
777 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
780 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
781 drm_rect_width(dest), drm_rect_height(dest),
784 VOP_WIN_SET(vop, win, act_info, act_info);
785 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
786 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
788 rb_swap = has_rb_swapped(fb->pixel_format);
789 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
791 if (is_alpha_support(fb->pixel_format) &&
792 (s->dsp_layer_sel & 0x3) != win->win_id) {
793 VOP_WIN_SET(vop, win, dst_alpha_ctl,
794 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
795 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
796 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
797 SRC_BLEND_M0(ALPHA_PER_PIX) |
798 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
799 SRC_FACTOR_M0(ALPHA_ONE);
800 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
802 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
805 VOP_WIN_SET(vop, win, enable, 1);
806 spin_unlock(&vop->reg_lock);
809 static const struct drm_plane_helper_funcs plane_helper_funcs = {
810 .prepare_fb = vop_plane_prepare_fb,
811 .cleanup_fb = vop_plane_cleanup_fb,
812 .atomic_check = vop_plane_atomic_check,
813 .atomic_update = vop_plane_atomic_update,
814 .atomic_disable = vop_plane_atomic_disable,
817 void vop_atomic_plane_reset(struct drm_plane *plane)
819 struct vop_win *win = to_vop_win(plane);
820 struct vop_plane_state *vop_plane_state =
821 to_vop_plane_state(plane->state);
823 if (plane->state && plane->state->fb)
824 drm_framebuffer_unreference(plane->state->fb);
826 kfree(vop_plane_state);
827 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
828 if (!vop_plane_state)
831 vop_plane_state->zpos = win->win_id;
832 plane->state = &vop_plane_state->base;
833 plane->state->plane = plane;
836 struct drm_plane_state *
837 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
839 struct vop_plane_state *old_vop_plane_state;
840 struct vop_plane_state *vop_plane_state;
842 if (WARN_ON(!plane->state))
845 old_vop_plane_state = to_vop_plane_state(plane->state);
846 vop_plane_state = kmemdup(old_vop_plane_state,
847 sizeof(*vop_plane_state), GFP_KERNEL);
848 if (!vop_plane_state)
851 __drm_atomic_helper_plane_duplicate_state(plane,
852 &vop_plane_state->base);
854 return &vop_plane_state->base;
857 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
858 struct drm_plane_state *state)
860 struct vop_plane_state *vop_state = to_vop_plane_state(state);
862 __drm_atomic_helper_plane_destroy_state(plane, state);
867 static int vop_atomic_plane_set_property(struct drm_plane *plane,
868 struct drm_plane_state *state,
869 struct drm_property *property,
872 struct vop_win *win = to_vop_win(plane);
873 struct vop_plane_state *plane_state = to_vop_plane_state(state);
875 if (property == win->vop->plane_zpos_prop) {
876 plane_state->zpos = val;
880 DRM_ERROR("failed to set vop plane property\n");
884 static int vop_atomic_plane_get_property(struct drm_plane *plane,
885 const struct drm_plane_state *state,
886 struct drm_property *property,
889 struct vop_win *win = to_vop_win(plane);
890 struct vop_plane_state *plane_state = to_vop_plane_state(state);
892 if (property == win->vop->plane_zpos_prop) {
893 *val = plane_state->zpos;
897 DRM_ERROR("failed to get vop plane property\n");
901 static const struct drm_plane_funcs vop_plane_funcs = {
902 .update_plane = drm_atomic_helper_update_plane,
903 .disable_plane = drm_atomic_helper_disable_plane,
904 .destroy = vop_plane_destroy,
905 .reset = vop_atomic_plane_reset,
906 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
907 .atomic_destroy_state = vop_atomic_plane_destroy_state,
908 .atomic_set_property = vop_atomic_plane_set_property,
909 .atomic_get_property = vop_atomic_plane_get_property,
912 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
914 struct vop *vop = to_vop(crtc);
917 if (WARN_ON(!vop->is_enabled))
920 spin_lock_irqsave(&vop->irq_lock, flags);
922 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
924 spin_unlock_irqrestore(&vop->irq_lock, flags);
929 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
931 struct vop *vop = to_vop(crtc);
934 if (WARN_ON(!vop->is_enabled))
937 spin_lock_irqsave(&vop->irq_lock, flags);
939 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
941 spin_unlock_irqrestore(&vop->irq_lock, flags);
944 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
946 struct vop *vop = to_vop(crtc);
948 reinit_completion(&vop->wait_update_complete);
949 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
952 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
953 struct drm_file *file_priv)
955 struct drm_device *drm = crtc->dev;
956 struct vop *vop = to_vop(crtc);
957 struct drm_pending_vblank_event *e;
960 spin_lock_irqsave(&drm->event_lock, flags);
962 if (e && e->base.file_priv == file_priv) {
965 e->base.destroy(&e->base);
966 file_priv->event_space += sizeof(e->event);
968 spin_unlock_irqrestore(&drm->event_lock, flags);
971 static const struct rockchip_crtc_funcs private_crtc_funcs = {
972 .enable_vblank = vop_crtc_enable_vblank,
973 .disable_vblank = vop_crtc_disable_vblank,
974 .wait_for_update = vop_crtc_wait_for_update,
975 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
978 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
979 const struct drm_display_mode *mode,
980 struct drm_display_mode *adjusted_mode)
982 struct vop *vop = to_vop(crtc);
984 adjusted_mode->clock =
985 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
990 static void vop_crtc_enable(struct drm_crtc *crtc)
992 struct vop *vop = to_vop(crtc);
993 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
994 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
995 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
996 u16 hdisplay = adjusted_mode->hdisplay;
997 u16 htotal = adjusted_mode->htotal;
998 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
999 u16 hact_end = hact_st + hdisplay;
1000 u16 vdisplay = adjusted_mode->vdisplay;
1001 u16 vtotal = adjusted_mode->vtotal;
1002 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1003 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1004 u16 vact_end = vact_st + vdisplay;
1009 * If dclk rate is zero, mean that scanout is stop,
1010 * we don't need wait any more.
1012 if (clk_get_rate(vop->dclk)) {
1014 * Rk3288 vop timing register is immediately, when configure
1015 * display timing on display time, may cause tearing.
1017 * Vop standby will take effect at end of current frame,
1018 * if dsp hold valid irq happen, it means standby complete.
1021 * standby and wait complete --> |----
1024 * |---> dsp hold irq
1025 * configure display timing --> |
1027 * | new frame start.
1030 reinit_completion(&vop->dsp_hold_completion);
1031 vop_dsp_hold_valid_irq_enable(vop);
1033 spin_lock(&vop->reg_lock);
1035 VOP_CTRL_SET(vop, standby, 1);
1037 spin_unlock(&vop->reg_lock);
1039 wait_for_completion(&vop->dsp_hold_completion);
1041 vop_dsp_hold_valid_irq_disable(vop);
1045 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1046 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1047 VOP_CTRL_SET(vop, pin_pol, val);
1048 switch (s->output_type) {
1049 case DRM_MODE_CONNECTOR_LVDS:
1050 VOP_CTRL_SET(vop, rgb_en, 1);
1051 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1053 case DRM_MODE_CONNECTOR_eDP:
1054 VOP_CTRL_SET(vop, edp_en, 1);
1055 VOP_CTRL_SET(vop, edp_pin_pol, val);
1057 case DRM_MODE_CONNECTOR_HDMIA:
1058 VOP_CTRL_SET(vop, hdmi_en, 1);
1059 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1061 case DRM_MODE_CONNECTOR_DSI:
1062 VOP_CTRL_SET(vop, mipi_en, 1);
1063 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1066 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1068 VOP_CTRL_SET(vop, out_mode, s->output_mode);
1070 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1071 val = hact_st << 16;
1073 VOP_CTRL_SET(vop, hact_st_end, val);
1074 VOP_CTRL_SET(vop, hpost_st_end, val);
1076 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1077 val = vact_st << 16;
1079 VOP_CTRL_SET(vop, vact_st_end, val);
1080 VOP_CTRL_SET(vop, vpost_st_end, val);
1082 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1084 VOP_CTRL_SET(vop, standby, 0);
1087 static int vop_zpos_cmp(const void *a, const void *b)
1089 struct vop_zpos *pa = (struct vop_zpos *)a;
1090 struct vop_zpos *pb = (struct vop_zpos *)b;
1092 return pb->zpos - pa->zpos;
1095 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1096 struct drm_crtc_state *state)
1098 struct drm_device *dev = crtc->dev;
1099 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1100 struct vop *vop = to_vop(crtc);
1101 const struct vop_data *vop_data = vop->data;
1102 struct drm_plane *plane;
1103 struct vop_zpos *pzpos;
1104 int dsp_layer_sel = 0;
1105 int i, cnt = 0, ret = 0;
1107 pzpos = kmalloc_array(vop->num_wins, sizeof(*pzpos), GFP_KERNEL);
1111 drm_atomic_crtc_state_for_each_plane(plane, state) {
1112 struct drm_plane_state *pstate;
1113 struct vop_plane_state *plane_state;
1114 struct vop_win *win = to_vop_win(plane);
1118 if (cnt >= vop->num_wins) {
1119 dev_err(dev->dev, "too many planes!\n");
1121 goto err_free_pzpos;
1123 pstate = state->state->plane_states[drm_plane_index(plane)];
1126 * plane might not have changed, in which case take
1130 pstate = plane->state;
1131 plane_state = to_vop_plane_state(pstate);
1132 pzpos[cnt].zpos = plane_state->zpos;
1133 pzpos[cnt].win_id = win->win_id;
1138 sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1140 WARN_ON(vop_data->win_size < cnt);
1141 for (i = 0; i < (vop_data->win_size - cnt); i++) {
1142 dsp_layer_sel <<= 2;
1144 * after sort, pzpos[0] is the top zpos layer.
1146 dsp_layer_sel |= pzpos[0].win_id;
1149 for (i = 0; i < cnt; i++) {
1150 struct vop_zpos *zpos = &pzpos[i];
1152 dsp_layer_sel <<= 2;
1153 dsp_layer_sel |= zpos->win_id;
1156 s->dsp_layer_sel = dsp_layer_sel;
1163 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1164 struct drm_crtc_state *old_crtc_state)
1166 struct rockchip_crtc_state *s =
1167 to_rockchip_crtc_state(crtc->state);
1168 struct vop *vop = to_vop(crtc);
1170 if (WARN_ON(!vop->is_enabled))
1173 spin_lock(&vop->reg_lock);
1175 VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1178 spin_unlock(&vop->reg_lock);
1181 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1182 struct drm_crtc_state *old_crtc_state)
1184 struct vop *vop = to_vop(crtc);
1186 if (crtc->state->event) {
1187 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1189 vop->event = crtc->state->event;
1190 crtc->state->event = NULL;
1194 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1195 .enable = vop_crtc_enable,
1196 .disable = vop_crtc_disable,
1197 .mode_fixup = vop_crtc_mode_fixup,
1198 .atomic_check = vop_crtc_atomic_check,
1199 .atomic_flush = vop_crtc_atomic_flush,
1200 .atomic_begin = vop_crtc_atomic_begin,
1203 static void vop_crtc_destroy(struct drm_crtc *crtc)
1205 drm_crtc_cleanup(crtc);
1208 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1210 struct rockchip_crtc_state *rockchip_state;
1212 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1213 if (!rockchip_state)
1216 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1217 return &rockchip_state->base;
1220 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1221 struct drm_crtc_state *state)
1223 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1225 __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1229 static const struct drm_crtc_funcs vop_crtc_funcs = {
1230 .set_config = drm_atomic_helper_set_config,
1231 .page_flip = drm_atomic_helper_page_flip,
1232 .destroy = vop_crtc_destroy,
1233 .reset = drm_atomic_helper_crtc_reset,
1234 .atomic_duplicate_state = vop_crtc_duplicate_state,
1235 .atomic_destroy_state = vop_crtc_destroy_state,
1238 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1240 struct drm_plane *plane = &vop_win->base;
1241 struct vop_plane_state *state = to_vop_plane_state(plane->state);
1242 dma_addr_t yrgb_mst;
1245 return VOP_WIN_GET(vop_win->vop, vop_win, enable) == 0;
1247 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win);
1249 return yrgb_mst == state->yrgb_mst;
1252 static void vop_handle_vblank(struct vop *vop)
1254 struct drm_device *drm = vop->drm_dev;
1255 struct drm_crtc *crtc = &vop->crtc;
1256 unsigned long flags;
1259 for (i = 0; i < vop->num_wins; i++) {
1260 if (!vop_win_pending_is_complete(&vop->win[i]))
1265 spin_lock_irqsave(&drm->event_lock, flags);
1267 drm_crtc_send_vblank_event(crtc, vop->event);
1268 drm_crtc_vblank_put(crtc);
1271 spin_unlock_irqrestore(&drm->event_lock, flags);
1273 if (!completion_done(&vop->wait_update_complete))
1274 complete(&vop->wait_update_complete);
1277 static irqreturn_t vop_isr(int irq, void *data)
1279 struct vop *vop = data;
1280 struct drm_crtc *crtc = &vop->crtc;
1281 uint32_t active_irqs;
1282 unsigned long flags;
1286 * interrupt register has interrupt status, enable and clear bits, we
1287 * must hold irq_lock to avoid a race with enable/disable_vblank().
1289 spin_lock_irqsave(&vop->irq_lock, flags);
1291 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1292 /* Clear all active interrupt sources */
1294 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1296 spin_unlock_irqrestore(&vop->irq_lock, flags);
1298 /* This is expected for vop iommu irqs, since the irq is shared */
1302 if (active_irqs & DSP_HOLD_VALID_INTR) {
1303 complete(&vop->dsp_hold_completion);
1304 active_irqs &= ~DSP_HOLD_VALID_INTR;
1308 if (active_irqs & FS_INTR) {
1309 drm_crtc_handle_vblank(crtc);
1310 vop_handle_vblank(vop);
1311 active_irqs &= ~FS_INTR;
1315 /* Unhandled irqs are spurious. */
1317 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1322 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1323 unsigned long possible_crtcs)
1325 struct drm_plane *share = NULL;
1329 share = &win->parent->base;
1331 ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1332 possible_crtcs, &vop_plane_funcs,
1333 win->data_formats, win->nformats, win->type);
1335 DRM_ERROR("failed to initialize plane\n");
1338 drm_plane_helper_add(&win->base, &plane_helper_funcs);
1339 drm_object_attach_property(&win->base.base,
1340 vop->plane_zpos_prop, win->win_id);
1344 static int vop_create_crtc(struct vop *vop)
1346 struct device *dev = vop->dev;
1347 struct drm_device *drm_dev = vop->drm_dev;
1348 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1349 struct drm_crtc *crtc = &vop->crtc;
1350 struct device_node *port;
1355 * Create drm_plane for primary and cursor planes first, since we need
1356 * to pass them to drm_crtc_init_with_planes, which sets the
1357 * "possible_crtcs" to the newly initialized crtc.
1359 for (i = 0; i < vop->num_wins; i++) {
1360 struct vop_win *win = &vop->win[i];
1362 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1363 win->type != DRM_PLANE_TYPE_CURSOR)
1366 ret = vop_plane_init(vop, win, 0);
1368 goto err_cleanup_planes;
1371 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1373 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1378 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1379 &vop_crtc_funcs, NULL);
1381 goto err_cleanup_planes;
1383 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1386 * Create drm_planes for overlay windows with possible_crtcs restricted
1387 * to the newly created crtc.
1389 for (i = 0; i < vop->num_wins; i++) {
1390 struct vop_win *win = &vop->win[i];
1391 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1393 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1396 ret = vop_plane_init(vop, win, possible_crtcs);
1398 goto err_cleanup_crtc;
1401 port = of_get_child_by_name(dev->of_node, "port");
1403 DRM_ERROR("no port node found in %s\n",
1404 dev->of_node->full_name);
1406 goto err_cleanup_crtc;
1409 init_completion(&vop->dsp_hold_completion);
1410 init_completion(&vop->wait_update_complete);
1412 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1417 drm_crtc_cleanup(crtc);
1419 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1421 drm_plane_cleanup(plane);
1425 static void vop_destroy_crtc(struct vop *vop)
1427 struct drm_crtc *crtc = &vop->crtc;
1428 struct drm_device *drm_dev = vop->drm_dev;
1429 struct drm_plane *plane, *tmp;
1431 rockchip_unregister_crtc_funcs(crtc);
1432 of_node_put(crtc->port);
1435 * We need to cleanup the planes now. Why?
1437 * The planes are "&vop->win[i].base". That means the memory is
1438 * all part of the big "struct vop" chunk of memory. That memory
1439 * was devm allocated and associated with this component. We need to
1440 * free it ourselves before vop_unbind() finishes.
1442 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1444 vop_plane_destroy(plane);
1447 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1448 * references the CRTC.
1450 drm_crtc_cleanup(crtc);
1453 static int vop_initial(struct vop *vop)
1455 const struct vop_data *vop_data = vop->data;
1456 const struct vop_reg_data *init_table = vop_data->init_table;
1457 struct reset_control *ahb_rst;
1460 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1461 if (IS_ERR(vop->hclk)) {
1462 dev_err(vop->dev, "failed to get hclk source\n");
1463 return PTR_ERR(vop->hclk);
1465 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1466 if (IS_ERR(vop->aclk)) {
1467 dev_err(vop->dev, "failed to get aclk source\n");
1468 return PTR_ERR(vop->aclk);
1470 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1471 if (IS_ERR(vop->dclk)) {
1472 dev_err(vop->dev, "failed to get dclk source\n");
1473 return PTR_ERR(vop->dclk);
1476 ret = clk_prepare(vop->dclk);
1478 dev_err(vop->dev, "failed to prepare dclk\n");
1482 /* Enable both the hclk and aclk to setup the vop */
1483 ret = clk_prepare_enable(vop->hclk);
1485 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1486 goto err_unprepare_dclk;
1489 ret = clk_prepare_enable(vop->aclk);
1491 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1492 goto err_disable_hclk;
1496 * do hclk_reset, reset all vop registers.
1498 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1499 if (IS_ERR(ahb_rst)) {
1500 dev_err(vop->dev, "failed to get ahb reset\n");
1501 ret = PTR_ERR(ahb_rst);
1502 goto err_disable_aclk;
1504 reset_control_assert(ahb_rst);
1505 usleep_range(10, 20);
1506 reset_control_deassert(ahb_rst);
1508 memcpy(vop->regsbak, vop->regs, vop->len);
1510 for (i = 0; i < vop_data->table_size; i++)
1511 vop_writel(vop, init_table[i].offset, init_table[i].value);
1513 for (i = 0; i < vop->num_wins; i++) {
1514 struct vop_win *win = &vop->win[i];
1516 VOP_WIN_SET(vop, win, enable, 0);
1522 * do dclk_reset, let all config take affect.
1524 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1525 if (IS_ERR(vop->dclk_rst)) {
1526 dev_err(vop->dev, "failed to get dclk reset\n");
1527 ret = PTR_ERR(vop->dclk_rst);
1528 goto err_disable_aclk;
1530 reset_control_assert(vop->dclk_rst);
1531 usleep_range(10, 20);
1532 reset_control_deassert(vop->dclk_rst);
1534 clk_disable(vop->hclk);
1535 clk_disable(vop->aclk);
1537 vop->is_enabled = false;
1542 clk_disable_unprepare(vop->aclk);
1544 clk_disable_unprepare(vop->hclk);
1546 clk_unprepare(vop->dclk);
1551 * Initialize the vop->win array elements.
1553 static int vop_win_init(struct vop *vop)
1555 const struct vop_data *vop_data = vop->data;
1557 unsigned int num_wins = 0;
1558 struct drm_property *prop;
1560 for (i = 0; i < vop_data->win_size; i++) {
1561 struct vop_win *vop_win = &vop->win[num_wins];
1562 const struct vop_win_data *win_data = &vop_data->win[i];
1564 vop_win->phy = win_data->phy;
1565 vop_win->offset = win_data->base;
1566 vop_win->type = win_data->type;
1567 vop_win->data_formats = win_data->phy->data_formats;
1568 vop_win->nformats = win_data->phy->nformats;
1570 vop_win->win_id = i;
1571 vop_win->area_id = 0;
1574 for (j = 0; j < win_data->area_size; j++) {
1575 struct vop_win *vop_area = &vop->win[num_wins];
1576 const struct vop_win_phy *area = win_data->area[j];
1578 vop_area->parent = vop_win;
1579 vop_area->offset = vop_win->offset;
1580 vop_area->phy = area;
1581 vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1582 vop_area->data_formats = vop_win->data_formats;
1583 vop_area->nformats = vop_win->nformats;
1584 vop_area->vop = vop;
1585 vop_area->win_id = i;
1586 vop_area->area_id = j;
1590 prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1591 "ZPOS", 0, vop->data->win_size);
1593 DRM_ERROR("failed to create zpos property\n");
1596 vop->plane_zpos_prop = prop;
1601 static int vop_bind(struct device *dev, struct device *master, void *data)
1603 struct platform_device *pdev = to_platform_device(dev);
1604 const struct vop_data *vop_data;
1605 struct drm_device *drm_dev = data;
1607 struct resource *res;
1612 vop_data = of_device_get_match_data(dev);
1616 for (i = 0; i < vop_data->win_size; i++) {
1617 const struct vop_win_data *win_data = &vop_data->win[i];
1619 num_wins += win_data->area_size + 1;
1622 /* Allocate vop struct and its vop_win array */
1623 alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1624 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1629 vop->data = vop_data;
1630 vop->drm_dev = drm_dev;
1631 vop->num_wins = num_wins;
1632 dev_set_drvdata(dev, vop);
1634 ret = vop_win_init(vop);
1638 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1639 vop->len = resource_size(res);
1640 vop->regs = devm_ioremap_resource(dev, res);
1641 if (IS_ERR(vop->regs))
1642 return PTR_ERR(vop->regs);
1644 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1648 ret = vop_initial(vop);
1650 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1654 irq = platform_get_irq(pdev, 0);
1656 dev_err(dev, "cannot find irq for vop\n");
1659 vop->irq = (unsigned int)irq;
1661 spin_lock_init(&vop->reg_lock);
1662 spin_lock_init(&vop->irq_lock);
1664 mutex_init(&vop->vsync_mutex);
1666 ret = devm_request_irq(dev, vop->irq, vop_isr,
1667 IRQF_SHARED, dev_name(dev), vop);
1671 /* IRQ is initially disabled; it gets enabled in power_on */
1672 disable_irq(vop->irq);
1674 ret = vop_create_crtc(vop);
1678 pm_runtime_enable(&pdev->dev);
1682 static void vop_unbind(struct device *dev, struct device *master, void *data)
1684 struct vop *vop = dev_get_drvdata(dev);
1686 pm_runtime_disable(dev);
1687 vop_destroy_crtc(vop);
1690 const struct component_ops vop_component_ops = {
1692 .unbind = vop_unbind,
1694 EXPORT_SYMBOL_GPL(vop_component_ops);