2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/component.h>
31 #include <linux/reset.h>
32 #include <linux/delay.h>
33 #include <linux/sort.h>
35 #include "rockchip_drm_drv.h"
36 #include "rockchip_drm_gem.h"
37 #include "rockchip_drm_fb.h"
38 #include "rockchip_drm_vop.h"
40 #define VOP_REG_SUPPORT(vop, reg) \
41 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
42 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
43 reg.end_minor >= VOP_MINOR(vop->data->version) && \
46 #define VOP_WIN_SUPPORT(vop, win, name) \
47 VOP_REG_SUPPORT(vop, win->phy->name)
49 #define VOP_CTRL_SUPPORT(vop, win, name) \
50 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
52 #define VOP_INTR_SUPPORT(vop, win, name) \
53 VOP_REG_SUPPORT(vop, vop->data->intr->name)
55 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
56 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
58 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
60 if (VOP_REG_SUPPORT(vop, reg)) \
61 __REG_SET(vop, off + reg.offset, mask, reg.shift, \
62 v, reg.write_mask, relaxed); \
64 dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
67 #define REG_SET(x, name, off, reg, v, relaxed) \
68 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
69 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
70 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
72 #define VOP_WIN_SET(x, win, name, v) \
73 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
74 #define VOP_SCL_SET(x, win, name, v) \
75 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
76 #define VOP_SCL_SET_EXT(x, win, name, v) \
77 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
79 #define VOP_CTRL_SET(x, name, v) \
80 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
82 #define VOP_INTR_GET(vop, name) \
83 vop_read_reg(vop, 0, &vop->data->ctrl->name)
85 #define VOP_INTR_SET(vop, name, mask, v) \
86 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
89 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
91 int i, reg = 0, mask = 0; \
92 for (i = 0; i < vop->data->intr->nintrs; i++) { \
93 if (vop->data->intr->intrs[i] & type) { \
98 VOP_INTR_SET(vop, name, mask, reg); \
100 #define VOP_INTR_GET_TYPE(vop, name, type) \
101 vop_get_intr_type(vop, &vop->data->intr->name, type)
103 #define VOP_CTRL_GET(x, name) \
104 vop_read_reg(x, 0, vop->data->ctrl->name)
106 #define VOP_WIN_GET(x, win, name) \
107 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
109 #define VOP_WIN_NAME(win, name) \
110 (vop_get_win_phy(win, &win->phy->name)->name)
112 #define VOP_WIN_GET_YRGBADDR(vop, win) \
113 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
115 #define to_vop(x) container_of(x, struct vop, crtc)
116 #define to_vop_win(x) container_of(x, struct vop_win, base)
117 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
124 struct vop_plane_state {
125 struct drm_plane_state base;
129 struct drm_rect dest;
135 struct vop_win *parent;
136 struct drm_plane base;
141 enum drm_plane_type type;
142 const struct vop_win_phy *phy;
143 const uint32_t *data_formats;
147 struct drm_property *rotation_prop;
148 struct vop_plane_state state;
152 struct drm_crtc crtc;
154 struct drm_device *drm_dev;
155 struct drm_property *plane_zpos_prop;
156 bool is_iommu_enabled;
157 bool is_iommu_needed;
159 /* mutex vsync_ work */
160 struct mutex vsync_mutex;
161 bool vsync_work_pending;
162 struct completion dsp_hold_completion;
163 struct completion wait_update_complete;
164 struct drm_pending_vblank_event *event;
166 const struct vop_data *data;
172 /* physical map length of vop register */
175 /* one time only one process allowed to config the register */
177 /* lock vop irq reg */
186 /* vop share memory frequency */
190 struct reset_control *dclk_rst;
192 struct vop_win win[];
195 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
197 writel(v, vop->regs + offset);
198 vop->regsbak[offset >> 2] = v;
201 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
203 return readl(vop->regs + offset);
206 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
207 const struct vop_reg *reg)
209 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
212 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
213 uint32_t mask, uint32_t shift, uint32_t v,
214 bool write_mask, bool relaxed)
220 v = ((v & mask) << shift) | (mask << (shift + 16));
222 uint32_t cached_val = vop->regsbak[offset >> 2];
224 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
225 vop->regsbak[offset >> 2] = v;
229 writel_relaxed(v, vop->regs + offset);
231 writel(v, vop->regs + offset);
234 static inline const struct vop_win_phy *
235 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
237 if (!reg->mask && win->parent)
238 return win->parent->phy;
243 static inline uint32_t vop_get_intr_type(struct vop *vop,
244 const struct vop_reg *reg, int type)
247 uint32_t regs = vop_read_reg(vop, 0, reg);
249 for (i = 0; i < vop->data->intr->nintrs; i++) {
250 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
251 ret |= vop->data->intr->intrs[i];
257 static inline void vop_cfg_done(struct vop *vop)
259 VOP_CTRL_SET(vop, cfg_done, 1);
262 static bool vop_is_allwin_disabled(struct vop *vop)
266 for (i = 0; i < vop->num_wins; i++) {
267 struct vop_win *win = &vop->win[i];
269 if (VOP_WIN_GET(vop, win, enable) != 0)
276 static bool vop_win_pending_is_complete(struct vop *vop)
281 for (i = 0; i < vop->num_wins; i++) {
282 struct vop_win *win = &vop->win[i];
283 struct drm_plane *plane = &win->base;
284 struct vop_plane_state *state =
285 to_vop_plane_state(plane->state);
286 if (!state->enable) {
287 if (VOP_WIN_GET(vop, win, enable) != 0)
291 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop, win);
292 if (yrgb_mst != state->yrgb_mst)
299 static bool has_rb_swapped(uint32_t format)
302 case DRM_FORMAT_XBGR8888:
303 case DRM_FORMAT_ABGR8888:
304 case DRM_FORMAT_BGR888:
305 case DRM_FORMAT_BGR565:
312 static enum vop_data_format vop_convert_format(uint32_t format)
315 case DRM_FORMAT_XRGB8888:
316 case DRM_FORMAT_ARGB8888:
317 case DRM_FORMAT_XBGR8888:
318 case DRM_FORMAT_ABGR8888:
319 return VOP_FMT_ARGB8888;
320 case DRM_FORMAT_RGB888:
321 case DRM_FORMAT_BGR888:
322 return VOP_FMT_RGB888;
323 case DRM_FORMAT_RGB565:
324 case DRM_FORMAT_BGR565:
325 return VOP_FMT_RGB565;
326 case DRM_FORMAT_NV12:
327 return VOP_FMT_YUV420SP;
328 case DRM_FORMAT_NV16:
329 return VOP_FMT_YUV422SP;
330 case DRM_FORMAT_NV24:
331 return VOP_FMT_YUV444SP;
333 DRM_ERROR("unsupport format[%08x]\n", format);
338 static bool is_yuv_support(uint32_t format)
341 case DRM_FORMAT_NV12:
342 case DRM_FORMAT_NV16:
343 case DRM_FORMAT_NV24:
350 static bool is_alpha_support(uint32_t format)
353 case DRM_FORMAT_ARGB8888:
354 case DRM_FORMAT_ABGR8888:
361 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
362 uint32_t dst, bool is_horizontal,
363 int vsu_mode, int *vskiplines)
365 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
368 if (mode == SCALE_UP)
369 val = GET_SCL_FT_BIC(src, dst);
370 else if (mode == SCALE_DOWN)
371 val = GET_SCL_FT_BILI_DN(src, dst);
373 if (mode == SCALE_UP) {
374 if (vsu_mode == SCALE_UP_BIL)
375 val = GET_SCL_FT_BILI_UP(src, dst);
377 val = GET_SCL_FT_BIC(src, dst);
378 } else if (mode == SCALE_DOWN) {
380 *vskiplines = scl_get_vskiplines(src, dst);
381 val = scl_get_bili_dn_vskip(src, dst,
384 val = GET_SCL_FT_BILI_DN(src, dst);
392 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
393 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
394 uint32_t dst_h, uint32_t pixel_format)
396 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
397 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
398 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
399 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
400 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
401 bool is_yuv = is_yuv_support(pixel_format);
402 uint16_t cbcr_src_w = src_w / hsub;
403 uint16_t cbcr_src_h = src_h / vsub;
413 DRM_ERROR("Maximum destination width (3840) exceeded\n");
417 if (!win->phy->scl->ext) {
418 VOP_SCL_SET(vop, win, scale_yrgb_x,
419 scl_cal_scale2(src_w, dst_w));
420 VOP_SCL_SET(vop, win, scale_yrgb_y,
421 scl_cal_scale2(src_h, dst_h));
423 VOP_SCL_SET(vop, win, scale_cbcr_x,
424 scl_cal_scale2(cbcr_src_w, dst_w));
425 VOP_SCL_SET(vop, win, scale_cbcr_y,
426 scl_cal_scale2(cbcr_src_h, dst_h));
431 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
432 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
435 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
436 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
437 if (cbcr_hor_scl_mode == SCALE_DOWN)
438 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
440 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
442 if (yrgb_hor_scl_mode == SCALE_DOWN)
443 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
445 lb_mode = scl_vop_cal_lb_mode(src_w, false);
448 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
449 if (lb_mode == LB_RGB_3840X2) {
450 if (yrgb_ver_scl_mode != SCALE_NONE) {
451 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
454 if (cbcr_ver_scl_mode != SCALE_NONE) {
455 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
458 vsu_mode = SCALE_UP_BIL;
459 } else if (lb_mode == LB_RGB_2560X4) {
460 vsu_mode = SCALE_UP_BIL;
462 vsu_mode = SCALE_UP_BIC;
465 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
467 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
468 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
469 false, vsu_mode, &vskiplines);
470 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
472 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
473 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
475 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
476 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
477 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
478 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
479 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
481 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
482 dst_w, true, 0, NULL);
483 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
484 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
485 dst_h, false, vsu_mode, &vskiplines);
486 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
488 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
489 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
490 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
491 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
492 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
493 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
494 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
498 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
502 spin_lock_irqsave(&vop->irq_lock, flags);
504 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
506 spin_unlock_irqrestore(&vop->irq_lock, flags);
509 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
513 spin_lock_irqsave(&vop->irq_lock, flags);
515 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
517 spin_unlock_irqrestore(&vop->irq_lock, flags);
520 static void vop_enable(struct drm_crtc *crtc)
522 struct vop *vop = to_vop(crtc);
525 ret = clk_prepare_enable(vop->hclk);
527 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
531 ret = clk_prepare_enable(vop->dclk);
533 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
534 goto err_disable_hclk;
537 ret = clk_prepare_enable(vop->aclk);
539 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
540 goto err_disable_dclk;
543 ret = pm_runtime_get_sync(vop->dev);
545 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
549 memcpy(vop->regsbak, vop->regs, vop->len);
551 VOP_CTRL_SET(vop, global_regdone_en, 1);
553 for (i = 0; i < vop->num_wins; i++) {
554 struct vop_win *win = &vop->win[i];
556 VOP_WIN_SET(vop, win, gate, 1);
559 spin_lock(&vop->reg_lock);
561 VOP_CTRL_SET(vop, standby, 0);
563 spin_unlock(&vop->reg_lock);
565 enable_irq(vop->irq);
567 drm_crtc_vblank_on(crtc);
572 clk_disable_unprepare(vop->dclk);
574 clk_disable_unprepare(vop->hclk);
577 static void vop_crtc_disable(struct drm_crtc *crtc)
579 struct vop *vop = to_vop(crtc);
583 * We need to make sure that all windows are disabled before we
584 * disable that crtc. Otherwise we might try to scan from a destroyed
587 for (i = 0; i < vop->num_wins; i++) {
588 struct vop_win *win = &vop->win[i];
590 spin_lock(&vop->reg_lock);
591 VOP_WIN_SET(vop, win, enable, 0);
592 spin_unlock(&vop->reg_lock);
596 drm_crtc_vblank_off(crtc);
599 * Vop standby will take effect at end of current frame,
600 * if dsp hold valid irq happen, it means standby complete.
602 * we must wait standby complete when we want to disable aclk,
603 * if not, memory bus maybe dead.
605 reinit_completion(&vop->dsp_hold_completion);
606 vop_dsp_hold_valid_irq_enable(vop);
608 spin_lock(&vop->reg_lock);
610 VOP_CTRL_SET(vop, standby, 1);
612 spin_unlock(&vop->reg_lock);
614 wait_for_completion(&vop->dsp_hold_completion);
616 vop_dsp_hold_valid_irq_disable(vop);
618 disable_irq(vop->irq);
620 if (vop->is_iommu_enabled) {
622 * vop standby complete, so iommu detach is safe.
624 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
625 vop->is_iommu_enabled = false;
628 pm_runtime_put(vop->dev);
629 clk_disable_unprepare(vop->dclk);
630 clk_disable_unprepare(vop->aclk);
631 clk_disable_unprepare(vop->hclk);
634 static void vop_plane_destroy(struct drm_plane *plane)
636 drm_plane_cleanup(plane);
639 static int vop_plane_prepare_fb(struct drm_plane *plane,
640 const struct drm_plane_state *new_state)
642 if (plane->state->fb)
643 drm_framebuffer_reference(plane->state->fb);
648 static void vop_plane_cleanup_fb(struct drm_plane *plane,
649 const struct drm_plane_state *old_state)
652 drm_framebuffer_unreference(old_state->fb);
655 static int vop_plane_atomic_check(struct drm_plane *plane,
656 struct drm_plane_state *state)
658 struct drm_crtc *crtc = state->crtc;
659 struct drm_framebuffer *fb = state->fb;
660 struct vop_win *win = to_vop_win(plane);
661 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
662 struct drm_crtc_state *crtc_state;
665 struct drm_rect *dest = &vop_plane_state->dest;
666 struct drm_rect *src = &vop_plane_state->src;
667 struct drm_rect clip;
668 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
669 DRM_PLANE_HELPER_NO_SCALING;
670 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
671 DRM_PLANE_HELPER_NO_SCALING;
673 crtc = crtc ? crtc : plane->state->crtc;
675 * Both crtc or plane->state->crtc can be null.
680 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
681 if (IS_ERR(crtc_state))
682 return PTR_ERR(crtc_state);
684 src->x1 = state->src_x;
685 src->y1 = state->src_y;
686 src->x2 = state->src_x + state->src_w;
687 src->y2 = state->src_y + state->src_h;
688 dest->x1 = state->crtc_x;
689 dest->y1 = state->crtc_y;
690 dest->x2 = state->crtc_x + state->crtc_w;
691 dest->y2 = state->crtc_y + state->crtc_h;
695 clip.x2 = crtc_state->mode.hdisplay;
696 clip.y2 = crtc_state->mode.vdisplay;
698 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
702 true, true, &visible);
709 vop_plane_state->format = vop_convert_format(fb->pixel_format);
710 if (vop_plane_state->format < 0)
711 return vop_plane_state->format;
714 * Src.x1 can be odd when do clip, but yuv plane start point
715 * need align with 2 pixel.
717 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
720 vop_plane_state->enable = true;
725 vop_plane_state->enable = false;
729 static void vop_plane_atomic_disable(struct drm_plane *plane,
730 struct drm_plane_state *old_state)
732 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
733 struct vop_win *win = to_vop_win(plane);
734 struct vop *vop = to_vop(old_state->crtc);
736 if (!old_state->crtc)
739 spin_lock(&vop->reg_lock);
741 VOP_WIN_SET(vop, win, enable, 0);
743 spin_unlock(&vop->reg_lock);
745 vop_plane_state->enable = false;
748 static void vop_plane_atomic_update(struct drm_plane *plane,
749 struct drm_plane_state *old_state)
751 struct drm_plane_state *state = plane->state;
752 struct drm_crtc *crtc = state->crtc;
753 struct vop_win *win = to_vop_win(plane);
754 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
755 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
756 struct vop *vop = to_vop(state->crtc);
757 struct drm_framebuffer *fb = state->fb;
758 unsigned int actual_w, actual_h;
759 unsigned int dsp_stx, dsp_sty;
760 uint32_t act_info, dsp_info, dsp_st;
761 struct drm_rect *src = &vop_plane_state->src;
762 struct drm_rect *dest = &vop_plane_state->dest;
763 unsigned long offset;
765 int ymirror, xmirror;
770 * can't update plane when vop is disabled.
775 if (!vop_plane_state->enable) {
776 vop_plane_atomic_disable(plane, old_state);
780 actual_w = drm_rect_width(src) >> 16;
781 actual_h = drm_rect_height(src) >> 16;
782 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
784 dsp_info = (drm_rect_height(dest) - 1) << 16;
785 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
787 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
788 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
789 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
791 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
792 if (state->rotation & BIT(DRM_REFLECT_Y))
793 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
795 offset += (src->y1 >> 16) * fb->pitches[0];
797 dma_addr = rockchip_fb_get_dma_addr(fb, 0, vop->dev);
798 vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
800 ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
801 xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
803 spin_lock(&vop->reg_lock);
805 VOP_WIN_SET(vop, win, xmirror, xmirror);
806 VOP_WIN_SET(vop, win, ymirror, ymirror);
807 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
808 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
809 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
810 if (is_yuv_support(fb->pixel_format)) {
811 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
812 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
813 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
815 offset = (src->x1 >> 16) * bpp / hsub;
816 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
818 dma_addr = rockchip_fb_get_dma_addr(fb, 1, vop->dev);
819 dma_addr += offset + fb->offsets[1];
820 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
821 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
824 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
825 drm_rect_width(dest), drm_rect_height(dest),
828 VOP_WIN_SET(vop, win, act_info, act_info);
829 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
830 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
832 rb_swap = has_rb_swapped(fb->pixel_format);
833 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
835 if (is_alpha_support(fb->pixel_format) &&
836 (s->dsp_layer_sel & 0x3) != win->win_id) {
837 VOP_WIN_SET(vop, win, dst_alpha_ctl,
838 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
839 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
840 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
841 SRC_BLEND_M0(ALPHA_PER_PIX) |
842 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
843 SRC_FACTOR_M0(ALPHA_ONE);
844 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
845 VOP_WIN_SET(vop, win, alpha_mode, 1);
846 VOP_WIN_SET(vop, win, alpha_en, 1);
848 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
849 VOP_WIN_SET(vop, win, alpha_en, 0);
852 VOP_WIN_SET(vop, win, enable, 1);
853 spin_unlock(&vop->reg_lock);
854 vop->is_iommu_needed = true;
857 static const struct drm_plane_helper_funcs plane_helper_funcs = {
858 .prepare_fb = vop_plane_prepare_fb,
859 .cleanup_fb = vop_plane_cleanup_fb,
860 .atomic_check = vop_plane_atomic_check,
861 .atomic_update = vop_plane_atomic_update,
862 .atomic_disable = vop_plane_atomic_disable,
865 void vop_atomic_plane_reset(struct drm_plane *plane)
867 struct vop_win *win = to_vop_win(plane);
868 struct vop_plane_state *vop_plane_state =
869 to_vop_plane_state(plane->state);
871 if (plane->state && plane->state->fb)
872 drm_framebuffer_unreference(plane->state->fb);
874 kfree(vop_plane_state);
875 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
876 if (!vop_plane_state)
879 vop_plane_state->zpos = win->win_id;
880 plane->state = &vop_plane_state->base;
881 plane->state->plane = plane;
884 struct drm_plane_state *
885 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
887 struct vop_plane_state *old_vop_plane_state;
888 struct vop_plane_state *vop_plane_state;
890 if (WARN_ON(!plane->state))
893 old_vop_plane_state = to_vop_plane_state(plane->state);
894 vop_plane_state = kmemdup(old_vop_plane_state,
895 sizeof(*vop_plane_state), GFP_KERNEL);
896 if (!vop_plane_state)
899 __drm_atomic_helper_plane_duplicate_state(plane,
900 &vop_plane_state->base);
902 return &vop_plane_state->base;
905 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
906 struct drm_plane_state *state)
908 struct vop_plane_state *vop_state = to_vop_plane_state(state);
910 __drm_atomic_helper_plane_destroy_state(plane, state);
915 static int vop_atomic_plane_set_property(struct drm_plane *plane,
916 struct drm_plane_state *state,
917 struct drm_property *property,
920 struct vop_win *win = to_vop_win(plane);
921 struct vop_plane_state *plane_state = to_vop_plane_state(state);
923 if (property == win->vop->plane_zpos_prop) {
924 plane_state->zpos = val;
928 if (property == win->rotation_prop) {
929 state->rotation = val;
933 DRM_ERROR("failed to set vop plane property\n");
937 static int vop_atomic_plane_get_property(struct drm_plane *plane,
938 const struct drm_plane_state *state,
939 struct drm_property *property,
942 struct vop_win *win = to_vop_win(plane);
943 struct vop_plane_state *plane_state = to_vop_plane_state(state);
945 if (property == win->vop->plane_zpos_prop) {
946 *val = plane_state->zpos;
950 if (property == win->rotation_prop) {
951 *val = state->rotation;
955 DRM_ERROR("failed to get vop plane property\n");
959 static const struct drm_plane_funcs vop_plane_funcs = {
960 .update_plane = drm_atomic_helper_update_plane,
961 .disable_plane = drm_atomic_helper_disable_plane,
962 .destroy = vop_plane_destroy,
963 .reset = vop_atomic_plane_reset,
964 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
965 .atomic_destroy_state = vop_atomic_plane_destroy_state,
966 .atomic_set_property = vop_atomic_plane_set_property,
967 .atomic_get_property = vop_atomic_plane_get_property,
970 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
972 struct vop *vop = to_vop(crtc);
975 spin_lock_irqsave(&vop->irq_lock, flags);
977 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
979 spin_unlock_irqrestore(&vop->irq_lock, flags);
984 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
986 struct vop *vop = to_vop(crtc);
989 spin_lock_irqsave(&vop->irq_lock, flags);
991 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
993 spin_unlock_irqrestore(&vop->irq_lock, flags);
996 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
998 struct vop *vop = to_vop(crtc);
1000 reinit_completion(&vop->wait_update_complete);
1001 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1004 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1005 struct drm_file *file_priv)
1007 struct drm_device *drm = crtc->dev;
1008 struct vop *vop = to_vop(crtc);
1009 struct drm_pending_vblank_event *e;
1010 unsigned long flags;
1012 spin_lock_irqsave(&drm->event_lock, flags);
1014 if (e && e->base.file_priv == file_priv) {
1017 e->base.destroy(&e->base);
1018 file_priv->event_space += sizeof(e->event);
1020 spin_unlock_irqrestore(&drm->event_lock, flags);
1023 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1024 .enable_vblank = vop_crtc_enable_vblank,
1025 .disable_vblank = vop_crtc_disable_vblank,
1026 .wait_for_update = vop_crtc_wait_for_update,
1027 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1030 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1031 const struct drm_display_mode *mode,
1032 struct drm_display_mode *adjusted_mode)
1034 struct vop *vop = to_vop(crtc);
1036 adjusted_mode->clock =
1037 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1042 static void vop_crtc_enable(struct drm_crtc *crtc)
1044 struct vop *vop = to_vop(crtc);
1045 const struct vop_data *vop_data = vop->data;
1046 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1047 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1048 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1049 u16 hdisplay = adjusted_mode->hdisplay;
1050 u16 htotal = adjusted_mode->htotal;
1051 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1052 u16 hact_end = hact_st + hdisplay;
1053 u16 vdisplay = adjusted_mode->vdisplay;
1054 u16 vtotal = adjusted_mode->vtotal;
1055 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1056 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1057 u16 vact_end = vact_st + vdisplay;
1062 * If dclk rate is zero, mean that scanout is stop,
1063 * we don't need wait any more.
1065 if (clk_get_rate(vop->dclk)) {
1067 * Rk3288 vop timing register is immediately, when configure
1068 * display timing on display time, may cause tearing.
1070 * Vop standby will take effect at end of current frame,
1071 * if dsp hold valid irq happen, it means standby complete.
1074 * standby and wait complete --> |----
1077 * |---> dsp hold irq
1078 * configure display timing --> |
1080 * | new frame start.
1083 reinit_completion(&vop->dsp_hold_completion);
1084 vop_dsp_hold_valid_irq_enable(vop);
1086 spin_lock(&vop->reg_lock);
1088 VOP_CTRL_SET(vop, standby, 1);
1090 spin_unlock(&vop->reg_lock);
1092 wait_for_completion(&vop->dsp_hold_completion);
1094 vop_dsp_hold_valid_irq_disable(vop);
1098 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1099 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1100 VOP_CTRL_SET(vop, pin_pol, val);
1101 switch (s->output_type) {
1102 case DRM_MODE_CONNECTOR_LVDS:
1103 VOP_CTRL_SET(vop, rgb_en, 1);
1104 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1106 case DRM_MODE_CONNECTOR_eDP:
1107 VOP_CTRL_SET(vop, edp_en, 1);
1108 VOP_CTRL_SET(vop, edp_pin_pol, val);
1110 case DRM_MODE_CONNECTOR_HDMIA:
1111 VOP_CTRL_SET(vop, hdmi_en, 1);
1112 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1114 case DRM_MODE_CONNECTOR_DSI:
1115 VOP_CTRL_SET(vop, mipi_en, 1);
1116 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1119 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1122 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1123 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1124 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1126 VOP_CTRL_SET(vop, out_mode, s->output_mode);
1128 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1129 val = hact_st << 16;
1131 VOP_CTRL_SET(vop, hact_st_end, val);
1132 VOP_CTRL_SET(vop, hpost_st_end, val);
1134 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1135 val = vact_st << 16;
1137 VOP_CTRL_SET(vop, vact_st_end, val);
1138 VOP_CTRL_SET(vop, vpost_st_end, val);
1140 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1142 VOP_CTRL_SET(vop, standby, 0);
1145 static int vop_zpos_cmp(const void *a, const void *b)
1147 struct vop_zpos *pa = (struct vop_zpos *)a;
1148 struct vop_zpos *pb = (struct vop_zpos *)b;
1150 return pa->zpos - pb->zpos;
1153 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1154 struct drm_crtc_state *crtc_state)
1156 struct drm_atomic_state *state = crtc_state->state;
1157 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1158 struct vop *vop = to_vop(crtc);
1159 const struct vop_data *vop_data = vop->data;
1160 struct drm_plane *plane;
1161 struct drm_plane_state *pstate;
1162 struct vop_plane_state *plane_state;
1163 struct vop_zpos *pzpos;
1164 int dsp_layer_sel = 0;
1165 int i, j, cnt = 0, ret = 0;
1167 pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1171 for (i = 0; i < vop_data->win_size; i++) {
1172 const struct vop_win_data *win_data = &vop_data->win[i];
1173 struct vop_win *win;
1178 for (j = 0; j < vop->num_wins; j++) {
1181 if (win->win_id == i && !win->area_id)
1184 if (WARN_ON(j >= vop->num_wins)) {
1186 goto err_free_pzpos;
1190 pstate = state->plane_states[drm_plane_index(plane)];
1192 * plane might not have changed, in which case take
1196 pstate = plane->state;
1197 plane_state = to_vop_plane_state(pstate);
1198 pzpos[cnt].zpos = plane_state->zpos;
1199 pzpos[cnt++].win_id = win->win_id;
1202 sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1204 for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1205 const struct vop_win_data *win_data = &vop_data->win[i];
1208 if (win_data->phy) {
1209 struct vop_zpos *zpos = &pzpos[cnt++];
1211 dsp_layer_sel |= zpos->win_id << shift;
1213 dsp_layer_sel |= i << shift;
1217 s->dsp_layer_sel = dsp_layer_sel;
1224 static void vop_cfg_update(struct drm_crtc *crtc,
1225 struct drm_crtc_state *old_crtc_state)
1227 struct rockchip_crtc_state *s =
1228 to_rockchip_crtc_state(crtc->state);
1229 struct vop *vop = to_vop(crtc);
1231 spin_lock(&vop->reg_lock);
1233 VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1236 spin_unlock(&vop->reg_lock);
1239 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1240 struct drm_crtc_state *old_crtc_state)
1242 struct vop *vop = to_vop(crtc);
1244 if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1246 if (!vop_is_allwin_disabled(vop)) {
1247 vop_cfg_update(crtc, old_crtc_state);
1248 while(!vop_win_pending_is_complete(vop));
1250 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1252 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
1254 vop->is_iommu_enabled = true;
1257 vop_cfg_update(crtc, old_crtc_state);
1260 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1261 struct drm_crtc_state *old_crtc_state)
1263 struct vop *vop = to_vop(crtc);
1265 if (crtc->state->event) {
1266 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1268 vop->event = crtc->state->event;
1269 crtc->state->event = NULL;
1273 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1274 .enable = vop_crtc_enable,
1275 .disable = vop_crtc_disable,
1276 .mode_fixup = vop_crtc_mode_fixup,
1277 .atomic_check = vop_crtc_atomic_check,
1278 .atomic_flush = vop_crtc_atomic_flush,
1279 .atomic_begin = vop_crtc_atomic_begin,
1282 static void vop_crtc_destroy(struct drm_crtc *crtc)
1284 drm_crtc_cleanup(crtc);
1287 static void vop_crtc_reset(struct drm_crtc *crtc)
1290 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1293 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1295 crtc->state->crtc = crtc;
1298 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1300 struct rockchip_crtc_state *rockchip_state;
1302 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1303 if (!rockchip_state)
1306 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1307 return &rockchip_state->base;
1310 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1311 struct drm_crtc_state *state)
1313 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1315 __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1319 static const struct drm_crtc_funcs vop_crtc_funcs = {
1320 .set_config = drm_atomic_helper_set_config,
1321 .page_flip = drm_atomic_helper_page_flip,
1322 .destroy = vop_crtc_destroy,
1323 .reset = vop_crtc_reset,
1324 .atomic_duplicate_state = vop_crtc_duplicate_state,
1325 .atomic_destroy_state = vop_crtc_destroy_state,
1328 static void vop_handle_vblank(struct vop *vop)
1330 struct drm_device *drm = vop->drm_dev;
1331 struct drm_crtc *crtc = &vop->crtc;
1332 unsigned long flags;
1334 if (!vop_win_pending_is_complete(vop))
1338 spin_lock_irqsave(&drm->event_lock, flags);
1340 drm_crtc_send_vblank_event(crtc, vop->event);
1341 drm_crtc_vblank_put(crtc);
1344 spin_unlock_irqrestore(&drm->event_lock, flags);
1346 if (!completion_done(&vop->wait_update_complete))
1347 complete(&vop->wait_update_complete);
1350 static irqreturn_t vop_isr(int irq, void *data)
1352 struct vop *vop = data;
1353 struct drm_crtc *crtc = &vop->crtc;
1354 uint32_t active_irqs;
1355 unsigned long flags;
1359 * interrupt register has interrupt status, enable and clear bits, we
1360 * must hold irq_lock to avoid a race with enable/disable_vblank().
1362 spin_lock_irqsave(&vop->irq_lock, flags);
1364 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1365 /* Clear all active interrupt sources */
1367 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1369 spin_unlock_irqrestore(&vop->irq_lock, flags);
1371 /* This is expected for vop iommu irqs, since the irq is shared */
1375 if (active_irqs & DSP_HOLD_VALID_INTR) {
1376 complete(&vop->dsp_hold_completion);
1377 active_irqs &= ~DSP_HOLD_VALID_INTR;
1381 if (active_irqs & FS_INTR) {
1382 drm_crtc_handle_vblank(crtc);
1383 vop_handle_vblank(vop);
1384 active_irqs &= ~FS_INTR;
1388 /* Unhandled irqs are spurious. */
1390 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1395 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1396 unsigned long possible_crtcs)
1398 struct drm_plane *share = NULL;
1399 unsigned int rotations = 0;
1400 struct drm_property *prop;
1404 share = &win->parent->base;
1406 ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1407 possible_crtcs, &vop_plane_funcs,
1408 win->data_formats, win->nformats, win->type);
1410 DRM_ERROR("failed to initialize plane\n");
1413 drm_plane_helper_add(&win->base, &plane_helper_funcs);
1414 drm_object_attach_property(&win->base.base,
1415 vop->plane_zpos_prop, win->win_id);
1417 if (VOP_WIN_SUPPORT(vop, win, xmirror))
1418 rotations |= BIT(DRM_REFLECT_X);
1420 if (VOP_WIN_SUPPORT(vop, win, ymirror))
1421 rotations |= BIT(DRM_REFLECT_Y);
1424 rotations |= BIT(DRM_ROTATE_0);
1425 prop = drm_mode_create_rotation_property(vop->drm_dev,
1428 DRM_ERROR("failed to create zpos property\n");
1431 drm_object_attach_property(&win->base.base, prop,
1433 win->rotation_prop = prop;
1439 static int vop_create_crtc(struct vop *vop)
1441 struct device *dev = vop->dev;
1442 struct drm_device *drm_dev = vop->drm_dev;
1443 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1444 struct drm_crtc *crtc = &vop->crtc;
1445 struct device_node *port;
1450 * Create drm_plane for primary and cursor planes first, since we need
1451 * to pass them to drm_crtc_init_with_planes, which sets the
1452 * "possible_crtcs" to the newly initialized crtc.
1454 for (i = 0; i < vop->num_wins; i++) {
1455 struct vop_win *win = &vop->win[i];
1457 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1458 win->type != DRM_PLANE_TYPE_CURSOR)
1461 ret = vop_plane_init(vop, win, 0);
1463 goto err_cleanup_planes;
1466 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1468 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1473 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1474 &vop_crtc_funcs, NULL);
1476 goto err_cleanup_planes;
1478 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1481 * Create drm_planes for overlay windows with possible_crtcs restricted
1482 * to the newly created crtc.
1484 for (i = 0; i < vop->num_wins; i++) {
1485 struct vop_win *win = &vop->win[i];
1486 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1488 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1491 ret = vop_plane_init(vop, win, possible_crtcs);
1493 goto err_cleanup_crtc;
1496 port = of_get_child_by_name(dev->of_node, "port");
1498 DRM_ERROR("no port node found in %s\n",
1499 dev->of_node->full_name);
1501 goto err_cleanup_crtc;
1504 init_completion(&vop->dsp_hold_completion);
1505 init_completion(&vop->wait_update_complete);
1507 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1512 drm_crtc_cleanup(crtc);
1514 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1516 drm_plane_cleanup(plane);
1520 static void vop_destroy_crtc(struct vop *vop)
1522 struct drm_crtc *crtc = &vop->crtc;
1523 struct drm_device *drm_dev = vop->drm_dev;
1524 struct drm_plane *plane, *tmp;
1526 rockchip_unregister_crtc_funcs(crtc);
1527 of_node_put(crtc->port);
1530 * We need to cleanup the planes now. Why?
1532 * The planes are "&vop->win[i].base". That means the memory is
1533 * all part of the big "struct vop" chunk of memory. That memory
1534 * was devm allocated and associated with this component. We need to
1535 * free it ourselves before vop_unbind() finishes.
1537 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1539 vop_plane_destroy(plane);
1542 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1543 * references the CRTC.
1545 drm_crtc_cleanup(crtc);
1549 * Initialize the vop->win array elements.
1551 static int vop_win_init(struct vop *vop)
1553 const struct vop_data *vop_data = vop->data;
1555 unsigned int num_wins = 0;
1556 struct drm_property *prop;
1558 for (i = 0; i < vop_data->win_size; i++) {
1559 struct vop_win *vop_win = &vop->win[num_wins];
1560 const struct vop_win_data *win_data = &vop_data->win[i];
1565 vop_win->phy = win_data->phy;
1566 vop_win->offset = win_data->base;
1567 vop_win->type = win_data->type;
1568 vop_win->data_formats = win_data->phy->data_formats;
1569 vop_win->nformats = win_data->phy->nformats;
1571 vop_win->win_id = i;
1572 vop_win->area_id = 0;
1575 for (j = 0; j < win_data->area_size; j++) {
1576 struct vop_win *vop_area = &vop->win[num_wins];
1577 const struct vop_win_phy *area = win_data->area[j];
1579 vop_area->parent = vop_win;
1580 vop_area->offset = vop_win->offset;
1581 vop_area->phy = area;
1582 vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1583 vop_area->data_formats = vop_win->data_formats;
1584 vop_area->nformats = vop_win->nformats;
1585 vop_area->vop = vop;
1586 vop_area->win_id = i;
1587 vop_area->area_id = j;
1592 vop->num_wins = num_wins;
1594 prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1595 "ZPOS", 0, vop->data->win_size);
1597 DRM_ERROR("failed to create zpos property\n");
1600 vop->plane_zpos_prop = prop;
1605 static int vop_bind(struct device *dev, struct device *master, void *data)
1607 struct platform_device *pdev = to_platform_device(dev);
1608 const struct vop_data *vop_data;
1609 struct drm_device *drm_dev = data;
1611 struct resource *res;
1616 vop_data = of_device_get_match_data(dev);
1620 for (i = 0; i < vop_data->win_size; i++) {
1621 const struct vop_win_data *win_data = &vop_data->win[i];
1623 num_wins += win_data->area_size + 1;
1626 /* Allocate vop struct and its vop_win array */
1627 alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1628 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1633 vop->data = vop_data;
1634 vop->drm_dev = drm_dev;
1635 vop->num_wins = num_wins;
1636 dev_set_drvdata(dev, vop);
1638 ret = vop_win_init(vop);
1642 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1643 vop->len = resource_size(res);
1644 vop->regs = devm_ioremap_resource(dev, res);
1645 if (IS_ERR(vop->regs))
1646 return PTR_ERR(vop->regs);
1648 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1652 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1653 if (IS_ERR(vop->hclk)) {
1654 dev_err(vop->dev, "failed to get hclk source\n");
1655 return PTR_ERR(vop->hclk);
1657 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1658 if (IS_ERR(vop->aclk)) {
1659 dev_err(vop->dev, "failed to get aclk source\n");
1660 return PTR_ERR(vop->aclk);
1662 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1663 if (IS_ERR(vop->dclk)) {
1664 dev_err(vop->dev, "failed to get dclk source\n");
1665 return PTR_ERR(vop->dclk);
1668 irq = platform_get_irq(pdev, 0);
1670 dev_err(dev, "cannot find irq for vop\n");
1673 vop->irq = (unsigned int)irq;
1675 spin_lock_init(&vop->reg_lock);
1676 spin_lock_init(&vop->irq_lock);
1678 mutex_init(&vop->vsync_mutex);
1680 ret = devm_request_irq(dev, vop->irq, vop_isr,
1681 IRQF_SHARED, dev_name(dev), vop);
1685 /* IRQ is initially disabled; it gets enabled in power_on */
1686 disable_irq(vop->irq);
1688 ret = vop_create_crtc(vop);
1692 pm_runtime_enable(&pdev->dev);
1696 static void vop_unbind(struct device *dev, struct device *master, void *data)
1698 struct vop *vop = dev_get_drvdata(dev);
1700 pm_runtime_disable(dev);
1701 vop_destroy_crtc(vop);
1704 const struct component_ops vop_component_ops = {
1706 .unbind = vop_unbind,
1708 EXPORT_SYMBOL_GPL(vop_component_ops);