2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Zheng Yang <zhengyang@rock-chips.com>
4 * Yakir Yang <ykk@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef __INNO_HDMI_H__
17 #define __INNO_HDMI_H__
19 #define DDC_SEGMENT_ADDR 0x30
26 #define HDMI_SCL_RATE (100*1000)
27 #define DDC_BUS_FREQ_L 0x4b
28 #define DDC_BUS_FREQ_H 0x4c
30 #define HDMI_SYS_CTRL 0x00
31 #define m_RST_ANALOG (1 << 6)
32 #define v_RST_ANALOG (0 << 6)
33 #define v_NOT_RST_ANALOG (1 << 6)
34 #define m_RST_DIGITAL (1 << 5)
35 #define v_RST_DIGITAL (0 << 5)
36 #define v_NOT_RST_DIGITAL (1 << 5)
37 #define m_REG_CLK_INV (1 << 4)
38 #define v_REG_CLK_NOT_INV (0 << 4)
39 #define v_REG_CLK_INV (1 << 4)
40 #define m_VCLK_INV (1 << 3)
41 #define v_VCLK_NOT_INV (0 << 3)
42 #define v_VCLK_INV (1 << 3)
43 #define m_REG_CLK_SOURCE (1 << 2)
44 #define v_REG_CLK_SOURCE_TMDS (0 << 2)
45 #define v_REG_CLK_SOURCE_SYS (1 << 2)
46 #define m_POWER (1 << 1)
47 #define v_PWR_ON (0 << 1)
48 #define v_PWR_OFF (1 << 1)
49 #define m_INT_POL (1 << 0)
50 #define v_INT_POL_HIGH 1
51 #define v_INT_POL_LOW 0
53 #define HDMI_VIDEO_CONTRL1 0x01
54 #define m_VIDEO_INPUT_FORMAT (7 << 1)
55 #define m_DE_SOURCE (1 << 0)
56 #define v_VIDEO_INPUT_FORMAT(n) (n << 1)
57 #define v_DE_EXTERNAL 1
58 #define v_DE_INTERNAL 0
60 VIDEO_INPUT_SDR_RGB444 = 0,
61 VIDEO_INPUT_DDR_RGB444 = 5,
62 VIDEO_INPUT_DDR_YCBCR422 = 6
65 #define HDMI_VIDEO_CONTRL2 0x02
66 #define m_VIDEO_OUTPUT_COLOR (3 << 6)
67 #define m_VIDEO_INPUT_BITS (3 << 4)
68 #define m_VIDEO_INPUT_CSP (1 << 0)
69 #define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6)
70 #define v_VIDEO_INPUT_BITS(n) (n << 4)
71 #define v_VIDEO_INPUT_CSP(n) (n << 0)
73 VIDEO_INPUT_12BITS = 0,
74 VIDEO_INPUT_10BITS = 1,
75 VIDEO_INPUT_REVERT = 2,
76 VIDEO_INPUT_8BITS = 3,
79 #define HDMI_VIDEO_CONTRL 0x03
80 #define m_VIDEO_AUTO_CSC (1 << 7)
81 #define v_VIDEO_AUTO_CSC(n) (n << 7)
82 #define m_VIDEO_C0_C2_SWAP (1 << 0)
83 #define v_VIDEO_C0_C2_SWAP(n) (n << 0)
85 C0_C2_CHANGE_ENABLE = 0,
86 C0_C2_CHANGE_DISABLE = 1,
91 #define HDMI_VIDEO_CONTRL3 0x04
92 #define m_COLOR_DEPTH_NOT_INDICATED (1 << 4)
93 #define m_SOF (1 << 3)
94 #define m_COLOR_RANGE (1 << 2)
95 #define m_CSC (1 << 0)
96 #define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4)
97 #define v_SOF_ENABLE (0 << 3)
98 #define v_SOF_DISABLE (1 << 3)
99 #define v_COLOR_RANGE_FULL (1 << 2)
100 #define v_COLOR_RANGE_LIMITED (0 << 2)
101 #define v_CSC_ENABLE 1
102 #define v_CSC_DISABLE 0
104 #define HDMI_AV_MUTE 0x05
105 #define m_AVMUTE_CLEAR (1 << 7)
106 #define m_AVMUTE_ENABLE (1 << 6)
107 #define m_AUDIO_PD (1 << 2)
108 #define m_AUDIO_MUTE (1 << 1)
109 #define m_VIDEO_BLACK (1 << 0)
110 #define v_AVMUTE_CLEAR(n) (n << 7)
111 #define v_AVMUTE_ENABLE(n) (n << 6)
112 #define v_AUDIO_MUTE(n) (n << 1)
113 #define v_AUDIO_PD(n) (n << 2)
114 #define v_VIDEO_MUTE(n) (n << 0)
116 #define HDMI_VIDEO_TIMING_CTL 0x08
117 #define v_HSYNC_POLARITY(n) (n << 3)
118 #define v_VSYNC_POLARITY(n) (n << 2)
119 #define v_INETLACE(n) (n << 1)
120 #define v_EXTERANL_VIDEO(n) (n << 0)
122 #define HDMI_VIDEO_EXT_HTOTAL_L 0x09
123 #define HDMI_VIDEO_EXT_HTOTAL_H 0x0a
124 #define HDMI_VIDEO_EXT_HBLANK_L 0x0b
125 #define HDMI_VIDEO_EXT_HBLANK_H 0x0c
126 #define HDMI_VIDEO_EXT_HDELAY_L 0x0d
127 #define HDMI_VIDEO_EXT_HDELAY_H 0x0e
128 #define HDMI_VIDEO_EXT_HDURATION_L 0x0f
129 #define HDMI_VIDEO_EXT_HDURATION_H 0x10
130 #define HDMI_VIDEO_EXT_VTOTAL_L 0x11
131 #define HDMI_VIDEO_EXT_VTOTAL_H 0x12
132 #define HDMI_VIDEO_EXT_VBLANK 0x13
133 #define HDMI_VIDEO_EXT_VDELAY 0x14
134 #define HDMI_VIDEO_EXT_VDURATION 0x15
136 #define HDMI_VIDEO_CSC_COEF 0x18
138 #define HDMI_AUDIO_CTRL1 0x35
140 CTS_SOURCE_INTERNAL = 0,
141 CTS_SOURCE_EXTERNAL = 1,
143 #define v_CTS_SOURCE(n) (n << 7)
146 DOWNSAMPLE_DISABLE = 0,
150 #define v_DOWN_SAMPLE(n) (n << 5)
153 AUDIO_SOURCE_IIS = 0,
154 AUDIO_SOURCE_SPDIF = 1,
156 #define v_AUDIO_SOURCE(n) (n << 3)
158 #define v_MCLK_ENABLE(n) (n << 2)
165 #define v_MCLK_RATIO(n) (n)
167 #define AUDIO_SAMPLE_RATE 0x37
178 #define AUDIO_I2S_MODE 0x38
183 I2S_CHANNEL_7_8 = 0xf
185 #define v_I2S_CHANNEL(n) ((n) << 2)
188 I2S_LEFT_JUSTIFIED = 1,
189 I2S_RIGHT_JUSTIFIED = 2,
191 #define v_I2S_MODE(n) (n)
193 #define AUDIO_I2S_MAP 0x39
194 #define AUDIO_I2S_SWAPS_SPDIF 0x3a
195 #define v_SPIDF_FREQ(n) (n)
198 #define N_441K 0x1880
199 #define N_882K 0x3100
200 #define N_1764K 0x6200
203 #define N_192K 0x6000
205 #define HDMI_AUDIO_CHANNEL_STATUS 0x3e
206 #define m_AUDIO_STATUS_NLPCM (1 << 7)
207 #define m_AUDIO_STATUS_USE (1 << 6)
208 #define m_AUDIO_STATUS_COPYRIGHT (1 << 5)
209 #define m_AUDIO_STATUS_ADDITION (3 << 2)
210 #define m_AUDIO_STATUS_CLK_ACCURACY (2 << 0)
211 #define v_AUDIO_STATUS_NLPCM(n) ((n & 1) << 7)
212 #define AUDIO_N_H 0x3f
213 #define AUDIO_N_M 0x40
214 #define AUDIO_N_L 0x41
216 #define HDMI_AUDIO_CTS_H 0x45
217 #define HDMI_AUDIO_CTS_M 0x46
218 #define HDMI_AUDIO_CTS_L 0x47
220 #define HDMI_DDC_CLK_L 0x4b
221 #define HDMI_DDC_CLK_H 0x4c
223 #define HDMI_EDID_SEGMENT_POINTER 0x4d
224 #define HDMI_EDID_WORD_ADDR 0x4e
225 #define HDMI_EDID_FIFO_OFFSET 0x4f
226 #define HDMI_EDID_FIFO_ADDR 0x50
228 #define HDMI_PACKET_SEND_MANUAL 0x9c
229 #define HDMI_PACKET_SEND_AUTO 0x9d
230 #define m_PACKET_GCP_EN (1 << 7)
231 #define m_PACKET_MSI_EN (1 << 6)
232 #define m_PACKET_SDI_EN (1 << 5)
233 #define m_PACKET_VSI_EN (1 << 4)
234 #define v_PACKET_GCP_EN(n) ((n & 1) << 7)
235 #define v_PACKET_MSI_EN(n) ((n & 1) << 6)
236 #define v_PACKET_SDI_EN(n) ((n & 1) << 5)
237 #define v_PACKET_VSI_EN(n) ((n & 1) << 4)
239 #define HDMI_CONTROL_PACKET_BUF_INDEX 0x9f
241 INFOFRAME_VSI = 0x05,
242 INFOFRAME_AVI = 0x06,
243 INFOFRAME_AAI = 0x08,
246 #define HDMI_CONTROL_PACKET_ADDR 0xa0
247 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
249 AVI_COLOR_MODE_RGB = 0,
250 AVI_COLOR_MODE_YCBCR422 = 1,
251 AVI_COLOR_MODE_YCBCR444 = 2,
252 AVI_COLORIMETRY_NO_DATA = 0,
254 AVI_COLORIMETRY_SMPTE_170M = 1,
255 AVI_COLORIMETRY_ITU709 = 2,
256 AVI_COLORIMETRY_EXTENDED = 3,
258 AVI_CODED_FRAME_ASPECT_NO_DATA = 0,
259 AVI_CODED_FRAME_ASPECT_4_3 = 1,
260 AVI_CODED_FRAME_ASPECT_16_9 = 2,
262 ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08,
263 ACTIVE_ASPECT_RATE_4_3 = 0x09,
264 ACTIVE_ASPECT_RATE_16_9 = 0x0A,
265 ACTIVE_ASPECT_RATE_14_9 = 0x0B,
268 #define HDMI_HDCP_CTRL 0x52
269 #define m_HDMI_DVI (1 << 1)
270 #define v_HDMI_DVI(n) (n << 1)
272 #define HDMI_INTERRUPT_MASK1 0xc0
273 #define HDMI_INTERRUPT_STATUS1 0xc1
274 #define m_INT_ACTIVE_VSYNC (1 << 5)
275 #define m_INT_EDID_READY (1 << 2)
277 #define HDMI_INTERRUPT_MASK2 0xc2
278 #define HDMI_INTERRUPT_STATUS2 0xc3
279 #define m_INT_HDCP_ERR (1 << 7)
280 #define m_INT_BKSV_FLAG (1 << 6)
281 #define m_INT_HDCP_OK (1 << 4)
283 #define HDMI_STATUS 0xc8
284 #define m_HOTPLUG (1 << 7)
285 #define m_MASK_INT_HOTPLUG (1 << 5)
286 #define m_INT_HOTPLUG (1 << 1)
287 #define v_MASK_INT_HOTPLUG(n) ((n & 0x1) << 5)
289 #define HDMI_COLORBAR 0xc9
291 #define HDMI_PHY_SYNC 0xce
292 #define HDMI_PHY_SYS_CTL 0xe0
293 #define m_TMDS_CLK_SOURCE (1 << 5)
294 #define v_TMDS_FROM_PLL (0 << 5)
295 #define v_TMDS_FROM_GEN (1 << 5)
296 #define m_PHASE_CLK (1 << 4)
297 #define v_DEFAULT_PHASE (0 << 4)
298 #define v_SYNC_PHASE (1 << 4)
299 #define m_TMDS_CURRENT_PWR (1 << 3)
300 #define v_TURN_ON_CURRENT (0 << 3)
301 #define v_CAT_OFF_CURRENT (1 << 3)
302 #define m_BANDGAP_PWR (1 << 2)
303 #define v_BANDGAP_PWR_UP (0 << 2)
304 #define v_BANDGAP_PWR_DOWN (1 << 2)
305 #define m_PLL_PWR (1 << 1)
306 #define v_PLL_PWR_UP (0 << 1)
307 #define v_PLL_PWR_DOWN (1 << 1)
308 #define m_TMDS_CHG_PWR (1 << 0)
309 #define v_TMDS_CHG_PWR_UP (0 << 0)
310 #define v_TMDS_CHG_PWR_DOWN (1 << 0)
312 #define HDMI_PHY_CHG_PWR 0xe1
313 #define v_CLK_CHG_PWR(n) ((n & 1) << 3)
314 #define v_DATA_CHG_PWR(n) ((n & 7) << 0)
316 #define HDMI_PHY_DRIVER 0xe2
317 #define v_CLK_MAIN_DRIVER(n) (n << 4)
318 #define v_DATA_MAIN_DRIVER(n) (n << 0)
320 #define HDMI_PHY_PRE_EMPHASIS 0xe3
321 #define v_PRE_EMPHASIS(n) ((n & 7) << 4)
322 #define v_CLK_PRE_DRIVER(n) ((n & 3) << 2)
323 #define v_DATA_PRE_DRIVER(n) ((n & 3) << 0)
325 #define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW 0xe7
326 #define v_FEEDBACK_DIV_LOW(n) (n & 0xff)
327 #define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH 0xe8
328 #define v_FEEDBACK_DIV_HIGH(n) (n & 1)
330 #define HDMI_PHY_PRE_DIV_RATIO 0xed
331 #define v_PRE_DIV_RATIO(n) (n & 0x1f)
333 #define HDMI_CEC_CTRL 0xd0
334 #define m_ADJUST_FOR_HISENSE (1 << 6)
335 #define m_REJECT_RX_BROADCAST (1 << 5)
336 #define m_BUSFREETIME_ENABLE (1 << 2)
337 #define m_REJECT_RX (1 << 1)
338 #define m_START_TX (1 << 0)
340 #define HDMI_CEC_DATA 0xd1
341 #define HDMI_CEC_TX_OFFSET 0xd2
342 #define HDMI_CEC_RX_OFFSET 0xd3
343 #define HDMI_CEC_CLK_H 0xd4
344 #define HDMI_CEC_CLK_L 0xd5
345 #define HDMI_CEC_TX_LENGTH 0xd6
346 #define HDMI_CEC_RX_LENGTH 0xd7
347 #define HDMI_CEC_TX_INT_MASK 0xd8
348 #define m_TX_DONE (1 << 3)
349 #define m_TX_NOACK (1 << 2)
350 #define m_TX_BROADCAST_REJ (1 << 1)
351 #define m_TX_BUSNOTFREE (1 << 0)
353 #define HDMI_CEC_RX_INT_MASK 0xd9
354 #define m_RX_LA_ERR (1 << 4)
355 #define m_RX_GLITCH (1 << 3)
356 #define m_RX_DONE (1 << 0)
358 #define HDMI_CEC_TX_INT 0xda
359 #define HDMI_CEC_RX_INT 0xdb
360 #define HDMI_CEC_BUSFREETIME_L 0xdc
361 #define HDMI_CEC_BUSFREETIME_H 0xdd
362 #define HDMI_CEC_LOGICADDR 0xde
364 #endif /* __INNO_HDMI_H__ */