drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15
  16 #include <drm/drm_of.h>
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_edid.h>
  20 #include <drm/drm_encoder_slave.h>
  21 #include <drm/bridge/dw_hdmi.h>
  22
  23 #include "rockchip_drm_drv.h"
  24 #include "rockchip_drm_vop.h"
  25
  26 #define RK3288_GRF_SOC_CON6             0x025C
  27 #define RK3288_HDMI_LCDC_SEL            BIT(4)
  28 #define RK3399_GRF_SOC_CON20            0x6250
  29 #define RK3399_HDMI_LCDC_SEL            BIT(6)
  30
  31 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
  32
  33 struct rockchip_hdmi {
  34         struct device *dev;
  35         struct regmap *regmap;
  36         struct drm_encoder encoder;
  37         enum dw_hdmi_devtype dev_type;
  38         struct clk *vpll_clk;
  39 };
  40
  41 #define to_rockchip_hdmi(x)     container_of(x, struct rockchip_hdmi, x)
  42
  43 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
  44         {
  45                 30666000, {
  46                         { 0x00b3, 0x0000 },
  47                         { 0x2153, 0x0000 },
  48                         { 0x40f3, 0x0000 },
  49                 },
  50         },  {
  51                 36800000, {
  52                         { 0x00b3, 0x0000 },
  53                         { 0x2153, 0x0000 },
  54                         { 0x40a2, 0x0001 },
  55                 },
  56         },  {
  57                 46000000, {
  58                         { 0x00b3, 0x0000 },
  59                         { 0x2142, 0x0001 },
  60                         { 0x40a2, 0x0001 },
  61                 },
  62         },  {
  63                 61333000, {
  64                         { 0x0072, 0x0001 },
  65                         { 0x2142, 0x0001 },
  66                         { 0x40a2, 0x0001 },
  67                 },
  68         },  {
  69                 73600000, {
  70                         { 0x0072, 0x0001 },
  71                         { 0x2142, 0x0001 },
  72                         { 0x4061, 0x0002 },
  73                 },
  74         },  {
  75                 92000000, {
  76                         { 0x0072, 0x0001 },
  77                         { 0x2145, 0x0002 },
  78                         { 0x4061, 0x0002 },
  79                 },
  80         },  {
  81                 122666000, {
  82                         { 0x0051, 0x0002 },
  83                         { 0x2145, 0x0002 },
  84                         { 0x4061, 0x0002 },
  85                 },
  86         },  {
  87                 147200000, {
  88                         { 0x0051, 0x0002 },
  89                         { 0x2145, 0x0002 },
  90                         { 0x4064, 0x0003 },
  91                 },
  92         },  {
  93                 184000000, {
  94                         { 0x0051, 0x0002 },
  95                         { 0x214c, 0x0003 },
  96                         { 0x4064, 0x0003 },
  97                 },
  98         },  {
  99                 226666000, {
 100                         { 0x0040, 0x0003 },
 101                         { 0x214c, 0x0003 },
 102                         { 0x4064, 0x0003 },
 103                 },
 104         },  {
 105                 272000000, {
 106                         { 0x0040, 0x0003 },
 107                         { 0x214c, 0x0003 },
 108                         { 0x5a64, 0x0003 },
 109                 },
 110         },  {
 111                 340000000, {
 112                         { 0x0040, 0x0003 },
 113                         { 0x3b4c, 0x0003 },
 114                         { 0x5a64, 0x0003 },
 115                 },
 116         },  {
 117                 600000000, {
 118                         { 0x1a40, 0x0003 },
 119                         { 0x3b4c, 0x0003 },
 120                         { 0x5a64, 0x0003 },
 121                 },
 122         },  {
 123                 ~0UL, {
 124                         { 0x0000, 0x0000 },
 125                         { 0x0000, 0x0000 },
 126                         { 0x0000, 0x0000 },
 127                 },
 128         }
 129 };
 130
 131 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
 132         /*      pixelclk    bpp8    bpp10   bpp12 */
 133         {
 134                 600000000, { 0x0000, 0x0000, 0x0000 },
 135         },  {
 136                 ~0UL,      { 0x0000, 0x0000, 0x0000},
 137         }
 138 };
 139
 140 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
 141         /*pixelclk   symbol   term   vlev*/
 142         { 74250000,  0x8009, 0x0004, 0x0272},
 143         { 165000000, 0x802b, 0x0004, 0x0209},
 144         { 297000000, 0x8039, 0x0005, 0x028d},
 145         { ~0UL,      0x0000, 0x0000, 0x0000}
 146 };
 147
 148 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
 149 {
 150         struct device_node *np = hdmi->dev->of_node;
 151         int ret;
 152
 153         hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 154         if (IS_ERR(hdmi->regmap)) {
 155                 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
 156                 return PTR_ERR(hdmi->regmap);
 157         }
 158
 159         hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
 160         if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
 161                 hdmi->vpll_clk = NULL;
 162         } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
 163                 return -EPROBE_DEFER;
 164         } else if (IS_ERR(hdmi->vpll_clk)) {
 165                 dev_err(hdmi->dev, "failed to get grf clock\n");
 166                 return PTR_ERR(hdmi->vpll_clk);
 167         }
 168
 169         ret = clk_prepare_enable(hdmi->vpll_clk);
 170         if (ret) {
 171                 dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
 172                 return ret;
 173         }
 174
 175         return 0;
 176 }
 177
 178 static enum drm_mode_status
 179 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
 180                             struct drm_display_mode *mode)
 181 {
 182         const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
 183         int pclk = mode->clock * 1000;
 184         bool valid = false;
 185         int i;
 186
 187         for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
 188                 if (pclk == mpll_cfg[i].mpixelclock) {
 189                         valid = true;
 190                         break;
 191                 }
 192         }
 193
 194         return (valid) ? MODE_OK : MODE_BAD;
 195 }
 196
 197 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
 198         .destroy = drm_encoder_cleanup,
 199 };
 200
 201 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
 202 {
 203 }
 204
 205 static bool
 206 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
 207                                     const struct drm_display_mode *mode,
 208                                     struct drm_display_mode *adj_mode)
 209 {
 210         return true;
 211 }
 212
 213 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
 214                                               struct drm_display_mode *mode,
 215                                               struct drm_display_mode *adj_mode)
 216 {
 217         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 218
 219         clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
 220 }
 221
 222 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
 223 {
 224         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 225         u32 lcdsel_grf_reg, lcdsel_mask;
 226         u32 val;
 227         int mux;
 228
 229         switch (hdmi->dev_type) {
 230         case RK3288_HDMI:
 231                 lcdsel_grf_reg = RK3288_GRF_SOC_CON6;
 232                 lcdsel_mask = RK3288_HDMI_LCDC_SEL;
 233                 break;
 234         case RK3399_HDMI:
 235                 lcdsel_grf_reg = RK3399_GRF_SOC_CON20;
 236                 lcdsel_mask = RK3399_HDMI_LCDC_SEL;
 237                 break;
 238         default:
 239                 return;
 240         };
 241
 242         mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
 243         if (mux)
 244                 val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask);
 245         else
 246                 val = HIWORD_UPDATE(0, lcdsel_mask);
 247
 248         regmap_write(hdmi->regmap, lcdsel_grf_reg, val);
 249         dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
 250                 (mux) ? "LIT" : "BIG");
 251 }
 252
 253 static int
 254 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
 255                                       struct drm_crtc_state *crtc_state,
 256                                       struct drm_connector_state *conn_state)
 257 {
 258         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 259
 260         s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
 261         s->output_type = DRM_MODE_CONNECTOR_HDMIA;
 262
 263         return 0;
 264 }
 265
 266 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
 267         .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
 268         .mode_set   = dw_hdmi_rockchip_encoder_mode_set,
 269         .enable     = dw_hdmi_rockchip_encoder_enable,
 270         .disable    = dw_hdmi_rockchip_encoder_disable,
 271         .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
 272 };
 273
 274 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
 275         .mode_valid = dw_hdmi_rockchip_mode_valid,
 276         .mpll_cfg   = rockchip_mpll_cfg,
 277         .cur_ctr    = rockchip_cur_ctr,
 278         .phy_config = rockchip_phy_config,
 279         .dev_type   = RK3288_HDMI,
 280 };
 281
 282 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
 283         .mode_valid = dw_hdmi_rockchip_mode_valid,
 284         .mpll_cfg   = rockchip_mpll_cfg,
 285         .cur_ctr    = rockchip_cur_ctr,
 286         .phy_config = rockchip_phy_config,
 287         .dev_type   = RK3399_HDMI,
 288 };
 289
 290 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
 291         { .compatible = "rockchip,rk3288-dw-hdmi",
 292           .data = &rk3288_hdmi_drv_data
 293         },
 294         { .compatible = "rockchip,rk3399-dw-hdmi",
 295           .data = &rk3399_hdmi_drv_data
 296         },
 297         {},
 298 };
 299 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
 300
 301 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 302                                  void *data)
 303 {
 304         struct platform_device *pdev = to_platform_device(dev);
 305         const struct dw_hdmi_plat_data *plat_data;
 306         const struct of_device_id *match;
 307         struct drm_device *drm = data;
 308         struct drm_encoder *encoder;
 309         struct rockchip_hdmi *hdmi;
 310         struct resource *iores;
 311         int irq;
 312         int ret;
 313
 314         if (!pdev->dev.of_node)
 315                 return -ENODEV;
 316
 317         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
 318         if (!hdmi)
 319                 return -ENOMEM;
 320
 321         match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
 322         plat_data = match->data;
 323         hdmi->dev = &pdev->dev;
 324         hdmi->dev_type = plat_data->dev_type;
 325         encoder = &hdmi->encoder;
 326
 327         irq = platform_get_irq(pdev, 0);
 328         if (irq < 0)
 329                 return irq;
 330
 331         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 332         if (!iores)
 333                 return -ENXIO;
 334
 335         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 336         /*
 337          * If we failed to find the CRTC(s) which this encoder is
 338          * supposed to be connected to, it's because the CRTC has
 339          * not been registered yet.  Defer probing, and hope that
 340          * the required CRTC is added later.
 341          */
 342         if (encoder->possible_crtcs == 0)
 343                 return -EPROBE_DEFER;
 344
 345         ret = rockchip_hdmi_parse_dt(hdmi);
 346         if (ret) {
 347                 dev_err(hdmi->dev, "Unable to parse OF data\n");
 348                 return ret;
 349         }
 350
 351         drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
 352         drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
 353                          DRM_MODE_ENCODER_TMDS, NULL);
 354
 355         ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
 356
 357         /*
 358          * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
 359          * which would have called the encoder cleanup.  Do it manually.
 360          */
 361         if (ret)
 362                 drm_encoder_cleanup(encoder);
 363
 364         return ret;
 365 }
 366
 367 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
 368                                     void *data)
 369 {
 370         return dw_hdmi_unbind(dev, master, data);
 371 }
 372
 373 static const struct component_ops dw_hdmi_rockchip_ops = {
 374         .bind   = dw_hdmi_rockchip_bind,
 375         .unbind = dw_hdmi_rockchip_unbind,
 376 };
 377
 378 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
 379 {
 380         return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
 381 }
 382
 383 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
 384 {
 385         component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
 386
 387         return 0;
 388 }
 389
 390 static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
 391         .probe  = dw_hdmi_rockchip_probe,
 392         .remove = dw_hdmi_rockchip_remove,
 393         .driver = {
 394                 .name = "dwhdmi-rockchip",
 395                 .of_match_table = dw_hdmi_rockchip_dt_ids,
 396         },
 397 };
 398
 399 module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
 400
 401 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
 402 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
 403 MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
 404 MODULE_LICENSE("GPL");
 405 MODULE_ALIAS("platform:dwhdmi-rockchip");