2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/clk.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
16 #include <drm/drm_of.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_edid.h>
20 #include <drm/drm_encoder_slave.h>
21 #include <drm/bridge/dw_hdmi.h>
23 #include "rockchip_drm_drv.h"
24 #include "rockchip_drm_vop.h"
26 #define RK3288_GRF_SOC_CON6 0x025C
27 #define RK3288_HDMI_LCDC_SEL BIT(4)
28 #define RK3399_GRF_SOC_CON20 0x6250
29 #define RK3399_HDMI_LCDC_SEL BIT(6)
31 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
33 struct rockchip_hdmi {
35 struct regmap *regmap;
36 struct drm_encoder encoder;
37 enum dw_hdmi_devtype dev_type;
42 #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
45 * There are some rates that would be ranged for better clock jitter at
46 * Chrome OS tree, like 25.175Mhz would range to 25.170732Mhz. But due
47 * to the clock is aglined to KHz in struct drm_display_mode, this would
48 * bring some inaccurate error if we still run the compute_n math, so
49 * let's just code an const table for it until we can actually get the
52 static const struct dw_hdmi_audio_tmds_n rockchip_werid_tmds_n_table[] = {
53 /* 25176471 for 25.175 MHz = 428000000 / 17. */
54 { .tmds = 25177000, .n_32k = 4352, .n_44k1 = 14994, .n_48k = 6528, },
55 /* 57290323 for 57.284 MHz */
56 { .tmds = 57291000, .n_32k = 3968, .n_44k1 = 4557, .n_48k = 5952, },
57 /* 74437500 for 74.44 MHz = 297750000 / 4 */
58 { .tmds = 74438000, .n_32k = 8192, .n_44k1 = 18816, .n_48k = 4096, },
59 /* 118666667 for 118.68 MHz */
60 { .tmds = 118667000, .n_32k = 4224, .n_44k1 = 5292, .n_48k = 6336, },
61 /* 121714286 for 121.75 MHz */
62 { .tmds = 121715000, .n_32k = 4480, .n_44k1 = 6174, .n_48k = 6272, },
63 /* 136800000 for 136.75 MHz */
64 { .tmds = 136800000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
66 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
69 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
157 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
158 /* pixelclk bpp8 bpp10 bpp12 */
160 600000000, { 0x0000, 0x0000, 0x0000 },
162 ~0UL, { 0x0000, 0x0000, 0x0000},
166 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
167 /*pixelclk symbol term vlev*/
168 { 74250000, 0x8009, 0x0004, 0x0272},
169 { 165000000, 0x802b, 0x0004, 0x0209},
170 { 297000000, 0x8039, 0x0005, 0x028d},
171 { 594000000, 0x8039, 0x0000, 0x019d},
172 { ~0UL, 0x0000, 0x0000, 0x0000}
175 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
177 struct device_node *np = hdmi->dev->of_node;
180 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
181 if (IS_ERR(hdmi->regmap)) {
182 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
183 return PTR_ERR(hdmi->regmap);
186 hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
187 if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
188 hdmi->vpll_clk = NULL;
189 } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
190 return -EPROBE_DEFER;
191 } else if (IS_ERR(hdmi->vpll_clk)) {
192 dev_err(hdmi->dev, "failed to get grf clock\n");
193 return PTR_ERR(hdmi->vpll_clk);
196 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
197 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
198 hdmi->grf_clk = NULL;
199 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
200 return -EPROBE_DEFER;
201 } else if (IS_ERR(hdmi->grf_clk)) {
202 dev_err(hdmi->dev, "failed to get grf clock\n");
203 return PTR_ERR(hdmi->grf_clk);
206 ret = clk_prepare_enable(hdmi->vpll_clk);
208 dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
215 static enum drm_mode_status
216 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
217 struct drm_display_mode *mode)
219 struct drm_encoder *encoder = connector->encoder;
220 enum drm_mode_status status = MODE_OK;
221 struct drm_device *dev = connector->dev;
222 struct rockchip_drm_private *priv = dev->dev_private;
223 struct drm_crtc *crtc;
226 * Pixel clocks we support are always < 2GHz and so fit in an
227 * int. We should make sure source rate does too so we don't get
228 * overflow when we multiply by 1000.
230 if (mode->clock > INT_MAX / 1000)
234 const struct drm_connector_helper_funcs *funcs;
236 funcs = connector->helper_private;
237 if (funcs->atomic_best_encoder)
238 encoder = funcs->atomic_best_encoder(connector,
241 encoder = funcs->best_encoder(connector);
244 if (!encoder || !encoder->possible_crtcs)
247 * ensure all drm display mode can work, if someone want support more
248 * resolutions, please limit the possible_crtc, only connect to
251 drm_for_each_crtc(crtc, connector->dev) {
252 int pipe = drm_crtc_index(crtc);
253 const struct rockchip_crtc_funcs *funcs =
254 priv->crtc_funcs[pipe];
256 if (!(encoder->possible_crtcs & drm_crtc_mask(crtc)))
258 if (!funcs || !funcs->mode_valid)
261 status = funcs->mode_valid(crtc, mode,
262 DRM_MODE_CONNECTOR_HDMIA);
263 if (status != MODE_OK)
270 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
271 .destroy = drm_encoder_cleanup,
274 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
278 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
280 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
281 struct drm_crtc *crtc = encoder->crtc;
282 u32 lcdsel_grf_reg, lcdsel_mask;
287 if (WARN_ON(!crtc || !crtc->state))
290 clk_set_rate(hdmi->vpll_clk,
291 crtc->state->adjusted_mode.crtc_clock * 1000);
293 switch (hdmi->dev_type) {
295 lcdsel_grf_reg = RK3288_GRF_SOC_CON6;
296 lcdsel_mask = RK3288_HDMI_LCDC_SEL;
299 lcdsel_grf_reg = RK3399_GRF_SOC_CON20;
300 lcdsel_mask = RK3399_HDMI_LCDC_SEL;
306 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
308 val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask);
310 val = HIWORD_UPDATE(0, lcdsel_mask);
312 ret = clk_prepare_enable(hdmi->grf_clk);
314 dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
318 regmap_write(hdmi->regmap, lcdsel_grf_reg, val);
319 dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
320 (mux) ? "LIT" : "BIG");
322 clk_disable_unprepare(hdmi->grf_clk);
326 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
327 struct drm_crtc_state *crtc_state,
328 struct drm_connector_state *conn_state)
330 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
332 if (crtc_state->mode.flags & DRM_MODE_FLAG_420_MASK) {
333 s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
334 s->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
336 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
337 s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
339 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
344 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
345 .enable = dw_hdmi_rockchip_encoder_enable,
346 .disable = dw_hdmi_rockchip_encoder_disable,
347 .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
350 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
351 .mode_valid = dw_hdmi_rockchip_mode_valid,
352 .mpll_cfg = rockchip_mpll_cfg,
353 .cur_ctr = rockchip_cur_ctr,
354 .phy_config = rockchip_phy_config,
355 .dev_type = RK3288_HDMI,
356 .tmds_n_table = rockchip_werid_tmds_n_table,
359 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
360 .mode_valid = dw_hdmi_rockchip_mode_valid,
361 .mpll_cfg = rockchip_mpll_cfg,
362 .cur_ctr = rockchip_cur_ctr,
363 .phy_config = rockchip_phy_config,
364 .dev_type = RK3399_HDMI,
367 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
368 { .compatible = "rockchip,rk3288-dw-hdmi",
369 .data = &rk3288_hdmi_drv_data
371 { .compatible = "rockchip,rk3399-dw-hdmi",
372 .data = &rk3399_hdmi_drv_data
376 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
378 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
381 struct platform_device *pdev = to_platform_device(dev);
382 const struct dw_hdmi_plat_data *plat_data;
383 const struct of_device_id *match;
384 struct drm_device *drm = data;
385 struct drm_encoder *encoder;
386 struct rockchip_hdmi *hdmi;
387 struct resource *iores;
391 if (!pdev->dev.of_node)
394 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
398 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
399 plat_data = match->data;
400 hdmi->dev = &pdev->dev;
401 hdmi->dev_type = plat_data->dev_type;
402 encoder = &hdmi->encoder;
404 irq = platform_get_irq(pdev, 0);
408 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
412 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
414 * If we failed to find the CRTC(s) which this encoder is
415 * supposed to be connected to, it's because the CRTC has
416 * not been registered yet. Defer probing, and hope that
417 * the required CRTC is added later.
419 if (encoder->possible_crtcs == 0)
420 return -EPROBE_DEFER;
422 ret = rockchip_hdmi_parse_dt(hdmi);
424 dev_err(hdmi->dev, "Unable to parse OF data\n");
428 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
429 drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
430 DRM_MODE_ENCODER_TMDS, NULL);
432 ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
435 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
436 * which would have called the encoder cleanup. Do it manually.
439 drm_encoder_cleanup(encoder);
444 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
447 return dw_hdmi_unbind(dev, master, data);
450 static const struct component_ops dw_hdmi_rockchip_ops = {
451 .bind = dw_hdmi_rockchip_bind,
452 .unbind = dw_hdmi_rockchip_unbind,
455 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
457 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
460 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
462 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
467 static int dw_hdmi_rockchip_suspend(struct device *dev)
469 dw_hdmi_suspend(dev);
474 static int dw_hdmi_rockchip_resume(struct device *dev)
481 static const struct dev_pm_ops dw_hdmi_pm_ops = {
482 SET_SYSTEM_SLEEP_PM_OPS(dw_hdmi_rockchip_suspend,
483 dw_hdmi_rockchip_resume)
486 static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
487 .probe = dw_hdmi_rockchip_probe,
488 .remove = dw_hdmi_rockchip_remove,
490 .name = "dwhdmi-rockchip",
491 .of_match_table = dw_hdmi_rockchip_dt_ids,
492 .pm = &dw_hdmi_pm_ops,
496 module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
498 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
499 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
500 MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
501 MODULE_LICENSE("GPL");
502 MODULE_ALIAS("platform:dwhdmi-rockchip");