drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drmP.h>
  27 #include <video/mipi_display.h>
  28 #include <asm/unaligned.h>
  29
  30 #include "rockchip_drm_drv.h"
  31 #include "rockchip_drm_vop.h"
  32
  33 #define DRIVER_NAME    "dw-mipi-dsi"
  34
  35 #define RK3288_GRF_SOC_CON6             0x025c
  36 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  37 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  38
  39 #define RK3366_GRF_SOC_CON0             0x0400
  40 #define RK3366_DSI_SEL_VOP_LIT          BIT(2)
  41
  42 #define RK3399_GRF_SOC_CON19            0x6250
  43 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  44 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  45
  46 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  47 #define RK3399_GRF_SOC_CON22            0x6258
  48 #define RK3399_GRF_DSI_MODE             0xffff0000
  49
  50 #define DSI_VERSION                     0x00
  51 #define DSI_PWR_UP                      0x04
  52 #define RESET                           0
  53 #define POWERUP                         BIT(0)
  54
  55 #define DSI_CLKMGR_CFG                  0x08
  56 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  57 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  58
  59 #define DSI_DPI_VCID                    0x0c
  60 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  61
  62 #define DSI_DPI_COLOR_CODING            0x10
  63 #define EN18_LOOSELY                    BIT(8)
  64 #define DPI_COLOR_CODING_16BIT_1        0x0
  65 #define DPI_COLOR_CODING_16BIT_2        0x1
  66 #define DPI_COLOR_CODING_16BIT_3        0x2
  67 #define DPI_COLOR_CODING_18BIT_1        0x3
  68 #define DPI_COLOR_CODING_18BIT_2        0x4
  69 #define DPI_COLOR_CODING_24BIT          0x5
  70
  71 #define DSI_DPI_CFG_POL                 0x14
  72 #define COLORM_ACTIVE_LOW               BIT(4)
  73 #define SHUTD_ACTIVE_LOW                BIT(3)
  74 #define HSYNC_ACTIVE_LOW                BIT(2)
  75 #define VSYNC_ACTIVE_LOW                BIT(1)
  76 #define DATAEN_ACTIVE_LOW               BIT(0)
  77
  78 #define DSI_DPI_LP_CMD_TIM              0x18
  79 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  80 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  81
  82 #define DSI_DBI_CFG                     0x20
  83 #define DSI_DBI_CMDSIZE                 0x28
  84
  85 #define DSI_PCKHDL_CFG                  0x2c
  86 #define EN_CRC_RX                       BIT(4)
  87 #define EN_ECC_RX                       BIT(3)
  88 #define EN_BTA                          BIT(2)
  89 #define EN_EOTP_RX                      BIT(1)
  90 #define EN_EOTP_TX                      BIT(0)
  91
  92 #define DSI_MODE_CFG                    0x34
  93 #define ENABLE_VIDEO_MODE               0
  94 #define ENABLE_CMD_MODE                 BIT(0)
  95
  96 #define DSI_VID_MODE_CFG                0x38
  97 #define VPG_EN                          BIT(16)
  98 #define FRAME_BTA_ACK                   BIT(14)
  99 #define LP_HFP_EN                       BIT(13)
 100 #define LP_HBP_EN                       BIT(12)
 101 #define ENABLE_LOW_POWER                (0xf << 8)
 102 #define ENABLE_LOW_POWER_MASK           (0xf << 8)
 103 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
 104 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
 105 #define VID_MODE_TYPE_BURST             0x2
 106
 107 #define DSI_VID_PKT_SIZE                0x3c
 108 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 109 #define VID_PKT_MAX_SIZE                0x3fff
 110
 111 #define DSI_VID_NUM_CHUMKS              0x40
 112 #define DSI_VID_NULL_PKT_SIZE           0x44
 113 #define DSI_VID_HSA_TIME                0x48
 114 #define DSI_VID_HBP_TIME                0x4c
 115 #define DSI_VID_HLINE_TIME              0x50
 116 #define DSI_VID_VSA_LINES               0x54
 117 #define DSI_VID_VBP_LINES               0x58
 118 #define DSI_VID_VFP_LINES               0x5c
 119 #define DSI_VID_VACTIVE_LINES           0x60
 120 #define DSI_CMD_MODE_CFG                0x68
 121 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 122 #define DCS_LW_TX_LP                    BIT(19)
 123 #define DCS_SR_0P_TX_LP                 BIT(18)
 124 #define DCS_SW_1P_TX_LP                 BIT(17)
 125 #define DCS_SW_0P_TX_LP                 BIT(16)
 126 #define GEN_LW_TX_LP                    BIT(14)
 127 #define GEN_SR_2P_TX_LP                 BIT(13)
 128 #define GEN_SR_1P_TX_LP                 BIT(12)
 129 #define GEN_SR_0P_TX_LP                 BIT(11)
 130 #define GEN_SW_2P_TX_LP                 BIT(10)
 131 #define GEN_SW_1P_TX_LP                 BIT(9)
 132 #define GEN_SW_0P_TX_LP                 BIT(8)
 133 #define EN_ACK_RQST                     BIT(1)
 134 #define EN_TEAR_FX                      BIT(0)
 135
 136 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 137                                          DCS_LW_TX_LP | \
 138                                          DCS_SR_0P_TX_LP | \
 139                                          DCS_SW_1P_TX_LP | \
 140                                          DCS_SW_0P_TX_LP | \
 141                                          GEN_LW_TX_LP | \
 142                                          GEN_SR_2P_TX_LP | \
 143                                          GEN_SR_1P_TX_LP | \
 144                                          GEN_SR_0P_TX_LP | \
 145                                          GEN_SW_2P_TX_LP | \
 146                                          GEN_SW_1P_TX_LP | \
 147                                          GEN_SW_0P_TX_LP)
 148
 149 #define DSI_GEN_HDR                     0x6c
 150 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 151 #define GEN_HDATA_MASK                  (0xffff << 8)
 152 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 153 #define GEN_HTYPE_MASK                  0xff
 154
 155 #define DSI_GEN_PLD_DATA                0x70
 156
 157 #define DSI_CMD_PKT_STATUS              0x74
 158 #define GEN_CMD_EMPTY                   BIT(0)
 159 #define GEN_CMD_FULL                    BIT(1)
 160 #define GEN_PLD_W_EMPTY                 BIT(2)
 161 #define GEN_PLD_W_FULL                  BIT(3)
 162 #define GEN_PLD_R_EMPTY                 BIT(4)
 163 #define GEN_PLD_R_FULL                  BIT(5)
 164 #define GEN_RD_CMD_BUSY                 BIT(6)
 165
 166 #define DSI_TO_CNT_CFG                  0x78
 167 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 168 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 169
 170 #define DSI_BTA_TO_CNT                  0x8c
 171 #define DSI_LPCLK_CTRL                  0x94
 172 #define AUTO_CLKLANE_CTRL               BIT(1)
 173 #define PHY_TXREQUESTCLKHS              BIT(0)
 174
 175 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 176 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 177 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 178
 179 #define DSI_PHY_TMR_CFG                 0x9c
 180 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 181 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 182 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 183
 184 #define DSI_PHY_RSTZ                    0xa0
 185 #define PHY_DISFORCEPLL                 0
 186 #define PHY_ENFORCEPLL                  BIT(3)
 187 #define PHY_DISABLECLK                  0
 188 #define PHY_ENABLECLK                   BIT(2)
 189 #define PHY_RSTZ                        0
 190 #define PHY_UNRSTZ                      BIT(1)
 191 #define PHY_SHUTDOWNZ                   0
 192 #define PHY_UNSHUTDOWNZ                 BIT(0)
 193
 194 #define DSI_PHY_IF_CFG                  0xa4
 195 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 196 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 197
 198 #define DSI_PHY_STATUS                  0xb0
 199 #define LOCK                            BIT(0)
 200 #define STOP_STATE_CLK_LANE             BIT(2)
 201
 202 #define DSI_PHY_TST_CTRL0               0xb4
 203 #define PHY_TESTCLK                     BIT(1)
 204 #define PHY_UNTESTCLK                   0
 205 #define PHY_TESTCLR                     BIT(0)
 206 #define PHY_UNTESTCLR                   0
 207
 208 #define DSI_PHY_TST_CTRL1               0xb8
 209 #define PHY_TESTEN                      BIT(16)
 210 #define PHY_UNTESTEN                    0
 211 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 212 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 213
 214 #define DSI_INT_ST0                     0xbc
 215 #define DSI_INT_ST1                     0xc0
 216 #define DSI_INT_MSK0                    0xc4
 217 #define DSI_INT_MSK1                    0xc8
 218
 219 #define PHY_STATUS_TIMEOUT_US           10000
 220 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 221
 222 #define BYPASS_VCO_RANGE        BIT(7)
 223 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 224 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 225 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 226 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 227 #define REF_BIAS_CUR_SEL        BIT(0)
 228
 229 #define CP_CURRENT_3MA          BIT(3)
 230 #define CP_PROGRAM_EN           BIT(7)
 231 #define LPF_PROGRAM_EN          BIT(6)
 232 #define LPF_RESISTORS_20_KOHM   0
 233
 234 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 235
 236 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 237 #define LOW_PROGRAM_EN          0
 238 #define HIGH_PROGRAM_EN         BIT(7)
 239 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 240 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 241 #define PLL_LOOP_DIV_EN         BIT(5)
 242 #define PLL_INPUT_DIV_EN        BIT(4)
 243
 244 #define POWER_CONTROL           BIT(6)
 245 #define INTERNAL_REG_CURRENT    BIT(3)
 246 #define BIAS_BLOCK_ON           BIT(2)
 247 #define BANDGAP_ON              BIT(0)
 248
 249 #define TER_RESISTOR_HIGH       BIT(7)
 250 #define TER_RESISTOR_LOW        0
 251 #define LEVEL_SHIFTERS_ON       BIT(6)
 252 #define TER_CAL_DONE            BIT(5)
 253 #define SETRD_MAX               (0x7 << 2)
 254 #define POWER_MANAGE            BIT(1)
 255 #define TER_RESISTORS_ON        BIT(0)
 256
 257 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 258 #define BANDGAP_SEL(val)        ((val) & 0x7)
 259 #define TLP_PROGRAM_EN          BIT(7)
 260 #define THS_PRE_PROGRAM_EN      BIT(7)
 261 #define THS_ZERO_PROGRAM_EN     BIT(6)
 262
 263 enum {
 264         BANDGAP_97_07,
 265         BANDGAP_98_05,
 266         BANDGAP_99_02,
 267         BANDGAP_100_00,
 268         BANDGAP_93_17,
 269         BANDGAP_94_15,
 270         BANDGAP_95_12,
 271         BANDGAP_96_10,
 272 };
 273
 274 enum {
 275         BIASEXTR_87_1,
 276         BIASEXTR_91_5,
 277         BIASEXTR_95_9,
 278         BIASEXTR_100,
 279         BIASEXTR_105_94,
 280         BIASEXTR_111_88,
 281         BIASEXTR_118_8,
 282         BIASEXTR_127_7,
 283 };
 284
 285 struct dw_mipi_dsi_plat_data {
 286         u32 dsi0_en_bit;
 287         u32 dsi1_en_bit;
 288         u32 grf_switch_reg;
 289         u32 grf_dsi0_mode;
 290         u32 grf_dsi0_mode_reg;
 291         unsigned int max_data_lanes;
 292         u32 max_bit_rate_per_lane;
 293         bool has_vop_sel;
 294         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 295                                            struct drm_display_mode *mode);
 296 };
 297
 298 struct mipi_dphy {
 299         /* SNPS PHY */
 300         struct clk *cfg_clk;
 301         struct clk *ref_clk;
 302         u16 input_div;
 303         u16 feedback_div;
 304
 305         /* Non-SNPS PHY */
 306         struct phy *phy;
 307         struct clk *hs_clk;
 308 };
 309
 310 struct dw_mipi_dsi {
 311         struct drm_encoder encoder;
 312         struct drm_connector connector;
 313         struct mipi_dsi_host dsi_host;
 314         struct mipi_dphy dphy;
 315         struct drm_panel *panel;
 316         struct device *dev;
 317         struct regmap *grf_regmap;
 318         struct reset_control *rst;
 319         void __iomem *base;
 320         struct clk *pclk;
 321
 322         unsigned long mode_flags;
 323         unsigned int lane_mbps; /* per lane */
 324         u32 channel;
 325         u32 lanes;
 326         u32 format;
 327         struct drm_display_mode mode;
 328
 329         const struct dw_mipi_dsi_plat_data *pdata;
 330 };
 331
 332 enum dw_mipi_dsi_mode {
 333         DSI_COMMAND_MODE,
 334         DSI_VIDEO_MODE,
 335 };
 336
 337 struct dphy_pll_testdin_map {
 338         unsigned int max_mbps;
 339         u8 testdin;
 340 };
 341
 342 /* The table is based on 27MHz DPHY pll reference clock. */
 343 static const struct dphy_pll_testdin_map dptdin_map[] = {
 344         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 345         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 346         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 347         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 348         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 349         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 350         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 351         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 352         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 353         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 354 };
 355
 356 static int max_mbps_to_testdin(unsigned int max_mbps)
 357 {
 358         int i;
 359
 360         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 361                 if (dptdin_map[i].max_mbps > max_mbps)
 362                         return dptdin_map[i].testdin;
 363
 364         return -EINVAL;
 365 }
 366
 367 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 368 {
 369         return container_of(host, struct dw_mipi_dsi, dsi_host);
 370 }
 371
 372 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 373 {
 374         return container_of(con, struct dw_mipi_dsi, connector);
 375 }
 376
 377 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 378 {
 379         return container_of(encoder, struct dw_mipi_dsi, encoder);
 380 }
 381 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 382 {
 383         writel(val, dsi->base + reg);
 384 }
 385
 386 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 387 {
 388         return readl(dsi->base + reg);
 389 }
 390
 391 static int rockchip_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi)
 392 {
 393         u32 sts;
 394         int ret;
 395
 396         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 397                                  sts, !(sts & GEN_PLD_W_FULL), 10,
 398                                  CMD_PKT_STATUS_TIMEOUT_US);
 399         if (ret < 0) {
 400                 dev_err(dsi->dev, "generic write payload fifo is full\n");
 401                 return ret;
 402         }
 403
 404         return 0;
 405 }
 406
 407 static int rockchip_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi)
 408 {
 409         u32 sts;
 410         int ret;
 411
 412         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 413                                  sts, !(sts & GEN_CMD_FULL), 10,
 414                                  CMD_PKT_STATUS_TIMEOUT_US);
 415         if (ret < 0) {
 416                 dev_err(dsi->dev, "generic write cmd fifo is full\n");
 417                 return ret;
 418         }
 419
 420         return 0;
 421 }
 422
 423 static int rockchip_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)
 424 {
 425         u32 sts;
 426         u32 mask;
 427         int ret;
 428
 429         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 430         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 431                                  sts, (sts & mask) == mask, 10,
 432                                  CMD_PKT_STATUS_TIMEOUT_US);
 433         if (ret < 0) {
 434                 dev_err(dsi->dev, "generic write fifo is full\n");
 435                 return ret;
 436         }
 437
 438         return 0;
 439 }
 440
 441 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 442                                  u8 test_data)
 443 {
 444         /*
 445          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 446          * is latched internally as the current test code. Test data is
 447          * programmed internally by rising edge on TESTCLK.
 448          */
 449         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 450
 451         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 452                                           PHY_TESTDIN(test_code));
 453
 454         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 455
 456         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 457                                           PHY_TESTDIN(test_data));
 458
 459         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 460 }
 461
 462 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 463 {
 464         int ret, testdin, vco, val;
 465
 466         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 467
 468         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 469         if (testdin < 0) {
 470                 dev_err(dsi->dev,
 471                         "failed to get testdin for %dmbps lane clock\n",
 472                         dsi->lane_mbps);
 473                 return testdin;
 474         }
 475
 476         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 477
 478         if (!IS_ERR(dsi->dphy.cfg_clk)) {
 479                 ret = clk_prepare_enable(dsi->dphy.cfg_clk);
 480                 if (ret) {
 481                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 482                         return ret;
 483                 }
 484         }
 485
 486         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 487                                          VCO_RANGE_CON_SEL(vco) |
 488                                          VCO_IN_CAP_CON_LOW |
 489                                          REF_BIAS_CUR_SEL);
 490
 491         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 492         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 493                                          LPF_RESISTORS_20_KOHM);
 494
 495         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 496
 497         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->dphy.input_div));
 498         val = LOOP_DIV_LOW_SEL(dsi->dphy.feedback_div) | LOW_PROGRAM_EN;
 499         dw_mipi_dsi_phy_write(dsi, 0x18, val);
 500         val = LOOP_DIV_HIGH_SEL(dsi->dphy.feedback_div) | HIGH_PROGRAM_EN;
 501         dw_mipi_dsi_phy_write(dsi, 0x18, val);
 502         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 503
 504         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 505                                          BIAS_BLOCK_ON | BANDGAP_ON);
 506
 507         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 508                                          SETRD_MAX | TER_RESISTORS_ON);
 509         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 510                                          SETRD_MAX | POWER_MANAGE |
 511                                          TER_RESISTORS_ON);
 512
 513         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 514                                          BIASEXTR_SEL(BIASEXTR_127_7));
 515         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 516                                          BANDGAP_SEL(BANDGAP_96_10));
 517
 518         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 519         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 520         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 521
 522         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 523                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 524
 525         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 526                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 527         if (ret < 0) {
 528                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 529                 goto phy_init_end;
 530         }
 531
 532         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 533                                  val, val & STOP_STATE_CLK_LANE, 1000,
 534                                  PHY_STATUS_TIMEOUT_US);
 535         if (ret < 0)
 536                 dev_err(dsi->dev,
 537                         "failed to wait for phy clk lane stop state\n");
 538
 539 phy_init_end:
 540         if (!IS_ERR(dsi->dphy.cfg_clk))
 541                 clk_disable_unprepare(dsi->dphy.cfg_clk);
 542
 543         return ret;
 544 }
 545
 546 static unsigned long rockchip_dsi_calc_bandwidth(struct dw_mipi_dsi *dsi)
 547 {
 548         int bpp;
 549         unsigned long mpclk, tmp;
 550         unsigned int target_mbps = 1000;
 551         unsigned int value;
 552         struct device_node *np = dsi->dev->of_node;
 553         unsigned int max_mbps;
 554         int lanes;
 555
 556         /* optional override of the desired bandwidth */
 557         if (!of_property_read_u32(np, "rockchip,lane-rate", &value))
 558                 return value;
 559
 560         max_mbps = dsi->pdata->max_bit_rate_per_lane / USEC_PER_SEC;
 561
 562         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 563         if (bpp < 0) {
 564                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 565                         dsi->format);
 566                 bpp = 24;
 567         }
 568
 569         lanes = dsi->lanes;
 570
 571         mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
 572         if (mpclk) {
 573                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 574                 tmp = mpclk * (bpp / lanes) * 10 / 9;
 575                 if (tmp < max_mbps)
 576                         target_mbps = tmp;
 577                 else
 578                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 579         }
 580
 581         return target_mbps * USEC_PER_SEC;
 582 }
 583
 584 static unsigned long dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
 585                                               unsigned long rate)
 586 {
 587         unsigned int i, pre;
 588         unsigned long pllref, tmp;
 589         unsigned int m = 1, n = 1;
 590         unsigned long target_mbps = rate / USEC_PER_SEC;
 591
 592         pllref = DIV_ROUND_UP(clk_get_rate(dsi->dphy.ref_clk), USEC_PER_SEC);
 593         tmp = pllref;
 594
 595         for (i = 1; i < 6; i++) {
 596                 pre = pllref / i;
 597                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 598                         tmp = target_mbps % pre;
 599                         n = i;
 600                         m = target_mbps / pre;
 601                 }
 602                 if (tmp == 0)
 603                         break;
 604         }
 605
 606         dsi->dphy.input_div = n;
 607         dsi->dphy.feedback_div = m;
 608
 609         return (pllref * m / n) * USEC_PER_SEC;
 610 }
 611
 612 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 613                                    struct mipi_dsi_device *device)
 614 {
 615         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 616
 617         if (device->lanes > dsi->pdata->max_data_lanes) {
 618                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 619                                 device->lanes);
 620                 return -EINVAL;
 621         }
 622
 623         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
 624                 dev_err(dsi->dev, "device mode is unsupported\n");
 625                 return -EINVAL;
 626         }
 627
 628         dsi->lanes = device->lanes;
 629         dsi->channel = device->channel;
 630         dsi->format = device->format;
 631         dsi->mode_flags = device->mode_flags;
 632
 633         dsi->panel = of_drm_find_panel(device->dev.of_node);
 634         if (!dsi->panel) {
 635                 DRM_ERROR("failed to find panel\n");
 636                 return -ENODEV;
 637         }
 638
 639         return 0;
 640 }
 641
 642 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 643                                    struct mipi_dsi_device *device)
 644 {
 645         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 646
 647         if (dsi->panel)
 648                 drm_panel_detach(dsi->panel);
 649
 650         dsi->panel = NULL;
 651         return 0;
 652 }
 653
 654 static void rockchip_set_transfer_mode(struct dw_mipi_dsi *dsi, int flags)
 655 {
 656         if (flags & MIPI_DSI_MSG_USE_LPM) {
 657                 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 658                 dsi_write(dsi, DSI_LPCLK_CTRL, 0);
 659         } else {
 660                 dsi_write(dsi, DSI_CMD_MODE_CFG, 0);
 661                 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 662         }
 663 }
 664
 665 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 666                                          const struct mipi_dsi_msg *msg)
 667 {
 668         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 669         struct mipi_dsi_packet packet;
 670         int ret;
 671         int val;
 672         int len = msg->tx_len;
 673
 674         /* create a packet to the DSI protocol */
 675         ret = mipi_dsi_create_packet(&packet, msg);
 676         if (ret) {
 677                 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 678                 return ret;
 679         }
 680
 681         rockchip_set_transfer_mode(dsi, msg->flags);
 682
 683         /* Send payload,  */
 684         while (DIV_ROUND_UP(packet.payload_length, 4)) {
 685                 /*
 686                  * Alternatively, you can always keep the FIFO
 687                  * nearly full by monitoring the FIFO state until
 688                  * it is not full, and then writea single word of data.
 689                  * This solution is more resource consuming
 690                  * but it simultaneously avoids FIFO starvation,
 691                  * making it possible to use FIFO sizes smaller than
 692                  * the amount of data of the longest packet to be written.
 693                  */
 694                 ret = rockchip_wait_w_pld_fifo_not_full(dsi);
 695                 if (ret)
 696                         return ret;
 697
 698                 if (packet.payload_length < 4) {
 699                         /* send residu payload */
 700                         val = 0;
 701                         memcpy(&val, packet.payload, packet.payload_length);
 702                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 703                         packet.payload_length = 0;
 704                 } else {
 705                         val = get_unaligned_le32(packet.payload);
 706                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 707                         packet.payload += 4;
 708                         packet.payload_length -= 4;
 709                 }
 710         }
 711
 712         ret = rockchip_wait_cmd_fifo_not_full(dsi);
 713         if (ret)
 714                 return ret;
 715
 716         /* Send packet header */
 717         val = get_unaligned_le32(packet.header);
 718         dsi_write(dsi, DSI_GEN_HDR, val);
 719
 720         ret = rockchip_wait_write_fifo_empty(dsi);
 721         if (ret)
 722                 return ret;
 723
 724         return len;
 725 }
 726
 727 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 728         .attach = dw_mipi_dsi_host_attach,
 729         .detach = dw_mipi_dsi_host_detach,
 730         .transfer = dw_mipi_dsi_host_transfer,
 731 };
 732
 733 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 734 {
 735         u32 val;
 736
 737         val = LP_HFP_EN | ENABLE_LOW_POWER;
 738
 739         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 740                 val |= VID_MODE_TYPE_BURST;
 741         else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 742                 val |= VID_MODE_TYPE_BURST_SYNC_PULSES;
 743         else
 744                 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS;
 745
 746         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 747 }
 748
 749 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 750                                  enum dw_mipi_dsi_mode mode)
 751 {
 752         if (mode == DSI_COMMAND_MODE)
 753                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 754         else
 755                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 756 }
 757
 758 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 759 {
 760         u32 esc_clk_div;
 761
 762         dsi_write(dsi, DSI_PWR_UP, RESET);
 763         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 764                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 765
 766         /* The maximum value of the escape clock frequency is 20MHz */
 767         esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20);
 768         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 769                   TX_ESC_CLK_DIVIDSION(esc_clk_div));
 770 }
 771
 772 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 773                                    struct drm_display_mode *mode)
 774 {
 775         u32 val = 0, color = 0;
 776
 777         switch (dsi->format) {
 778         case MIPI_DSI_FMT_RGB888:
 779                 color = DPI_COLOR_CODING_24BIT;
 780                 break;
 781         case MIPI_DSI_FMT_RGB666:
 782                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 783                 break;
 784         case MIPI_DSI_FMT_RGB666_PACKED:
 785                 color = DPI_COLOR_CODING_18BIT_1;
 786                 break;
 787         case MIPI_DSI_FMT_RGB565:
 788                 color = DPI_COLOR_CODING_16BIT_1;
 789                 break;
 790         }
 791
 792         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 793                 val |= VSYNC_ACTIVE_LOW;
 794         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 795                 val |= HSYNC_ACTIVE_LOW;
 796
 797         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 798         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 799         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 800         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 801                   | INVACT_LPCMD_TIME(4));
 802 }
 803
 804 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 805 {
 806         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 807 }
 808
 809 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 810                                             struct drm_display_mode *mode)
 811 {
 812         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 813 }
 814
 815 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 816 {
 817         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 818         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 819 }
 820
 821 /* Get lane byte clock cycles. */
 822 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 823                                            u32 hcomponent)
 824 {
 825         u32 lbcc;
 826
 827         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 828
 829         if (dsi->mode.clock == 0) {
 830                 dev_err(dsi->dev, "dsi mode clock is 0!\n");
 831                 return 0;
 832         }
 833
 834         return DIV_ROUND_CLOSEST_ULL(lbcc, dsi->mode.clock);
 835 }
 836
 837 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 838 {
 839         u32 htotal, hsa, hbp, lbcc;
 840         struct drm_display_mode *mode = &dsi->mode;
 841
 842         htotal = mode->htotal;
 843         hsa = mode->hsync_end - mode->hsync_start;
 844         hbp = mode->htotal - mode->hsync_end;
 845
 846         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 847         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 848
 849         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 850         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 851
 852         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 853         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 854 }
 855
 856 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 857 {
 858         u32 vactive, vsa, vfp, vbp;
 859         struct drm_display_mode *mode = &dsi->mode;
 860
 861         vactive = mode->vdisplay;
 862         vsa = mode->vsync_end - mode->vsync_start;
 863         vfp = mode->vsync_start - mode->vdisplay;
 864         vbp = mode->vtotal - mode->vsync_end;
 865
 866         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 867         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 868         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 869         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 870 }
 871
 872 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 873 {
 874         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
 875                   | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
 876
 877         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 878                   | PHY_CLKLP2HS_TIME(0x40));
 879 }
 880
 881 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 882 {
 883         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 884                   N_LANES(dsi->lanes));
 885 }
 886
 887 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 888 {
 889         dsi_read(dsi, DSI_INT_ST0);
 890         dsi_read(dsi, DSI_INT_ST1);
 891         dsi_write(dsi, DSI_INT_MSK0, 0);
 892         dsi_write(dsi, DSI_INT_MSK1, 0);
 893 }
 894
 895 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 896                                         struct drm_display_mode *mode,
 897                                         struct drm_display_mode *adjusted_mode)
 898 {
 899         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 900
 901         drm_mode_copy(&dsi->mode, adjusted_mode);
 902 }
 903
 904 static void rockchip_dsi_pre_disable(struct dw_mipi_dsi *dsi)
 905 {
 906         if (clk_prepare_enable(dsi->pclk)) {
 907                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 908                 return;
 909         }
 910
 911         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
 912 }
 913
 914 static void rockchip_dsi_disable(struct dw_mipi_dsi *dsi)
 915 {
 916         /* host */
 917         dsi_write(dsi, DSI_LPCLK_CTRL, 0);
 918         dsi_write(dsi, DSI_PWR_UP, RESET);
 919
 920         /* phy */
 921         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 922         if (dsi->dphy.phy) {
 923                 clk_disable_unprepare(dsi->dphy.hs_clk);
 924                 phy_power_off(dsi->dphy.phy);
 925         }
 926
 927         pm_runtime_put(dsi->dev);
 928         clk_disable_unprepare(dsi->pclk);
 929 }
 930
 931 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 932 {
 933         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 934
 935         if (dsi->panel)
 936                 drm_panel_disable(dsi->panel);
 937
 938         rockchip_dsi_pre_disable(dsi);
 939
 940         if (dsi->panel)
 941                 drm_panel_unprepare(dsi->panel);
 942
 943         rockchip_dsi_disable(dsi);
 944 }
 945
 946 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 947                                         const struct drm_display_mode *mode,
 948                                         struct drm_display_mode *adjusted_mode)
 949 {
 950         return true;
 951 }
 952
 953 static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
 954 {
 955         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 956         int val = 0;
 957
 958         if (pdata->grf_dsi0_mode_reg)
 959                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 960                              pdata->grf_dsi0_mode);
 961
 962         if (vop_id)
 963                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 964         else
 965                 val = pdata->dsi0_en_bit << 16;
 966
 967         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 968
 969         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (vop_id) ? "LIT" : "BIG");
 970 }
 971
 972 static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
 973 {
 974         unsigned long bw, rate;
 975         int ret;
 976
 977         if (clk_prepare_enable(dsi->pclk)) {
 978                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 979                 return;
 980         }
 981
 982         if (clk_prepare_enable(dsi->dphy.ref_clk)) {
 983                 dev_err(dsi->dev, "Failed to enable pllref_clk\n");
 984                 return;
 985         }
 986
 987         pm_runtime_get_sync(dsi->dev);
 988
 989         if (dsi->rst) {
 990                 /* MIPI DSI APB software reset request. */
 991                 reset_control_assert(dsi->rst);
 992                 udelay(10);
 993                 reset_control_deassert(dsi->rst);
 994                 udelay(10);
 995         }
 996
 997         bw = rockchip_dsi_calc_bandwidth(dsi);
 998
 999         if (dsi->dphy.phy) {
1000                 rate = clk_round_rate(dsi->dphy.hs_clk, bw);
1001                 ret = clk_set_rate(dsi->dphy.hs_clk, rate);
1002                 if (ret) {
1003                         dev_err(dsi->dev, "failed to set hs clock rate: %lu\n",
1004                                 rate);
1005                         return;
1006                 }
1007
1008                 clk_prepare_enable(dsi->dphy.hs_clk);
1009                 phy_power_on(dsi->dphy.phy);
1010         } else {
1011                 rate = dw_mipi_dsi_get_lane_bps(dsi, bw);
1012         }
1013
1014         dsi->lane_mbps = rate / USEC_PER_SEC;
1015
1016         dev_info(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n",
1017                  dsi->lane_mbps, dsi->lanes);
1018 }
1019
1020 static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
1021 {
1022         dw_mipi_dsi_init(dsi);
1023         dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
1024         dw_mipi_dsi_packet_handler_config(dsi);
1025         dw_mipi_dsi_video_mode_config(dsi);
1026         dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
1027         dw_mipi_dsi_command_mode_config(dsi);
1028         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
1029         dw_mipi_dsi_line_timer_config(dsi);
1030         dw_mipi_dsi_vertical_timing_config(dsi);
1031         dw_mipi_dsi_dphy_timing_config(dsi);
1032         dw_mipi_dsi_dphy_interface_config(dsi);
1033         dw_mipi_dsi_clear_err(dsi);
1034 }
1035
1036 static void rockchip_dsi_init(struct dw_mipi_dsi *dsi)
1037 {
1038         rockchip_dsi_pre_init(dsi);
1039         rockchip_dsi_host_init(dsi);
1040         dw_mipi_dsi_phy_init(dsi);
1041 }
1042
1043 static void rockchip_dsi_enable(struct dw_mipi_dsi *dsi)
1044 {
1045         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
1046         dw_mipi_dsi_set_mode(dsi, DSI_VIDEO_MODE);
1047         clk_disable_unprepare(dsi->dphy.ref_clk);
1048         clk_disable_unprepare(dsi->pclk);
1049 }
1050
1051 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
1052 {
1053         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1054         int vop_id;
1055
1056         vop_id = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
1057
1058         rockchip_dsi_grf_config(dsi, vop_id);
1059         rockchip_dsi_init(dsi);
1060
1061         if (dsi->panel)
1062                 drm_panel_prepare(dsi->panel);
1063
1064         rockchip_dsi_enable(dsi);
1065
1066         if (dsi->panel)
1067                 drm_panel_enable(dsi->panel);
1068 }
1069
1070 static int
1071 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
1072                                  struct drm_crtc_state *crtc_state,
1073                                  struct drm_connector_state *conn_state)
1074 {
1075         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1076         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1077         struct drm_connector *connector = conn_state->connector;
1078         struct drm_display_info *info = &connector->display_info;
1079
1080         switch (dsi->format) {
1081         case MIPI_DSI_FMT_RGB888:
1082                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1083                 break;
1084         case MIPI_DSI_FMT_RGB666:
1085                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1086                 break;
1087         case MIPI_DSI_FMT_RGB565:
1088                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1089                 break;
1090         default:
1091                 WARN_ON(1);
1092                 return -EINVAL;
1093         }
1094
1095         s->output_type = DRM_MODE_CONNECTOR_DSI;
1096         if (info->num_bus_formats)
1097                 s->bus_format = info->bus_formats[0];
1098
1099         return 0;
1100 }
1101
1102 static struct drm_encoder_helper_funcs
1103 dw_mipi_dsi_encoder_helper_funcs = {
1104         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1105         .mode_set = dw_mipi_dsi_encoder_mode_set,
1106         .enable = dw_mipi_dsi_encoder_enable,
1107         .disable = dw_mipi_dsi_encoder_disable,
1108         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1109 };
1110
1111 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1112         .destroy = drm_encoder_cleanup,
1113 };
1114
1115 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1116 {
1117         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1118
1119         return drm_panel_get_modes(dsi->panel);
1120 }
1121
1122 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1123                                         struct drm_connector *connector,
1124                                         struct drm_display_mode *mode)
1125 {
1126         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1127
1128         enum drm_mode_status mode_status = MODE_OK;
1129
1130         if (dsi->pdata->mode_valid)
1131                 mode_status = dsi->pdata->mode_valid(connector, mode);
1132
1133         return mode_status;
1134 }
1135
1136 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1137                                         struct drm_connector *connector)
1138 {
1139         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1140
1141         return &dsi->encoder;
1142 }
1143
1144 static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
1145 {
1146         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1147
1148         if (dsi->panel)
1149                 drm_panel_loader_protect(dsi->panel, on);
1150         if (on)
1151                 pm_runtime_get_sync(dsi->dev);
1152         else
1153                 pm_runtime_put(dsi->dev);
1154
1155         return 0;
1156 }
1157
1158 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1159         .loader_protect = dw_mipi_loader_protect,
1160         .get_modes = dw_mipi_dsi_connector_get_modes,
1161         .mode_valid = dw_mipi_dsi_mode_valid,
1162         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1163 };
1164
1165 static enum drm_connector_status
1166 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1167 {
1168         return connector_status_connected;
1169 }
1170
1171 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1172 {
1173         drm_connector_unregister(connector);
1174         drm_connector_cleanup(connector);
1175 }
1176
1177 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1178         .dpms = drm_atomic_helper_connector_dpms,
1179         .fill_modes = drm_helper_probe_single_connector_modes,
1180         .detect = dw_mipi_dsi_detect,
1181         .destroy = dw_mipi_dsi_drm_connector_destroy,
1182         .reset = drm_atomic_helper_connector_reset,
1183         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1184         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1185 };
1186
1187 static int dw_mipi_dsi_register(struct drm_device *drm,
1188                                       struct dw_mipi_dsi *dsi)
1189 {
1190         struct drm_encoder *encoder = &dsi->encoder;
1191         struct drm_connector *connector = &dsi->connector;
1192         struct device *dev = dsi->dev;
1193         int ret;
1194
1195         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1196                                                              dev->of_node);
1197         /*
1198          * If we failed to find the CRTC(s) which this encoder is
1199          * supposed to be connected to, it's because the CRTC has
1200          * not been registered yet.  Defer probing, and hope that
1201          * the required CRTC is added later.
1202          */
1203         if (encoder->possible_crtcs == 0)
1204                 return -EPROBE_DEFER;
1205
1206         drm_encoder_helper_add(&dsi->encoder,
1207                                &dw_mipi_dsi_encoder_helper_funcs);
1208         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1209                          DRM_MODE_ENCODER_DSI, NULL);
1210         if (ret) {
1211                 dev_err(dev, "Failed to initialize encoder with drm\n");
1212                 return ret;
1213         }
1214
1215         drm_connector_helper_add(connector,
1216                         &dw_mipi_dsi_connector_helper_funcs);
1217
1218         drm_connector_init(drm, &dsi->connector,
1219                            &dw_mipi_dsi_atomic_connector_funcs,
1220                            DRM_MODE_CONNECTOR_DSI);
1221
1222         drm_panel_attach(dsi->panel, &dsi->connector);
1223
1224         dsi->connector.port = dev->of_node;
1225
1226         drm_mode_connector_attach_encoder(connector, encoder);
1227
1228         return 0;
1229 }
1230
1231 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1232         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1233         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1234         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1235         .max_data_lanes = 4,
1236         .max_bit_rate_per_lane = 1500000000,
1237         .has_vop_sel = true,
1238 };
1239
1240 static struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data = {
1241         .dsi0_en_bit = RK3366_DSI_SEL_VOP_LIT,
1242         .grf_switch_reg = RK3366_GRF_SOC_CON0,
1243         .max_data_lanes = 4,
1244         .max_bit_rate_per_lane = 1000000000,
1245         .has_vop_sel = true,
1246 };
1247
1248 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1249         .max_data_lanes = 4,
1250         .max_bit_rate_per_lane = 1000000000,
1251 };
1252
1253 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1254         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1255         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1256         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1257         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1258         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1259         .max_data_lanes = 4,
1260         .max_bit_rate_per_lane = 1500000000,
1261         .has_vop_sel = true,
1262 };
1263
1264 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1265         {
1266          .compatible = "rockchip,rk3288-mipi-dsi",
1267          .data = &rk3288_mipi_dsi_drv_data,
1268         }, {
1269          .compatible = "rockchip,rk3366-mipi-dsi",
1270          .data = &rk3366_mipi_dsi_drv_data,
1271         }, {
1272          .compatible = "rockchip,rk3368-mipi-dsi",
1273          .data = &rk3368_mipi_dsi_drv_data,
1274         }, {
1275          .compatible = "rockchip,rk3399-mipi-dsi",
1276          .data = &rk3399_mipi_dsi_drv_data,
1277         },
1278         { /* sentinel */ }
1279 };
1280 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1281
1282 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1283                              void *data)
1284 {
1285         struct drm_device *drm = data;
1286         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1287         int ret;
1288
1289         if (!dsi->panel)
1290                 return -EPROBE_DEFER;
1291
1292         ret = dw_mipi_dsi_register(drm, dsi);
1293         if (ret) {
1294                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1295                 return ret;
1296         }
1297
1298         dev_set_drvdata(dev, dsi);
1299
1300         pm_runtime_enable(dev);
1301
1302         return ret;
1303 }
1304
1305 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1306         void *data)
1307 {
1308         pm_runtime_disable(dev);
1309 }
1310
1311 static const struct component_ops dw_mipi_dsi_ops = {
1312         .bind   = dw_mipi_dsi_bind,
1313         .unbind = dw_mipi_dsi_unbind,
1314 };
1315
1316 static int rockchip_dsi_get_reset_handle(struct dw_mipi_dsi *dsi)
1317 {
1318         struct device *dev = dsi->dev;
1319
1320         dsi->rst = devm_reset_control_get_optional(dev, "apb");
1321         if (IS_ERR(dsi->rst)) {
1322                 dev_info(dev, "no reset control specified\n");
1323                 dsi->rst = NULL;
1324         }
1325
1326         return 0;
1327 }
1328
1329 static int rockchip_dsi_grf_regmap(struct dw_mipi_dsi *dsi)
1330 {
1331         struct device_node *np = dsi->dev->of_node;
1332
1333         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1334         if (IS_ERR(dsi->grf_regmap)) {
1335                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1336                 return PTR_ERR(dsi->grf_regmap);
1337         }
1338
1339         return 0;
1340 }
1341
1342 static int rockchip_dsi_clk_get(struct dw_mipi_dsi *dsi)
1343 {
1344         struct device *dev = dsi->dev;
1345         int ret;
1346
1347         dsi->pclk = devm_clk_get(dev, "pclk");
1348         if (IS_ERR(dsi->pclk)) {
1349                 ret = PTR_ERR(dsi->pclk);
1350                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1351                 return ret;
1352         }
1353
1354         return 0;
1355 }
1356
1357 static int rockchip_dsi_dphy_parse(struct dw_mipi_dsi *dsi)
1358 {
1359         struct device *dev = dsi->dev;
1360         int ret;
1361
1362         dsi->dphy.phy = devm_phy_optional_get(dev, "mipi_dphy");
1363         if (IS_ERR(dsi->dphy.phy)) {
1364                 ret = PTR_ERR(dsi->dphy.phy);
1365                 dev_err(dev, "failed to get mipi dphy: %d\n", ret);
1366                 return ret;
1367         }
1368
1369         if (dsi->dphy.phy) {
1370                 dev_dbg(dev, "Use Non-SNPS PHY\n");
1371
1372                 dsi->dphy.hs_clk = devm_clk_get(dev, "hs_clk");
1373                 if (IS_ERR(dsi->dphy.hs_clk)) {
1374                         dev_err(dev, "failed to get PHY high-speed clock\n");
1375                         return PTR_ERR(dsi->dphy.hs_clk);
1376                 }
1377         } else {
1378                 dev_dbg(dev, "Use SNPS PHY\n");
1379
1380                 dsi->dphy.ref_clk = devm_clk_get(dev, "ref");
1381                 if (IS_ERR(dsi->dphy.ref_clk)) {
1382                         dev_err(dev, "failed to get PHY reference clock\n");
1383                         return PTR_ERR(dsi->dphy.ref_clk);
1384                 }
1385
1386                 /* Check if cfg_clk provided */
1387                 dsi->dphy.cfg_clk = devm_clk_get(dev, "phy_cfg");
1388                 if (IS_ERR(dsi->dphy.cfg_clk)) {
1389                         if (PTR_ERR(dsi->dphy.cfg_clk) != -ENOENT) {
1390                                 dev_err(dev, "failed to get PHY config clk\n");
1391                                 return PTR_ERR(dsi->dphy.cfg_clk);
1392                         }
1393
1394                         /* Otherwise mark the cfg_clk pointer to NULL */
1395                         dsi->dphy.cfg_clk = NULL;
1396                 }
1397         }
1398
1399         return 0;
1400 }
1401
1402 static int rockchip_dsi_ioremap_resource(struct platform_device *pdev,
1403                                          struct dw_mipi_dsi *dsi)
1404 {
1405         struct device *dev = &pdev->dev;
1406         struct resource *res;
1407
1408         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1409         if (!res)
1410                 return -ENODEV;
1411
1412         dsi->base = devm_ioremap_resource(dev, res);
1413         if (IS_ERR(dsi->base))
1414                 return PTR_ERR(dsi->base);
1415
1416         return 0;
1417 }
1418
1419 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1420 {
1421         struct device *dev = &pdev->dev;
1422         const struct of_device_id *of_id =
1423                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1424         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1425         struct dw_mipi_dsi *dsi;
1426         int ret;
1427
1428         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1429         if (!dsi)
1430                 return -ENOMEM;
1431
1432         dsi->dev = dev;
1433         dsi->pdata = pdata;
1434
1435         rockchip_dsi_ioremap_resource(pdev, dsi);
1436         rockchip_dsi_clk_get(dsi);
1437         rockchip_dsi_dphy_parse(dsi);
1438         rockchip_dsi_grf_regmap(dsi);
1439         rockchip_dsi_get_reset_handle(dsi);
1440
1441         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1442         dsi->dsi_host.dev = &pdev->dev;
1443
1444         ret = mipi_dsi_host_register(&dsi->dsi_host);
1445         if (ret)
1446                 return ret;
1447
1448         platform_set_drvdata(pdev, dsi);
1449         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1450         if (ret)
1451                 mipi_dsi_host_unregister(&dsi->dsi_host);
1452
1453         return ret;
1454 }
1455
1456 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1457 {
1458         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1459
1460         if (dsi)
1461                 mipi_dsi_host_unregister(&dsi->dsi_host);
1462         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1463         return 0;
1464 }
1465
1466 static struct platform_driver dw_mipi_dsi_driver = {
1467         .probe          = dw_mipi_dsi_probe,
1468         .remove         = dw_mipi_dsi_remove,
1469         .driver         = {
1470                 .of_match_table = dw_mipi_dsi_dt_ids,
1471                 .name   = DRIVER_NAME,
1472         },
1473 };
1474 module_platform_driver(dw_mipi_dsi_driver);
1475
1476 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1477 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1478 MODULE_LICENSE("GPL");
1479 MODULE_ALIAS("platform:" DRIVER_NAME);