drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_crtc.h>
  20 #include <drm/drm_crtc_helper.h>
  21 #include <drm/drm_mipi_dsi.h>
  22 #include <drm/drm_of.h>
  23 #include <drm/drm_panel.h>
  24 #include <drm/drmP.h>
  25 #include <video/mipi_display.h>
  26
  27 #include "rockchip_drm_drv.h"
  28 #include "rockchip_drm_vop.h"
  29
  30 #define DRIVER_NAME    "dw-mipi-dsi"
  31
  32 #define RK3288_GRF_SOC_CON6             0x025c
  33 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  34 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  35
  36 #define RK3399_GRF_SOC_CON19            0x6250
  37 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  38 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  39
  40 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  41 #define RK3399_GRF_SOC_CON22            0x6258
  42 #define RK3399_GRF_DSI_MODE             0xffff0000
  43
  44 #define DSI_VERSION                     0x00
  45 #define DSI_PWR_UP                      0x04
  46 #define RESET                           0
  47 #define POWERUP                         BIT(0)
  48
  49 #define DSI_CLKMGR_CFG                  0x08
  50 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  51 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  52
  53 #define DSI_DPI_VCID                    0x0c
  54 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  55
  56 #define DSI_DPI_COLOR_CODING            0x10
  57 #define EN18_LOOSELY                    BIT(8)
  58 #define DPI_COLOR_CODING_16BIT_1        0x0
  59 #define DPI_COLOR_CODING_16BIT_2        0x1
  60 #define DPI_COLOR_CODING_16BIT_3        0x2
  61 #define DPI_COLOR_CODING_18BIT_1        0x3
  62 #define DPI_COLOR_CODING_18BIT_2        0x4
  63 #define DPI_COLOR_CODING_24BIT          0x5
  64
  65 #define DSI_DPI_CFG_POL                 0x14
  66 #define COLORM_ACTIVE_LOW               BIT(4)
  67 #define SHUTD_ACTIVE_LOW                BIT(3)
  68 #define HSYNC_ACTIVE_LOW                BIT(2)
  69 #define VSYNC_ACTIVE_LOW                BIT(1)
  70 #define DATAEN_ACTIVE_LOW               BIT(0)
  71
  72 #define DSI_DPI_LP_CMD_TIM              0x18
  73 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  74 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  75
  76 #define DSI_DBI_CFG                     0x20
  77 #define DSI_DBI_CMDSIZE                 0x28
  78
  79 #define DSI_PCKHDL_CFG                  0x2c
  80 #define EN_CRC_RX                       BIT(4)
  81 #define EN_ECC_RX                       BIT(3)
  82 #define EN_BTA                          BIT(2)
  83 #define EN_EOTP_RX                      BIT(1)
  84 #define EN_EOTP_TX                      BIT(0)
  85
  86 #define DSI_MODE_CFG                    0x34
  87 #define ENABLE_VIDEO_MODE               0
  88 #define ENABLE_CMD_MODE                 BIT(0)
  89
  90 #define DSI_VID_MODE_CFG                0x38
  91 #define FRAME_BTA_ACK                   BIT(14)
  92 #define ENABLE_LOW_POWER                (0x3f << 8)
  93 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  94 #define VID_MODE_TYPE_BURST_SYNC_PULSES         0x2
  95 #define VID_MODE_TYPE_MASK                      0x3
  96
  97 #define DSI_VID_PKT_SIZE                0x3c
  98 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
  99 #define VID_PKT_MAX_SIZE                0x3fff
 100
 101 #define DSI_VID_HSA_TIME                0x48
 102 #define DSI_VID_HBP_TIME                0x4c
 103 #define DSI_VID_HLINE_TIME              0x50
 104 #define DSI_VID_VSA_LINES               0x54
 105 #define DSI_VID_VBP_LINES               0x58
 106 #define DSI_VID_VFP_LINES               0x5c
 107 #define DSI_VID_VACTIVE_LINES           0x60
 108 #define DSI_CMD_MODE_CFG                0x68
 109 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 110 #define DCS_LW_TX_LP                    BIT(19)
 111 #define DCS_SR_0P_TX_LP                 BIT(18)
 112 #define DCS_SW_1P_TX_LP                 BIT(17)
 113 #define DCS_SW_0P_TX_LP                 BIT(16)
 114 #define GEN_LW_TX_LP                    BIT(14)
 115 #define GEN_SR_2P_TX_LP                 BIT(13)
 116 #define GEN_SR_1P_TX_LP                 BIT(12)
 117 #define GEN_SR_0P_TX_LP                 BIT(11)
 118 #define GEN_SW_2P_TX_LP                 BIT(10)
 119 #define GEN_SW_1P_TX_LP                 BIT(9)
 120 #define GEN_SW_0P_TX_LP                 BIT(8)
 121 #define EN_ACK_RQST                     BIT(1)
 122 #define EN_TEAR_FX                      BIT(0)
 123
 124 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 125                                          DCS_LW_TX_LP | \
 126                                          DCS_SR_0P_TX_LP | \
 127                                          DCS_SW_1P_TX_LP | \
 128                                          DCS_SW_0P_TX_LP | \
 129                                          GEN_LW_TX_LP | \
 130                                          GEN_SR_2P_TX_LP | \
 131                                          GEN_SR_1P_TX_LP | \
 132                                          GEN_SR_0P_TX_LP | \
 133                                          GEN_SW_2P_TX_LP | \
 134                                          GEN_SW_1P_TX_LP | \
 135                                          GEN_SW_0P_TX_LP)
 136
 137 #define DSI_GEN_HDR                     0x6c
 138 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 139 #define GEN_HDATA_MASK                  (0xffff << 8)
 140 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 141 #define GEN_HTYPE_MASK                  0xff
 142
 143 #define DSI_GEN_PLD_DATA                0x70
 144
 145 #define DSI_CMD_PKT_STATUS              0x74
 146 #define GEN_CMD_EMPTY                   BIT(0)
 147 #define GEN_CMD_FULL                    BIT(1)
 148 #define GEN_PLD_W_EMPTY                 BIT(2)
 149 #define GEN_PLD_W_FULL                  BIT(3)
 150 #define GEN_PLD_R_EMPTY                 BIT(4)
 151 #define GEN_PLD_R_FULL                  BIT(5)
 152 #define GEN_RD_CMD_BUSY                 BIT(6)
 153
 154 #define DSI_TO_CNT_CFG                  0x78
 155 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 156 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 157
 158 #define DSI_BTA_TO_CNT                  0x8c
 159 #define DSI_LPCLK_CTRL                  0x94
 160 #define AUTO_CLKLANE_CTRL               BIT(1)
 161 #define PHY_TXREQUESTCLKHS              BIT(0)
 162
 163 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 164 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 165 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 166
 167 #define DSI_PHY_TMR_CFG                 0x9c
 168 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 169 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 170 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 171
 172 #define DSI_PHY_RSTZ                    0xa0
 173 #define PHY_DISFORCEPLL                 0
 174 #define PHY_ENFORCEPLL                  BIT(3)
 175 #define PHY_DISABLECLK                  0
 176 #define PHY_ENABLECLK                   BIT(2)
 177 #define PHY_RSTZ                        0
 178 #define PHY_UNRSTZ                      BIT(1)
 179 #define PHY_SHUTDOWNZ                   0
 180 #define PHY_UNSHUTDOWNZ                 BIT(0)
 181
 182 #define DSI_PHY_IF_CFG                  0xa4
 183 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 184 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 185
 186 #define DSI_PHY_STATUS                  0xb0
 187 #define LOCK                            BIT(0)
 188 #define STOP_STATE_CLK_LANE             BIT(2)
 189
 190 #define DSI_PHY_TST_CTRL0               0xb4
 191 #define PHY_TESTCLK                     BIT(1)
 192 #define PHY_UNTESTCLK                   0
 193 #define PHY_TESTCLR                     BIT(0)
 194 #define PHY_UNTESTCLR                   0
 195
 196 #define DSI_PHY_TST_CTRL1               0xb8
 197 #define PHY_TESTEN                      BIT(16)
 198 #define PHY_UNTESTEN                    0
 199 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 200 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 201
 202 #define DSI_INT_ST0                     0xbc
 203 #define DSI_INT_ST1                     0xc0
 204 #define DSI_INT_MSK0                    0xc4
 205 #define DSI_INT_MSK1                    0xc8
 206
 207 #define PHY_STATUS_TIMEOUT_US           10000
 208 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 209
 210 #define BYPASS_VCO_RANGE        BIT(7)
 211 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 212 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 213 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 214 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 215 #define REF_BIAS_CUR_SEL        BIT(0)
 216
 217 #define CP_CURRENT_3MA          BIT(3)
 218 #define CP_PROGRAM_EN           BIT(7)
 219 #define LPF_PROGRAM_EN          BIT(6)
 220 #define LPF_RESISTORS_20_KOHM   0
 221
 222 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 223
 224 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 225 #define LOW_PROGRAM_EN          0
 226 #define HIGH_PROGRAM_EN         BIT(7)
 227 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 228 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 229 #define PLL_LOOP_DIV_EN         BIT(5)
 230 #define PLL_INPUT_DIV_EN        BIT(4)
 231
 232 #define POWER_CONTROL           BIT(6)
 233 #define INTERNAL_REG_CURRENT    BIT(3)
 234 #define BIAS_BLOCK_ON           BIT(2)
 235 #define BANDGAP_ON              BIT(0)
 236
 237 #define TER_RESISTOR_HIGH       BIT(7)
 238 #define TER_RESISTOR_LOW        0
 239 #define LEVEL_SHIFTERS_ON       BIT(6)
 240 #define TER_CAL_DONE            BIT(5)
 241 #define SETRD_MAX               (0x7 << 2)
 242 #define POWER_MANAGE            BIT(1)
 243 #define TER_RESISTORS_ON        BIT(0)
 244
 245 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 246 #define BANDGAP_SEL(val)        ((val) & 0x7)
 247 #define TLP_PROGRAM_EN          BIT(7)
 248 #define THS_PRE_PROGRAM_EN      BIT(7)
 249 #define THS_ZERO_PROGRAM_EN     BIT(6)
 250
 251 enum {
 252         BANDGAP_97_07,
 253         BANDGAP_98_05,
 254         BANDGAP_99_02,
 255         BANDGAP_100_00,
 256         BANDGAP_93_17,
 257         BANDGAP_94_15,
 258         BANDGAP_95_12,
 259         BANDGAP_96_10,
 260 };
 261
 262 enum {
 263         BIASEXTR_87_1,
 264         BIASEXTR_91_5,
 265         BIASEXTR_95_9,
 266         BIASEXTR_100,
 267         BIASEXTR_105_94,
 268         BIASEXTR_111_88,
 269         BIASEXTR_118_8,
 270         BIASEXTR_127_7,
 271 };
 272
 273 struct dw_mipi_dsi_plat_data {
 274         u32 dsi0_en_bit;
 275         u32 dsi1_en_bit;
 276         u32 grf_switch_reg;
 277         u32 grf_dsi0_mode;
 278         u32 grf_dsi0_mode_reg;
 279         unsigned int max_data_lanes;
 280         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 281                                            struct drm_display_mode *mode);
 282 };
 283
 284 struct dw_mipi_dsi {
 285         struct drm_encoder encoder;
 286         struct drm_connector connector;
 287         struct mipi_dsi_host dsi_host;
 288         struct drm_panel *panel;
 289         struct device *dev;
 290         struct regmap *grf_regmap;
 291         void __iomem *base;
 292
 293         struct clk *pllref_clk;
 294         struct clk *pclk;
 295         struct clk *phy_cfg_clk;
 296
 297         int dpms_mode;
 298         unsigned int lane_mbps; /* per lane */
 299         u32 channel;
 300         u32 lanes;
 301         u32 format;
 302         u16 input_div;
 303         u16 feedback_div;
 304         struct drm_display_mode *mode;
 305
 306         const struct dw_mipi_dsi_plat_data *pdata;
 307 };
 308
 309 enum dw_mipi_dsi_mode {
 310         DW_MIPI_DSI_CMD_MODE,
 311         DW_MIPI_DSI_VID_MODE,
 312 };
 313
 314 struct dphy_pll_testdin_map {
 315         unsigned int max_mbps;
 316         u8 testdin;
 317 };
 318
 319 /* The table is based on 27MHz DPHY pll reference clock. */
 320 static const struct dphy_pll_testdin_map dptdin_map[] = {
 321         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 322         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 323         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 324         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 325         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 326         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 327         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 328         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 329         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 330         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 331 };
 332
 333 static int max_mbps_to_testdin(unsigned int max_mbps)
 334 {
 335         int i;
 336
 337         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 338                 if (dptdin_map[i].max_mbps > max_mbps)
 339                         return dptdin_map[i].testdin;
 340
 341         return -EINVAL;
 342 }
 343
 344 /*
 345  * The controller should generate 2 frames before
 346  * preparing the peripheral.
 347  */
 348 static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
 349 {
 350         int refresh, two_frames;
 351
 352         refresh = drm_mode_vrefresh(dsi->mode);
 353         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 354         msleep(two_frames);
 355 }
 356
 357 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 358 {
 359         return container_of(host, struct dw_mipi_dsi, dsi_host);
 360 }
 361
 362 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 363 {
 364         return container_of(con, struct dw_mipi_dsi, connector);
 365 }
 366
 367 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 368 {
 369         return container_of(encoder, struct dw_mipi_dsi, encoder);
 370 }
 371 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 372 {
 373         writel(val, dsi->base + reg);
 374 }
 375
 376 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 377 {
 378         return readl(dsi->base + reg);
 379 }
 380
 381 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 382                                  u8 test_data)
 383 {
 384         /*
 385          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 386          * is latched internally as the current test code. Test data is
 387          * programmed internally by rising edge on TESTCLK.
 388          */
 389         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 390
 391         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 392                                           PHY_TESTDIN(test_code));
 393
 394         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 395
 396         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 397                                           PHY_TESTDIN(test_data));
 398
 399         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 400 }
 401
 402 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 403 {
 404         int ret, testdin, vco, val;
 405
 406         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 407
 408         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 409         if (testdin < 0) {
 410                 dev_err(dsi->dev,
 411                         "failed to get testdin for %dmbps lane clock\n",
 412                         dsi->lane_mbps);
 413                 return testdin;
 414         }
 415
 416         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 417
 418         if (!IS_ERR(dsi->phy_cfg_clk)) {
 419                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 420                 if (ret) {
 421                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 422                         return ret;
 423                 }
 424         }
 425
 426         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 427                                          VCO_RANGE_CON_SEL(vco) |
 428                                          VCO_IN_CAP_CON_LOW |
 429                                          REF_BIAS_CUR_SEL);
 430
 431         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 432         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 433                                          LPF_RESISTORS_20_KOHM);
 434
 435         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 436
 437         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 438         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 439         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 440                                          LOW_PROGRAM_EN);
 441         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 442                                          HIGH_PROGRAM_EN);
 443
 444         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 445                                          BIAS_BLOCK_ON | BANDGAP_ON);
 446
 447         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 448                                          SETRD_MAX | TER_RESISTORS_ON);
 449         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 450                                          SETRD_MAX | POWER_MANAGE |
 451                                          TER_RESISTORS_ON);
 452
 453         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 454                                          BIASEXTR_SEL(BIASEXTR_127_7));
 455         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 456                                          BANDGAP_SEL(BANDGAP_96_10));
 457
 458         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 459         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
 460         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 461
 462         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 463                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 464
 465
 466         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 467                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 468         if (ret < 0) {
 469                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 470                 goto phy_init_end;
 471         }
 472
 473         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 474                                  val, val & STOP_STATE_CLK_LANE, 1000,
 475                                  PHY_STATUS_TIMEOUT_US);
 476         if (ret < 0)
 477                 dev_err(dsi->dev,
 478                         "failed to wait for phy clk lane stop state\n");
 479
 480 phy_init_end:
 481         if (!IS_ERR(dsi->phy_cfg_clk))
 482                 clk_disable_unprepare(dsi->phy_cfg_clk);
 483
 484         return ret;
 485 }
 486
 487 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 488 {
 489         unsigned int i, pre;
 490         unsigned long mpclk, pllref, tmp;
 491         unsigned int m = 1, n = 1, target_mbps = 1000;
 492         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 493         int bpp;
 494
 495         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 496         if (bpp < 0) {
 497                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 498                         dsi->format);
 499                 return bpp;
 500         }
 501
 502         mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC);
 503         if (mpclk) {
 504                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 505                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
 506                 if (tmp < max_mbps)
 507                         target_mbps = tmp;
 508                 else
 509                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 510         }
 511
 512         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 513         tmp = pllref;
 514
 515         for (i = 1; i < 6; i++) {
 516                 pre = pllref / i;
 517                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 518                         tmp = target_mbps % pre;
 519                         n = i;
 520                         m = target_mbps / pre;
 521                 }
 522                 if (tmp == 0)
 523                         break;
 524         }
 525
 526         dsi->lane_mbps = pllref / n * m;
 527         dsi->input_div = n;
 528         dsi->feedback_div = m;
 529
 530         return 0;
 531 }
 532
 533 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 534                                    struct mipi_dsi_device *device)
 535 {
 536         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 537
 538         if (device->lanes > dsi->pdata->max_data_lanes) {
 539                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 540                                 device->lanes);
 541                 return -EINVAL;
 542         }
 543
 544         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ||
 545             !(device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) {
 546                 dev_err(dsi->dev, "device mode is unsupported\n");
 547                 return -EINVAL;
 548         }
 549
 550         dsi->lanes = device->lanes;
 551         dsi->channel = device->channel;
 552         dsi->format = device->format;
 553         dsi->panel = of_drm_find_panel(device->dev.of_node);
 554         if (!dsi->panel) {
 555                 DRM_ERROR("failed to find panel\n");
 556                 return -ENODEV;
 557         }
 558
 559         return 0;
 560 }
 561
 562 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 563                                    struct mipi_dsi_device *device)
 564 {
 565         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 566
 567         if (dsi->panel)
 568                 drm_panel_detach(dsi->panel);
 569
 570         dsi->panel = NULL;
 571         return 0;
 572 }
 573
 574 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
 575 {
 576         int ret;
 577
 578         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 579                                  val, !(val & GEN_CMD_FULL), 1000,
 580                                  CMD_PKT_STATUS_TIMEOUT_US);
 581         if (ret < 0) {
 582                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 583                 return ret;
 584         }
 585
 586         dsi_write(dsi, DSI_GEN_HDR, val);
 587
 588         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 589                                  val, val & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
 590                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 591         if (ret < 0) {
 592                 dev_err(dsi->dev, "failed to write command FIFO\n");
 593                 return ret;
 594         }
 595
 596         return 0;
 597 }
 598
 599 static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
 600                                        const struct mipi_dsi_msg *msg)
 601 {
 602         const u16 *tx_buf = msg->tx_buf;
 603         u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
 604
 605         if (msg->tx_len > 2) {
 606                 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
 607                         msg->tx_len);
 608                 return -EINVAL;
 609         }
 610
 611         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 612 }
 613
 614 static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
 615                                       const struct mipi_dsi_msg *msg)
 616 {
 617         const u32 *tx_buf = msg->tx_buf;
 618         int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
 619         u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
 620         u32 remainder = 0;
 621
 622         if (msg->tx_len < 3) {
 623                 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
 624                         msg->tx_len);
 625                 return -EINVAL;
 626         }
 627
 628         while (DIV_ROUND_UP(len, pld_data_bytes)) {
 629                 if (len < pld_data_bytes) {
 630                         memcpy(&remainder, tx_buf, len);
 631                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 632                         len = 0;
 633                 } else {
 634                         dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
 635                         tx_buf++;
 636                         len -= pld_data_bytes;
 637                 }
 638
 639                 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 640                                          val, !(val & GEN_PLD_W_FULL), 1000,
 641                                          CMD_PKT_STATUS_TIMEOUT_US);
 642                 if (ret < 0) {
 643                         dev_err(dsi->dev,
 644                                 "failed to get available write payload FIFO\n");
 645                         return ret;
 646                 }
 647         }
 648
 649         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 650 }
 651
 652 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 653                                          const struct mipi_dsi_msg *msg)
 654 {
 655         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 656         int ret;
 657
 658         switch (msg->type) {
 659         case MIPI_DSI_DCS_SHORT_WRITE:
 660         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 661         case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
 662                 ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
 663                 break;
 664         case MIPI_DSI_DCS_LONG_WRITE:
 665                 ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
 666                 break;
 667         default:
 668                 dev_err(dsi->dev, "unsupported message type\n");
 669                 ret = -EINVAL;
 670         }
 671
 672         return ret;
 673 }
 674
 675 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 676         .attach = dw_mipi_dsi_host_attach,
 677         .detach = dw_mipi_dsi_host_detach,
 678         .transfer = dw_mipi_dsi_host_transfer,
 679 };
 680
 681 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 682 {
 683         u32 val;
 684
 685         val = VID_MODE_TYPE_BURST_SYNC_PULSES | ENABLE_LOW_POWER;
 686
 687         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 688 }
 689
 690 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 691                                  enum dw_mipi_dsi_mode mode)
 692 {
 693         if (mode == DW_MIPI_DSI_CMD_MODE) {
 694                 dsi_write(dsi, DSI_PWR_UP, RESET);
 695                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 696                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 697         } else {
 698                 dsi_write(dsi, DSI_PWR_UP, RESET);
 699                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 700                 dw_mipi_dsi_video_mode_config(dsi);
 701                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 702         }
 703 }
 704
 705 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 706 {
 707         dsi_write(dsi, DSI_PWR_UP, RESET);
 708         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 709 }
 710
 711 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 712 {
 713         dsi_write(dsi, DSI_PWR_UP, RESET);
 714         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 715                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 716         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 717                   TX_ESC_CLK_DIVIDSION(7));
 718         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 719 }
 720
 721 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 722                                    struct drm_display_mode *mode)
 723 {
 724         u32 val = 0, color = 0;
 725
 726         switch (dsi->format) {
 727         case MIPI_DSI_FMT_RGB888:
 728                 color = DPI_COLOR_CODING_24BIT;
 729                 break;
 730         case MIPI_DSI_FMT_RGB666:
 731                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 732                 break;
 733         case MIPI_DSI_FMT_RGB666_PACKED:
 734                 color = DPI_COLOR_CODING_18BIT_1;
 735                 break;
 736         case MIPI_DSI_FMT_RGB565:
 737                 color = DPI_COLOR_CODING_16BIT_1;
 738                 break;
 739         }
 740
 741         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 742                 val |= VSYNC_ACTIVE_LOW;
 743         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 744                 val |= HSYNC_ACTIVE_LOW;
 745
 746         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 747         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 748         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 749         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 750                   | INVACT_LPCMD_TIME(4));
 751 }
 752
 753 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 754 {
 755         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 756 }
 757
 758 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 759                                             struct drm_display_mode *mode)
 760 {
 761         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 762 }
 763
 764 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 765 {
 766         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 767         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 768         dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 769         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 770 }
 771
 772 /* Get lane byte clock cycles. */
 773 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 774                                            u32 hcomponent)
 775 {
 776         u32 frac, lbcc;
 777
 778         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 779
 780         frac = lbcc % dsi->mode->clock;
 781         lbcc = lbcc / dsi->mode->clock;
 782         if (frac)
 783                 lbcc++;
 784
 785         return lbcc;
 786 }
 787
 788 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 789 {
 790         u32 htotal, hsa, hbp, lbcc;
 791         struct drm_display_mode *mode = dsi->mode;
 792
 793         htotal = mode->htotal;
 794         hsa = mode->hsync_end - mode->hsync_start;
 795         hbp = mode->htotal - mode->hsync_end;
 796
 797         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 798         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 799
 800         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 801         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 802
 803         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 804         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 805 }
 806
 807 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 808 {
 809         u32 vactive, vsa, vfp, vbp;
 810         struct drm_display_mode *mode = dsi->mode;
 811
 812         vactive = mode->vdisplay;
 813         vsa = mode->vsync_end - mode->vsync_start;
 814         vfp = mode->vsync_start - mode->vdisplay;
 815         vbp = mode->vtotal - mode->vsync_end;
 816
 817         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 818         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 819         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 820         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 821 }
 822
 823 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 824 {
 825         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
 826                   | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
 827
 828         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 829                   | PHY_CLKLP2HS_TIME(0x40));
 830 }
 831
 832 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 833 {
 834         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 835                   N_LANES(dsi->lanes));
 836 }
 837
 838 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 839 {
 840         dsi_read(dsi, DSI_INT_ST0);
 841         dsi_read(dsi, DSI_INT_ST1);
 842         dsi_write(dsi, DSI_INT_MSK0, 0);
 843         dsi_write(dsi, DSI_INT_MSK1, 0);
 844 }
 845
 846 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 847                                         struct drm_display_mode *mode,
 848                                         struct drm_display_mode *adjusted_mode)
 849 {
 850         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 851         int ret;
 852
 853         if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
 854                 return;
 855
 856         dsi->mode = adjusted_mode;
 857
 858         ret = dw_mipi_dsi_get_lane_bps(dsi);
 859         if (ret < 0)
 860                 return;
 861
 862         if (clk_prepare_enable(dsi->pclk)) {
 863                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 864                 return;
 865         }
 866
 867         pm_runtime_get_sync(dsi->dev);
 868
 869         dw_mipi_dsi_init(dsi);
 870         dw_mipi_dsi_dpi_config(dsi, mode);
 871         dw_mipi_dsi_packet_handler_config(dsi);
 872         dw_mipi_dsi_video_mode_config(dsi);
 873         dw_mipi_dsi_video_packet_config(dsi, mode);
 874         dw_mipi_dsi_command_mode_config(dsi);
 875         dw_mipi_dsi_line_timer_config(dsi);
 876         dw_mipi_dsi_vertical_timing_config(dsi);
 877         dw_mipi_dsi_dphy_timing_config(dsi);
 878         dw_mipi_dsi_dphy_interface_config(dsi);
 879         dw_mipi_dsi_clear_err(dsi);
 880         if (drm_panel_prepare(dsi->panel))
 881                 dev_err(dsi->dev, "failed to prepare panel\n");
 882
 883         clk_disable_unprepare(dsi->pclk);
 884 }
 885
 886 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 887 {
 888         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 889
 890         if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
 891                 return;
 892
 893         drm_panel_disable(dsi->panel);
 894
 895         if (clk_prepare_enable(dsi->pclk)) {
 896                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 897                 return;
 898         }
 899
 900         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 901         drm_panel_unprepare(dsi->panel);
 902         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 903
 904         /*
 905          * This is necessary to make sure the peripheral will be driven
 906          * normally when the display is enabled again later.
 907          */
 908         msleep(120);
 909
 910         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 911         dw_mipi_dsi_disable(dsi);
 912         pm_runtime_put(dsi->dev);
 913         clk_disable_unprepare(dsi->pclk);
 914         dsi->dpms_mode = DRM_MODE_DPMS_OFF;
 915 }
 916
 917 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 918                                         const struct drm_display_mode *mode,
 919                                         struct drm_display_mode *adjusted_mode)
 920 {
 921         return true;
 922 }
 923
 924 static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
 925 {
 926         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 927         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 928         int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 929         u32 val;
 930
 931         if (clk_prepare_enable(dsi->pclk)) {
 932                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 933                 return;
 934         }
 935
 936         if (pdata->grf_dsi0_mode_reg)
 937                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 938                              pdata->grf_dsi0_mode);
 939
 940         dw_mipi_dsi_phy_init(dsi);
 941         dw_mipi_dsi_wait_for_two_frames(dsi);
 942
 943         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 944         drm_panel_enable(dsi->panel);
 945
 946         clk_disable_unprepare(dsi->pclk);
 947
 948         if (mux)
 949                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 950         else
 951                 val = pdata->dsi0_en_bit << 16;
 952
 953         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 954         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 955         dsi->dpms_mode = DRM_MODE_DPMS_ON;
 956 }
 957
 958 static int
 959 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 960                                  struct drm_crtc_state *crtc_state,
 961                                  struct drm_connector_state *conn_state)
 962 {
 963         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 964         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 965
 966         switch (dsi->format) {
 967         case MIPI_DSI_FMT_RGB888:
 968                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 969                 break;
 970         case MIPI_DSI_FMT_RGB666:
 971                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
 972                 break;
 973         case MIPI_DSI_FMT_RGB565:
 974                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
 975                 break;
 976         default:
 977                 WARN_ON(1);
 978                 return -EINVAL;
 979         }
 980
 981         s->output_type = DRM_MODE_CONNECTOR_DSI;
 982
 983         return 0;
 984 }
 985
 986 static struct drm_encoder_helper_funcs
 987 dw_mipi_dsi_encoder_helper_funcs = {
 988         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
 989         .commit = dw_mipi_dsi_encoder_commit,
 990         .mode_set = dw_mipi_dsi_encoder_mode_set,
 991         .disable = dw_mipi_dsi_encoder_disable,
 992         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
 993 };
 994
 995 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
 996         .destroy = drm_encoder_cleanup,
 997 };
 998
 999 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1000 {
1001         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1002
1003         return drm_panel_get_modes(dsi->panel);
1004 }
1005
1006 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1007                                         struct drm_connector *connector,
1008                                         struct drm_display_mode *mode)
1009 {
1010         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1011
1012         enum drm_mode_status mode_status = MODE_OK;
1013
1014         if (dsi->pdata->mode_valid)
1015                 mode_status = dsi->pdata->mode_valid(connector, mode);
1016
1017         return mode_status;
1018 }
1019
1020 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1021                                         struct drm_connector *connector)
1022 {
1023         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1024
1025         return &dsi->encoder;
1026 }
1027
1028 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1029         .get_modes = dw_mipi_dsi_connector_get_modes,
1030         .mode_valid = dw_mipi_dsi_mode_valid,
1031         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1032 };
1033
1034 static enum drm_connector_status
1035 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1036 {
1037         return connector_status_connected;
1038 }
1039
1040 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1041 {
1042         drm_connector_unregister(connector);
1043         drm_connector_cleanup(connector);
1044 }
1045
1046 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1047         .dpms = drm_atomic_helper_connector_dpms,
1048         .fill_modes = drm_helper_probe_single_connector_modes,
1049         .detect = dw_mipi_dsi_detect,
1050         .destroy = dw_mipi_dsi_drm_connector_destroy,
1051         .reset = drm_atomic_helper_connector_reset,
1052         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1053         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1054 };
1055
1056 static int dw_mipi_dsi_register(struct drm_device *drm,
1057                                       struct dw_mipi_dsi *dsi)
1058 {
1059         struct drm_encoder *encoder = &dsi->encoder;
1060         struct drm_connector *connector = &dsi->connector;
1061         struct device *dev = dsi->dev;
1062         int ret;
1063
1064         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1065                                                              dev->of_node);
1066         /*
1067          * If we failed to find the CRTC(s) which this encoder is
1068          * supposed to be connected to, it's because the CRTC has
1069          * not been registered yet.  Defer probing, and hope that
1070          * the required CRTC is added later.
1071          */
1072         if (encoder->possible_crtcs == 0)
1073                 return -EPROBE_DEFER;
1074
1075         drm_encoder_helper_add(&dsi->encoder,
1076                                &dw_mipi_dsi_encoder_helper_funcs);
1077         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1078                          DRM_MODE_ENCODER_DSI, NULL);
1079         if (ret) {
1080                 dev_err(dev, "Failed to initialize encoder with drm\n");
1081                 return ret;
1082         }
1083
1084         drm_connector_helper_add(connector,
1085                         &dw_mipi_dsi_connector_helper_funcs);
1086
1087         drm_connector_init(drm, &dsi->connector,
1088                            &dw_mipi_dsi_atomic_connector_funcs,
1089                            DRM_MODE_CONNECTOR_DSI);
1090
1091         drm_panel_attach(dsi->panel, &dsi->connector);
1092
1093         dsi->connector.port = dev->of_node;
1094
1095         drm_mode_connector_attach_encoder(connector, encoder);
1096
1097         return 0;
1098 }
1099
1100 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1101 {
1102         struct device_node *np = dsi->dev->of_node;
1103
1104         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1105         if (IS_ERR(dsi->grf_regmap)) {
1106                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1107                 return PTR_ERR(dsi->grf_regmap);
1108         }
1109
1110         return 0;
1111 }
1112
1113 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1114         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1115         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1116         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1117         .max_data_lanes = 4,
1118 };
1119
1120 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1121         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1122         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1123         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1124         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1125         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1126         .max_data_lanes = 4,
1127 };
1128
1129 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1130         {
1131          .compatible = "rockchip,rk3288-mipi-dsi",
1132          .data = &rk3288_mipi_dsi_drv_data,
1133         },{
1134          .compatible = "rockchip,rk3399-mipi-dsi",
1135          .data = &rk3399_mipi_dsi_drv_data,
1136         },
1137         { /* sentinel */ }
1138 };
1139 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1140
1141 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1142                              void *data)
1143 {
1144         struct platform_device *pdev = to_platform_device(dev);
1145         struct drm_device *drm = data;
1146         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1147         struct resource *res;
1148         int ret;
1149
1150         dsi->dpms_mode = DRM_MODE_DPMS_OFF;
1151
1152         if (!dsi->panel)
1153                 return -EPROBE_DEFER;
1154
1155         ret = rockchip_mipi_parse_dt(dsi);
1156         if (ret)
1157                 return ret;
1158
1159         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1160         if (!res)
1161                 return -ENODEV;
1162
1163         dsi->base = devm_ioremap_resource(dev, res);
1164         if (IS_ERR(dsi->base))
1165                 return PTR_ERR(dsi->base);
1166
1167         dsi->pllref_clk = devm_clk_get(dev, "ref");
1168         if (IS_ERR(dsi->pllref_clk)) {
1169                 ret = PTR_ERR(dsi->pllref_clk);
1170                 dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
1171                 return ret;
1172         }
1173
1174         dsi->pclk = devm_clk_get(dev, "pclk");
1175         if (IS_ERR(dsi->pclk)) {
1176                 ret = PTR_ERR(dsi->pclk);
1177                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1178                 return ret;
1179         }
1180
1181         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1182         if (IS_ERR(dsi->phy_cfg_clk))
1183                 dev_dbg(dev, "have not phy_cfg_clk\n");
1184
1185         ret = clk_prepare_enable(dsi->pllref_clk);
1186         if (ret) {
1187                 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1188                 return ret;
1189         }
1190
1191         ret = dw_mipi_dsi_register(drm, dsi);
1192         if (ret) {
1193                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1194                 goto err_pllref;
1195         }
1196
1197         dev_set_drvdata(dev, dsi);
1198
1199         pm_runtime_enable(dev);
1200
1201         return 0;
1202
1203 err_pllref:
1204         clk_disable_unprepare(dsi->pllref_clk);
1205         return ret;
1206 }
1207
1208 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1209         void *data)
1210 {
1211         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1212
1213         pm_runtime_disable(dev);
1214         clk_disable_unprepare(dsi->pllref_clk);
1215 }
1216
1217 static const struct component_ops dw_mipi_dsi_ops = {
1218         .bind   = dw_mipi_dsi_bind,
1219         .unbind = dw_mipi_dsi_unbind,
1220 };
1221
1222 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1223 {
1224         struct device *dev = &pdev->dev;
1225         const struct of_device_id *of_id =
1226                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1227         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1228         struct dw_mipi_dsi *dsi;
1229         int ret;
1230
1231         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1232         if (!dsi)
1233                 return -ENOMEM;
1234
1235         dsi->dev = dev;
1236         dsi->pdata = pdata;
1237         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1238         dsi->dsi_host.dev = &pdev->dev;
1239
1240         ret = mipi_dsi_host_register(&dsi->dsi_host);
1241         if (ret)
1242                 return ret;
1243
1244         platform_set_drvdata(pdev, dsi);
1245         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1246         if (ret)
1247                 mipi_dsi_host_unregister(&dsi->dsi_host);
1248
1249         return ret;
1250 }
1251
1252 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1253 {
1254         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1255
1256         if (dsi)
1257                 mipi_dsi_host_unregister(&dsi->dsi_host);
1258         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1259         return 0;
1260 }
1261
1262 static struct platform_driver dw_mipi_dsi_driver = {
1263         .probe          = dw_mipi_dsi_probe,
1264         .remove         = dw_mipi_dsi_remove,
1265         .driver         = {
1266                 .of_match_table = dw_mipi_dsi_dt_ids,
1267                 .name   = DRIVER_NAME,
1268         },
1269 };
1270 module_platform_driver(dw_mipi_dsi_driver);
1271
1272 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1273 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1274 MODULE_LICENSE("GPL");
1275 MODULE_ALIAS("platform:" DRIVER_NAME);