drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drmP.h>
  27 #include <video/mipi_display.h>
  28 #include <asm/unaligned.h>
  29
  30 #include "rockchip_drm_drv.h"
  31 #include "rockchip_drm_vop.h"
  32
  33 #define DRIVER_NAME    "dw-mipi-dsi"
  34
  35 #define RK3288_GRF_SOC_CON6             0x025c
  36 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  37 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  38
  39 #define RK3366_GRF_SOC_CON0             0x0400
  40 #define RK3366_DSI_SEL_VOP_LIT          BIT(2)
  41
  42 #define RK3399_GRF_SOC_CON19            0x6250
  43 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  44 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  45
  46 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  47 #define RK3399_GRF_SOC_CON22            0x6258
  48 #define RK3399_GRF_DSI_MODE             0xffff0000
  49
  50 #define DSI_VERSION                     0x00
  51 #define DSI_PWR_UP                      0x04
  52 #define RESET                           0
  53 #define POWERUP                         BIT(0)
  54
  55 #define DSI_CLKMGR_CFG                  0x08
  56 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  57 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  58
  59 #define DSI_DPI_VCID                    0x0c
  60 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  61
  62 #define DSI_DPI_COLOR_CODING            0x10
  63 #define EN18_LOOSELY                    BIT(8)
  64 #define DPI_COLOR_CODING_16BIT_1        0x0
  65 #define DPI_COLOR_CODING_16BIT_2        0x1
  66 #define DPI_COLOR_CODING_16BIT_3        0x2
  67 #define DPI_COLOR_CODING_18BIT_1        0x3
  68 #define DPI_COLOR_CODING_18BIT_2        0x4
  69 #define DPI_COLOR_CODING_24BIT          0x5
  70
  71 #define DSI_DPI_CFG_POL                 0x14
  72 #define COLORM_ACTIVE_LOW               BIT(4)
  73 #define SHUTD_ACTIVE_LOW                BIT(3)
  74 #define HSYNC_ACTIVE_LOW                BIT(2)
  75 #define VSYNC_ACTIVE_LOW                BIT(1)
  76 #define DATAEN_ACTIVE_LOW               BIT(0)
  77
  78 #define DSI_DPI_LP_CMD_TIM              0x18
  79 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  80 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  81
  82 #define DSI_DBI_CFG                     0x20
  83 #define DSI_DBI_CMDSIZE                 0x28
  84
  85 #define DSI_PCKHDL_CFG                  0x2c
  86 #define EN_CRC_RX                       BIT(4)
  87 #define EN_ECC_RX                       BIT(3)
  88 #define EN_BTA                          BIT(2)
  89 #define EN_EOTP_RX                      BIT(1)
  90 #define EN_EOTP_TX                      BIT(0)
  91
  92 #define DSI_MODE_CFG                    0x34
  93 #define ENABLE_VIDEO_MODE               0
  94 #define ENABLE_CMD_MODE                 BIT(0)
  95
  96 #define DSI_VID_MODE_CFG                0x38
  97 #define VPG_EN                          BIT(16)
  98 #define FRAME_BTA_ACK                   BIT(14)
  99 #define LP_HFP_EN                       BIT(13)
 100 #define LP_HBP_EN                       BIT(12)
 101 #define ENABLE_LOW_POWER                (0xf << 8)
 102 #define ENABLE_LOW_POWER_MASK           (0xf << 8)
 103 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
 104 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
 105 #define VID_MODE_TYPE_BURST             0x2
 106
 107 #define DSI_VID_PKT_SIZE                0x3c
 108 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 109 #define VID_PKT_MAX_SIZE                0x3fff
 110
 111 #define DSI_VID_NUM_CHUMKS              0x40
 112 #define DSI_VID_NULL_PKT_SIZE           0x44
 113 #define DSI_VID_HSA_TIME                0x48
 114 #define DSI_VID_HBP_TIME                0x4c
 115 #define DSI_VID_HLINE_TIME              0x50
 116 #define DSI_VID_VSA_LINES               0x54
 117 #define DSI_VID_VBP_LINES               0x58
 118 #define DSI_VID_VFP_LINES               0x5c
 119 #define DSI_VID_VACTIVE_LINES           0x60
 120 #define DSI_CMD_MODE_CFG                0x68
 121 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 122 #define DCS_LW_TX_LP                    BIT(19)
 123 #define DCS_SR_0P_TX_LP                 BIT(18)
 124 #define DCS_SW_1P_TX_LP                 BIT(17)
 125 #define DCS_SW_0P_TX_LP                 BIT(16)
 126 #define GEN_LW_TX_LP                    BIT(14)
 127 #define GEN_SR_2P_TX_LP                 BIT(13)
 128 #define GEN_SR_1P_TX_LP                 BIT(12)
 129 #define GEN_SR_0P_TX_LP                 BIT(11)
 130 #define GEN_SW_2P_TX_LP                 BIT(10)
 131 #define GEN_SW_1P_TX_LP                 BIT(9)
 132 #define GEN_SW_0P_TX_LP                 BIT(8)
 133 #define EN_ACK_RQST                     BIT(1)
 134 #define EN_TEAR_FX                      BIT(0)
 135
 136 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 137                                          DCS_LW_TX_LP | \
 138                                          DCS_SR_0P_TX_LP | \
 139                                          DCS_SW_1P_TX_LP | \
 140                                          DCS_SW_0P_TX_LP | \
 141                                          GEN_LW_TX_LP | \
 142                                          GEN_SR_2P_TX_LP | \
 143                                          GEN_SR_1P_TX_LP | \
 144                                          GEN_SR_0P_TX_LP | \
 145                                          GEN_SW_2P_TX_LP | \
 146                                          GEN_SW_1P_TX_LP | \
 147                                          GEN_SW_0P_TX_LP)
 148
 149 #define DSI_GEN_HDR                     0x6c
 150 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 151 #define GEN_HDATA_MASK                  (0xffff << 8)
 152 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 153 #define GEN_HTYPE_MASK                  0xff
 154
 155 #define DSI_GEN_PLD_DATA                0x70
 156
 157 #define DSI_CMD_PKT_STATUS              0x74
 158 #define GEN_CMD_EMPTY                   BIT(0)
 159 #define GEN_CMD_FULL                    BIT(1)
 160 #define GEN_PLD_W_EMPTY                 BIT(2)
 161 #define GEN_PLD_W_FULL                  BIT(3)
 162 #define GEN_PLD_R_EMPTY                 BIT(4)
 163 #define GEN_PLD_R_FULL                  BIT(5)
 164 #define GEN_RD_CMD_BUSY                 BIT(6)
 165
 166 #define DSI_TO_CNT_CFG                  0x78
 167 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 168 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 169
 170 #define DSI_BTA_TO_CNT                  0x8c
 171 #define DSI_LPCLK_CTRL                  0x94
 172 #define AUTO_CLKLANE_CTRL               BIT(1)
 173 #define PHY_TXREQUESTCLKHS              BIT(0)
 174
 175 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 176 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 177 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 178
 179 #define DSI_PHY_TMR_CFG                 0x9c
 180 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 181 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 182 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 183
 184 #define DSI_PHY_RSTZ                    0xa0
 185 #define PHY_DISFORCEPLL                 0
 186 #define PHY_ENFORCEPLL                  BIT(3)
 187 #define PHY_DISABLECLK                  0
 188 #define PHY_ENABLECLK                   BIT(2)
 189 #define PHY_RSTZ                        0
 190 #define PHY_UNRSTZ                      BIT(1)
 191 #define PHY_SHUTDOWNZ                   0
 192 #define PHY_UNSHUTDOWNZ                 BIT(0)
 193
 194 #define DSI_PHY_IF_CFG                  0xa4
 195 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 196 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 197
 198 #define DSI_PHY_STATUS                  0xb0
 199 #define LOCK                            BIT(0)
 200 #define STOP_STATE_CLK_LANE             BIT(2)
 201
 202 #define DSI_PHY_TST_CTRL0               0xb4
 203 #define PHY_TESTCLK                     BIT(1)
 204 #define PHY_UNTESTCLK                   0
 205 #define PHY_TESTCLR                     BIT(0)
 206 #define PHY_UNTESTCLR                   0
 207
 208 #define DSI_PHY_TST_CTRL1               0xb8
 209 #define PHY_TESTEN                      BIT(16)
 210 #define PHY_UNTESTEN                    0
 211 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 212 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 213
 214 #define DSI_INT_ST0                     0xbc
 215 #define DSI_INT_ST1                     0xc0
 216 #define DSI_INT_MSK0                    0xc4
 217 #define DSI_INT_MSK1                    0xc8
 218
 219 #define PHY_STATUS_TIMEOUT_US           10000
 220 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 221
 222 #define BYPASS_VCO_RANGE        BIT(7)
 223 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 224 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 225 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 226 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 227 #define REF_BIAS_CUR_SEL        BIT(0)
 228
 229 #define CP_CURRENT_3MA          BIT(3)
 230 #define CP_PROGRAM_EN           BIT(7)
 231 #define LPF_PROGRAM_EN          BIT(6)
 232 #define LPF_RESISTORS_20_KOHM   0
 233
 234 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 235
 236 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 237 #define LOW_PROGRAM_EN          0
 238 #define HIGH_PROGRAM_EN         BIT(7)
 239 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 240 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 241 #define PLL_LOOP_DIV_EN         BIT(5)
 242 #define PLL_INPUT_DIV_EN        BIT(4)
 243
 244 #define POWER_CONTROL           BIT(6)
 245 #define INTERNAL_REG_CURRENT    BIT(3)
 246 #define BIAS_BLOCK_ON           BIT(2)
 247 #define BANDGAP_ON              BIT(0)
 248
 249 #define TER_RESISTOR_HIGH       BIT(7)
 250 #define TER_RESISTOR_LOW        0
 251 #define LEVEL_SHIFTERS_ON       BIT(6)
 252 #define TER_CAL_DONE            BIT(5)
 253 #define SETRD_MAX               (0x7 << 2)
 254 #define POWER_MANAGE            BIT(1)
 255 #define TER_RESISTORS_ON        BIT(0)
 256
 257 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 258 #define BANDGAP_SEL(val)        ((val) & 0x7)
 259 #define TLP_PROGRAM_EN          BIT(7)
 260 #define THS_PRE_PROGRAM_EN      BIT(7)
 261 #define THS_ZERO_PROGRAM_EN     BIT(6)
 262
 263 enum {
 264         BANDGAP_97_07,
 265         BANDGAP_98_05,
 266         BANDGAP_99_02,
 267         BANDGAP_100_00,
 268         BANDGAP_93_17,
 269         BANDGAP_94_15,
 270         BANDGAP_95_12,
 271         BANDGAP_96_10,
 272 };
 273
 274 enum {
 275         BIASEXTR_87_1,
 276         BIASEXTR_91_5,
 277         BIASEXTR_95_9,
 278         BIASEXTR_100,
 279         BIASEXTR_105_94,
 280         BIASEXTR_111_88,
 281         BIASEXTR_118_8,
 282         BIASEXTR_127_7,
 283 };
 284
 285 struct dw_mipi_dsi_plat_data {
 286         u32 dsi0_en_bit;
 287         u32 dsi1_en_bit;
 288         u32 grf_switch_reg;
 289         u32 grf_dsi0_mode;
 290         u32 grf_dsi0_mode_reg;
 291         unsigned int max_data_lanes;
 292         u32 max_bit_rate_per_lane;
 293         bool has_vop_sel;
 294         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 295                                            struct drm_display_mode *mode);
 296 };
 297
 298 struct dw_mipi_dsi {
 299         struct drm_encoder encoder;
 300         struct drm_connector connector;
 301         struct mipi_dsi_host dsi_host;
 302         struct phy *phy;
 303         struct drm_panel *panel;
 304         struct device *dev;
 305         struct regmap *grf_regmap;
 306         struct reset_control *rst;
 307         void __iomem *base;
 308
 309         struct clk *pllref_clk;
 310         struct clk *pclk;
 311         struct clk *phy_cfg_clk;
 312
 313         unsigned long mode_flags;
 314         unsigned int lane_mbps; /* per lane */
 315         u32 channel;
 316         u32 lanes;
 317         u32 format;
 318         u16 input_div;
 319         u16 feedback_div;
 320         struct drm_display_mode mode;
 321
 322         const struct dw_mipi_dsi_plat_data *pdata;
 323 };
 324
 325 enum dw_mipi_dsi_mode {
 326         DSI_COMMAND_MODE,
 327         DSI_VIDEO_MODE,
 328 };
 329
 330 struct dphy_pll_testdin_map {
 331         unsigned int max_mbps;
 332         u8 testdin;
 333 };
 334
 335 /* The table is based on 27MHz DPHY pll reference clock. */
 336 static const struct dphy_pll_testdin_map dptdin_map[] = {
 337         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 338         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 339         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 340         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 341         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 342         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 343         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 344         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 345         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 346         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 347 };
 348
 349 static int max_mbps_to_testdin(unsigned int max_mbps)
 350 {
 351         int i;
 352
 353         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 354                 if (dptdin_map[i].max_mbps > max_mbps)
 355                         return dptdin_map[i].testdin;
 356
 357         return -EINVAL;
 358 }
 359
 360 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 361 {
 362         return container_of(host, struct dw_mipi_dsi, dsi_host);
 363 }
 364
 365 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 366 {
 367         return container_of(con, struct dw_mipi_dsi, connector);
 368 }
 369
 370 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 371 {
 372         return container_of(encoder, struct dw_mipi_dsi, encoder);
 373 }
 374 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 375 {
 376         writel(val, dsi->base + reg);
 377 }
 378
 379 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 380 {
 381         return readl(dsi->base + reg);
 382 }
 383
 384 static int rockchip_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi)
 385 {
 386         u32 sts;
 387         int ret;
 388
 389         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 390                                  sts, !(sts & GEN_PLD_W_FULL), 10,
 391                                  CMD_PKT_STATUS_TIMEOUT_US);
 392         if (ret < 0) {
 393                 dev_err(dsi->dev, "generic write payload fifo is full\n");
 394                 return ret;
 395         }
 396
 397         return 0;
 398 }
 399
 400 static int rockchip_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi)
 401 {
 402         u32 sts;
 403         int ret;
 404
 405         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 406                                  sts, !(sts & GEN_CMD_FULL), 10,
 407                                  CMD_PKT_STATUS_TIMEOUT_US);
 408         if (ret < 0) {
 409                 dev_err(dsi->dev, "generic write cmd fifo is full\n");
 410                 return ret;
 411         }
 412
 413         return 0;
 414 }
 415
 416 static int rockchip_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)
 417 {
 418         u32 sts;
 419         u32 mask;
 420         int ret;
 421
 422         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 423         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 424                                  sts, (sts & mask) == mask, 10,
 425                                  CMD_PKT_STATUS_TIMEOUT_US);
 426         if (ret < 0) {
 427                 dev_err(dsi->dev, "generic write fifo is full\n");
 428                 return ret;
 429         }
 430
 431         return 0;
 432 }
 433
 434 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 435                                  u8 test_data)
 436 {
 437         /*
 438          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 439          * is latched internally as the current test code. Test data is
 440          * programmed internally by rising edge on TESTCLK.
 441          */
 442         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 443
 444         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 445                                           PHY_TESTDIN(test_code));
 446
 447         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 448
 449         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 450                                           PHY_TESTDIN(test_data));
 451
 452         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 453 }
 454
 455 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 456 {
 457         int ret, testdin, vco, val;
 458
 459         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 460
 461         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 462         if (testdin < 0) {
 463                 dev_err(dsi->dev,
 464                         "failed to get testdin for %dmbps lane clock\n",
 465                         dsi->lane_mbps);
 466                 return testdin;
 467         }
 468
 469         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 470
 471         if (!IS_ERR(dsi->phy_cfg_clk)) {
 472                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 473                 if (ret) {
 474                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 475                         return ret;
 476                 }
 477         }
 478
 479         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 480                                          VCO_RANGE_CON_SEL(vco) |
 481                                          VCO_IN_CAP_CON_LOW |
 482                                          REF_BIAS_CUR_SEL);
 483
 484         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 485         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 486                                          LPF_RESISTORS_20_KOHM);
 487
 488         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 489
 490         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 491         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 492                                          LOW_PROGRAM_EN);
 493         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 494                                          HIGH_PROGRAM_EN);
 495         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 496
 497         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 498                                          BIAS_BLOCK_ON | BANDGAP_ON);
 499
 500         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 501                                          SETRD_MAX | TER_RESISTORS_ON);
 502         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 503                                          SETRD_MAX | POWER_MANAGE |
 504                                          TER_RESISTORS_ON);
 505
 506         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 507                                          BIASEXTR_SEL(BIASEXTR_127_7));
 508         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 509                                          BANDGAP_SEL(BANDGAP_96_10));
 510
 511         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 512         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 513         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 514
 515         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 516                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 517
 518         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 519                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 520         if (ret < 0) {
 521                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 522                 goto phy_init_end;
 523         }
 524
 525         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 526                                  val, val & STOP_STATE_CLK_LANE, 1000,
 527                                  PHY_STATUS_TIMEOUT_US);
 528         if (ret < 0)
 529                 dev_err(dsi->dev,
 530                         "failed to wait for phy clk lane stop state\n");
 531
 532 phy_init_end:
 533         if (!IS_ERR(dsi->phy_cfg_clk))
 534                 clk_disable_unprepare(dsi->phy_cfg_clk);
 535
 536         return ret;
 537 }
 538
 539 static int rockchip_dsi_calc_bandwidth(struct dw_mipi_dsi *dsi)
 540 {
 541         int bpp;
 542         unsigned long mpclk, tmp;
 543         unsigned int target_mbps = 1000;
 544         unsigned int value;
 545         struct device_node *np = dsi->dev->of_node;
 546         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 547         int lanes;
 548
 549         /* optional override of the desired bandwidth */
 550         if (!of_property_read_u32(np, "rockchip,lane-rate", &value))
 551                 return value;
 552
 553         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 554         if (bpp < 0) {
 555                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 556                         dsi->format);
 557                 bpp = 24;
 558         }
 559
 560         lanes = dsi->lanes;
 561
 562         mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
 563         if (mpclk) {
 564                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 565                 tmp = mpclk * (bpp / lanes) * 10 / 9;
 566                 if (tmp < max_mbps)
 567                         target_mbps = tmp;
 568                 else
 569                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 570         }
 571
 572         return target_mbps;
 573 }
 574
 575 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 576 {
 577         unsigned int i, pre;
 578         unsigned long pllref, tmp;
 579         unsigned int m = 1, n = 1, target_mbps;
 580
 581         target_mbps = rockchip_dsi_calc_bandwidth(dsi);
 582
 583         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 584         tmp = pllref;
 585
 586         for (i = 1; i < 6; i++) {
 587                 pre = pllref / i;
 588                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 589                         tmp = target_mbps % pre;
 590                         n = i;
 591                         m = target_mbps / pre;
 592                 }
 593                 if (tmp == 0)
 594                         break;
 595         }
 596
 597         dsi->lane_mbps = pllref / n * m;
 598         dsi->input_div = n;
 599         dsi->feedback_div = m;
 600
 601         return 0;
 602 }
 603
 604 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 605                                    struct mipi_dsi_device *device)
 606 {
 607         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 608
 609         if (device->lanes > dsi->pdata->max_data_lanes) {
 610                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 611                                 device->lanes);
 612                 return -EINVAL;
 613         }
 614
 615         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
 616                 dev_err(dsi->dev, "device mode is unsupported\n");
 617                 return -EINVAL;
 618         }
 619
 620         dsi->lanes = device->lanes;
 621         dsi->channel = device->channel;
 622         dsi->format = device->format;
 623         dsi->mode_flags = device->mode_flags;
 624
 625         dsi->panel = of_drm_find_panel(device->dev.of_node);
 626         if (!dsi->panel) {
 627                 DRM_ERROR("failed to find panel\n");
 628                 return -ENODEV;
 629         }
 630
 631         return 0;
 632 }
 633
 634 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 635                                    struct mipi_dsi_device *device)
 636 {
 637         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 638
 639         if (dsi->panel)
 640                 drm_panel_detach(dsi->panel);
 641
 642         dsi->panel = NULL;
 643         return 0;
 644 }
 645
 646 static void rockchip_set_transfer_mode(struct dw_mipi_dsi *dsi, int flags)
 647 {
 648         if (flags & MIPI_DSI_MSG_USE_LPM) {
 649                 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 650                 dsi_write(dsi, DSI_LPCLK_CTRL, 0);
 651         } else {
 652                 dsi_write(dsi, DSI_CMD_MODE_CFG, 0);
 653                 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 654         }
 655 }
 656
 657 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 658                                          const struct mipi_dsi_msg *msg)
 659 {
 660         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 661         struct mipi_dsi_packet packet;
 662         int ret;
 663         int val;
 664         int len = msg->tx_len;
 665
 666         /* create a packet to the DSI protocol */
 667         ret = mipi_dsi_create_packet(&packet, msg);
 668         if (ret) {
 669                 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 670                 return ret;
 671         }
 672
 673         rockchip_set_transfer_mode(dsi, msg->flags);
 674
 675         /* Send payload,  */
 676         while (DIV_ROUND_UP(packet.payload_length, 4)) {
 677                 /*
 678                  * Alternatively, you can always keep the FIFO
 679                  * nearly full by monitoring the FIFO state until
 680                  * it is not full, and then writea single word of data.
 681                  * This solution is more resource consuming
 682                  * but it simultaneously avoids FIFO starvation,
 683                  * making it possible to use FIFO sizes smaller than
 684                  * the amount of data of the longest packet to be written.
 685                  */
 686                 ret = rockchip_wait_w_pld_fifo_not_full(dsi);
 687                 if (ret)
 688                         return ret;
 689
 690                 if (packet.payload_length < 4) {
 691                         /* send residu payload */
 692                         val = 0;
 693                         memcpy(&val, packet.payload, packet.payload_length);
 694                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 695                         packet.payload_length = 0;
 696                 } else {
 697                         val = get_unaligned_le32(packet.payload);
 698                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 699                         packet.payload += 4;
 700                         packet.payload_length -= 4;
 701                 }
 702         }
 703
 704         ret = rockchip_wait_cmd_fifo_not_full(dsi);
 705         if (ret)
 706                 return ret;
 707
 708         /* Send packet header */
 709         val = get_unaligned_le32(packet.header);
 710         dsi_write(dsi, DSI_GEN_HDR, val);
 711
 712         ret = rockchip_wait_write_fifo_empty(dsi);
 713         if (ret)
 714                 return ret;
 715
 716         return len;
 717 }
 718
 719 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 720         .attach = dw_mipi_dsi_host_attach,
 721         .detach = dw_mipi_dsi_host_detach,
 722         .transfer = dw_mipi_dsi_host_transfer,
 723 };
 724
 725 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 726 {
 727         u32 val;
 728
 729         val = LP_HFP_EN | ENABLE_LOW_POWER;
 730
 731         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 732                 val |= VID_MODE_TYPE_BURST;
 733         else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 734                 val |= VID_MODE_TYPE_BURST_SYNC_PULSES;
 735         else
 736                 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS;
 737
 738         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 739 }
 740
 741 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 742                                  enum dw_mipi_dsi_mode mode)
 743 {
 744         if (mode == DSI_COMMAND_MODE)
 745                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 746         else
 747                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 748 }
 749
 750 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 751 {
 752         u32 esc_clk_div;
 753
 754         dsi_write(dsi, DSI_PWR_UP, RESET);
 755         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 756                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 757
 758         /* The maximum value of the escape clock frequency is 20MHz */
 759         esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20);
 760         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 761                   TX_ESC_CLK_DIVIDSION(esc_clk_div));
 762 }
 763
 764 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 765                                    struct drm_display_mode *mode)
 766 {
 767         u32 val = 0, color = 0;
 768
 769         switch (dsi->format) {
 770         case MIPI_DSI_FMT_RGB888:
 771                 color = DPI_COLOR_CODING_24BIT;
 772                 break;
 773         case MIPI_DSI_FMT_RGB666:
 774                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 775                 break;
 776         case MIPI_DSI_FMT_RGB666_PACKED:
 777                 color = DPI_COLOR_CODING_18BIT_1;
 778                 break;
 779         case MIPI_DSI_FMT_RGB565:
 780                 color = DPI_COLOR_CODING_16BIT_1;
 781                 break;
 782         }
 783
 784         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 785                 val |= VSYNC_ACTIVE_LOW;
 786         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 787                 val |= HSYNC_ACTIVE_LOW;
 788
 789         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 790         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 791         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 792         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 793                   | INVACT_LPCMD_TIME(4));
 794 }
 795
 796 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 797 {
 798         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 799 }
 800
 801 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 802                                             struct drm_display_mode *mode)
 803 {
 804         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 805 }
 806
 807 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 808 {
 809         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 810         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 811 }
 812
 813 /* Get lane byte clock cycles. */
 814 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 815                                            u32 hcomponent)
 816 {
 817         u32 lbcc;
 818
 819         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 820
 821         if (dsi->mode.clock == 0) {
 822                 dev_err(dsi->dev, "dsi mode clock is 0!\n");
 823                 return 0;
 824         }
 825
 826         return DIV_ROUND_CLOSEST_ULL(lbcc, dsi->mode.clock);
 827 }
 828
 829 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 830 {
 831         u32 htotal, hsa, hbp, lbcc;
 832         struct drm_display_mode *mode = &dsi->mode;
 833
 834         htotal = mode->htotal;
 835         hsa = mode->hsync_end - mode->hsync_start;
 836         hbp = mode->htotal - mode->hsync_end;
 837
 838         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 839         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 840
 841         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 842         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 843
 844         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 845         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 846 }
 847
 848 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 849 {
 850         u32 vactive, vsa, vfp, vbp;
 851         struct drm_display_mode *mode = &dsi->mode;
 852
 853         vactive = mode->vdisplay;
 854         vsa = mode->vsync_end - mode->vsync_start;
 855         vfp = mode->vsync_start - mode->vdisplay;
 856         vbp = mode->vtotal - mode->vsync_end;
 857
 858         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 859         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 860         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 861         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 862 }
 863
 864 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 865 {
 866         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
 867                   | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
 868
 869         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 870                   | PHY_CLKLP2HS_TIME(0x40));
 871 }
 872
 873 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 874 {
 875         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 876                   N_LANES(dsi->lanes));
 877 }
 878
 879 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 880 {
 881         dsi_read(dsi, DSI_INT_ST0);
 882         dsi_read(dsi, DSI_INT_ST1);
 883         dsi_write(dsi, DSI_INT_MSK0, 0);
 884         dsi_write(dsi, DSI_INT_MSK1, 0);
 885 }
 886
 887 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 888                                         struct drm_display_mode *mode,
 889                                         struct drm_display_mode *adjusted_mode)
 890 {
 891         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 892
 893         drm_mode_copy(&dsi->mode, adjusted_mode);
 894 }
 895
 896 static void rockchip_dsi_pre_disable(struct dw_mipi_dsi *dsi)
 897 {
 898         if (clk_prepare_enable(dsi->pclk)) {
 899                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 900                 return;
 901         }
 902
 903         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
 904 }
 905
 906 static void rockchip_dsi_disable(struct dw_mipi_dsi *dsi)
 907 {
 908         /* host */
 909         dsi_write(dsi, DSI_LPCLK_CTRL, 0);
 910         dsi_write(dsi, DSI_PWR_UP, RESET);
 911
 912         /* phy */
 913         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 914         if (dsi->phy)
 915                 phy_power_off(dsi->phy);
 916
 917         pm_runtime_put(dsi->dev);
 918         clk_disable_unprepare(dsi->pclk);
 919 }
 920
 921 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 922 {
 923         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 924
 925         if (dsi->panel)
 926                 drm_panel_disable(dsi->panel);
 927
 928         rockchip_dsi_pre_disable(dsi);
 929
 930         if (dsi->panel)
 931                 drm_panel_unprepare(dsi->panel);
 932
 933         rockchip_dsi_disable(dsi);
 934 }
 935
 936 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 937                                         const struct drm_display_mode *mode,
 938                                         struct drm_display_mode *adjusted_mode)
 939 {
 940         return true;
 941 }
 942
 943 static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
 944 {
 945         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 946         int val = 0;
 947
 948         if (pdata->grf_dsi0_mode_reg)
 949                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 950                              pdata->grf_dsi0_mode);
 951
 952         if (vop_id)
 953                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 954         else
 955                 val = pdata->dsi0_en_bit << 16;
 956
 957         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 958
 959         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (vop_id) ? "LIT" : "BIG");
 960 }
 961
 962 static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
 963 {
 964         if (clk_prepare_enable(dsi->pclk)) {
 965                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 966                 return;
 967         }
 968
 969         if (clk_prepare_enable(dsi->pllref_clk)) {
 970                 dev_err(dsi->dev, "Failed to enable pllref_clk\n");
 971                 return;
 972         }
 973
 974         pm_runtime_get_sync(dsi->dev);
 975
 976         if (dsi->rst) {
 977                 /* MIPI DSI APB software reset request. */
 978                 reset_control_assert(dsi->rst);
 979                 udelay(10);
 980                 reset_control_deassert(dsi->rst);
 981                 udelay(10);
 982         }
 983
 984         if (dsi->phy) {
 985                 phy_power_on(dsi->phy);
 986
 987                 /*
 988                  * If using the third party PHY, we get the lane
 989                  * rate information from PHY.
 990                  */
 991                 dsi->lane_mbps = phy_get_bus_width(dsi->phy);
 992         } else {
 993                 dw_mipi_dsi_get_lane_bps(dsi);
 994         }
 995 }
 996
 997 static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
 998 {
 999         dw_mipi_dsi_init(dsi);
1000         dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
1001         dw_mipi_dsi_packet_handler_config(dsi);
1002         dw_mipi_dsi_video_mode_config(dsi);
1003         dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
1004         dw_mipi_dsi_command_mode_config(dsi);
1005         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
1006         dw_mipi_dsi_line_timer_config(dsi);
1007         dw_mipi_dsi_vertical_timing_config(dsi);
1008         dw_mipi_dsi_dphy_timing_config(dsi);
1009         dw_mipi_dsi_dphy_interface_config(dsi);
1010         dw_mipi_dsi_clear_err(dsi);
1011 }
1012
1013 static void rockchip_dsi_init(struct dw_mipi_dsi *dsi)
1014 {
1015         rockchip_dsi_pre_init(dsi);
1016         rockchip_dsi_host_init(dsi);
1017         dw_mipi_dsi_phy_init(dsi);
1018 }
1019
1020 static void rockchip_dsi_enable(struct dw_mipi_dsi *dsi)
1021 {
1022         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
1023         dw_mipi_dsi_set_mode(dsi, DSI_VIDEO_MODE);
1024         clk_disable_unprepare(dsi->pllref_clk);
1025         clk_disable_unprepare(dsi->pclk);
1026 }
1027
1028 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
1029 {
1030         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1031         int vop_id;
1032
1033         vop_id = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
1034
1035         rockchip_dsi_grf_config(dsi, vop_id);
1036         rockchip_dsi_init(dsi);
1037
1038         if (dsi->panel)
1039                 drm_panel_prepare(dsi->panel);
1040
1041         rockchip_dsi_enable(dsi);
1042
1043         if (dsi->panel)
1044                 drm_panel_enable(dsi->panel);
1045 }
1046
1047 static int
1048 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
1049                                  struct drm_crtc_state *crtc_state,
1050                                  struct drm_connector_state *conn_state)
1051 {
1052         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1053         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1054         struct drm_connector *connector = conn_state->connector;
1055         struct drm_display_info *info = &connector->display_info;
1056
1057         switch (dsi->format) {
1058         case MIPI_DSI_FMT_RGB888:
1059                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1060                 break;
1061         case MIPI_DSI_FMT_RGB666:
1062                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1063                 break;
1064         case MIPI_DSI_FMT_RGB565:
1065                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1066                 break;
1067         default:
1068                 WARN_ON(1);
1069                 return -EINVAL;
1070         }
1071
1072         s->output_type = DRM_MODE_CONNECTOR_DSI;
1073         if (info->num_bus_formats)
1074                 s->bus_format = info->bus_formats[0];
1075
1076         return 0;
1077 }
1078
1079 static struct drm_encoder_helper_funcs
1080 dw_mipi_dsi_encoder_helper_funcs = {
1081         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1082         .mode_set = dw_mipi_dsi_encoder_mode_set,
1083         .enable = dw_mipi_dsi_encoder_enable,
1084         .disable = dw_mipi_dsi_encoder_disable,
1085         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1086 };
1087
1088 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1089         .destroy = drm_encoder_cleanup,
1090 };
1091
1092 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1093 {
1094         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1095
1096         return drm_panel_get_modes(dsi->panel);
1097 }
1098
1099 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1100                                         struct drm_connector *connector,
1101                                         struct drm_display_mode *mode)
1102 {
1103         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1104
1105         enum drm_mode_status mode_status = MODE_OK;
1106
1107         if (dsi->pdata->mode_valid)
1108                 mode_status = dsi->pdata->mode_valid(connector, mode);
1109
1110         return mode_status;
1111 }
1112
1113 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1114                                         struct drm_connector *connector)
1115 {
1116         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1117
1118         return &dsi->encoder;
1119 }
1120
1121 static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
1122 {
1123         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1124
1125         if (dsi->panel)
1126                 drm_panel_loader_protect(dsi->panel, on);
1127         if (on)
1128                 pm_runtime_get_sync(dsi->dev);
1129         else
1130                 pm_runtime_put(dsi->dev);
1131
1132         return 0;
1133 }
1134
1135 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1136         .loader_protect = dw_mipi_loader_protect,
1137         .get_modes = dw_mipi_dsi_connector_get_modes,
1138         .mode_valid = dw_mipi_dsi_mode_valid,
1139         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1140 };
1141
1142 static enum drm_connector_status
1143 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1144 {
1145         return connector_status_connected;
1146 }
1147
1148 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1149 {
1150         drm_connector_unregister(connector);
1151         drm_connector_cleanup(connector);
1152 }
1153
1154 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1155         .dpms = drm_atomic_helper_connector_dpms,
1156         .fill_modes = drm_helper_probe_single_connector_modes,
1157         .detect = dw_mipi_dsi_detect,
1158         .destroy = dw_mipi_dsi_drm_connector_destroy,
1159         .reset = drm_atomic_helper_connector_reset,
1160         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1161         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1162 };
1163
1164 static int dw_mipi_dsi_register(struct drm_device *drm,
1165                                       struct dw_mipi_dsi *dsi)
1166 {
1167         struct drm_encoder *encoder = &dsi->encoder;
1168         struct drm_connector *connector = &dsi->connector;
1169         struct device *dev = dsi->dev;
1170         int ret;
1171
1172         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1173                                                              dev->of_node);
1174         /*
1175          * If we failed to find the CRTC(s) which this encoder is
1176          * supposed to be connected to, it's because the CRTC has
1177          * not been registered yet.  Defer probing, and hope that
1178          * the required CRTC is added later.
1179          */
1180         if (encoder->possible_crtcs == 0)
1181                 return -EPROBE_DEFER;
1182
1183         drm_encoder_helper_add(&dsi->encoder,
1184                                &dw_mipi_dsi_encoder_helper_funcs);
1185         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1186                          DRM_MODE_ENCODER_DSI, NULL);
1187         if (ret) {
1188                 dev_err(dev, "Failed to initialize encoder with drm\n");
1189                 return ret;
1190         }
1191
1192         drm_connector_helper_add(connector,
1193                         &dw_mipi_dsi_connector_helper_funcs);
1194
1195         drm_connector_init(drm, &dsi->connector,
1196                            &dw_mipi_dsi_atomic_connector_funcs,
1197                            DRM_MODE_CONNECTOR_DSI);
1198
1199         drm_panel_attach(dsi->panel, &dsi->connector);
1200
1201         dsi->connector.port = dev->of_node;
1202
1203         drm_mode_connector_attach_encoder(connector, encoder);
1204
1205         return 0;
1206 }
1207
1208 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1209         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1210         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1211         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1212         .max_data_lanes = 4,
1213         .max_bit_rate_per_lane = 1500000000,
1214         .has_vop_sel = true,
1215 };
1216
1217 static struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data = {
1218         .dsi0_en_bit = RK3366_DSI_SEL_VOP_LIT,
1219         .grf_switch_reg = RK3366_GRF_SOC_CON0,
1220         .max_data_lanes = 4,
1221         .max_bit_rate_per_lane = 1000000000,
1222         .has_vop_sel = true,
1223 };
1224
1225 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1226         .max_data_lanes = 4,
1227         .max_bit_rate_per_lane = 1000000000,
1228 };
1229
1230 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1231         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1232         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1233         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1234         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1235         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1236         .max_data_lanes = 4,
1237         .max_bit_rate_per_lane = 1500000000,
1238         .has_vop_sel = true,
1239 };
1240
1241 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1242         {
1243          .compatible = "rockchip,rk3288-mipi-dsi",
1244          .data = &rk3288_mipi_dsi_drv_data,
1245         }, {
1246          .compatible = "rockchip,rk3366-mipi-dsi",
1247          .data = &rk3366_mipi_dsi_drv_data,
1248         }, {
1249          .compatible = "rockchip,rk3368-mipi-dsi",
1250          .data = &rk3368_mipi_dsi_drv_data,
1251         }, {
1252          .compatible = "rockchip,rk3399-mipi-dsi",
1253          .data = &rk3399_mipi_dsi_drv_data,
1254         },
1255         { /* sentinel */ }
1256 };
1257 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1258
1259 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1260                              void *data)
1261 {
1262         struct drm_device *drm = data;
1263         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1264         int ret;
1265
1266         if (!dsi->panel)
1267                 return -EPROBE_DEFER;
1268
1269         ret = dw_mipi_dsi_register(drm, dsi);
1270         if (ret) {
1271                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1272                 return ret;
1273         }
1274
1275         dev_set_drvdata(dev, dsi);
1276
1277         pm_runtime_enable(dev);
1278
1279         return ret;
1280 }
1281
1282 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1283         void *data)
1284 {
1285         pm_runtime_disable(dev);
1286 }
1287
1288 static const struct component_ops dw_mipi_dsi_ops = {
1289         .bind   = dw_mipi_dsi_bind,
1290         .unbind = dw_mipi_dsi_unbind,
1291 };
1292
1293 static int rockchip_dsi_get_reset_handle(struct dw_mipi_dsi *dsi)
1294 {
1295         struct device *dev = dsi->dev;
1296
1297         dsi->rst = devm_reset_control_get_optional(dev, "apb");
1298         if (IS_ERR(dsi->rst)) {
1299                 dev_info(dev, "no reset control specified\n");
1300                 dsi->rst = NULL;
1301         }
1302
1303         return 0;
1304 }
1305
1306 static int rockchip_dsi_grf_regmap(struct dw_mipi_dsi *dsi)
1307 {
1308         struct device_node *np = dsi->dev->of_node;
1309
1310         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1311         if (IS_ERR(dsi->grf_regmap)) {
1312                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1313                 return PTR_ERR(dsi->grf_regmap);
1314         }
1315
1316         return 0;
1317 }
1318
1319 static int rockchip_dsi_clk_get(struct dw_mipi_dsi *dsi)
1320 {
1321         struct device *dev = dsi->dev;
1322         int ret;
1323
1324         dsi->pclk = devm_clk_get(dev, "pclk");
1325         if (IS_ERR(dsi->pclk)) {
1326                 ret = PTR_ERR(dsi->pclk);
1327                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1328                 return ret;
1329         }
1330
1331         dsi->pllref_clk = devm_clk_get(dev, "ref");
1332         if (IS_ERR(dsi->pllref_clk)) {
1333                 dev_info(dev, "No PHY reference clock specified\n");
1334                 dsi->pllref_clk = NULL;
1335         }
1336
1337         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1338         if (IS_ERR(dsi->phy_cfg_clk)) {
1339                 dev_info(dev, "No PHY APB clock specified\n");
1340                 dsi->phy_cfg_clk = NULL;
1341         }
1342
1343         return 0;
1344 }
1345
1346 static int rockchip_dsi_dphy_parse(struct dw_mipi_dsi *dsi)
1347 {
1348         struct device *dev = dsi->dev;
1349         int ret;
1350
1351         dsi->phy = devm_phy_optional_get(dev, "mipi_dphy");
1352         if (IS_ERR(dsi->phy)) {
1353                 ret = PTR_ERR(dsi->phy);
1354                 dev_err(dev, "failed to get mipi dphy: %d\n", ret);
1355                 return ret;
1356         }
1357
1358         return 0;
1359 }
1360
1361 static int rockchip_dsi_ioremap_resource(struct platform_device *pdev,
1362                                          struct dw_mipi_dsi *dsi)
1363 {
1364         struct device *dev = &pdev->dev;
1365         struct resource *res;
1366
1367         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1368         if (!res)
1369                 return -ENODEV;
1370
1371         dsi->base = devm_ioremap_resource(dev, res);
1372         if (IS_ERR(dsi->base))
1373                 return PTR_ERR(dsi->base);
1374
1375         return 0;
1376 }
1377
1378 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1379 {
1380         struct device *dev = &pdev->dev;
1381         const struct of_device_id *of_id =
1382                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1383         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1384         struct dw_mipi_dsi *dsi;
1385         int ret;
1386
1387         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1388         if (!dsi)
1389                 return -ENOMEM;
1390
1391         dsi->dev = dev;
1392         dsi->pdata = pdata;
1393
1394         rockchip_dsi_ioremap_resource(pdev, dsi);
1395         rockchip_dsi_clk_get(dsi);
1396         rockchip_dsi_dphy_parse(dsi);
1397         rockchip_dsi_grf_regmap(dsi);
1398         rockchip_dsi_get_reset_handle(dsi);
1399
1400         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1401         dsi->dsi_host.dev = &pdev->dev;
1402
1403         ret = mipi_dsi_host_register(&dsi->dsi_host);
1404         if (ret)
1405                 return ret;
1406
1407         platform_set_drvdata(pdev, dsi);
1408         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1409         if (ret)
1410                 mipi_dsi_host_unregister(&dsi->dsi_host);
1411
1412         return ret;
1413 }
1414
1415 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1416 {
1417         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1418
1419         if (dsi)
1420                 mipi_dsi_host_unregister(&dsi->dsi_host);
1421         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1422         return 0;
1423 }
1424
1425 static struct platform_driver dw_mipi_dsi_driver = {
1426         .probe          = dw_mipi_dsi_probe,
1427         .remove         = dw_mipi_dsi_remove,
1428         .driver         = {
1429                 .of_match_table = dw_mipi_dsi_dt_ids,
1430                 .name   = DRIVER_NAME,
1431         },
1432 };
1433 module_platform_driver(dw_mipi_dsi_driver);
1434
1435 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1436 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1437 MODULE_LICENSE("GPL");
1438 MODULE_ALIAS("platform:" DRIVER_NAME);