Merge tag 'edac_urgent_for_4.2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / radeon / vce_v2_0.c
1 /*
2  * Copyright 2013 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  * Authors: Christian König <christian.koenig@amd.com>
26  */
27
28 #include <linux/firmware.h>
29 #include <drm/drmP.h>
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "cikd.h"
33
34 #define VCE_V2_0_FW_SIZE        (256 * 1024)
35 #define VCE_V2_0_STACK_SIZE     (64 * 1024)
36 #define VCE_V2_0_DATA_SIZE      (23552 * RADEON_MAX_VCE_HANDLES)
37
38 static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
39 {
40         u32 tmp;
41
42         if (gated) {
43                 tmp = RREG32(VCE_CLOCK_GATING_B);
44                 tmp |= 0xe70000;
45                 WREG32(VCE_CLOCK_GATING_B, tmp);
46
47                 tmp = RREG32(VCE_UENC_CLOCK_GATING);
48                 tmp |= 0xff000000;
49                 WREG32(VCE_UENC_CLOCK_GATING, tmp);
50
51                 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
52                 tmp &= ~0x3fc;
53                 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
54
55                 WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
56     } else {
57                 tmp = RREG32(VCE_CLOCK_GATING_B);
58                 tmp |= 0xe7;
59                 tmp &= ~0xe70000;
60                 WREG32(VCE_CLOCK_GATING_B, tmp);
61
62                 tmp = RREG32(VCE_UENC_CLOCK_GATING);
63                 tmp |= 0x1fe000;
64                 tmp &= ~0xff000000;
65                 WREG32(VCE_UENC_CLOCK_GATING, tmp);
66
67                 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
68                 tmp |= 0x3fc;
69                 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
70         }
71 }
72
73 static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated)
74 {
75         u32 orig, tmp;
76
77         tmp = RREG32(VCE_CLOCK_GATING_B);
78         tmp &= ~0x00060006;
79         if (gated) {
80                 tmp |= 0xe10000;
81         } else {
82                 tmp |= 0xe1;
83                 tmp &= ~0xe10000;
84         }
85         WREG32(VCE_CLOCK_GATING_B, tmp);
86
87         orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
88         tmp &= ~0x1fe000;
89         tmp &= ~0xff000000;
90         if (tmp != orig)
91                 WREG32(VCE_UENC_CLOCK_GATING, tmp);
92
93         orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
94         tmp &= ~0x3fc;
95         if (tmp != orig)
96                 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
97
98         if (gated)
99                 WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
100 }
101
102 static void vce_v2_0_disable_cg(struct radeon_device *rdev)
103 {
104         WREG32(VCE_CGTT_CLK_OVERRIDE, 7);
105 }
106
107 void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)
108 {
109         bool sw_cg = false;
110
111         if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
112                 if (sw_cg)
113                         vce_v2_0_set_sw_cg(rdev, true);
114                 else
115                         vce_v2_0_set_dyn_cg(rdev, true);
116         } else {
117                 vce_v2_0_disable_cg(rdev);
118
119                 if (sw_cg)
120                         vce_v2_0_set_sw_cg(rdev, false);
121                 else
122                         vce_v2_0_set_dyn_cg(rdev, false);
123         }
124 }
125
126 static void vce_v2_0_init_cg(struct radeon_device *rdev)
127 {
128         u32 tmp;
129
130         tmp = RREG32(VCE_CLOCK_GATING_A);
131         tmp &= ~(CGC_CLK_GATE_DLY_TIMER_MASK | CGC_CLK_GATER_OFF_DLY_TIMER_MASK);
132         tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4));
133         tmp |= CGC_UENC_WAIT_AWAKE;
134         WREG32(VCE_CLOCK_GATING_A, tmp);
135
136         tmp = RREG32(VCE_UENC_CLOCK_GATING);
137         tmp &= ~(CLOCK_ON_DELAY_MASK | CLOCK_OFF_DELAY_MASK);
138         tmp |= (CLOCK_ON_DELAY(0) | CLOCK_OFF_DELAY(4));
139         WREG32(VCE_UENC_CLOCK_GATING, tmp);
140
141         tmp = RREG32(VCE_CLOCK_GATING_B);
142         tmp |= 0x10;
143         tmp &= ~0x100000;
144         WREG32(VCE_CLOCK_GATING_B, tmp);
145 }
146
147 unsigned vce_v2_0_bo_size(struct radeon_device *rdev)
148 {
149         WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE);
150         return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE;
151 }
152
153 int vce_v2_0_resume(struct radeon_device *rdev)
154 {
155         uint64_t addr = rdev->vce.gpu_addr;
156         uint32_t size;
157
158         WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
159         WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
160         WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
161         WREG32(VCE_CLOCK_GATING_B, 0xf7);
162
163         WREG32(VCE_LMI_CTRL, 0x00398000);
164         WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
165         WREG32(VCE_LMI_SWAP_CNTL, 0);
166         WREG32(VCE_LMI_SWAP_CNTL1, 0);
167         WREG32(VCE_LMI_VM_CTRL, 0);
168
169         WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
170
171         addr &= 0xff;
172         size = VCE_V2_0_FW_SIZE;
173         WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
174         WREG32(VCE_VCPU_CACHE_SIZE0, size);
175
176         addr += size;
177         size = VCE_V2_0_STACK_SIZE;
178         WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
179         WREG32(VCE_VCPU_CACHE_SIZE1, size);
180
181         addr += size;
182         size = VCE_V2_0_DATA_SIZE;
183         WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
184         WREG32(VCE_VCPU_CACHE_SIZE2, size);
185
186         WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
187
188         WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,
189                  ~VCE_SYS_INT_TRAP_INTERRUPT_EN);
190
191         vce_v2_0_init_cg(rdev);
192
193         return 0;
194 }