2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
25 #include <linux/firmware.h>
30 #include "radeon_ucode.h"
32 static int si_set_smc_sram_address(struct radeon_device *rdev,
33 u32 smc_address, u32 limit)
37 if ((smc_address + 3) > limit)
40 WREG32(SMC_IND_INDEX_0, smc_address);
41 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
46 int si_copy_bytes_to_smc(struct radeon_device *rdev,
47 u32 smc_start_address,
48 const u8 *src, u32 byte_count, u32 limit)
52 u32 data, original_data, addr, extra_shift;
54 if (smc_start_address & 3)
56 if ((smc_start_address + byte_count) > limit)
59 addr = smc_start_address;
61 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
62 while (byte_count >= 4) {
63 /* SMC address space is BE */
64 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
66 ret = si_set_smc_sram_address(rdev, addr, limit);
70 WREG32(SMC_IND_DATA_0, data);
77 /* RMW for the final bytes */
81 ret = si_set_smc_sram_address(rdev, addr, limit);
85 original_data = RREG32(SMC_IND_DATA_0);
87 extra_shift = 8 * (4 - byte_count);
89 while (byte_count > 0) {
90 /* SMC address space is BE */
91 data = (data << 8) + *src++;
97 data |= (original_data & ~((~0UL) << extra_shift));
99 ret = si_set_smc_sram_address(rdev, addr, limit);
103 WREG32(SMC_IND_DATA_0, data);
107 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
112 void si_start_smc(struct radeon_device *rdev)
114 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
118 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
121 void si_reset_smc(struct radeon_device *rdev)
125 RREG32(CB_CGTT_SCLK_CTRL);
126 RREG32(CB_CGTT_SCLK_CTRL);
127 RREG32(CB_CGTT_SCLK_CTRL);
128 RREG32(CB_CGTT_SCLK_CTRL);
130 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
132 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
135 int si_program_jump_on_start(struct radeon_device *rdev)
137 static u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
139 return si_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1);
142 void si_stop_smc_clock(struct radeon_device *rdev)
144 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
148 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
151 void si_start_smc_clock(struct radeon_device *rdev)
153 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
157 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
160 bool si_is_smc_running(struct radeon_device *rdev)
162 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
163 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
165 if (!(rst & RST_REG) && !(clk & CK_DISABLE))
171 PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
176 if (!si_is_smc_running(rdev))
177 return PPSMC_Result_Failed;
179 WREG32(SMC_MESSAGE_0, msg);
181 for (i = 0; i < rdev->usec_timeout; i++) {
182 tmp = RREG32(SMC_RESP_0);
187 tmp = RREG32(SMC_RESP_0);
189 return (PPSMC_Result)tmp;
192 PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev)
197 if (!si_is_smc_running(rdev))
198 return PPSMC_Result_OK;
200 for (i = 0; i < rdev->usec_timeout; i++) {
201 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
202 if ((tmp & CKEN) == 0)
207 return PPSMC_Result_OK;
210 int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)
213 u32 ucode_start_address;
221 switch (rdev->family) {
223 ucode_start_address = TAHITI_SMC_UCODE_START;
224 ucode_size = TAHITI_SMC_UCODE_SIZE;
227 ucode_start_address = PITCAIRN_SMC_UCODE_START;
228 ucode_size = PITCAIRN_SMC_UCODE_SIZE;
231 ucode_start_address = VERDE_SMC_UCODE_START;
232 ucode_size = VERDE_SMC_UCODE_SIZE;
235 ucode_start_address = OLAND_SMC_UCODE_START;
236 ucode_size = OLAND_SMC_UCODE_SIZE;
239 ucode_start_address = HAINAN_SMC_UCODE_START;
240 ucode_size = HAINAN_SMC_UCODE_SIZE;
243 DRM_ERROR("unknown asic in smc ucode loader\n");
250 src = (const u8 *)rdev->smc_fw->data;
251 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
252 WREG32(SMC_IND_INDEX_0, ucode_start_address);
253 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
254 while (ucode_size >= 4) {
255 /* SMC address space is BE */
256 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
258 WREG32(SMC_IND_DATA_0, data);
263 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
264 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
269 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
270 u32 *value, u32 limit)
275 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
276 ret = si_set_smc_sram_address(rdev, smc_address, limit);
278 *value = RREG32(SMC_IND_DATA_0);
279 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
284 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
285 u32 value, u32 limit)
290 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
291 ret = si_set_smc_sram_address(rdev, smc_address, limit);
293 WREG32(SMC_IND_DATA_0, value);
294 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);