2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon_asic.h"
31 #include <linux/math64.h>
32 #include <linux/seq_file.h>
34 #define MC_CG_ARB_FREQ_F0 0x0a
35 #define MC_CG_ARB_FREQ_F1 0x0b
36 #define MC_CG_ARB_FREQ_F2 0x0c
37 #define MC_CG_ARB_FREQ_F3 0x0d
39 #define SMC_RAM_END 0x20000
41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
43 static const struct si_cac_config_reg cac_weights_tahiti[] =
45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
108 static const struct si_cac_config_reg lcac_tahiti[] =
110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
200 static const struct si_cac_config_reg cac_override_tahiti[] =
205 static const struct si_powertune_data powertune_data_tahiti =
236 static const struct si_dte_data dte_data_tahiti =
238 { 1159409, 0, 0, 0, 0 },
247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
254 static const struct si_dte_data dte_data_tahiti_le =
256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
272 static const struct si_dte_data dte_data_tahiti_pro =
274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
275 { 0x0, 0x0, 0x0, 0x0, 0x0 },
283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
290 static const struct si_dte_data dte_data_new_zealand =
292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
308 static const struct si_dte_data dte_data_aruba_pro =
310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
311 { 0x0, 0x0, 0x0, 0x0, 0x0 },
319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
326 static const struct si_dte_data dte_data_malta =
328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
329 { 0x0, 0x0, 0x0, 0x0, 0x0 },
337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
344 struct si_cac_config_reg cac_weights_pitcairn[] =
346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
409 static const struct si_cac_config_reg lcac_pitcairn[] =
411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
500 static const struct si_cac_config_reg cac_override_pitcairn[] =
505 static const struct si_powertune_data powertune_data_pitcairn =
536 static const struct si_dte_data dte_data_pitcairn =
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
554 static const struct si_dte_data dte_data_curacao_xt =
556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
557 { 0x0, 0x0, 0x0, 0x0, 0x0 },
565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
572 static const struct si_dte_data dte_data_curacao_pro =
574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
575 { 0x0, 0x0, 0x0, 0x0, 0x0 },
583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
590 static const struct si_dte_data dte_data_neptune_xt =
592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
593 { 0x0, 0x0, 0x0, 0x0, 0x0 },
601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
738 static const struct si_cac_config_reg cac_weights_heathrow[] =
740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
933 static const struct si_cac_config_reg lcac_cape_verde[] =
935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
992 static const struct si_cac_config_reg cac_override_cape_verde[] =
997 static const struct si_powertune_data powertune_data_cape_verde =
999 ((1 << 16) | 0x6993),
1028 static const struct si_dte_data dte_data_cape_verde =
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1046 static const struct si_dte_data dte_data_venus_xtx =
1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1064 static const struct si_dte_data dte_data_venus_xt =
1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1082 static const struct si_dte_data dte_data_venus_pro =
1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1100 struct si_cac_config_reg cac_weights_oland[] =
1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1425 static const struct si_cac_config_reg lcac_oland[] =
1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1519 static const struct si_cac_config_reg cac_override_oland[] =
1524 static const struct si_powertune_data powertune_data_oland =
1526 ((1 << 16) | 0x6993),
1555 static const struct si_powertune_data powertune_data_mars_pro =
1557 ((1 << 16) | 0x6993),
1586 static const struct si_dte_data dte_data_oland =
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1604 static const struct si_dte_data dte_data_mars_pro =
1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1622 static const struct si_dte_data dte_data_sun_xt =
1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1706 static const struct si_powertune_data powertune_data_hainan =
1708 ((1 << 16) | 0x6993),
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1744 static int si_populate_voltage_value(struct radeon_device *rdev,
1745 const struct atom_voltage_table *table,
1746 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1747 static int si_get_std_voltage_value(struct radeon_device *rdev,
1748 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1750 static int si_write_smc_soft_register(struct radeon_device *rdev,
1751 u16 reg_offset, u32 value);
1752 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1753 struct rv7xx_pl *pl,
1754 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1755 static int si_calculate_sclk_params(struct radeon_device *rdev,
1757 SISLANDS_SMC_SCLK_VALUE *sclk);
1759 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1760 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1764 struct si_power_info *pi = rdev->pm.dpm.priv;
1769 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1770 u16 v, s32 t, u32 ileakage, u32 *leakage)
1772 s64 kt, kv, leakage_w, i_leakage, vddc;
1773 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1776 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1777 vddc = div64_s64(drm_int2fixp(v), 1000);
1778 temperature = div64_s64(drm_int2fixp(t), 1000);
1780 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1781 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1782 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1783 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1784 t_ref = drm_int2fixp(coeff->t_ref);
1786 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1787 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1788 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1789 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1791 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1793 *leakage = drm_fixp2int(leakage_w * 1000);
1796 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1797 const struct ni_leakage_coeffients *coeff,
1803 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1806 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1807 const u32 fixed_kt, u16 v,
1808 u32 ileakage, u32 *leakage)
1810 s64 kt, kv, leakage_w, i_leakage, vddc;
1812 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1813 vddc = div64_s64(drm_int2fixp(v), 1000);
1815 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1816 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1817 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1819 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1821 *leakage = drm_fixp2int(leakage_w * 1000);
1824 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1825 const struct ni_leakage_coeffients *coeff,
1831 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1835 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1836 struct si_dte_data *dte_data)
1838 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1839 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1840 u32 k = dte_data->k;
1841 u32 t_max = dte_data->max_t;
1842 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1843 u32 t_0 = dte_data->t0;
1846 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1847 dte_data->tdep_count = 3;
1849 for (i = 0; i < k; i++) {
1851 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1852 (p_limit2 * (u32)100);
1855 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1857 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1858 dte_data->tdep_r[i] = dte_data->r[4];
1861 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1865 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1867 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1868 struct si_power_info *si_pi = si_get_pi(rdev);
1869 bool update_dte_from_pl2 = false;
1871 if (rdev->family == CHIP_TAHITI) {
1872 si_pi->cac_weights = cac_weights_tahiti;
1873 si_pi->lcac_config = lcac_tahiti;
1874 si_pi->cac_override = cac_override_tahiti;
1875 si_pi->powertune_data = &powertune_data_tahiti;
1876 si_pi->dte_data = dte_data_tahiti;
1878 switch (rdev->pdev->device) {
1880 si_pi->dte_data.enable_dte_by_default = true;
1883 si_pi->dte_data = dte_data_new_zealand;
1889 si_pi->dte_data = dte_data_aruba_pro;
1890 update_dte_from_pl2 = true;
1893 si_pi->dte_data = dte_data_malta;
1894 update_dte_from_pl2 = true;
1897 si_pi->dte_data = dte_data_tahiti_pro;
1898 update_dte_from_pl2 = true;
1901 if (si_pi->dte_data.enable_dte_by_default == true)
1902 DRM_ERROR("DTE is not enabled!\n");
1905 } else if (rdev->family == CHIP_PITCAIRN) {
1906 switch (rdev->pdev->device) {
1909 si_pi->cac_weights = cac_weights_pitcairn;
1910 si_pi->lcac_config = lcac_pitcairn;
1911 si_pi->cac_override = cac_override_pitcairn;
1912 si_pi->powertune_data = &powertune_data_pitcairn;
1913 si_pi->dte_data = dte_data_curacao_xt;
1914 update_dte_from_pl2 = true;
1918 si_pi->cac_weights = cac_weights_pitcairn;
1919 si_pi->lcac_config = lcac_pitcairn;
1920 si_pi->cac_override = cac_override_pitcairn;
1921 si_pi->powertune_data = &powertune_data_pitcairn;
1922 si_pi->dte_data = dte_data_curacao_pro;
1923 update_dte_from_pl2 = true;
1927 si_pi->cac_weights = cac_weights_pitcairn;
1928 si_pi->lcac_config = lcac_pitcairn;
1929 si_pi->cac_override = cac_override_pitcairn;
1930 si_pi->powertune_data = &powertune_data_pitcairn;
1931 si_pi->dte_data = dte_data_neptune_xt;
1932 update_dte_from_pl2 = true;
1935 si_pi->cac_weights = cac_weights_pitcairn;
1936 si_pi->lcac_config = lcac_pitcairn;
1937 si_pi->cac_override = cac_override_pitcairn;
1938 si_pi->powertune_data = &powertune_data_pitcairn;
1939 si_pi->dte_data = dte_data_pitcairn;
1942 } else if (rdev->family == CHIP_VERDE) {
1943 si_pi->lcac_config = lcac_cape_verde;
1944 si_pi->cac_override = cac_override_cape_verde;
1945 si_pi->powertune_data = &powertune_data_cape_verde;
1947 switch (rdev->pdev->device) {
1952 si_pi->cac_weights = cac_weights_cape_verde_pro;
1953 si_pi->dte_data = dte_data_cape_verde;
1956 si_pi->cac_weights = cac_weights_cape_verde_pro;
1957 si_pi->dte_data = dte_data_sun_xt;
1961 si_pi->cac_weights = cac_weights_heathrow;
1962 si_pi->dte_data = dte_data_cape_verde;
1966 si_pi->cac_weights = cac_weights_chelsea_xt;
1967 si_pi->dte_data = dte_data_cape_verde;
1970 si_pi->cac_weights = cac_weights_chelsea_pro;
1971 si_pi->dte_data = dte_data_cape_verde;
1974 si_pi->cac_weights = cac_weights_heathrow;
1975 si_pi->dte_data = dte_data_venus_xtx;
1978 si_pi->cac_weights = cac_weights_heathrow;
1979 si_pi->dte_data = dte_data_venus_xt;
1985 si_pi->cac_weights = cac_weights_chelsea_pro;
1986 si_pi->dte_data = dte_data_venus_pro;
1989 si_pi->cac_weights = cac_weights_cape_verde;
1990 si_pi->dte_data = dte_data_cape_verde;
1993 } else if (rdev->family == CHIP_OLAND) {
1994 switch (rdev->pdev->device) {
1999 si_pi->cac_weights = cac_weights_mars_pro;
2000 si_pi->lcac_config = lcac_mars_pro;
2001 si_pi->cac_override = cac_override_oland;
2002 si_pi->powertune_data = &powertune_data_mars_pro;
2003 si_pi->dte_data = dte_data_mars_pro;
2004 update_dte_from_pl2 = true;
2010 si_pi->cac_weights = cac_weights_mars_xt;
2011 si_pi->lcac_config = lcac_mars_pro;
2012 si_pi->cac_override = cac_override_oland;
2013 si_pi->powertune_data = &powertune_data_mars_pro;
2014 si_pi->dte_data = dte_data_mars_pro;
2015 update_dte_from_pl2 = true;
2020 si_pi->cac_weights = cac_weights_oland_pro;
2021 si_pi->lcac_config = lcac_mars_pro;
2022 si_pi->cac_override = cac_override_oland;
2023 si_pi->powertune_data = &powertune_data_mars_pro;
2024 si_pi->dte_data = dte_data_mars_pro;
2025 update_dte_from_pl2 = true;
2028 si_pi->cac_weights = cac_weights_oland_xt;
2029 si_pi->lcac_config = lcac_mars_pro;
2030 si_pi->cac_override = cac_override_oland;
2031 si_pi->powertune_data = &powertune_data_mars_pro;
2032 si_pi->dte_data = dte_data_mars_pro;
2033 update_dte_from_pl2 = true;
2036 si_pi->cac_weights = cac_weights_oland;
2037 si_pi->lcac_config = lcac_oland;
2038 si_pi->cac_override = cac_override_oland;
2039 si_pi->powertune_data = &powertune_data_oland;
2040 si_pi->dte_data = dte_data_oland;
2043 } else if (rdev->family == CHIP_HAINAN) {
2044 si_pi->cac_weights = cac_weights_hainan;
2045 si_pi->lcac_config = lcac_oland;
2046 si_pi->cac_override = cac_override_oland;
2047 si_pi->powertune_data = &powertune_data_hainan;
2048 si_pi->dte_data = dte_data_sun_xt;
2049 update_dte_from_pl2 = true;
2051 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2055 ni_pi->enable_power_containment = false;
2056 ni_pi->enable_cac = false;
2057 ni_pi->enable_sq_ramping = false;
2058 si_pi->enable_dte = false;
2060 if (si_pi->powertune_data->enable_powertune_by_default) {
2061 ni_pi->enable_power_containment= true;
2062 ni_pi->enable_cac = true;
2063 if (si_pi->dte_data.enable_dte_by_default) {
2064 si_pi->enable_dte = true;
2065 if (update_dte_from_pl2)
2066 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2069 ni_pi->enable_sq_ramping = true;
2072 ni_pi->driver_calculate_cac_leakage = true;
2073 ni_pi->cac_configuration_required = true;
2075 if (ni_pi->cac_configuration_required) {
2076 ni_pi->support_cac_long_term_average = true;
2077 si_pi->dyn_powertune_data.l2_lta_window_size =
2078 si_pi->powertune_data->l2_lta_window_size_default;
2079 si_pi->dyn_powertune_data.lts_truncate =
2080 si_pi->powertune_data->lts_truncate_default;
2082 ni_pi->support_cac_long_term_average = false;
2083 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2084 si_pi->dyn_powertune_data.lts_truncate = 0;
2087 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2090 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2095 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2100 u32 cac_window_size;
2102 xclk = radeon_get_xclk(rdev);
2107 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2108 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2110 wintime = (cac_window_size * 100) / xclk;
2115 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2117 return power_in_watts;
2120 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2121 bool adjust_polarity,
2124 u32 *near_tdp_limit)
2126 u32 adjustment_delta, max_tdp_limit;
2128 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2131 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2133 if (adjust_polarity) {
2134 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2135 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2137 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2138 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2139 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2140 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2142 *near_tdp_limit = 0;
2145 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2147 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2153 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2154 struct radeon_ps *radeon_state)
2156 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2157 struct si_power_info *si_pi = si_get_pi(rdev);
2159 if (ni_pi->enable_power_containment) {
2160 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2161 PP_SIslands_PAPMParameters *papm_parm;
2162 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2163 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2168 if (scaling_factor == 0)
2171 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2173 ret = si_calculate_adjusted_tdp_limits(rdev,
2175 rdev->pm.dpm.tdp_adjustment,
2181 smc_table->dpm2Params.TDPLimit =
2182 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2183 smc_table->dpm2Params.NearTDPLimit =
2184 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2185 smc_table->dpm2Params.SafePowerLimit =
2186 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2188 ret = si_copy_bytes_to_smc(rdev,
2189 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2190 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2191 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2197 if (si_pi->enable_ppm) {
2198 papm_parm = &si_pi->papm_parm;
2199 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2200 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2201 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2202 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2203 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2204 papm_parm->PlatformPowerLimit = 0xffffffff;
2205 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2207 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2209 sizeof(PP_SIslands_PAPMParameters),
2218 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2219 struct radeon_ps *radeon_state)
2221 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2222 struct si_power_info *si_pi = si_get_pi(rdev);
2224 if (ni_pi->enable_power_containment) {
2225 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2226 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2229 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2231 smc_table->dpm2Params.NearTDPLimit =
2232 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2233 smc_table->dpm2Params.SafePowerLimit =
2234 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2236 ret = si_copy_bytes_to_smc(rdev,
2237 (si_pi->state_table_start +
2238 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2239 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2240 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2250 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2251 const u16 prev_std_vddc,
2252 const u16 curr_std_vddc)
2254 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2255 u64 prev_vddc = (u64)prev_std_vddc;
2256 u64 curr_vddc = (u64)curr_std_vddc;
2257 u64 pwr_efficiency_ratio, n, d;
2259 if ((prev_vddc == 0) || (curr_vddc == 0))
2262 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2263 d = prev_vddc * prev_vddc;
2264 pwr_efficiency_ratio = div64_u64(n, d);
2266 if (pwr_efficiency_ratio > (u64)0xFFFF)
2269 return (u16)pwr_efficiency_ratio;
2272 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2273 struct radeon_ps *radeon_state)
2275 struct si_power_info *si_pi = si_get_pi(rdev);
2277 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2278 radeon_state->vclk && radeon_state->dclk)
2284 static int si_populate_power_containment_values(struct radeon_device *rdev,
2285 struct radeon_ps *radeon_state,
2286 SISLANDS_SMC_SWSTATE *smc_state)
2288 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2289 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2290 struct ni_ps *state = ni_get_ps(radeon_state);
2291 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2298 u16 pwr_efficiency_ratio;
2300 bool disable_uvd_power_tune;
2303 if (ni_pi->enable_power_containment == false)
2306 if (state->performance_level_count == 0)
2309 if (smc_state->levelCount != state->performance_level_count)
2312 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2314 smc_state->levels[0].dpm2.MaxPS = 0;
2315 smc_state->levels[0].dpm2.NearTDPDec = 0;
2316 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2317 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2318 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2320 for (i = 1; i < state->performance_level_count; i++) {
2321 prev_sclk = state->performance_levels[i-1].sclk;
2322 max_sclk = state->performance_levels[i].sclk;
2324 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2326 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2328 if (prev_sclk > max_sclk)
2331 if ((max_ps_percent == 0) ||
2332 (prev_sclk == max_sclk) ||
2333 disable_uvd_power_tune) {
2334 min_sclk = max_sclk;
2335 } else if (i == 1) {
2336 min_sclk = prev_sclk;
2338 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2341 if (min_sclk < state->performance_levels[0].sclk)
2342 min_sclk = state->performance_levels[0].sclk;
2347 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2348 state->performance_levels[i-1].vddc, &vddc);
2352 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2356 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2357 state->performance_levels[i].vddc, &vddc);
2361 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2365 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2366 prev_std_vddc, curr_std_vddc);
2368 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2369 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2370 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2371 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2372 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2378 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2379 struct radeon_ps *radeon_state,
2380 SISLANDS_SMC_SWSTATE *smc_state)
2382 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2383 struct ni_ps *state = ni_get_ps(radeon_state);
2384 u32 sq_power_throttle, sq_power_throttle2;
2385 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2388 if (state->performance_level_count == 0)
2391 if (smc_state->levelCount != state->performance_level_count)
2394 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2397 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2398 enable_sq_ramping = false;
2400 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2401 enable_sq_ramping = false;
2403 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2404 enable_sq_ramping = false;
2406 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2407 enable_sq_ramping = false;
2409 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2410 enable_sq_ramping = false;
2412 for (i = 0; i < state->performance_level_count; i++) {
2413 sq_power_throttle = 0;
2414 sq_power_throttle2 = 0;
2416 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2417 enable_sq_ramping) {
2418 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2419 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2420 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2421 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2422 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2424 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2425 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2428 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2429 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2435 static int si_enable_power_containment(struct radeon_device *rdev,
2436 struct radeon_ps *radeon_new_state,
2439 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2440 PPSMC_Result smc_result;
2443 if (ni_pi->enable_power_containment) {
2445 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2446 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2447 if (smc_result != PPSMC_Result_OK) {
2449 ni_pi->pc_enabled = false;
2451 ni_pi->pc_enabled = true;
2455 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2456 if (smc_result != PPSMC_Result_OK)
2458 ni_pi->pc_enabled = false;
2465 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2467 struct si_power_info *si_pi = si_get_pi(rdev);
2469 struct si_dte_data *dte_data = &si_pi->dte_data;
2470 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2475 if (dte_data == NULL)
2476 si_pi->enable_dte = false;
2478 if (si_pi->enable_dte == false)
2481 if (dte_data->k <= 0)
2484 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2485 if (dte_tables == NULL) {
2486 si_pi->enable_dte = false;
2490 table_size = dte_data->k;
2492 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2493 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2495 tdep_count = dte_data->tdep_count;
2496 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2497 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2499 dte_tables->K = cpu_to_be32(table_size);
2500 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2501 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2502 dte_tables->WindowSize = dte_data->window_size;
2503 dte_tables->temp_select = dte_data->temp_select;
2504 dte_tables->DTE_mode = dte_data->dte_mode;
2505 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2510 for (i = 0; i < table_size; i++) {
2511 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2512 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2515 dte_tables->Tdep_count = tdep_count;
2517 for (i = 0; i < (u32)tdep_count; i++) {
2518 dte_tables->T_limits[i] = dte_data->t_limits[i];
2519 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2520 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2523 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2524 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2530 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2533 struct si_power_info *si_pi = si_get_pi(rdev);
2534 struct radeon_cac_leakage_table *table =
2535 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2546 for (i = 0; i < table->count; i++) {
2547 if (table->entries[i].vddc > *max)
2548 *max = table->entries[i].vddc;
2549 if (table->entries[i].vddc < *min)
2550 *min = table->entries[i].vddc;
2553 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2556 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2558 if (v0_loadline > 0xFFFFUL)
2561 *min = (u16)v0_loadline;
2563 if ((*min > *max) || (*max == 0) || (*min == 0))
2569 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2571 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2572 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2575 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2576 PP_SIslands_CacConfig *cac_tables,
2577 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2580 struct si_power_info *si_pi = si_get_pi(rdev);
2588 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2590 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2591 t = (1000 * (i * t_step + t0));
2593 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2594 voltage = vddc_max - (vddc_step * j);
2596 si_calculate_leakage_for_v_and_t(rdev,
2597 &si_pi->powertune_data->leakage_coefficients,
2600 si_pi->dyn_powertune_data.cac_leakage,
2603 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2605 if (smc_leakage > 0xFFFF)
2606 smc_leakage = 0xFFFF;
2608 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2609 cpu_to_be16((u16)smc_leakage);
2615 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2616 PP_SIslands_CacConfig *cac_tables,
2617 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2619 struct si_power_info *si_pi = si_get_pi(rdev);
2626 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2628 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2629 voltage = vddc_max - (vddc_step * j);
2631 si_calculate_leakage_for_v(rdev,
2632 &si_pi->powertune_data->leakage_coefficients,
2633 si_pi->powertune_data->fixed_kt,
2635 si_pi->dyn_powertune_data.cac_leakage,
2638 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2640 if (smc_leakage > 0xFFFF)
2641 smc_leakage = 0xFFFF;
2643 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2644 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2645 cpu_to_be16((u16)smc_leakage);
2650 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2652 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2653 struct si_power_info *si_pi = si_get_pi(rdev);
2654 PP_SIslands_CacConfig *cac_tables = NULL;
2655 u16 vddc_max, vddc_min, vddc_step;
2657 u32 load_line_slope, reg;
2659 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2661 if (ni_pi->enable_cac == false)
2664 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2668 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2669 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2670 WREG32(CG_CAC_CTRL, reg);
2672 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2673 si_pi->dyn_powertune_data.dc_pwr_value =
2674 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2675 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2676 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2678 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2680 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2684 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2685 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2689 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2690 ret = si_init_dte_leakage_table(rdev, cac_tables,
2691 vddc_max, vddc_min, vddc_step,
2694 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2695 vddc_max, vddc_min, vddc_step);
2699 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2701 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2702 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2703 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2704 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2705 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2706 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2707 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2708 cac_tables->calculation_repeats = cpu_to_be32(2);
2709 cac_tables->dc_cac = cpu_to_be32(0);
2710 cac_tables->log2_PG_LKG_SCALE = 12;
2711 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2712 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2713 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2715 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2716 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2721 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2725 ni_pi->enable_cac = false;
2726 ni_pi->enable_power_containment = false;
2734 static int si_program_cac_config_registers(struct radeon_device *rdev,
2735 const struct si_cac_config_reg *cac_config_regs)
2737 const struct si_cac_config_reg *config_regs = cac_config_regs;
2738 u32 data = 0, offset;
2743 while (config_regs->offset != 0xFFFFFFFF) {
2744 switch (config_regs->type) {
2745 case SISLANDS_CACCONFIG_CGIND:
2746 offset = SMC_CG_IND_START + config_regs->offset;
2747 if (offset < SMC_CG_IND_END)
2748 data = RREG32_SMC(offset);
2751 data = RREG32(config_regs->offset << 2);
2755 data &= ~config_regs->mask;
2756 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2758 switch (config_regs->type) {
2759 case SISLANDS_CACCONFIG_CGIND:
2760 offset = SMC_CG_IND_START + config_regs->offset;
2761 if (offset < SMC_CG_IND_END)
2762 WREG32_SMC(offset, data);
2765 WREG32(config_regs->offset << 2, data);
2773 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2775 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2776 struct si_power_info *si_pi = si_get_pi(rdev);
2779 if ((ni_pi->enable_cac == false) ||
2780 (ni_pi->cac_configuration_required == false))
2783 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2786 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2789 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2796 static int si_enable_smc_cac(struct radeon_device *rdev,
2797 struct radeon_ps *radeon_new_state,
2800 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2801 struct si_power_info *si_pi = si_get_pi(rdev);
2802 PPSMC_Result smc_result;
2805 if (ni_pi->enable_cac) {
2807 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2808 if (ni_pi->support_cac_long_term_average) {
2809 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2810 if (smc_result != PPSMC_Result_OK)
2811 ni_pi->support_cac_long_term_average = false;
2814 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2815 if (smc_result != PPSMC_Result_OK) {
2817 ni_pi->cac_enabled = false;
2819 ni_pi->cac_enabled = true;
2822 if (si_pi->enable_dte) {
2823 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2824 if (smc_result != PPSMC_Result_OK)
2828 } else if (ni_pi->cac_enabled) {
2829 if (si_pi->enable_dte)
2830 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2832 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2834 ni_pi->cac_enabled = false;
2836 if (ni_pi->support_cac_long_term_average)
2837 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2843 static int si_init_smc_spll_table(struct radeon_device *rdev)
2845 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2846 struct si_power_info *si_pi = si_get_pi(rdev);
2847 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2848 SISLANDS_SMC_SCLK_VALUE sclk_params;
2856 if (si_pi->spll_table_start == 0)
2859 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2860 if (spll_table == NULL)
2863 for (i = 0; i < 256; i++) {
2864 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2868 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2869 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2870 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2871 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2873 fb_div &= ~0x00001FFF;
2877 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2879 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2881 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2883 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2889 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2890 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2891 spll_table->freq[i] = cpu_to_be32(tmp);
2893 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2894 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2895 spll_table->ss[i] = cpu_to_be32(tmp);
2902 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2903 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2907 ni_pi->enable_power_containment = false;
2914 struct si_dpm_quirk {
2923 /* cards with dpm stability problems */
2924 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2925 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2926 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2927 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2931 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2932 struct radeon_ps *rps)
2934 struct ni_ps *ps = ni_get_ps(rps);
2935 struct radeon_clock_and_voltage_limits *max_limits;
2936 bool disable_mclk_switching = false;
2937 bool disable_sclk_switching = false;
2940 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2941 u32 max_sclk = 0, max_mclk = 0;
2943 struct si_dpm_quirk *p = si_dpm_quirk_list;
2945 /* Apply dpm quirks */
2946 while (p && p->chip_device != 0) {
2947 if (rdev->pdev->vendor == p->chip_vendor &&
2948 rdev->pdev->device == p->chip_device &&
2949 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
2950 rdev->pdev->subsystem_device == p->subsys_device) {
2951 max_sclk = p->max_sclk;
2952 max_mclk = p->max_mclk;
2958 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2959 ni_dpm_vblank_too_short(rdev))
2960 disable_mclk_switching = true;
2962 if (rps->vclk || rps->dclk) {
2963 disable_mclk_switching = true;
2964 disable_sclk_switching = true;
2967 if (rdev->pm.dpm.ac_power)
2968 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2970 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2972 for (i = ps->performance_level_count - 2; i >= 0; i--) {
2973 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2974 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2976 if (rdev->pm.dpm.ac_power == false) {
2977 for (i = 0; i < ps->performance_level_count; i++) {
2978 if (ps->performance_levels[i].mclk > max_limits->mclk)
2979 ps->performance_levels[i].mclk = max_limits->mclk;
2980 if (ps->performance_levels[i].sclk > max_limits->sclk)
2981 ps->performance_levels[i].sclk = max_limits->sclk;
2982 if (ps->performance_levels[i].vddc > max_limits->vddc)
2983 ps->performance_levels[i].vddc = max_limits->vddc;
2984 if (ps->performance_levels[i].vddci > max_limits->vddci)
2985 ps->performance_levels[i].vddci = max_limits->vddci;
2989 /* limit clocks to max supported clocks based on voltage dependency tables */
2990 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2992 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2994 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2997 for (i = 0; i < ps->performance_level_count; i++) {
2998 if (max_sclk_vddc) {
2999 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3000 ps->performance_levels[i].sclk = max_sclk_vddc;
3002 if (max_mclk_vddci) {
3003 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3004 ps->performance_levels[i].mclk = max_mclk_vddci;
3006 if (max_mclk_vddc) {
3007 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3008 ps->performance_levels[i].mclk = max_mclk_vddc;
3011 if (ps->performance_levels[i].mclk > max_mclk)
3012 ps->performance_levels[i].mclk = max_mclk;
3015 if (ps->performance_levels[i].sclk > max_sclk)
3016 ps->performance_levels[i].sclk = max_sclk;
3020 /* XXX validate the min clocks required for display */
3022 if (disable_mclk_switching) {
3023 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3024 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3026 mclk = ps->performance_levels[0].mclk;
3027 vddci = ps->performance_levels[0].vddci;
3030 if (disable_sclk_switching) {
3031 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3032 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3034 sclk = ps->performance_levels[0].sclk;
3035 vddc = ps->performance_levels[0].vddc;
3038 /* adjusted low state */
3039 ps->performance_levels[0].sclk = sclk;
3040 ps->performance_levels[0].mclk = mclk;
3041 ps->performance_levels[0].vddc = vddc;
3042 ps->performance_levels[0].vddci = vddci;
3044 if (disable_sclk_switching) {
3045 sclk = ps->performance_levels[0].sclk;
3046 for (i = 1; i < ps->performance_level_count; i++) {
3047 if (sclk < ps->performance_levels[i].sclk)
3048 sclk = ps->performance_levels[i].sclk;
3050 for (i = 0; i < ps->performance_level_count; i++) {
3051 ps->performance_levels[i].sclk = sclk;
3052 ps->performance_levels[i].vddc = vddc;
3055 for (i = 1; i < ps->performance_level_count; i++) {
3056 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3057 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3058 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3059 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3063 if (disable_mclk_switching) {
3064 mclk = ps->performance_levels[0].mclk;
3065 for (i = 1; i < ps->performance_level_count; i++) {
3066 if (mclk < ps->performance_levels[i].mclk)
3067 mclk = ps->performance_levels[i].mclk;
3069 for (i = 0; i < ps->performance_level_count; i++) {
3070 ps->performance_levels[i].mclk = mclk;
3071 ps->performance_levels[i].vddci = vddci;
3074 for (i = 1; i < ps->performance_level_count; i++) {
3075 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3076 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3077 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3078 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3082 for (i = 0; i < ps->performance_level_count; i++)
3083 btc_adjust_clock_combinations(rdev, max_limits,
3084 &ps->performance_levels[i]);
3086 for (i = 0; i < ps->performance_level_count; i++) {
3087 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3088 ps->performance_levels[i].sclk,
3089 max_limits->vddc, &ps->performance_levels[i].vddc);
3090 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3091 ps->performance_levels[i].mclk,
3092 max_limits->vddci, &ps->performance_levels[i].vddci);
3093 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3094 ps->performance_levels[i].mclk,
3095 max_limits->vddc, &ps->performance_levels[i].vddc);
3096 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3097 rdev->clock.current_dispclk,
3098 max_limits->vddc, &ps->performance_levels[i].vddc);
3101 for (i = 0; i < ps->performance_level_count; i++) {
3102 btc_apply_voltage_delta_rules(rdev,
3103 max_limits->vddc, max_limits->vddci,
3104 &ps->performance_levels[i].vddc,
3105 &ps->performance_levels[i].vddci);
3108 ps->dc_compatible = true;
3109 for (i = 0; i < ps->performance_level_count; i++) {
3110 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3111 ps->dc_compatible = false;
3117 static int si_read_smc_soft_register(struct radeon_device *rdev,
3118 u16 reg_offset, u32 *value)
3120 struct si_power_info *si_pi = si_get_pi(rdev);
3122 return si_read_smc_sram_dword(rdev,
3123 si_pi->soft_regs_start + reg_offset, value,
3128 static int si_write_smc_soft_register(struct radeon_device *rdev,
3129 u16 reg_offset, u32 value)
3131 struct si_power_info *si_pi = si_get_pi(rdev);
3133 return si_write_smc_sram_dword(rdev,
3134 si_pi->soft_regs_start + reg_offset,
3135 value, si_pi->sram_end);
3138 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3141 u32 tmp, width, row, column, bank, density;
3142 bool is_memory_gddr5, is_special;
3144 tmp = RREG32(MC_SEQ_MISC0);
3145 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3146 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3147 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3149 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3150 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3152 tmp = RREG32(MC_ARB_RAMCFG);
3153 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3154 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3155 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3157 density = (1 << (row + column - 20 + bank)) * width;
3159 if ((rdev->pdev->device == 0x6819) &&
3160 is_memory_gddr5 && is_special && (density == 0x400))
3166 static void si_get_leakage_vddc(struct radeon_device *rdev)
3168 struct si_power_info *si_pi = si_get_pi(rdev);
3169 u16 vddc, count = 0;
3172 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3173 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3175 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3176 si_pi->leakage_voltage.entries[count].voltage = vddc;
3177 si_pi->leakage_voltage.entries[count].leakage_index =
3178 SISLANDS_LEAKAGE_INDEX0 + i;
3182 si_pi->leakage_voltage.count = count;
3185 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3186 u32 index, u16 *leakage_voltage)
3188 struct si_power_info *si_pi = si_get_pi(rdev);
3191 if (leakage_voltage == NULL)
3194 if ((index & 0xff00) != 0xff00)
3197 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3200 if (index < SISLANDS_LEAKAGE_INDEX0)
3203 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3204 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3205 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3212 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3214 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3215 bool want_thermal_protection;
3216 enum radeon_dpm_event_src dpm_event_src;
3221 want_thermal_protection = false;
3223 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3224 want_thermal_protection = true;
3225 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3227 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3228 want_thermal_protection = true;
3229 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3231 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3232 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3233 want_thermal_protection = true;
3234 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3238 if (want_thermal_protection) {
3239 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3240 if (pi->thermal_protection)
3241 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3243 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3247 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3248 enum radeon_dpm_auto_throttle_src source,
3251 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3254 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3255 pi->active_auto_throttle_sources |= 1 << source;
3256 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3259 if (pi->active_auto_throttle_sources & (1 << source)) {
3260 pi->active_auto_throttle_sources &= ~(1 << source);
3261 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3266 static void si_start_dpm(struct radeon_device *rdev)
3268 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3271 static void si_stop_dpm(struct radeon_device *rdev)
3273 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3276 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3279 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3281 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3286 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3291 if (thermal_level == 0) {
3292 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3293 if (ret == PPSMC_Result_OK)
3301 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3303 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3308 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3311 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3318 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3319 PPSMC_Msg msg, u32 parameter)
3321 WREG32(SMC_SCRATCH0, parameter);
3322 return si_send_msg_to_smc(rdev, msg);
3325 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3327 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3330 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3334 int si_dpm_force_performance_level(struct radeon_device *rdev,
3335 enum radeon_dpm_forced_level level)
3337 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3338 struct ni_ps *ps = ni_get_ps(rps);
3339 u32 levels = ps->performance_level_count;
3341 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3342 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3345 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3347 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3348 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3351 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3353 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3354 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3357 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3361 rdev->pm.dpm.forced_level = level;
3367 static int si_set_boot_state(struct radeon_device *rdev)
3369 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3374 static int si_set_sw_state(struct radeon_device *rdev)
3376 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3380 static int si_halt_smc(struct radeon_device *rdev)
3382 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3385 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3389 static int si_resume_smc(struct radeon_device *rdev)
3391 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3394 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3398 static void si_dpm_start_smc(struct radeon_device *rdev)
3400 si_program_jump_on_start(rdev);
3402 si_start_smc_clock(rdev);
3405 static void si_dpm_stop_smc(struct radeon_device *rdev)
3408 si_stop_smc_clock(rdev);
3411 static int si_process_firmware_header(struct radeon_device *rdev)
3413 struct si_power_info *si_pi = si_get_pi(rdev);
3417 ret = si_read_smc_sram_dword(rdev,
3418 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3419 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3420 &tmp, si_pi->sram_end);
3424 si_pi->state_table_start = tmp;
3426 ret = si_read_smc_sram_dword(rdev,
3427 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3428 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3429 &tmp, si_pi->sram_end);
3433 si_pi->soft_regs_start = tmp;
3435 ret = si_read_smc_sram_dword(rdev,
3436 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3437 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3438 &tmp, si_pi->sram_end);
3442 si_pi->mc_reg_table_start = tmp;
3444 ret = si_read_smc_sram_dword(rdev,
3445 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3446 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3447 &tmp, si_pi->sram_end);
3451 si_pi->fan_table_start = tmp;
3453 ret = si_read_smc_sram_dword(rdev,
3454 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3455 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3456 &tmp, si_pi->sram_end);
3460 si_pi->arb_table_start = tmp;
3462 ret = si_read_smc_sram_dword(rdev,
3463 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3464 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3465 &tmp, si_pi->sram_end);
3469 si_pi->cac_table_start = tmp;
3471 ret = si_read_smc_sram_dword(rdev,
3472 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3473 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3474 &tmp, si_pi->sram_end);
3478 si_pi->dte_table_start = tmp;
3480 ret = si_read_smc_sram_dword(rdev,
3481 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3482 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3483 &tmp, si_pi->sram_end);
3487 si_pi->spll_table_start = tmp;
3489 ret = si_read_smc_sram_dword(rdev,
3490 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3491 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3492 &tmp, si_pi->sram_end);
3496 si_pi->papm_cfg_table_start = tmp;
3501 static void si_read_clock_registers(struct radeon_device *rdev)
3503 struct si_power_info *si_pi = si_get_pi(rdev);
3505 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3506 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3507 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3508 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3509 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3510 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3511 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3512 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3513 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3514 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3515 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3516 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3517 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3518 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3519 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3522 static void si_enable_thermal_protection(struct radeon_device *rdev,
3526 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3528 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3531 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3533 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3537 static int si_enter_ulp_state(struct radeon_device *rdev)
3539 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3546 static int si_exit_ulp_state(struct radeon_device *rdev)
3550 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3554 for (i = 0; i < rdev->usec_timeout; i++) {
3555 if (RREG32(SMC_RESP_0) == 1)
3564 static int si_notify_smc_display_change(struct radeon_device *rdev,
3567 PPSMC_Msg msg = has_display ?
3568 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3570 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3574 static void si_program_response_times(struct radeon_device *rdev)
3576 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3577 u32 vddc_dly, acpi_dly, vbi_dly;
3578 u32 reference_clock;
3580 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3582 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3583 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3585 if (voltage_response_time == 0)
3586 voltage_response_time = 1000;
3588 acpi_delay_time = 15000;
3589 vbi_time_out = 100000;
3591 reference_clock = radeon_get_xclk(rdev);
3593 vddc_dly = (voltage_response_time * reference_clock) / 100;
3594 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3595 vbi_dly = (vbi_time_out * reference_clock) / 100;
3597 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3598 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3599 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3600 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3603 static void si_program_ds_registers(struct radeon_device *rdev)
3605 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3606 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3608 if (eg_pi->sclk_deep_sleep) {
3609 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3610 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3611 ~AUTOSCALE_ON_SS_CLEAR);
3615 static void si_program_display_gap(struct radeon_device *rdev)
3620 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3621 if (rdev->pm.dpm.new_active_crtc_count > 0)
3622 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3624 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3626 if (rdev->pm.dpm.new_active_crtc_count > 1)
3627 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3629 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3631 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3633 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3634 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3636 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3637 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3638 /* find the first active crtc */
3639 for (i = 0; i < rdev->num_crtc; i++) {
3640 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3643 if (i == rdev->num_crtc)
3648 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3649 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3650 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3653 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3654 * This can be a problem on PowerXpress systems or if you want to use the card
3655 * for offscreen rendering or compute if there are no crtcs enabled.
3657 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3660 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3662 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3666 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3668 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3669 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3673 static void si_setup_bsp(struct radeon_device *rdev)
3675 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3676 u32 xclk = radeon_get_xclk(rdev);
3678 r600_calculate_u_and_p(pi->asi,
3684 r600_calculate_u_and_p(pi->pasi,
3691 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3692 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3694 WREG32(CG_BSP, pi->dsp);
3697 static void si_program_git(struct radeon_device *rdev)
3699 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3702 static void si_program_tp(struct radeon_device *rdev)
3705 enum r600_td td = R600_TD_DFLT;
3707 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3708 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3710 if (td == R600_TD_AUTO)
3711 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3713 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3715 if (td == R600_TD_UP)
3716 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3718 if (td == R600_TD_DOWN)
3719 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3722 static void si_program_tpp(struct radeon_device *rdev)
3724 WREG32(CG_TPC, R600_TPC_DFLT);
3727 static void si_program_sstp(struct radeon_device *rdev)
3729 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3732 static void si_enable_display_gap(struct radeon_device *rdev)
3734 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3736 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3737 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3738 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3740 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3741 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3742 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3743 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3746 static void si_program_vc(struct radeon_device *rdev)
3748 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3750 WREG32(CG_FTV, pi->vrc);
3753 static void si_clear_vc(struct radeon_device *rdev)
3758 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3762 if (memory_clock < 10000)
3764 else if (memory_clock >= 80000)
3765 mc_para_index = 0x0f;
3767 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3768 return mc_para_index;
3771 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3776 if (memory_clock < 12500)
3777 mc_para_index = 0x00;
3778 else if (memory_clock > 47500)
3779 mc_para_index = 0x0f;
3781 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3783 if (memory_clock < 65000)
3784 mc_para_index = 0x00;
3785 else if (memory_clock > 135000)
3786 mc_para_index = 0x0f;
3788 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3790 return mc_para_index;
3793 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3795 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3796 bool strobe_mode = false;
3799 if (mclk <= pi->mclk_strobe_mode_threshold)
3803 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3805 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3808 result |= SISLANDS_SMC_STROBE_ENABLE;
3813 static int si_upload_firmware(struct radeon_device *rdev)
3815 struct si_power_info *si_pi = si_get_pi(rdev);
3819 si_stop_smc_clock(rdev);
3821 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3826 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3827 const struct atom_voltage_table *table,
3828 const struct radeon_phase_shedding_limits_table *limits)
3830 u32 data, num_bits, num_levels;
3832 if ((table == NULL) || (limits == NULL))
3835 data = table->mask_low;
3837 num_bits = hweight32(data);
3842 num_levels = (1 << num_bits);
3844 if (table->count != num_levels)
3847 if (limits->count != (num_levels - 1))
3853 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3854 u32 max_voltage_steps,
3855 struct atom_voltage_table *voltage_table)
3857 unsigned int i, diff;
3859 if (voltage_table->count <= max_voltage_steps)
3862 diff = voltage_table->count - max_voltage_steps;
3864 for (i= 0; i < max_voltage_steps; i++)
3865 voltage_table->entries[i] = voltage_table->entries[i + diff];
3867 voltage_table->count = max_voltage_steps;
3870 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3871 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3872 struct atom_voltage_table *voltage_table)
3876 if (voltage_dependency_table == NULL)
3879 voltage_table->mask_low = 0;
3880 voltage_table->phase_delay = 0;
3882 voltage_table->count = voltage_dependency_table->count;
3883 for (i = 0; i < voltage_table->count; i++) {
3884 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3885 voltage_table->entries[i].smio_low = 0;
3891 static int si_construct_voltage_tables(struct radeon_device *rdev)
3893 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3894 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3895 struct si_power_info *si_pi = si_get_pi(rdev);
3898 if (pi->voltage_control) {
3899 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3900 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3904 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3905 si_trim_voltage_table_to_fit_state_table(rdev,
3906 SISLANDS_MAX_NO_VREG_STEPS,
3907 &eg_pi->vddc_voltage_table);
3908 } else if (si_pi->voltage_control_svi2) {
3909 ret = si_get_svi2_voltage_table(rdev,
3910 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3911 &eg_pi->vddc_voltage_table);
3918 if (eg_pi->vddci_control) {
3919 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3920 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3924 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3925 si_trim_voltage_table_to_fit_state_table(rdev,
3926 SISLANDS_MAX_NO_VREG_STEPS,
3927 &eg_pi->vddci_voltage_table);
3929 if (si_pi->vddci_control_svi2) {
3930 ret = si_get_svi2_voltage_table(rdev,
3931 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3932 &eg_pi->vddci_voltage_table);
3937 if (pi->mvdd_control) {
3938 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3939 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3942 pi->mvdd_control = false;
3946 if (si_pi->mvdd_voltage_table.count == 0) {
3947 pi->mvdd_control = false;
3951 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3952 si_trim_voltage_table_to_fit_state_table(rdev,
3953 SISLANDS_MAX_NO_VREG_STEPS,
3954 &si_pi->mvdd_voltage_table);
3957 if (si_pi->vddc_phase_shed_control) {
3958 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3959 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3961 si_pi->vddc_phase_shed_control = false;
3963 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3964 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3965 si_pi->vddc_phase_shed_control = false;
3971 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3972 const struct atom_voltage_table *voltage_table,
3973 SISLANDS_SMC_STATETABLE *table)
3977 for (i = 0; i < voltage_table->count; i++)
3978 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3981 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3982 SISLANDS_SMC_STATETABLE *table)
3984 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3985 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3986 struct si_power_info *si_pi = si_get_pi(rdev);
3989 if (si_pi->voltage_control_svi2) {
3990 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
3991 si_pi->svc_gpio_id);
3992 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
3993 si_pi->svd_gpio_id);
3994 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
3997 if (eg_pi->vddc_voltage_table.count) {
3998 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3999 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4000 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4002 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4003 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4004 table->maxVDDCIndexInPPTable = i;
4010 if (eg_pi->vddci_voltage_table.count) {
4011 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4013 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4014 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4018 if (si_pi->mvdd_voltage_table.count) {
4019 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4021 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4022 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4025 if (si_pi->vddc_phase_shed_control) {
4026 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4027 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4028 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4030 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4031 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4033 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4034 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4036 si_pi->vddc_phase_shed_control = false;
4044 static int si_populate_voltage_value(struct radeon_device *rdev,
4045 const struct atom_voltage_table *table,
4046 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4050 for (i = 0; i < table->count; i++) {
4051 if (value <= table->entries[i].value) {
4052 voltage->index = (u8)i;
4053 voltage->value = cpu_to_be16(table->entries[i].value);
4058 if (i >= table->count)
4064 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4065 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4067 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4068 struct si_power_info *si_pi = si_get_pi(rdev);
4070 if (pi->mvdd_control) {
4071 if (mclk <= pi->mvdd_split_frequency)
4074 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4076 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4081 static int si_get_std_voltage_value(struct radeon_device *rdev,
4082 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4086 bool voltage_found = false;
4087 *std_voltage = be16_to_cpu(voltage->value);
4089 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4090 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4091 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4094 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4095 if (be16_to_cpu(voltage->value) ==
4096 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4097 voltage_found = true;
4098 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4100 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4103 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4108 if (!voltage_found) {
4109 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4110 if (be16_to_cpu(voltage->value) <=
4111 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4112 voltage_found = true;
4113 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4115 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4118 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4124 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4125 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4132 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4133 u16 value, u8 index,
4134 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4136 voltage->index = index;
4137 voltage->value = cpu_to_be16(value);
4142 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4143 const struct radeon_phase_shedding_limits_table *limits,
4144 u16 voltage, u32 sclk, u32 mclk,
4145 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4149 for (i = 0; i < limits->count; i++) {
4150 if ((voltage <= limits->entries[i].voltage) &&
4151 (sclk <= limits->entries[i].sclk) &&
4152 (mclk <= limits->entries[i].mclk))
4156 smc_voltage->phase_settings = (u8)i;
4161 static int si_init_arb_table_index(struct radeon_device *rdev)
4163 struct si_power_info *si_pi = si_get_pi(rdev);
4167 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4172 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4174 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4177 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4179 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4182 static int si_reset_to_default(struct radeon_device *rdev)
4184 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4188 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4190 struct si_power_info *si_pi = si_get_pi(rdev);
4194 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4195 &tmp, si_pi->sram_end);
4199 tmp = (tmp >> 24) & 0xff;
4201 if (tmp == MC_CG_ARB_FREQ_F0)
4204 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4207 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4211 u32 dram_refresh_rate;
4212 u32 mc_arb_rfsh_rate;
4213 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4218 dram_rows = 1 << (tmp + 10);
4220 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4221 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4223 return mc_arb_rfsh_rate;
4226 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4227 struct rv7xx_pl *pl,
4228 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4234 arb_regs->mc_arb_rfsh_rate =
4235 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4237 radeon_atom_set_engine_dram_timings(rdev,
4241 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4242 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4243 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4245 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4246 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4247 arb_regs->mc_arb_burst_time = (u8)burst_time;
4252 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4253 struct radeon_ps *radeon_state,
4254 unsigned int first_arb_set)
4256 struct si_power_info *si_pi = si_get_pi(rdev);
4257 struct ni_ps *state = ni_get_ps(radeon_state);
4258 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4261 for (i = 0; i < state->performance_level_count; i++) {
4262 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4265 ret = si_copy_bytes_to_smc(rdev,
4266 si_pi->arb_table_start +
4267 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4268 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4270 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4279 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4280 struct radeon_ps *radeon_new_state)
4282 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4283 SISLANDS_DRIVER_STATE_ARB_INDEX);
4286 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4287 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4289 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4290 struct si_power_info *si_pi = si_get_pi(rdev);
4292 if (pi->mvdd_control)
4293 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4294 si_pi->mvdd_bootup_value, voltage);
4299 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4300 struct radeon_ps *radeon_initial_state,
4301 SISLANDS_SMC_STATETABLE *table)
4303 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4304 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4305 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4306 struct si_power_info *si_pi = si_get_pi(rdev);
4310 table->initialState.levels[0].mclk.vDLL_CNTL =
4311 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4312 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4313 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4314 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4315 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4316 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4317 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4318 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4319 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4320 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4321 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4322 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4323 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4324 table->initialState.levels[0].mclk.vMPLL_SS =
4325 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4326 table->initialState.levels[0].mclk.vMPLL_SS2 =
4327 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4329 table->initialState.levels[0].mclk.mclk_value =
4330 cpu_to_be32(initial_state->performance_levels[0].mclk);
4332 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4333 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4334 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4335 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4336 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4337 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4338 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4339 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4340 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4341 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4342 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4343 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4345 table->initialState.levels[0].sclk.sclk_value =
4346 cpu_to_be32(initial_state->performance_levels[0].sclk);
4348 table->initialState.levels[0].arbRefreshState =
4349 SISLANDS_INITIAL_STATE_ARB_INDEX;
4351 table->initialState.levels[0].ACIndex = 0;
4353 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4354 initial_state->performance_levels[0].vddc,
4355 &table->initialState.levels[0].vddc);
4360 ret = si_get_std_voltage_value(rdev,
4361 &table->initialState.levels[0].vddc,
4364 si_populate_std_voltage_value(rdev, std_vddc,
4365 table->initialState.levels[0].vddc.index,
4366 &table->initialState.levels[0].std_vddc);
4369 if (eg_pi->vddci_control)
4370 si_populate_voltage_value(rdev,
4371 &eg_pi->vddci_voltage_table,
4372 initial_state->performance_levels[0].vddci,
4373 &table->initialState.levels[0].vddci);
4375 if (si_pi->vddc_phase_shed_control)
4376 si_populate_phase_shedding_value(rdev,
4377 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4378 initial_state->performance_levels[0].vddc,
4379 initial_state->performance_levels[0].sclk,
4380 initial_state->performance_levels[0].mclk,
4381 &table->initialState.levels[0].vddc);
4383 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4385 reg = CG_R(0xffff) | CG_L(0);
4386 table->initialState.levels[0].aT = cpu_to_be32(reg);
4388 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4390 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4392 if (pi->mem_gddr5) {
4393 table->initialState.levels[0].strobeMode =
4394 si_get_strobe_mode_settings(rdev,
4395 initial_state->performance_levels[0].mclk);
4397 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4398 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4400 table->initialState.levels[0].mcFlags = 0;
4403 table->initialState.levelCount = 1;
4405 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4407 table->initialState.levels[0].dpm2.MaxPS = 0;
4408 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4409 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4410 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4411 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4413 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4414 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4416 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4417 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4422 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4423 SISLANDS_SMC_STATETABLE *table)
4425 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4426 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4427 struct si_power_info *si_pi = si_get_pi(rdev);
4428 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4429 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4430 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4431 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4432 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4433 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4434 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4435 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4436 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4437 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4438 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4442 table->ACPIState = table->initialState;
4444 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4446 if (pi->acpi_vddc) {
4447 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4448 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4452 ret = si_get_std_voltage_value(rdev,
4453 &table->ACPIState.levels[0].vddc, &std_vddc);
4455 si_populate_std_voltage_value(rdev, std_vddc,
4456 table->ACPIState.levels[0].vddc.index,
4457 &table->ACPIState.levels[0].std_vddc);
4459 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4461 if (si_pi->vddc_phase_shed_control) {
4462 si_populate_phase_shedding_value(rdev,
4463 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4467 &table->ACPIState.levels[0].vddc);
4470 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4471 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4475 ret = si_get_std_voltage_value(rdev,
4476 &table->ACPIState.levels[0].vddc, &std_vddc);
4479 si_populate_std_voltage_value(rdev, std_vddc,
4480 table->ACPIState.levels[0].vddc.index,
4481 &table->ACPIState.levels[0].std_vddc);
4483 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4484 si_pi->sys_pcie_mask,
4485 si_pi->boot_pcie_gen,
4488 if (si_pi->vddc_phase_shed_control)
4489 si_populate_phase_shedding_value(rdev,
4490 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4491 pi->min_vddc_in_table,
4494 &table->ACPIState.levels[0].vddc);
4497 if (pi->acpi_vddc) {
4498 if (eg_pi->acpi_vddci)
4499 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4501 &table->ACPIState.levels[0].vddci);
4504 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4505 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4507 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4509 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4510 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4512 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4513 cpu_to_be32(dll_cntl);
4514 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4515 cpu_to_be32(mclk_pwrmgt_cntl);
4516 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4517 cpu_to_be32(mpll_ad_func_cntl);
4518 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4519 cpu_to_be32(mpll_dq_func_cntl);
4520 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4521 cpu_to_be32(mpll_func_cntl);
4522 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4523 cpu_to_be32(mpll_func_cntl_1);
4524 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4525 cpu_to_be32(mpll_func_cntl_2);
4526 table->ACPIState.levels[0].mclk.vMPLL_SS =
4527 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4528 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4529 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4531 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4532 cpu_to_be32(spll_func_cntl);
4533 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4534 cpu_to_be32(spll_func_cntl_2);
4535 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4536 cpu_to_be32(spll_func_cntl_3);
4537 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4538 cpu_to_be32(spll_func_cntl_4);
4540 table->ACPIState.levels[0].mclk.mclk_value = 0;
4541 table->ACPIState.levels[0].sclk.sclk_value = 0;
4543 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4545 if (eg_pi->dynamic_ac_timing)
4546 table->ACPIState.levels[0].ACIndex = 0;
4548 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4549 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4550 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4551 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4552 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4554 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4555 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4557 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4558 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4563 static int si_populate_ulv_state(struct radeon_device *rdev,
4564 SISLANDS_SMC_SWSTATE *state)
4566 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4567 struct si_power_info *si_pi = si_get_pi(rdev);
4568 struct si_ulv_param *ulv = &si_pi->ulv;
4569 u32 sclk_in_sr = 1350; /* ??? */
4572 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4575 if (eg_pi->sclk_deep_sleep) {
4576 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4577 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4579 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4581 if (ulv->one_pcie_lane_in_ulv)
4582 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4583 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4584 state->levels[0].ACIndex = 1;
4585 state->levels[0].std_vddc = state->levels[0].vddc;
4586 state->levelCount = 1;
4588 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4594 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4596 struct si_power_info *si_pi = si_get_pi(rdev);
4597 struct si_ulv_param *ulv = &si_pi->ulv;
4598 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4601 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4606 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4607 ulv->volt_change_delay);
4609 ret = si_copy_bytes_to_smc(rdev,
4610 si_pi->arb_table_start +
4611 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4612 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4614 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4620 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4622 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4624 pi->mvdd_split_frequency = 30000;
4627 static int si_init_smc_table(struct radeon_device *rdev)
4629 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4630 struct si_power_info *si_pi = si_get_pi(rdev);
4631 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4632 const struct si_ulv_param *ulv = &si_pi->ulv;
4633 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4638 si_populate_smc_voltage_tables(rdev, table);
4640 switch (rdev->pm.int_thermal_type) {
4641 case THERMAL_TYPE_SI:
4642 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4643 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4645 case THERMAL_TYPE_NONE:
4646 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4649 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4653 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4654 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4656 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4657 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4658 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4661 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4662 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4665 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4667 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4668 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4670 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4671 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4672 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4673 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4677 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4681 ret = si_populate_smc_acpi_state(rdev, table);
4685 table->driverState = table->initialState;
4687 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4688 SISLANDS_INITIAL_STATE_ARB_INDEX);
4692 if (ulv->supported && ulv->pl.vddc) {
4693 ret = si_populate_ulv_state(rdev, &table->ULVState);
4697 ret = si_program_ulv_memory_timing_parameters(rdev);
4701 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4702 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4704 lane_width = radeon_get_pcie_lanes(rdev);
4705 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4707 table->ULVState = table->initialState;
4710 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4711 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4715 static int si_calculate_sclk_params(struct radeon_device *rdev,
4717 SISLANDS_SMC_SCLK_VALUE *sclk)
4719 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4720 struct si_power_info *si_pi = si_get_pi(rdev);
4721 struct atom_clock_dividers dividers;
4722 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4723 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4724 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4725 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4726 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4727 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4729 u32 reference_clock = rdev->clock.spll.reference_freq;
4730 u32 reference_divider;
4734 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4735 engine_clock, false, ÷rs);
4739 reference_divider = 1 + dividers.ref_div;
4741 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4742 do_div(tmp, reference_clock);
4745 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4746 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4747 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4749 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4750 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4752 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4753 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4754 spll_func_cntl_3 |= SPLL_DITHEN;
4757 struct radeon_atom_ss ss;
4758 u32 vco_freq = engine_clock * dividers.post_div;
4760 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4761 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4762 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4763 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4765 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4766 cg_spll_spread_spectrum |= CLK_S(clk_s);
4767 cg_spll_spread_spectrum |= SSEN;
4769 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4770 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4774 sclk->sclk_value = engine_clock;
4775 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4776 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4777 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4778 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4779 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4780 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4785 static int si_populate_sclk_value(struct radeon_device *rdev,
4787 SISLANDS_SMC_SCLK_VALUE *sclk)
4789 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4792 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4794 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4795 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4796 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4797 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4798 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4799 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4800 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4806 static int si_populate_mclk_value(struct radeon_device *rdev,
4809 SISLANDS_SMC_MCLK_VALUE *mclk,
4813 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4814 struct si_power_info *si_pi = si_get_pi(rdev);
4815 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4816 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4817 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4818 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4819 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4820 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4821 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4822 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4823 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4824 struct atom_mpll_param mpll_param;
4827 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4831 mpll_func_cntl &= ~BWCTRL_MASK;
4832 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4834 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4835 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4836 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4838 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4839 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4841 if (pi->mem_gddr5) {
4842 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4843 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4844 YCLK_POST_DIV(mpll_param.post_div);
4848 struct radeon_atom_ss ss;
4851 u32 reference_clock = rdev->clock.mpll.reference_freq;
4854 freq_nom = memory_clock * 4;
4856 freq_nom = memory_clock * 2;
4858 tmp = freq_nom / reference_clock;
4860 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4861 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4862 u32 clks = reference_clock * 5 / ss.rate;
4863 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4865 mpll_ss1 &= ~CLKV_MASK;
4866 mpll_ss1 |= CLKV(clkv);
4868 mpll_ss2 &= ~CLKS_MASK;
4869 mpll_ss2 |= CLKS(clks);
4873 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4874 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4877 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4879 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4881 mclk->mclk_value = cpu_to_be32(memory_clock);
4882 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4883 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4884 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4885 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4886 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4887 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4888 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4889 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4890 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4895 static void si_populate_smc_sp(struct radeon_device *rdev,
4896 struct radeon_ps *radeon_state,
4897 SISLANDS_SMC_SWSTATE *smc_state)
4899 struct ni_ps *ps = ni_get_ps(radeon_state);
4900 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4903 for (i = 0; i < ps->performance_level_count - 1; i++)
4904 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4906 smc_state->levels[ps->performance_level_count - 1].bSP =
4907 cpu_to_be32(pi->psp);
4910 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4911 struct rv7xx_pl *pl,
4912 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4914 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4915 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4916 struct si_power_info *si_pi = si_get_pi(rdev);
4920 bool gmc_pg = false;
4922 if (eg_pi->pcie_performance_request &&
4923 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4924 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4926 level->gen2PCIE = (u8)pl->pcie_gen;
4928 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4934 if (pi->mclk_stutter_mode_threshold &&
4935 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4936 !eg_pi->uvd_enabled &&
4937 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4938 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4939 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4942 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4945 if (pi->mem_gddr5) {
4946 if (pl->mclk > pi->mclk_edc_enable_threshold)
4947 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4949 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4950 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4952 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4954 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4955 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4956 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4957 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4959 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4961 dll_state_on = false;
4964 level->strobeMode = si_get_strobe_mode_settings(rdev,
4967 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4970 ret = si_populate_mclk_value(rdev,
4974 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4978 ret = si_populate_voltage_value(rdev,
4979 &eg_pi->vddc_voltage_table,
4980 pl->vddc, &level->vddc);
4985 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4989 ret = si_populate_std_voltage_value(rdev, std_vddc,
4990 level->vddc.index, &level->std_vddc);
4994 if (eg_pi->vddci_control) {
4995 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4996 pl->vddci, &level->vddci);
5001 if (si_pi->vddc_phase_shed_control) {
5002 ret = si_populate_phase_shedding_value(rdev,
5003 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5012 level->MaxPoweredUpCU = si_pi->max_cu;
5014 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5019 static int si_populate_smc_t(struct radeon_device *rdev,
5020 struct radeon_ps *radeon_state,
5021 SISLANDS_SMC_SWSTATE *smc_state)
5023 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5024 struct ni_ps *state = ni_get_ps(radeon_state);
5030 if (state->performance_level_count >= 9)
5033 if (state->performance_level_count < 2) {
5034 a_t = CG_R(0xffff) | CG_L(0);
5035 smc_state->levels[0].aT = cpu_to_be32(a_t);
5039 smc_state->levels[0].aT = cpu_to_be32(0);
5041 for (i = 0; i <= state->performance_level_count - 2; i++) {
5042 ret = r600_calculate_at(
5043 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5045 state->performance_levels[i + 1].sclk,
5046 state->performance_levels[i].sclk,
5051 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5052 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5055 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5056 a_t |= CG_R(t_l * pi->bsp / 20000);
5057 smc_state->levels[i].aT = cpu_to_be32(a_t);
5059 high_bsp = (i == state->performance_level_count - 2) ?
5061 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5062 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5068 static int si_disable_ulv(struct radeon_device *rdev)
5070 struct si_power_info *si_pi = si_get_pi(rdev);
5071 struct si_ulv_param *ulv = &si_pi->ulv;
5074 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5080 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5081 struct radeon_ps *radeon_state)
5083 const struct si_power_info *si_pi = si_get_pi(rdev);
5084 const struct si_ulv_param *ulv = &si_pi->ulv;
5085 const struct ni_ps *state = ni_get_ps(radeon_state);
5088 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5091 /* XXX validate against display requirements! */
5093 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5094 if (rdev->clock.current_dispclk <=
5095 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5097 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5102 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5108 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5109 struct radeon_ps *radeon_new_state)
5111 const struct si_power_info *si_pi = si_get_pi(rdev);
5112 const struct si_ulv_param *ulv = &si_pi->ulv;
5114 if (ulv->supported) {
5115 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5116 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5122 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5123 struct radeon_ps *radeon_state,
5124 SISLANDS_SMC_SWSTATE *smc_state)
5126 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5127 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5128 struct si_power_info *si_pi = si_get_pi(rdev);
5129 struct ni_ps *state = ni_get_ps(radeon_state);
5132 u32 sclk_in_sr = 1350; /* ??? */
5134 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5137 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5139 if (radeon_state->vclk && radeon_state->dclk) {
5140 eg_pi->uvd_enabled = true;
5141 if (eg_pi->smu_uvd_hs)
5142 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5144 eg_pi->uvd_enabled = false;
5147 if (state->dc_compatible)
5148 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5150 smc_state->levelCount = 0;
5151 for (i = 0; i < state->performance_level_count; i++) {
5152 if (eg_pi->sclk_deep_sleep) {
5153 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5154 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5155 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5157 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5161 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5162 &smc_state->levels[i]);
5163 smc_state->levels[i].arbRefreshState =
5164 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5169 if (ni_pi->enable_power_containment)
5170 smc_state->levels[i].displayWatermark =
5171 (state->performance_levels[i].sclk < threshold) ?
5172 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5174 smc_state->levels[i].displayWatermark = (i < 2) ?
5175 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5177 if (eg_pi->dynamic_ac_timing)
5178 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5180 smc_state->levels[i].ACIndex = 0;
5182 smc_state->levelCount++;
5185 si_write_smc_soft_register(rdev,
5186 SI_SMC_SOFT_REGISTER_watermark_threshold,
5189 si_populate_smc_sp(rdev, radeon_state, smc_state);
5191 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5193 ni_pi->enable_power_containment = false;
5195 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5197 ni_pi->enable_sq_ramping = false;
5199 return si_populate_smc_t(rdev, radeon_state, smc_state);
5202 static int si_upload_sw_state(struct radeon_device *rdev,
5203 struct radeon_ps *radeon_new_state)
5205 struct si_power_info *si_pi = si_get_pi(rdev);
5206 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5208 u32 address = si_pi->state_table_start +
5209 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5210 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5211 ((new_state->performance_level_count - 1) *
5212 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5213 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5215 memset(smc_state, 0, state_size);
5217 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5221 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5222 state_size, si_pi->sram_end);
5227 static int si_upload_ulv_state(struct radeon_device *rdev)
5229 struct si_power_info *si_pi = si_get_pi(rdev);
5230 struct si_ulv_param *ulv = &si_pi->ulv;
5233 if (ulv->supported && ulv->pl.vddc) {
5234 u32 address = si_pi->state_table_start +
5235 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5236 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5237 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5239 memset(smc_state, 0, state_size);
5241 ret = si_populate_ulv_state(rdev, smc_state);
5243 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5244 state_size, si_pi->sram_end);
5250 static int si_upload_smc_data(struct radeon_device *rdev)
5252 struct radeon_crtc *radeon_crtc = NULL;
5255 if (rdev->pm.dpm.new_active_crtc_count == 0)
5258 for (i = 0; i < rdev->num_crtc; i++) {
5259 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5260 radeon_crtc = rdev->mode_info.crtcs[i];
5265 if (radeon_crtc == NULL)
5268 if (radeon_crtc->line_time <= 0)
5271 if (si_write_smc_soft_register(rdev,
5272 SI_SMC_SOFT_REGISTER_crtc_index,
5273 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5276 if (si_write_smc_soft_register(rdev,
5277 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5278 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5281 if (si_write_smc_soft_register(rdev,
5282 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5283 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5289 static int si_set_mc_special_registers(struct radeon_device *rdev,
5290 struct si_mc_reg_table *table)
5292 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5296 for (i = 0, j = table->last; i < table->last; i++) {
5297 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5299 switch (table->mc_reg_address[i].s1 << 2) {
5301 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5302 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5303 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5304 for (k = 0; k < table->num_entries; k++)
5305 table->mc_reg_table_entry[k].mc_data[j] =
5306 ((temp_reg & 0xffff0000)) |
5307 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5309 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5312 temp_reg = RREG32(MC_PMG_CMD_MRS);
5313 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5314 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5315 for (k = 0; k < table->num_entries; k++) {
5316 table->mc_reg_table_entry[k].mc_data[j] =
5317 (temp_reg & 0xffff0000) |
5318 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5320 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5323 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5326 if (!pi->mem_gddr5) {
5327 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5328 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5329 for (k = 0; k < table->num_entries; k++)
5330 table->mc_reg_table_entry[k].mc_data[j] =
5331 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5333 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5337 case MC_SEQ_RESERVE_M:
5338 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5339 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5340 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5341 for(k = 0; k < table->num_entries; k++)
5342 table->mc_reg_table_entry[k].mc_data[j] =
5343 (temp_reg & 0xffff0000) |
5344 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5346 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5359 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5364 case MC_SEQ_RAS_TIMING >> 2:
5365 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5367 case MC_SEQ_CAS_TIMING >> 2:
5368 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5370 case MC_SEQ_MISC_TIMING >> 2:
5371 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5373 case MC_SEQ_MISC_TIMING2 >> 2:
5374 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5376 case MC_SEQ_RD_CTL_D0 >> 2:
5377 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5379 case MC_SEQ_RD_CTL_D1 >> 2:
5380 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5382 case MC_SEQ_WR_CTL_D0 >> 2:
5383 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5385 case MC_SEQ_WR_CTL_D1 >> 2:
5386 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5388 case MC_PMG_CMD_EMRS >> 2:
5389 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5391 case MC_PMG_CMD_MRS >> 2:
5392 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5394 case MC_PMG_CMD_MRS1 >> 2:
5395 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5397 case MC_SEQ_PMG_TIMING >> 2:
5398 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5400 case MC_PMG_CMD_MRS2 >> 2:
5401 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5403 case MC_SEQ_WR_CTL_2 >> 2:
5404 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5414 static void si_set_valid_flag(struct si_mc_reg_table *table)
5418 for (i = 0; i < table->last; i++) {
5419 for (j = 1; j < table->num_entries; j++) {
5420 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5421 table->valid_flag |= 1 << i;
5428 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5433 for (i = 0; i < table->last; i++)
5434 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5435 address : table->mc_reg_address[i].s1;
5439 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5440 struct si_mc_reg_table *si_table)
5444 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5446 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5449 for (i = 0; i < table->last; i++)
5450 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5451 si_table->last = table->last;
5453 for (i = 0; i < table->num_entries; i++) {
5454 si_table->mc_reg_table_entry[i].mclk_max =
5455 table->mc_reg_table_entry[i].mclk_max;
5456 for (j = 0; j < table->last; j++) {
5457 si_table->mc_reg_table_entry[i].mc_data[j] =
5458 table->mc_reg_table_entry[i].mc_data[j];
5461 si_table->num_entries = table->num_entries;
5466 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5468 struct si_power_info *si_pi = si_get_pi(rdev);
5469 struct atom_mc_reg_table *table;
5470 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5471 u8 module_index = rv770_get_memory_module_index(rdev);
5474 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5478 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5479 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5480 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5481 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5482 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5483 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5484 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5485 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5486 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5487 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5488 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5489 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5490 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5491 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5493 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5497 ret = si_copy_vbios_mc_reg_table(table, si_table);
5501 si_set_s0_mc_reg_index(si_table);
5503 ret = si_set_mc_special_registers(rdev, si_table);
5507 si_set_valid_flag(si_table);
5516 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5517 SMC_SIslands_MCRegisters *mc_reg_table)
5519 struct si_power_info *si_pi = si_get_pi(rdev);
5522 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5523 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5524 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5526 mc_reg_table->address[i].s0 =
5527 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5528 mc_reg_table->address[i].s1 =
5529 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5533 mc_reg_table->last = (u8)i;
5536 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5537 SMC_SIslands_MCRegisterSet *data,
5538 u32 num_entries, u32 valid_flag)
5542 for(i = 0, j = 0; j < num_entries; j++) {
5543 if (valid_flag & (1 << j)) {
5544 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5550 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5551 struct rv7xx_pl *pl,
5552 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5554 struct si_power_info *si_pi = si_get_pi(rdev);
5557 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5558 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5562 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5565 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5566 mc_reg_table_data, si_pi->mc_reg_table.last,
5567 si_pi->mc_reg_table.valid_flag);
5570 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5571 struct radeon_ps *radeon_state,
5572 SMC_SIslands_MCRegisters *mc_reg_table)
5574 struct ni_ps *state = ni_get_ps(radeon_state);
5577 for (i = 0; i < state->performance_level_count; i++) {
5578 si_convert_mc_reg_table_entry_to_smc(rdev,
5579 &state->performance_levels[i],
5580 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5584 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5585 struct radeon_ps *radeon_boot_state)
5587 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5588 struct si_power_info *si_pi = si_get_pi(rdev);
5589 struct si_ulv_param *ulv = &si_pi->ulv;
5590 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5592 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5594 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5596 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5598 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5599 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5601 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5602 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5603 si_pi->mc_reg_table.last,
5604 si_pi->mc_reg_table.valid_flag);
5606 if (ulv->supported && ulv->pl.vddc != 0)
5607 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5608 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5610 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5611 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5612 si_pi->mc_reg_table.last,
5613 si_pi->mc_reg_table.valid_flag);
5615 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5617 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5618 (u8 *)smc_mc_reg_table,
5619 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5622 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5623 struct radeon_ps *radeon_new_state)
5625 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5626 struct si_power_info *si_pi = si_get_pi(rdev);
5627 u32 address = si_pi->mc_reg_table_start +
5628 offsetof(SMC_SIslands_MCRegisters,
5629 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5630 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5632 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5634 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5637 return si_copy_bytes_to_smc(rdev, address,
5638 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5639 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5644 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5647 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5649 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5652 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5653 struct radeon_ps *radeon_state)
5655 struct ni_ps *state = ni_get_ps(radeon_state);
5657 u16 pcie_speed, max_speed = 0;
5659 for (i = 0; i < state->performance_level_count; i++) {
5660 pcie_speed = state->performance_levels[i].pcie_gen;
5661 if (max_speed < pcie_speed)
5662 max_speed = pcie_speed;
5667 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5671 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5672 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5674 return (u16)speed_cntl;
5677 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5678 struct radeon_ps *radeon_new_state,
5679 struct radeon_ps *radeon_current_state)
5681 struct si_power_info *si_pi = si_get_pi(rdev);
5682 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5683 enum radeon_pcie_gen current_link_speed;
5685 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5686 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5688 current_link_speed = si_pi->force_pcie_gen;
5690 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5691 si_pi->pspp_notify_required = false;
5692 if (target_link_speed > current_link_speed) {
5693 switch (target_link_speed) {
5694 #if defined(CONFIG_ACPI)
5695 case RADEON_PCIE_GEN3:
5696 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5698 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5699 if (current_link_speed == RADEON_PCIE_GEN2)
5701 case RADEON_PCIE_GEN2:
5702 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5706 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5710 if (target_link_speed < current_link_speed)
5711 si_pi->pspp_notify_required = true;
5715 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5716 struct radeon_ps *radeon_new_state,
5717 struct radeon_ps *radeon_current_state)
5719 struct si_power_info *si_pi = si_get_pi(rdev);
5720 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5723 if (si_pi->pspp_notify_required) {
5724 if (target_link_speed == RADEON_PCIE_GEN3)
5725 request = PCIE_PERF_REQ_PECI_GEN3;
5726 else if (target_link_speed == RADEON_PCIE_GEN2)
5727 request = PCIE_PERF_REQ_PECI_GEN2;
5729 request = PCIE_PERF_REQ_PECI_GEN1;
5731 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5732 (si_get_current_pcie_speed(rdev) > 0))
5735 #if defined(CONFIG_ACPI)
5736 radeon_acpi_pcie_performance_request(rdev, request, false);
5742 static int si_ds_request(struct radeon_device *rdev,
5743 bool ds_status_on, u32 count_write)
5745 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5747 if (eg_pi->sclk_deep_sleep) {
5749 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5753 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5754 PPSMC_Result_OK) ? 0 : -EINVAL;
5760 static void si_set_max_cu_value(struct radeon_device *rdev)
5762 struct si_power_info *si_pi = si_get_pi(rdev);
5764 if (rdev->family == CHIP_VERDE) {
5765 switch (rdev->pdev->device) {
5801 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5802 struct radeon_clock_voltage_dependency_table *table)
5806 u16 leakage_voltage;
5809 for (i = 0; i < table->count; i++) {
5810 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5811 table->entries[i].v,
5812 &leakage_voltage)) {
5814 table->entries[i].v = leakage_voltage;
5824 for (j = (table->count - 2); j >= 0; j--) {
5825 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5826 table->entries[j].v : table->entries[j + 1].v;
5832 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5836 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5837 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5838 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5839 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5840 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5841 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5845 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5846 struct radeon_ps *radeon_new_state,
5847 struct radeon_ps *radeon_current_state)
5850 u32 new_lane_width =
5851 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5852 u32 current_lane_width =
5853 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5855 if (new_lane_width != current_lane_width) {
5856 radeon_set_pcie_lanes(rdev, new_lane_width);
5857 lane_width = radeon_get_pcie_lanes(rdev);
5858 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5862 void si_dpm_setup_asic(struct radeon_device *rdev)
5866 r = si_mc_load_microcode(rdev);
5868 DRM_ERROR("Failed to load MC firmware!\n");
5869 rv770_get_memory_type(rdev);
5870 si_read_clock_registers(rdev);
5871 si_enable_acpi_power_management(rdev);
5874 static int si_thermal_enable_alert(struct radeon_device *rdev,
5877 u32 thermal_int = RREG32(CG_THERMAL_INT);
5880 PPSMC_Result result;
5882 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5883 WREG32(CG_THERMAL_INT, thermal_int);
5884 rdev->irq.dpm_thermal = false;
5885 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5886 if (result != PPSMC_Result_OK) {
5887 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5891 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5892 WREG32(CG_THERMAL_INT, thermal_int);
5893 rdev->irq.dpm_thermal = true;
5899 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5900 int min_temp, int max_temp)
5902 int low_temp = 0 * 1000;
5903 int high_temp = 255 * 1000;
5905 if (low_temp < min_temp)
5906 low_temp = min_temp;
5907 if (high_temp > max_temp)
5908 high_temp = max_temp;
5909 if (high_temp < low_temp) {
5910 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5914 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5915 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5916 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5918 rdev->pm.dpm.thermal.min_temp = low_temp;
5919 rdev->pm.dpm.thermal.max_temp = high_temp;
5924 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
5926 struct si_power_info *si_pi = si_get_pi(rdev);
5929 if (si_pi->fan_ctrl_is_in_default_mode) {
5930 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
5931 si_pi->fan_ctrl_default_mode = tmp;
5932 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
5934 si_pi->fan_ctrl_is_in_default_mode = false;
5937 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
5939 WREG32(CG_FDO_CTRL2, tmp);
5941 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
5942 tmp |= FDO_PWM_MODE(mode);
5943 WREG32(CG_FDO_CTRL2, tmp);
5946 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
5948 struct si_power_info *si_pi = si_get_pi(rdev);
5949 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
5951 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
5952 u16 fdo_min, slope1, slope2;
5953 u32 reference_clock, tmp;
5957 if (!si_pi->fan_table_start) {
5958 rdev->pm.dpm.fan.ucode_fan_control = false;
5962 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
5965 rdev->pm.dpm.fan.ucode_fan_control = false;
5969 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
5970 do_div(tmp64, 10000);
5971 fdo_min = (u16)tmp64;
5973 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
5974 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
5976 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
5977 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
5979 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
5980 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
5982 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
5983 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
5984 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
5986 fan_table.slope1 = cpu_to_be16(slope1);
5987 fan_table.slope2 = cpu_to_be16(slope2);
5989 fan_table.fdo_min = cpu_to_be16(fdo_min);
5991 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
5993 fan_table.hys_up = cpu_to_be16(1);
5995 fan_table.hys_slope = cpu_to_be16(1);
5997 fan_table.temp_resp_lim = cpu_to_be16(5);
5999 reference_clock = radeon_get_xclk(rdev);
6001 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6002 reference_clock) / 1600);
6004 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6006 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6007 fan_table.temp_src = (uint8_t)tmp;
6009 ret = si_copy_bytes_to_smc(rdev,
6010 si_pi->fan_table_start,
6016 DRM_ERROR("Failed to load fan table to the SMC.");
6017 rdev->pm.dpm.fan.ucode_fan_control = false;
6023 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6025 struct si_power_info *si_pi = si_get_pi(rdev);
6028 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6029 if (ret == PPSMC_Result_OK) {
6030 si_pi->fan_is_controlled_by_smc = true;
6037 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6039 struct si_power_info *si_pi = si_get_pi(rdev);
6042 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6044 if (ret == PPSMC_Result_OK) {
6045 si_pi->fan_is_controlled_by_smc = false;
6052 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6058 if (rdev->pm.no_fan)
6061 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6062 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6067 tmp64 = (u64)duty * 100;
6068 do_div(tmp64, duty100);
6069 *speed = (u32)tmp64;
6077 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6080 struct si_power_info *si_pi = si_get_pi(rdev);
6085 if (rdev->pm.no_fan)
6088 if (si_pi->fan_is_controlled_by_smc)
6094 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6099 tmp64 = (u64)speed * duty100;
6103 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6104 tmp |= FDO_STATIC_DUTY(duty);
6105 WREG32(CG_FDO_CTRL0, tmp);
6110 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6113 /* stop auto-manage */
6114 if (rdev->pm.dpm.fan.ucode_fan_control)
6115 si_fan_ctrl_stop_smc_fan_control(rdev);
6116 si_fan_ctrl_set_static_mode(rdev, mode);
6118 /* restart auto-manage */
6119 if (rdev->pm.dpm.fan.ucode_fan_control)
6120 si_thermal_start_smc_fan_control(rdev);
6122 si_fan_ctrl_set_default_mode(rdev);
6126 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6128 struct si_power_info *si_pi = si_get_pi(rdev);
6131 if (si_pi->fan_is_controlled_by_smc)
6134 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6135 return (tmp >> FDO_PWM_MODE_SHIFT);
6139 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6143 u32 xclk = radeon_get_xclk(rdev);
6145 if (rdev->pm.no_fan)
6148 if (rdev->pm.fan_pulses_per_revolution == 0)
6151 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6152 if (tach_period == 0)
6155 *speed = 60 * xclk * 10000 / tach_period;
6160 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6163 u32 tach_period, tmp;
6164 u32 xclk = radeon_get_xclk(rdev);
6166 if (rdev->pm.no_fan)
6169 if (rdev->pm.fan_pulses_per_revolution == 0)
6172 if ((speed < rdev->pm.fan_min_rpm) ||
6173 (speed > rdev->pm.fan_max_rpm))
6176 if (rdev->pm.dpm.fan.ucode_fan_control)
6177 si_fan_ctrl_stop_smc_fan_control(rdev);
6179 tach_period = 60 * xclk * 10000 / (8 * speed);
6180 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6181 tmp |= TARGET_PERIOD(tach_period);
6182 WREG32(CG_TACH_CTRL, tmp);
6184 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6190 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6192 struct si_power_info *si_pi = si_get_pi(rdev);
6195 if (!si_pi->fan_ctrl_is_in_default_mode) {
6196 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6197 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6198 WREG32(CG_FDO_CTRL2, tmp);
6200 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6201 tmp |= TMIN(si_pi->t_min);
6202 WREG32(CG_FDO_CTRL2, tmp);
6203 si_pi->fan_ctrl_is_in_default_mode = true;
6207 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6209 if (rdev->pm.dpm.fan.ucode_fan_control) {
6210 si_fan_ctrl_start_smc_fan_control(rdev);
6211 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6215 static void si_thermal_initialize(struct radeon_device *rdev)
6219 if (rdev->pm.fan_pulses_per_revolution) {
6220 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6221 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6222 WREG32(CG_TACH_CTRL, tmp);
6225 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6226 tmp |= TACH_PWM_RESP_RATE(0x28);
6227 WREG32(CG_FDO_CTRL2, tmp);
6230 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6234 si_thermal_initialize(rdev);
6235 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6238 ret = si_thermal_enable_alert(rdev, true);
6241 if (rdev->pm.dpm.fan.ucode_fan_control) {
6242 ret = si_halt_smc(rdev);
6245 ret = si_thermal_setup_fan_table(rdev);
6248 ret = si_resume_smc(rdev);
6251 si_thermal_start_smc_fan_control(rdev);
6257 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6259 if (!rdev->pm.no_fan) {
6260 si_fan_ctrl_set_default_mode(rdev);
6261 si_fan_ctrl_stop_smc_fan_control(rdev);
6265 int si_dpm_enable(struct radeon_device *rdev)
6267 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6268 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6269 struct si_power_info *si_pi = si_get_pi(rdev);
6270 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6273 if (si_is_smc_running(rdev))
6275 if (pi->voltage_control || si_pi->voltage_control_svi2)
6276 si_enable_voltage_control(rdev, true);
6277 if (pi->mvdd_control)
6278 si_get_mvdd_configuration(rdev);
6279 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6280 ret = si_construct_voltage_tables(rdev);
6282 DRM_ERROR("si_construct_voltage_tables failed\n");
6286 if (eg_pi->dynamic_ac_timing) {
6287 ret = si_initialize_mc_reg_table(rdev);
6289 eg_pi->dynamic_ac_timing = false;
6292 si_enable_spread_spectrum(rdev, true);
6293 if (pi->thermal_protection)
6294 si_enable_thermal_protection(rdev, true);
6296 si_program_git(rdev);
6297 si_program_tp(rdev);
6298 si_program_tpp(rdev);
6299 si_program_sstp(rdev);
6300 si_enable_display_gap(rdev);
6301 si_program_vc(rdev);
6302 ret = si_upload_firmware(rdev);
6304 DRM_ERROR("si_upload_firmware failed\n");
6307 ret = si_process_firmware_header(rdev);
6309 DRM_ERROR("si_process_firmware_header failed\n");
6312 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6314 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6317 ret = si_init_smc_table(rdev);
6319 DRM_ERROR("si_init_smc_table failed\n");
6322 ret = si_init_smc_spll_table(rdev);
6324 DRM_ERROR("si_init_smc_spll_table failed\n");
6327 ret = si_init_arb_table_index(rdev);
6329 DRM_ERROR("si_init_arb_table_index failed\n");
6332 if (eg_pi->dynamic_ac_timing) {
6333 ret = si_populate_mc_reg_table(rdev, boot_ps);
6335 DRM_ERROR("si_populate_mc_reg_table failed\n");
6339 ret = si_initialize_smc_cac_tables(rdev);
6341 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6344 ret = si_initialize_hardware_cac_manager(rdev);
6346 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6349 ret = si_initialize_smc_dte_tables(rdev);
6351 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6354 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6356 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6359 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6361 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6364 si_program_response_times(rdev);
6365 si_program_ds_registers(rdev);
6366 si_dpm_start_smc(rdev);
6367 ret = si_notify_smc_display_change(rdev, false);
6369 DRM_ERROR("si_notify_smc_display_change failed\n");
6372 si_enable_sclk_control(rdev, true);
6375 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6377 si_thermal_start_thermal_controller(rdev);
6379 ni_update_current_ps(rdev, boot_ps);
6384 static int si_set_temperature_range(struct radeon_device *rdev)
6388 ret = si_thermal_enable_alert(rdev, false);
6391 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6394 ret = si_thermal_enable_alert(rdev, true);
6401 int si_dpm_late_enable(struct radeon_device *rdev)
6405 ret = si_set_temperature_range(rdev);
6412 void si_dpm_disable(struct radeon_device *rdev)
6414 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6415 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6417 if (!si_is_smc_running(rdev))
6419 si_thermal_stop_thermal_controller(rdev);
6420 si_disable_ulv(rdev);
6422 if (pi->thermal_protection)
6423 si_enable_thermal_protection(rdev, false);
6424 si_enable_power_containment(rdev, boot_ps, false);
6425 si_enable_smc_cac(rdev, boot_ps, false);
6426 si_enable_spread_spectrum(rdev, false);
6427 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6429 si_reset_to_default(rdev);
6430 si_dpm_stop_smc(rdev);
6431 si_force_switch_to_arb_f0(rdev);
6433 ni_update_current_ps(rdev, boot_ps);
6436 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6438 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6439 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6440 struct radeon_ps *new_ps = &requested_ps;
6442 ni_update_requested_ps(rdev, new_ps);
6444 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6449 static int si_power_control_set_level(struct radeon_device *rdev)
6451 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6454 ret = si_restrict_performance_levels_before_switch(rdev);
6457 ret = si_halt_smc(rdev);
6460 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6463 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6466 ret = si_resume_smc(rdev);
6469 ret = si_set_sw_state(rdev);
6475 int si_dpm_set_power_state(struct radeon_device *rdev)
6477 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6478 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6479 struct radeon_ps *old_ps = &eg_pi->current_rps;
6482 ret = si_disable_ulv(rdev);
6484 DRM_ERROR("si_disable_ulv failed\n");
6487 ret = si_restrict_performance_levels_before_switch(rdev);
6489 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6492 if (eg_pi->pcie_performance_request)
6493 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6494 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6495 ret = si_enable_power_containment(rdev, new_ps, false);
6497 DRM_ERROR("si_enable_power_containment failed\n");
6500 ret = si_enable_smc_cac(rdev, new_ps, false);
6502 DRM_ERROR("si_enable_smc_cac failed\n");
6505 ret = si_halt_smc(rdev);
6507 DRM_ERROR("si_halt_smc failed\n");
6510 ret = si_upload_sw_state(rdev, new_ps);
6512 DRM_ERROR("si_upload_sw_state failed\n");
6515 ret = si_upload_smc_data(rdev);
6517 DRM_ERROR("si_upload_smc_data failed\n");
6520 ret = si_upload_ulv_state(rdev);
6522 DRM_ERROR("si_upload_ulv_state failed\n");
6525 if (eg_pi->dynamic_ac_timing) {
6526 ret = si_upload_mc_reg_table(rdev, new_ps);
6528 DRM_ERROR("si_upload_mc_reg_table failed\n");
6532 ret = si_program_memory_timing_parameters(rdev, new_ps);
6534 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6537 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6539 ret = si_resume_smc(rdev);
6541 DRM_ERROR("si_resume_smc failed\n");
6544 ret = si_set_sw_state(rdev);
6546 DRM_ERROR("si_set_sw_state failed\n");
6549 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6550 if (eg_pi->pcie_performance_request)
6551 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6552 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6554 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6557 ret = si_enable_smc_cac(rdev, new_ps, true);
6559 DRM_ERROR("si_enable_smc_cac failed\n");
6562 ret = si_enable_power_containment(rdev, new_ps, true);
6564 DRM_ERROR("si_enable_power_containment failed\n");
6568 ret = si_power_control_set_level(rdev);
6570 DRM_ERROR("si_power_control_set_level failed\n");
6577 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6579 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6580 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6582 ni_update_current_ps(rdev, new_ps);
6586 void si_dpm_reset_asic(struct radeon_device *rdev)
6588 si_restrict_performance_levels_before_switch(rdev);
6589 si_disable_ulv(rdev);
6590 si_set_boot_state(rdev);
6594 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6596 si_program_display_gap(rdev);
6600 struct _ATOM_POWERPLAY_INFO info;
6601 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6602 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6603 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6604 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6605 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6608 union pplib_clock_info {
6609 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6610 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6611 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6612 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6613 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6616 union pplib_power_state {
6617 struct _ATOM_PPLIB_STATE v1;
6618 struct _ATOM_PPLIB_STATE_V2 v2;
6621 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6622 struct radeon_ps *rps,
6623 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6626 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6627 rps->class = le16_to_cpu(non_clock_info->usClassification);
6628 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6630 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6631 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6632 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6633 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6634 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6635 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6641 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6642 rdev->pm.dpm.boot_ps = rps;
6643 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6644 rdev->pm.dpm.uvd_ps = rps;
6647 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6648 struct radeon_ps *rps, int index,
6649 union pplib_clock_info *clock_info)
6651 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6652 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6653 struct si_power_info *si_pi = si_get_pi(rdev);
6654 struct ni_ps *ps = ni_get_ps(rps);
6655 u16 leakage_voltage;
6656 struct rv7xx_pl *pl = &ps->performance_levels[index];
6659 ps->performance_level_count = index + 1;
6661 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6662 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6663 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6664 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6666 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6667 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6668 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6669 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6670 si_pi->sys_pcie_mask,
6671 si_pi->boot_pcie_gen,
6672 clock_info->si.ucPCIEGen);
6674 /* patch up vddc if necessary */
6675 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6678 pl->vddc = leakage_voltage;
6680 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6681 pi->acpi_vddc = pl->vddc;
6682 eg_pi->acpi_vddci = pl->vddci;
6683 si_pi->acpi_pcie_gen = pl->pcie_gen;
6686 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6688 /* XXX disable for A0 tahiti */
6689 si_pi->ulv.supported = false;
6690 si_pi->ulv.pl = *pl;
6691 si_pi->ulv.one_pcie_lane_in_ulv = false;
6692 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6693 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6694 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6697 if (pi->min_vddc_in_table > pl->vddc)
6698 pi->min_vddc_in_table = pl->vddc;
6700 if (pi->max_vddc_in_table < pl->vddc)
6701 pi->max_vddc_in_table = pl->vddc;
6703 /* patch up boot state */
6704 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6705 u16 vddc, vddci, mvdd;
6706 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6707 pl->mclk = rdev->clock.default_mclk;
6708 pl->sclk = rdev->clock.default_sclk;
6711 si_pi->mvdd_bootup_value = mvdd;
6714 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6715 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6716 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6717 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6718 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6719 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6723 static int si_parse_power_table(struct radeon_device *rdev)
6725 struct radeon_mode_info *mode_info = &rdev->mode_info;
6726 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6727 union pplib_power_state *power_state;
6728 int i, j, k, non_clock_array_index, clock_array_index;
6729 union pplib_clock_info *clock_info;
6730 struct _StateArray *state_array;
6731 struct _ClockInfoArray *clock_info_array;
6732 struct _NonClockInfoArray *non_clock_info_array;
6733 union power_info *power_info;
6734 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6737 u8 *power_state_offset;
6740 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6741 &frev, &crev, &data_offset))
6743 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6745 state_array = (struct _StateArray *)
6746 (mode_info->atom_context->bios + data_offset +
6747 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6748 clock_info_array = (struct _ClockInfoArray *)
6749 (mode_info->atom_context->bios + data_offset +
6750 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6751 non_clock_info_array = (struct _NonClockInfoArray *)
6752 (mode_info->atom_context->bios + data_offset +
6753 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6755 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6756 state_array->ucNumEntries, GFP_KERNEL);
6757 if (!rdev->pm.dpm.ps)
6759 power_state_offset = (u8 *)state_array->states;
6760 for (i = 0; i < state_array->ucNumEntries; i++) {
6762 power_state = (union pplib_power_state *)power_state_offset;
6763 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6764 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6765 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6766 if (!rdev->pm.power_state[i].clock_info)
6768 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6770 kfree(rdev->pm.dpm.ps);
6773 rdev->pm.dpm.ps[i].ps_priv = ps;
6774 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6776 non_clock_info_array->ucEntrySize);
6778 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6779 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6780 clock_array_index = idx[j];
6781 if (clock_array_index >= clock_info_array->ucNumEntries)
6783 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6785 clock_info = (union pplib_clock_info *)
6786 ((u8 *)&clock_info_array->clockInfo[0] +
6787 (clock_array_index * clock_info_array->ucEntrySize));
6788 si_parse_pplib_clock_info(rdev,
6789 &rdev->pm.dpm.ps[i], k,
6793 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6795 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6799 int si_dpm_init(struct radeon_device *rdev)
6801 struct rv7xx_power_info *pi;
6802 struct evergreen_power_info *eg_pi;
6803 struct ni_power_info *ni_pi;
6804 struct si_power_info *si_pi;
6805 struct atom_clock_dividers dividers;
6809 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6812 rdev->pm.dpm.priv = si_pi;
6817 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6819 si_pi->sys_pcie_mask = 0;
6821 si_pi->sys_pcie_mask = mask;
6822 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6823 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6825 si_set_max_cu_value(rdev);
6827 rv770_get_max_vddc(rdev);
6828 si_get_leakage_vddc(rdev);
6829 si_patch_dependency_tables_based_on_leakage(rdev);
6832 eg_pi->acpi_vddci = 0;
6833 pi->min_vddc_in_table = 0;
6834 pi->max_vddc_in_table = 0;
6836 ret = r600_get_platform_caps(rdev);
6840 ret = si_parse_power_table(rdev);
6843 ret = r600_parse_extended_power_table(rdev);
6847 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6848 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6849 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6850 r600_free_extended_power_table(rdev);
6853 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6854 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6855 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6856 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6857 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6858 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6859 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6860 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6861 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6863 if (rdev->pm.dpm.voltage_response_time == 0)
6864 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6865 if (rdev->pm.dpm.backbias_response_time == 0)
6866 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6868 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6869 0, false, ÷rs);
6871 pi->ref_div = dividers.ref_div + 1;
6873 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6875 eg_pi->smu_uvd_hs = false;
6877 pi->mclk_strobe_mode_threshold = 40000;
6878 if (si_is_special_1gb_platform(rdev))
6879 pi->mclk_stutter_mode_threshold = 0;
6881 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6882 pi->mclk_edc_enable_threshold = 40000;
6883 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6885 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6887 pi->voltage_control =
6888 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6889 VOLTAGE_OBJ_GPIO_LUT);
6890 if (!pi->voltage_control) {
6891 si_pi->voltage_control_svi2 =
6892 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6894 if (si_pi->voltage_control_svi2)
6895 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6896 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
6900 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
6901 VOLTAGE_OBJ_GPIO_LUT);
6903 eg_pi->vddci_control =
6904 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6905 VOLTAGE_OBJ_GPIO_LUT);
6906 if (!eg_pi->vddci_control)
6907 si_pi->vddci_control_svi2 =
6908 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6911 si_pi->vddc_phase_shed_control =
6912 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6913 VOLTAGE_OBJ_PHASE_LUT);
6915 rv770_get_engine_memory_ss(rdev);
6917 pi->asi = RV770_ASI_DFLT;
6918 pi->pasi = CYPRESS_HASI_DFLT;
6919 pi->vrc = SISLANDS_VRC_DFLT;
6921 pi->gfx_clock_gating = true;
6923 eg_pi->sclk_deep_sleep = true;
6924 si_pi->sclk_deep_sleep_above_low = false;
6926 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6927 pi->thermal_protection = true;
6929 pi->thermal_protection = false;
6931 eg_pi->dynamic_ac_timing = true;
6933 eg_pi->light_sleep = true;
6934 #if defined(CONFIG_ACPI)
6935 eg_pi->pcie_performance_request =
6936 radeon_acpi_is_pcie_performance_request_supported(rdev);
6938 eg_pi->pcie_performance_request = false;
6941 si_pi->sram_end = SMC_RAM_END;
6943 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6944 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6945 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6946 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6947 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6948 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6949 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6951 si_initialize_powertune_defaults(rdev);
6953 /* make sure dc limits are valid */
6954 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6955 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6956 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6957 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6959 si_pi->fan_ctrl_is_in_default_mode = true;
6964 void si_dpm_fini(struct radeon_device *rdev)
6968 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6969 kfree(rdev->pm.dpm.ps[i].ps_priv);
6971 kfree(rdev->pm.dpm.ps);
6972 kfree(rdev->pm.dpm.priv);
6973 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6974 r600_free_extended_power_table(rdev);
6977 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6980 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6981 struct radeon_ps *rps = &eg_pi->current_rps;
6982 struct ni_ps *ps = ni_get_ps(rps);
6983 struct rv7xx_pl *pl;
6985 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6986 CURRENT_STATE_INDEX_SHIFT;
6988 if (current_index >= ps->performance_level_count) {
6989 seq_printf(m, "invalid dpm profile %d\n", current_index);
6991 pl = &ps->performance_levels[current_index];
6992 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6993 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6994 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6998 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7000 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7001 struct radeon_ps *rps = &eg_pi->current_rps;
7002 struct ni_ps *ps = ni_get_ps(rps);
7003 struct rv7xx_pl *pl;
7005 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7006 CURRENT_STATE_INDEX_SHIFT;
7008 if (current_index >= ps->performance_level_count) {
7011 pl = &ps->performance_levels[current_index];
7016 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7018 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7019 struct radeon_ps *rps = &eg_pi->current_rps;
7020 struct ni_ps *ps = ni_get_ps(rps);
7021 struct rv7xx_pl *pl;
7023 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7024 CURRENT_STATE_INDEX_SHIFT;
7026 if (current_index >= ps->performance_level_count) {
7029 pl = &ps->performance_levels[current_index];