drivers/gpu/drm/radeon/rs780_dpm.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include "drmP.h"
  26 #include "radeon.h"
  27 #include "rs780d.h"
  28 #include "r600_dpm.h"
  29 #include "rs780_dpm.h"
  30 #include "atom.h"
  31
  32 static struct igp_ps *rs780_get_ps(struct radeon_ps *rps)
  33 {
  34         struct igp_ps *ps = rps->ps_priv;
  35
  36         return ps;
  37 }
  38
  39 static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev)
  40 {
  41         struct igp_power_info *pi = rdev->pm.dpm.priv;
  42
  43         return pi;
  44 }
  45
  46 static void rs780_get_pm_mode_parameters(struct radeon_device *rdev)
  47 {
  48         struct igp_power_info *pi = rs780_get_pi(rdev);
  49         struct radeon_mode_info *minfo = &rdev->mode_info;
  50         struct drm_crtc *crtc;
  51         struct radeon_crtc *radeon_crtc;
  52         int i;
  53
  54         /* defaults */
  55         pi->crtc_id = 0;
  56         pi->refresh_rate = 60;
  57
  58         for (i = 0; i < rdev->num_crtc; i++) {
  59                 crtc = (struct drm_crtc *)minfo->crtcs[i];
  60                 if (crtc && crtc->enabled) {
  61                         radeon_crtc = to_radeon_crtc(crtc);
  62                         pi->crtc_id = radeon_crtc->crtc_id;
  63                         if (crtc->mode.htotal && crtc->mode.vtotal)
  64                                 pi->refresh_rate =
  65                                         (crtc->mode.clock * 1000) /
  66                                         (crtc->mode.htotal * crtc->mode.vtotal);
  67                         break;
  68                 }
  69         }
  70 }
  71
  72 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
  73
  74 static int rs780_initialize_dpm_power_state(struct radeon_device *rdev,
  75                                             struct radeon_ps *boot_ps)
  76 {
  77         struct atom_clock_dividers dividers;
  78         struct igp_ps *default_state = rs780_get_ps(boot_ps);
  79         int i, ret;
  80
  81         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
  82                                              default_state->sclk_low, false, &dividers);
  83         if (ret)
  84                 return ret;
  85
  86         r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
  87         r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
  88         r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
  89
  90         if (dividers.enable_post_div)
  91                 r600_engine_clock_entry_enable_post_divider(rdev, 0, true);
  92         else
  93                 r600_engine_clock_entry_enable_post_divider(rdev, 0, false);
  94
  95         r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT);
  96         r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false);
  97
  98         r600_engine_clock_entry_enable(rdev, 0, true);
  99         for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++)
 100                 r600_engine_clock_entry_enable(rdev, i, false);
 101
 102         r600_enable_mclk_control(rdev, false);
 103         r600_voltage_control_enable_pins(rdev, 0);
 104
 105         return 0;
 106 }
 107
 108 static int rs780_initialize_dpm_parameters(struct radeon_device *rdev,
 109                                            struct radeon_ps *boot_ps)
 110 {
 111         int ret = 0;
 112         int i;
 113
 114         r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT);
 115
 116         r600_set_at(rdev, 0, 0, 0, 0);
 117
 118         r600_set_git(rdev, R600_GICST_DFLT);
 119
 120         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
 121                 r600_set_tc(rdev, i, 0, 0);
 122
 123         r600_select_td(rdev, R600_TD_DFLT);
 124         r600_set_vrc(rdev, 0);
 125
 126         r600_set_tpu(rdev, R600_TPU_DFLT);
 127         r600_set_tpc(rdev, R600_TPC_DFLT);
 128
 129         r600_set_sstu(rdev, R600_SSTU_DFLT);
 130         r600_set_sst(rdev, R600_SST_DFLT);
 131
 132         r600_set_fctu(rdev, R600_FCTU_DFLT);
 133         r600_set_fct(rdev, R600_FCT_DFLT);
 134
 135         r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
 136         r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
 137         r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
 138         r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
 139         r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
 140
 141         r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
 142         r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT);
 143         r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
 144
 145         ret = rs780_initialize_dpm_power_state(rdev, boot_ps);
 146
 147         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW,     0);
 148         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM,  0);
 149         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,    0);
 150
 151         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,    0);
 152         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
 153         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,   0);
 154
 155         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW,    0);
 156         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
 157         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,   0);
 158
 159         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,    R600_DISPLAY_WATERMARK_HIGH);
 160         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH);
 161         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,   R600_DISPLAY_WATERMARK_HIGH);
 162
 163         r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false);
 164         r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
 165         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
 166         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
 167
 168         r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW);
 169
 170         r600_set_vrc(rdev, RS780_CGFTV_DFLT);
 171
 172         return ret;
 173 }
 174
 175 static void rs780_start_dpm(struct radeon_device *rdev)
 176 {
 177         r600_enable_sclk_control(rdev, false);
 178         r600_enable_mclk_control(rdev, false);
 179
 180         r600_dynamicpm_enable(rdev, true);
 181
 182         radeon_wait_for_vblank(rdev, 0);
 183         radeon_wait_for_vblank(rdev, 1);
 184
 185         r600_enable_spll_bypass(rdev, true);
 186         r600_wait_for_spll_change(rdev);
 187         r600_enable_spll_bypass(rdev, false);
 188         r600_wait_for_spll_change(rdev);
 189
 190         r600_enable_spll_bypass(rdev, true);
 191         r600_wait_for_spll_change(rdev);
 192         r600_enable_spll_bypass(rdev, false);
 193         r600_wait_for_spll_change(rdev);
 194
 195         r600_enable_sclk_control(rdev, true);
 196 }
 197
 198
 199 static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev)
 200 {
 201         WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
 202                  ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN);
 203
 204         WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
 205                  RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT),
 206                  ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK);
 207 }
 208
 209 static void rs780_preset_starting_fbdiv(struct radeon_device *rdev)
 210 {
 211         u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
 212
 213         WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
 214                  ~STARTING_FEEDBACK_DIV_MASK);
 215
 216         WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
 217                  ~FORCED_FEEDBACK_DIV_MASK);
 218
 219         WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
 220 }
 221
 222 static void rs780_voltage_scaling_init(struct radeon_device *rdev)
 223 {
 224         struct igp_power_info *pi = rs780_get_pi(rdev);
 225         struct drm_device *dev = rdev->ddev;
 226         u32 fv_throt_pwm_fb_div_range[3];
 227         u32 fv_throt_pwm_range[4];
 228
 229         if (dev->pdev->device == 0x9614) {
 230                 fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
 231                 fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
 232                 fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
 233         } else if ((dev->pdev->device == 0x9714) ||
 234                    (dev->pdev->device == 0x9715)) {
 235                 fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
 236                 fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
 237                 fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
 238         } else {
 239                 fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT;
 240                 fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT;
 241                 fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT;
 242         }
 243
 244         if (pi->pwm_voltage_control) {
 245                 fv_throt_pwm_range[0] = pi->min_voltage;
 246                 fv_throt_pwm_range[1] = pi->min_voltage;
 247                 fv_throt_pwm_range[2] = pi->max_voltage;
 248                 fv_throt_pwm_range[3] = pi->max_voltage;
 249         } else {
 250                 fv_throt_pwm_range[0] = pi->invert_pwm_required ?
 251                         RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT;
 252                 fv_throt_pwm_range[1] = pi->invert_pwm_required ?
 253                         RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT;
 254                 fv_throt_pwm_range[2] = pi->invert_pwm_required ?
 255                         RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT;
 256                 fv_throt_pwm_range[3] = pi->invert_pwm_required ?
 257                         RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT;
 258         }
 259
 260         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 261                  STARTING_PWM_HIGHTIME(pi->max_voltage),
 262                  ~STARTING_PWM_HIGHTIME_MASK);
 263
 264         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 265                  NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period),
 266                  ~NUMBER_OF_CYCLES_IN_PERIOD_MASK);
 267
 268         WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
 269                  ~FORCE_STARTING_PWM_HIGHTIME);
 270
 271         if (pi->invert_pwm_required)
 272                 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
 273         else
 274                 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);
 275
 276         rs780_voltage_scaling_enable(rdev, true);
 277
 278         WREG32(FVTHROT_PWM_CTRL_REG1,
 279                (MIN_PWM_HIGHTIME(pi->min_voltage) |
 280                 MAX_PWM_HIGHTIME(pi->max_voltage)));
 281
 282         WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);
 283         WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);
 284         WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);
 285         WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);
 286
 287         WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
 288                  RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]),
 289                  ~RANGE0_PWM_FEEDBACK_DIV_MASK);
 290
 291         WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,
 292                (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) |
 293                 RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2])));
 294
 295         WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,
 296                (RANGE0_PWM(fv_throt_pwm_range[1]) |
 297                 RANGE1_PWM(fv_throt_pwm_range[2])));
 298         WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,
 299                (RANGE2_PWM(fv_throt_pwm_range[1]) |
 300                 RANGE3_PWM(fv_throt_pwm_range[2])));
 301 }
 302
 303 static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
 304 {
 305         if (enable)
 306                 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE,
 307                          ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
 308         else
 309                 WREG32_P(FVTHROT_CNTRL_REG, 0,
 310                          ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
 311 }
 312
 313 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
 314 {
 315         if (enable)
 316                 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);
 317         else
 318                 WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);
 319 }
 320
 321 static void rs780_set_engine_clock_wfc(struct radeon_device *rdev)
 322 {
 323         WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);
 324         WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);
 325         WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);
 326         WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);
 327         WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);
 328
 329         WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);
 330         WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);
 331         WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);
 332         WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);
 333         WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);
 334 }
 335
 336 static void rs780_set_engine_clock_sc(struct radeon_device *rdev)
 337 {
 338         WREG32_P(FVTHROT_FBDIV_REG2,
 339                  FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT),
 340                  ~FB_DIV_TIMER_VAL_MASK);
 341
 342         WREG32_P(FVTHROT_CNTRL_REG,
 343                  REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf),
 344                  ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK));
 345 }
 346
 347 static void rs780_set_engine_clock_tdc(struct radeon_device *rdev)
 348 {
 349         WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE));
 350 }
 351
 352 static void rs780_set_engine_clock_ssc(struct radeon_device *rdev)
 353 {
 354         WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);
 355         WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);
 356         WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);
 357         WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);
 358
 359         WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);
 360 }
 361
 362 static void rs780_program_at(struct radeon_device *rdev)
 363 {
 364         struct igp_power_info *pi = rs780_get_pi(rdev);
 365
 366         WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);
 367         WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);
 368         WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);
 369         WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);
 370         WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);
 371 }
 372
 373 static void rs780_disable_vbios_powersaving(struct radeon_device *rdev)
 374 {
 375         WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
 376 }
 377
 378 static void rs780_force_voltage_to_high(struct radeon_device *rdev)
 379 {
 380         struct igp_power_info *pi = rs780_get_pi(rdev);
 381         struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
 382
 383         if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
 384             (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
 385                 return;
 386
 387         WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
 388
 389         udelay(1);
 390
 391         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 392                  STARTING_PWM_HIGHTIME(pi->max_voltage),
 393                  ~STARTING_PWM_HIGHTIME_MASK);
 394
 395         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 396                  FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME);
 397
 398         WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,
 399                 ~RANGE_PWM_FEEDBACK_DIV_EN);
 400
 401         udelay(1);
 402
 403         WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
 404 }
 405
 406 static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
 407                                           struct radeon_ps *new_ps,
 408                                           struct radeon_ps *old_ps)
 409 {
 410         struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers;
 411         struct igp_ps *new_state = rs780_get_ps(new_ps);
 412         struct igp_ps *old_state = rs780_get_ps(old_ps);
 413         int ret;
 414
 415         if ((new_state->sclk_high == old_state->sclk_high) &&
 416             (new_state->sclk_low == old_state->sclk_low))
 417                 return 0;
 418
 419         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 420                                              new_state->sclk_low, false, &min_dividers);
 421         if (ret)
 422                 return ret;
 423
 424         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 425                                              new_state->sclk_high, false, &max_dividers);
 426         if (ret)
 427                 return ret;
 428
 429         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 430                                              old_state->sclk_high, false, &current_max_dividers);
 431         if (ret)
 432                 return ret;
 433
 434         WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
 435
 436         WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(max_dividers.fb_div),
 437                  ~FORCED_FEEDBACK_DIV_MASK);
 438         WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(max_dividers.fb_div),
 439                  ~STARTING_FEEDBACK_DIV_MASK);
 440         WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
 441
 442         udelay(100);
 443
 444         WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
 445
 446         if (max_dividers.fb_div > min_dividers.fb_div) {
 447                 WREG32_P(FVTHROT_FBDIV_REG0,
 448                          MIN_FEEDBACK_DIV(min_dividers.fb_div) |
 449                          MAX_FEEDBACK_DIV(max_dividers.fb_div),
 450                          ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK));
 451
 452                 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
 453         }
 454
 455         return 0;
 456 }
 457
 458 static void rs780_set_engine_clock_spc(struct radeon_device *rdev,
 459                                        struct radeon_ps *new_ps,
 460                                        struct radeon_ps *old_ps)
 461 {
 462         struct igp_ps *new_state = rs780_get_ps(new_ps);
 463         struct igp_ps *old_state = rs780_get_ps(old_ps);
 464         struct igp_power_info *pi = rs780_get_pi(rdev);
 465
 466         if ((new_state->sclk_high == old_state->sclk_high) &&
 467             (new_state->sclk_low == old_state->sclk_low))
 468                 return;
 469
 470         if (pi->crtc_id == 0)
 471                 WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);
 472         else
 473                 WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);
 474
 475 }
 476
 477 static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev,
 478                                               struct radeon_ps *new_ps,
 479                                               struct radeon_ps *old_ps)
 480 {
 481         struct igp_ps *new_state = rs780_get_ps(new_ps);
 482         struct igp_ps *old_state = rs780_get_ps(old_ps);
 483
 484         if ((new_state->sclk_high == old_state->sclk_high) &&
 485             (new_state->sclk_low == old_state->sclk_low))
 486                 return;
 487
 488         rs780_clk_scaling_enable(rdev, true);
 489 }
 490
 491 static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,
 492                                             enum rs780_vddc_level vddc)
 493 {
 494         struct igp_power_info *pi = rs780_get_pi(rdev);
 495
 496         if (vddc == RS780_VDDC_LEVEL_HIGH)
 497                 return pi->max_voltage;
 498         else if (vddc == RS780_VDDC_LEVEL_LOW)
 499                 return pi->min_voltage;
 500         else
 501                 return pi->max_voltage;
 502 }
 503
 504 static void rs780_enable_voltage_scaling(struct radeon_device *rdev,
 505                                          struct radeon_ps *new_ps)
 506 {
 507         struct igp_ps *new_state = rs780_get_ps(new_ps);
 508         struct igp_power_info *pi = rs780_get_pi(rdev);
 509         enum rs780_vddc_level vddc_high, vddc_low;
 510
 511         udelay(100);
 512
 513         if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
 514             (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
 515                 return;
 516
 517         vddc_high = rs780_get_voltage_for_vddc_level(rdev,
 518                                                      new_state->max_voltage);
 519         vddc_low = rs780_get_voltage_for_vddc_level(rdev,
 520                                                     new_state->min_voltage);
 521
 522         WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
 523
 524         udelay(1);
 525         if (vddc_high > vddc_low) {
 526                 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
 527                          RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN);
 528
 529                 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);
 530         } else if (vddc_high == vddc_low) {
 531                 if (pi->max_voltage != vddc_high) {
 532                         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 533                                  STARTING_PWM_HIGHTIME(vddc_high),
 534                                  ~STARTING_PWM_HIGHTIME_MASK);
 535
 536                         WREG32_P(FVTHROT_PWM_CTRL_REG0,
 537                                  FORCE_STARTING_PWM_HIGHTIME,
 538                                  ~FORCE_STARTING_PWM_HIGHTIME);
 539                 }
 540         }
 541
 542         WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
 543 }
 544
 545 static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
 546                                                      struct radeon_ps *new_ps,
 547                                                      struct radeon_ps *old_ps)
 548 {
 549         struct igp_ps *new_state = rs780_get_ps(new_ps);
 550         struct igp_ps *current_state = rs780_get_ps(old_ps);
 551
 552         if ((new_ps->vclk == old_ps->vclk) &&
 553             (new_ps->dclk == old_ps->dclk))
 554                 return;
 555
 556         if (new_state->sclk_high >= current_state->sclk_high)
 557                 return;
 558
 559         radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
 560 }
 561
 562 static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
 563                                                     struct radeon_ps *new_ps,
 564                                                     struct radeon_ps *old_ps)
 565 {
 566         struct igp_ps *new_state = rs780_get_ps(new_ps);
 567         struct igp_ps *current_state = rs780_get_ps(old_ps);
 568
 569         if ((new_ps->vclk == old_ps->vclk) &&
 570             (new_ps->dclk == old_ps->dclk))
 571                 return;
 572
 573         if (new_state->sclk_high < current_state->sclk_high)
 574                 return;
 575
 576         radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
 577 }
 578
 579 int rs780_dpm_enable(struct radeon_device *rdev)
 580 {
 581         struct igp_power_info *pi = rs780_get_pi(rdev);
 582         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
 583         int ret;
 584
 585         rs780_get_pm_mode_parameters(rdev);
 586         rs780_disable_vbios_powersaving(rdev);
 587
 588         if (r600_dynamicpm_enabled(rdev))
 589                 return -EINVAL;
 590         ret = rs780_initialize_dpm_parameters(rdev, boot_ps);
 591         if (ret)
 592                 return ret;
 593         rs780_start_dpm(rdev);
 594
 595         rs780_preset_ranges_slow_clk_fbdiv_en(rdev);
 596         rs780_preset_starting_fbdiv(rdev);
 597         if (pi->voltage_control)
 598                 rs780_voltage_scaling_init(rdev);
 599         rs780_clk_scaling_enable(rdev, true);
 600         rs780_set_engine_clock_sc(rdev);
 601         rs780_set_engine_clock_wfc(rdev);
 602         rs780_program_at(rdev);
 603         rs780_set_engine_clock_tdc(rdev);
 604         rs780_set_engine_clock_ssc(rdev);
 605
 606         if (pi->gfx_clock_gating)
 607                 r600_gfx_clockgating_enable(rdev, true);
 608
 609         if (rdev->irq.installed && (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
 610                 ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
 611                 if (ret)
 612                         return ret;
 613                 rdev->irq.dpm_thermal = true;
 614                 radeon_irq_set(rdev);
 615         }
 616
 617         return 0;
 618 }
 619
 620 void rs780_dpm_disable(struct radeon_device *rdev)
 621 {
 622         struct igp_power_info *pi = rs780_get_pi(rdev);
 623
 624         r600_dynamicpm_enable(rdev, false);
 625
 626         rs780_clk_scaling_enable(rdev, false);
 627         rs780_voltage_scaling_enable(rdev, false);
 628
 629         if (pi->gfx_clock_gating)
 630                 r600_gfx_clockgating_enable(rdev, false);
 631
 632         if (rdev->irq.installed &&
 633             (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
 634                 rdev->irq.dpm_thermal = false;
 635                 radeon_irq_set(rdev);
 636         }
 637 }
 638
 639 int rs780_dpm_set_power_state(struct radeon_device *rdev)
 640 {
 641         struct igp_power_info *pi = rs780_get_pi(rdev);
 642         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
 643         struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
 644         int ret;
 645
 646         rs780_get_pm_mode_parameters(rdev);
 647
 648         rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
 649
 650         if (pi->voltage_control) {
 651                 rs780_force_voltage_to_high(rdev);
 652                 mdelay(5);
 653         }
 654
 655         ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps);
 656         if (ret)
 657                 return ret;
 658         rs780_set_engine_clock_spc(rdev, new_ps, old_ps);
 659
 660         rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps);
 661
 662         if (pi->voltage_control)
 663                 rs780_enable_voltage_scaling(rdev, new_ps);
 664
 665         rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
 666
 667         return 0;
 668 }
 669
 670 void rs780_dpm_setup_asic(struct radeon_device *rdev)
 671 {
 672
 673 }
 674
 675 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev)
 676 {
 677         rs780_get_pm_mode_parameters(rdev);
 678         rs780_program_at(rdev);
 679 }
 680
 681 union igp_info {
 682         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 683         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 684 };
 685
 686 union power_info {
 687         struct _ATOM_POWERPLAY_INFO info;
 688         struct _ATOM_POWERPLAY_INFO_V2 info_2;
 689         struct _ATOM_POWERPLAY_INFO_V3 info_3;
 690         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
 691         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
 692         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
 693 };
 694
 695 union pplib_clock_info {
 696         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
 697         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
 698         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
 699         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
 700 };
 701
 702 union pplib_power_state {
 703         struct _ATOM_PPLIB_STATE v1;
 704         struct _ATOM_PPLIB_STATE_V2 v2;
 705 };
 706
 707 static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
 708                                              struct radeon_ps *rps,
 709                                              struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
 710                                              u8 table_rev)
 711 {
 712         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
 713         rps->class = le16_to_cpu(non_clock_info->usClassification);
 714         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
 715
 716         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
 717                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
 718                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
 719         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
 720                 rps->vclk = RS780_DEFAULT_VCLK_FREQ;
 721                 rps->dclk = RS780_DEFAULT_DCLK_FREQ;
 722         } else {
 723                 rps->vclk = 0;
 724                 rps->dclk = 0;
 725         }
 726
 727         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
 728                 rdev->pm.dpm.boot_ps = rps;
 729         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
 730                 rdev->pm.dpm.uvd_ps = rps;
 731 }
 732
 733 static void rs780_parse_pplib_clock_info(struct radeon_device *rdev,
 734                                          struct radeon_ps *rps,
 735                                          union pplib_clock_info *clock_info)
 736 {
 737         struct igp_ps *ps = rs780_get_ps(rps);
 738         u32 sclk;
 739
 740         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
 741         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
 742         ps->sclk_low = sclk;
 743         sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow);
 744         sclk |= clock_info->rs780.ucHighEngineClockHigh << 16;
 745         ps->sclk_high = sclk;
 746         switch (le16_to_cpu(clock_info->rs780.usVDDC)) {
 747         case ATOM_PPLIB_RS780_VOLTAGE_NONE:
 748         default:
 749                 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN;
 750                 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN;
 751                 break;
 752         case ATOM_PPLIB_RS780_VOLTAGE_LOW:
 753                 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
 754                 ps->max_voltage = RS780_VDDC_LEVEL_LOW;
 755                 break;
 756         case ATOM_PPLIB_RS780_VOLTAGE_HIGH:
 757                 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
 758                 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
 759                 break;
 760         case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE:
 761                 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
 762                 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
 763                 break;
 764         }
 765         ps->flags = le32_to_cpu(clock_info->rs780.ulFlags);
 766
 767         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
 768                 ps->sclk_low = rdev->clock.default_sclk;
 769                 ps->sclk_high = rdev->clock.default_sclk;
 770                 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
 771                 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
 772         }
 773 }
 774
 775 static int rs780_parse_power_table(struct radeon_device *rdev)
 776 {
 777         struct radeon_mode_info *mode_info = &rdev->mode_info;
 778         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
 779         union pplib_power_state *power_state;
 780         int i;
 781         union pplib_clock_info *clock_info;
 782         union power_info *power_info;
 783         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
 784         u16 data_offset;
 785         u8 frev, crev;
 786         struct igp_ps *ps;
 787
 788         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
 789                                    &frev, &crev, &data_offset))
 790                 return -EINVAL;
 791         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
 792
 793         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
 794                                   power_info->pplib.ucNumStates, GFP_KERNEL);
 795         if (!rdev->pm.dpm.ps)
 796                 return -ENOMEM;
 797         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
 798         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
 799         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
 800
 801         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
 802                 power_state = (union pplib_power_state *)
 803                         (mode_info->atom_context->bios + data_offset +
 804                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
 805                          i * power_info->pplib.ucStateEntrySize);
 806                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
 807                         (mode_info->atom_context->bios + data_offset +
 808                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
 809                          (power_state->v1.ucNonClockStateIndex *
 810                           power_info->pplib.ucNonClockSize));
 811                 if (power_info->pplib.ucStateEntrySize - 1) {
 812                         clock_info = (union pplib_clock_info *)
 813                                 (mode_info->atom_context->bios + data_offset +
 814                                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
 815                                  (power_state->v1.ucClockStateIndices[0] *
 816                                   power_info->pplib.ucClockInfoSize));
 817                         ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL);
 818                         if (ps == NULL) {
 819                                 kfree(rdev->pm.dpm.ps);
 820                                 return -ENOMEM;
 821                         }
 822                         rdev->pm.dpm.ps[i].ps_priv = ps;
 823                         rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
 824                                                          non_clock_info,
 825                                                          power_info->pplib.ucNonClockSize);
 826                         rs780_parse_pplib_clock_info(rdev,
 827                                                      &rdev->pm.dpm.ps[i],
 828                                                      clock_info);
 829                 }
 830         }
 831         rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
 832         return 0;
 833 }
 834
 835 int rs780_dpm_init(struct radeon_device *rdev)
 836 {
 837         struct igp_power_info *pi;
 838         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 839         union igp_info *info;
 840         u16 data_offset;
 841         u8 frev, crev;
 842         int ret;
 843
 844         pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL);
 845         if (pi == NULL)
 846                 return -ENOMEM;
 847         rdev->pm.dpm.priv = pi;
 848
 849         ret = rs780_parse_power_table(rdev);
 850         if (ret)
 851                 return ret;
 852
 853         pi->voltage_control = false;
 854         pi->gfx_clock_gating = true;
 855
 856         if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
 857                                    &frev, &crev, &data_offset)) {
 858                 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
 859
 860                 /* Get various system informations from bios */
 861                 switch (crev) {
 862                 case 1:
 863                         pi->num_of_cycles_in_period =
 864                                 info->info.ucNumberOfCyclesInPeriod;
 865                         pi->num_of_cycles_in_period |=
 866                                 info->info.ucNumberOfCyclesInPeriodHi << 8;
 867                         pi->invert_pwm_required =
 868                                 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
 869                         pi->boot_voltage = info->info.ucStartingPWM_HighTime;
 870                         pi->max_voltage = info->info.ucMaxNBVoltage;
 871                         pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8;
 872                         pi->min_voltage = info->info.ucMinNBVoltage;
 873                         pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8;
 874                         pi->inter_voltage_low =
 875                                 le16_to_cpu(info->info.usInterNBVoltageLow);
 876                         pi->inter_voltage_high =
 877                                 le16_to_cpu(info->info.usInterNBVoltageHigh);
 878                         pi->voltage_control = true;
 879                         pi->bootup_uma_clk = info->info.usK8MemoryClock * 100;
 880                         break;
 881                 case 2:
 882                         pi->num_of_cycles_in_period =
 883                                 le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod);
 884                         pi->invert_pwm_required =
 885                                 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
 886                         pi->boot_voltage =
 887                                 le16_to_cpu(info->info_2.usBootUpNBVoltage);
 888                         pi->max_voltage =
 889                                 le16_to_cpu(info->info_2.usMaxNBVoltage);
 890                         pi->min_voltage =
 891                                 le16_to_cpu(info->info_2.usMinNBVoltage);
 892                         pi->system_config =
 893                                 le32_to_cpu(info->info_2.ulSystemConfig);
 894                         pi->pwm_voltage_control =
 895                                 (pi->system_config & 0x4) ? true : false;
 896                         pi->voltage_control = true;
 897                         pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock);
 898                         break;
 899                 default:
 900                         DRM_ERROR("No integrated system info for your GPU\n");
 901                         return -EINVAL;
 902                 }
 903                 if (pi->min_voltage > pi->max_voltage)
 904                         pi->voltage_control = false;
 905                 if (pi->pwm_voltage_control) {
 906                         if ((pi->num_of_cycles_in_period == 0) ||
 907                             (pi->max_voltage == 0) ||
 908                             (pi->min_voltage == 0))
 909                                 pi->voltage_control = false;
 910                 } else {
 911                         if ((pi->num_of_cycles_in_period == 0) ||
 912                             (pi->max_voltage == 0))
 913                                 pi->voltage_control = false;
 914                 }
 915
 916                 return 0;
 917         }
 918         radeon_dpm_fini(rdev);
 919         return -EINVAL;
 920 }
 921
 922 void rs780_dpm_print_power_state(struct radeon_device *rdev,
 923                                  struct radeon_ps *rps)
 924 {
 925         struct igp_ps *ps = rs780_get_ps(rps);
 926
 927         r600_dpm_print_class_info(rps->class, rps->class2);
 928         r600_dpm_print_cap_info(rps->caps);
 929         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
 930         printk("\t\tpower level 0    sclk: %u vddc_index: %d\n",
 931                ps->sclk_low, ps->min_voltage);
 932         printk("\t\tpower level 1    sclk: %u vddc_index: %d\n",
 933                ps->sclk_high, ps->max_voltage);
 934         r600_dpm_print_ps_status(rdev, rps);
 935 }
 936
 937 void rs780_dpm_fini(struct radeon_device *rdev)
 938 {
 939         int i;
 940
 941         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 942                 kfree(rdev->pm.dpm.ps[i].ps_priv);
 943         }
 944         kfree(rdev->pm.dpm.ps);
 945         kfree(rdev->pm.dpm.priv);
 946 }
 947
 948 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)
 949 {
 950         struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
 951
 952         if (low)
 953                 return requested_state->sclk_low;
 954         else
 955                 return requested_state->sclk_high;
 956 }
 957
 958 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)
 959 {
 960         struct igp_power_info *pi = rs780_get_pi(rdev);
 961
 962         return pi->bootup_uma_clk;
 963 }