2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 /* RS600 / Radeon X1250/X1270 integrated GPU
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
40 #include "radeon_asic.h"
44 #include "rs600_reg_safe.h"
46 static void rs600_gpu_init(struct radeon_device *rdev);
47 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
49 static const u32 crtc_offsets[2] =
52 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
55 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
63 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
77 * avivo_wait_for_vblank - vblank wait asic callback.
79 * @rdev: radeon_device pointer
80 * @crtc: crtc to wait for vblank on
82 * Wait for vblank on the requested crtc (r5xx-r7xx).
84 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
88 if (crtc >= rdev->num_crtc)
91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
94 /* depending on when we hit vblank, we may be close to active; if so,
95 * wait for another frame.
97 while (avivo_is_in_vblank(rdev, crtc)) {
99 if (!avivo_is_counter_moving(rdev, crtc))
104 while (!avivo_is_in_vblank(rdev, crtc)) {
105 if (i++ % 100 == 0) {
106 if (!avivo_is_counter_moving(rdev, crtc))
112 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
114 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
115 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
118 /* Lock the graphics update lock */
119 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
120 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
122 /* update the scanout addresses */
123 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
125 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
128 /* Wait for update_pending to go high. */
129 for (i = 0; i < rdev->usec_timeout; i++) {
130 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
134 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
136 /* Unlock the lock, so double-buffering can take place inside vblank */
137 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
138 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
141 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
143 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
145 /* Return current update_pending status: */
146 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
147 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
150 void avivo_program_fmt(struct drm_encoder *encoder)
152 struct drm_device *dev = encoder->dev;
153 struct radeon_device *rdev = dev->dev_private;
154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
155 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
158 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
161 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
162 bpc = radeon_get_monitor_bpc(connector);
163 dither = radeon_connector->dither;
166 /* LVDS FMT is set up by atom */
167 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
175 if (dither == RADEON_FMT_DITHER_ENABLE)
176 /* XXX sort out optimal dither settings */
177 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
179 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
182 if (dither == RADEON_FMT_DITHER_ENABLE)
183 /* XXX sort out optimal dither settings */
184 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
185 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
187 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
188 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
196 switch (radeon_encoder->encoder_id) {
197 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
198 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
200 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
201 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
203 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
204 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
206 case ENCODER_OBJECT_ID_INTERNAL_DDI:
207 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
214 void rs600_pm_misc(struct radeon_device *rdev)
216 int requested_index = rdev->pm.requested_power_state_index;
217 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
218 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
219 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
220 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
222 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
223 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
224 tmp = RREG32(voltage->gpio.reg);
225 if (voltage->active_high)
226 tmp |= voltage->gpio.mask;
228 tmp &= ~(voltage->gpio.mask);
229 WREG32(voltage->gpio.reg, tmp);
231 udelay(voltage->delay);
233 tmp = RREG32(voltage->gpio.reg);
234 if (voltage->active_high)
235 tmp &= ~voltage->gpio.mask;
237 tmp |= voltage->gpio.mask;
238 WREG32(voltage->gpio.reg, tmp);
240 udelay(voltage->delay);
242 } else if (voltage->type == VOLTAGE_VDDC)
243 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
245 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
246 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
247 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
248 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
249 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
250 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
251 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
252 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
253 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
254 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
257 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
258 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
260 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
262 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
263 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
264 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
265 if (voltage->delay) {
266 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
267 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
269 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
271 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
272 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
274 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
275 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
276 hdp_dyn_cntl &= ~HDP_FORCEON;
278 hdp_dyn_cntl |= HDP_FORCEON;
279 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
281 /* mc_host_dyn seems to cause hangs from time to time */
282 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
283 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
284 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
286 mc_host_dyn_cntl |= MC_HOST_FORCEON;
287 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
289 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
290 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
291 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
293 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
294 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
297 if ((rdev->flags & RADEON_IS_PCIE) &&
298 !(rdev->flags & RADEON_IS_IGP) &&
299 rdev->asic->pm.set_pcie_lanes &&
301 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
302 radeon_set_pcie_lanes(rdev,
304 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
308 void rs600_pm_prepare(struct radeon_device *rdev)
310 struct drm_device *ddev = rdev->ddev;
311 struct drm_crtc *crtc;
312 struct radeon_crtc *radeon_crtc;
315 /* disable any active CRTCs */
316 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
317 radeon_crtc = to_radeon_crtc(crtc);
318 if (radeon_crtc->enabled) {
319 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
320 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
321 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
326 void rs600_pm_finish(struct radeon_device *rdev)
328 struct drm_device *ddev = rdev->ddev;
329 struct drm_crtc *crtc;
330 struct radeon_crtc *radeon_crtc;
333 /* enable any active CRTCs */
334 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
335 radeon_crtc = to_radeon_crtc(crtc);
336 if (radeon_crtc->enabled) {
337 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
338 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
339 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
344 /* hpd for digital panel detect/disconnect */
345 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
348 bool connected = false;
352 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
353 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
357 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
358 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
367 void rs600_hpd_set_polarity(struct radeon_device *rdev,
368 enum radeon_hpd_id hpd)
371 bool connected = rs600_hpd_sense(rdev, hpd);
375 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
377 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
379 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
380 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
383 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
385 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
387 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
388 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
395 void rs600_hpd_init(struct radeon_device *rdev)
397 struct drm_device *dev = rdev->ddev;
398 struct drm_connector *connector;
401 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
402 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
403 switch (radeon_connector->hpd.hpd) {
405 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
406 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
409 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
410 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
415 enable |= 1 << radeon_connector->hpd.hpd;
416 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
418 radeon_irq_kms_enable_hpd(rdev, enable);
421 void rs600_hpd_fini(struct radeon_device *rdev)
423 struct drm_device *dev = rdev->ddev;
424 struct drm_connector *connector;
425 unsigned disable = 0;
427 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
428 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
429 switch (radeon_connector->hpd.hpd) {
431 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
432 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
435 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
436 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
441 disable |= 1 << radeon_connector->hpd.hpd;
443 radeon_irq_kms_disable_hpd(rdev, disable);
446 int rs600_asic_reset(struct radeon_device *rdev)
448 struct rv515_mc_save save;
452 status = RREG32(R_000E40_RBBM_STATUS);
453 if (!G_000E40_GUI_ACTIVE(status)) {
456 /* Stops all mc clients */
457 rv515_mc_stop(rdev, &save);
458 status = RREG32(R_000E40_RBBM_STATUS);
459 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
461 WREG32(RADEON_CP_CSQ_CNTL, 0);
462 tmp = RREG32(RADEON_CP_RB_CNTL);
463 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
464 WREG32(RADEON_CP_RB_RPTR_WR, 0);
465 WREG32(RADEON_CP_RB_WPTR, 0);
466 WREG32(RADEON_CP_RB_CNTL, tmp);
467 pci_save_state(rdev->pdev);
468 /* disable bus mastering */
469 pci_clear_master(rdev->pdev);
472 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
473 S_0000F0_SOFT_RESET_GA(1));
474 RREG32(R_0000F0_RBBM_SOFT_RESET);
476 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
478 status = RREG32(R_000E40_RBBM_STATUS);
479 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
481 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
482 RREG32(R_0000F0_RBBM_SOFT_RESET);
484 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
486 status = RREG32(R_000E40_RBBM_STATUS);
487 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
489 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
490 RREG32(R_0000F0_RBBM_SOFT_RESET);
492 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
494 status = RREG32(R_000E40_RBBM_STATUS);
495 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
496 /* restore PCI & busmastering */
497 pci_restore_state(rdev->pdev);
498 /* Check if GPU is idle */
499 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
500 dev_err(rdev->dev, "failed to reset GPU\n");
503 dev_info(rdev->dev, "GPU reset succeed\n");
504 rv515_mc_resume(rdev, &save);
511 void rs600_gart_tlb_flush(struct radeon_device *rdev)
515 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
516 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
517 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
519 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
520 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
521 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
523 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
524 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
525 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
526 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
529 static int rs600_gart_init(struct radeon_device *rdev)
533 if (rdev->gart.robj) {
534 WARN(1, "RS600 GART already initialized\n");
537 /* Initialize common gart structure */
538 r = radeon_gart_init(rdev);
542 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
543 return radeon_gart_table_vram_alloc(rdev);
546 static int rs600_gart_enable(struct radeon_device *rdev)
551 if (rdev->gart.robj == NULL) {
552 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
555 r = radeon_gart_table_vram_pin(rdev);
558 /* Enable bus master */
559 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
560 WREG32(RADEON_BUS_CNTL, tmp);
561 /* FIXME: setup default page */
562 WREG32_MC(R_000100_MC_PT0_CNTL,
563 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
564 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
566 for (i = 0; i < 19; i++) {
567 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
568 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
569 S_00016C_SYSTEM_ACCESS_MODE_MASK(
570 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
571 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
572 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
573 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
574 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
575 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
577 /* enable first context */
578 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
579 S_000102_ENABLE_PAGE_TABLE(1) |
580 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
582 /* disable all other contexts */
583 for (i = 1; i < 8; i++)
584 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
586 /* setup the page table */
587 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
588 rdev->gart.table_addr);
589 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
590 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
591 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
593 /* System context maps to VRAM space */
594 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
595 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
597 /* enable page tables */
598 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
599 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
600 tmp = RREG32_MC(R_000009_MC_CNTL1);
601 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
602 rs600_gart_tlb_flush(rdev);
603 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
604 (unsigned)(rdev->mc.gtt_size >> 20),
605 (unsigned long long)rdev->gart.table_addr);
606 rdev->gart.ready = true;
610 static void rs600_gart_disable(struct radeon_device *rdev)
614 /* FIXME: disable out of gart access */
615 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
616 tmp = RREG32_MC(R_000009_MC_CNTL1);
617 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
618 radeon_gart_table_vram_unpin(rdev);
621 static void rs600_gart_fini(struct radeon_device *rdev)
623 radeon_gart_fini(rdev);
624 rs600_gart_disable(rdev);
625 radeon_gart_table_vram_free(rdev);
628 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
629 uint64_t addr, uint32_t flags)
631 void __iomem *ptr = (void *)rdev->gart.ptr;
633 addr = addr & 0xFFFFFFFFFFFFF000ULL;
634 addr |= R600_PTE_SYSTEM;
635 if (flags & RADEON_GART_PAGE_VALID)
636 addr |= R600_PTE_VALID;
637 if (flags & RADEON_GART_PAGE_READ)
638 addr |= R600_PTE_READABLE;
639 if (flags & RADEON_GART_PAGE_WRITE)
640 addr |= R600_PTE_WRITEABLE;
641 if (flags & RADEON_GART_PAGE_SNOOP)
642 addr |= R600_PTE_SNOOPED;
643 writeq(addr, ptr + (i * 8));
646 int rs600_irq_set(struct radeon_device *rdev)
649 uint32_t mode_int = 0;
650 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
651 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
652 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
653 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
655 if (ASIC_IS_DCE2(rdev))
656 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
657 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
661 if (!rdev->irq.installed) {
662 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
663 WREG32(R_000040_GEN_INT_CNTL, 0);
666 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
667 tmp |= S_000040_SW_INT_EN(1);
669 if (rdev->irq.crtc_vblank_int[0] ||
670 atomic_read(&rdev->irq.pflip[0])) {
671 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
673 if (rdev->irq.crtc_vblank_int[1] ||
674 atomic_read(&rdev->irq.pflip[1])) {
675 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
677 if (rdev->irq.hpd[0]) {
678 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
680 if (rdev->irq.hpd[1]) {
681 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
683 if (rdev->irq.afmt[0]) {
684 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
686 WREG32(R_000040_GEN_INT_CNTL, tmp);
687 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
688 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
689 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
690 if (ASIC_IS_DCE2(rdev))
691 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
695 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
697 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
698 uint32_t irq_mask = S_000044_SW_INT(1);
701 if (G_000044_DISPLAY_INT_STAT(irqs)) {
702 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
703 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
704 WREG32(R_006534_D1MODE_VBLANK_STATUS,
705 S_006534_D1MODE_VBLANK_ACK(1));
707 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
708 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
709 S_006D34_D2MODE_VBLANK_ACK(1));
711 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
712 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
713 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
714 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
716 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
717 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
718 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
719 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
722 rdev->irq.stat_regs.r500.disp_int = 0;
725 if (ASIC_IS_DCE2(rdev)) {
726 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
727 S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
728 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
729 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
730 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
731 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
734 rdev->irq.stat_regs.r500.hdmi0_status = 0;
737 WREG32(R_000044_GEN_INT_STATUS, irqs);
739 return irqs & irq_mask;
742 void rs600_irq_disable(struct radeon_device *rdev)
744 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
745 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
746 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
747 WREG32(R_000040_GEN_INT_CNTL, 0);
748 WREG32(R_006540_DxMODE_INT_MASK, 0);
749 /* Wait and acknowledge irq */
754 int rs600_irq_process(struct radeon_device *rdev)
756 u32 status, msi_rearm;
757 bool queue_hotplug = false;
758 bool queue_hdmi = false;
760 status = rs600_irq_ack(rdev);
762 !rdev->irq.stat_regs.r500.disp_int &&
763 !rdev->irq.stat_regs.r500.hdmi0_status) {
767 rdev->irq.stat_regs.r500.disp_int ||
768 rdev->irq.stat_regs.r500.hdmi0_status) {
770 if (G_000044_SW_INT(status)) {
771 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
773 /* Vertical blank interrupts */
774 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
775 if (rdev->irq.crtc_vblank_int[0]) {
776 drm_handle_vblank(rdev->ddev, 0);
777 rdev->pm.vblank_sync = true;
778 wake_up(&rdev->irq.vblank_queue);
780 if (atomic_read(&rdev->irq.pflip[0]))
781 radeon_crtc_handle_vblank(rdev, 0);
783 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
784 if (rdev->irq.crtc_vblank_int[1]) {
785 drm_handle_vblank(rdev->ddev, 1);
786 rdev->pm.vblank_sync = true;
787 wake_up(&rdev->irq.vblank_queue);
789 if (atomic_read(&rdev->irq.pflip[1]))
790 radeon_crtc_handle_vblank(rdev, 1);
792 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
793 queue_hotplug = true;
796 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
797 queue_hotplug = true;
800 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
802 DRM_DEBUG("HDMI0\n");
804 status = rs600_irq_ack(rdev);
807 schedule_work(&rdev->hotplug_work);
809 schedule_work(&rdev->audio_work);
810 if (rdev->msi_enabled) {
811 switch (rdev->family) {
815 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
816 WREG32(RADEON_BUS_CNTL, msi_rearm);
817 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
820 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
827 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
830 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
832 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
835 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
839 for (i = 0; i < rdev->usec_timeout; i++) {
840 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
847 static void rs600_gpu_init(struct radeon_device *rdev)
849 r420_pipes_init(rdev);
850 /* Wait for mc idle */
851 if (rs600_mc_wait_for_idle(rdev))
852 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
855 static void rs600_mc_init(struct radeon_device *rdev)
859 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
860 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
861 rdev->mc.vram_is_ddr = true;
862 rdev->mc.vram_width = 128;
863 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
864 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
865 rdev->mc.visible_vram_size = rdev->mc.aper_size;
866 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
867 base = RREG32_MC(R_000004_MC_FB_LOCATION);
868 base = G_000004_MC_FB_START(base) << 16;
869 radeon_vram_location(rdev, &rdev->mc, base);
870 rdev->mc.gtt_base_align = 0;
871 radeon_gtt_location(rdev, &rdev->mc);
872 radeon_update_bandwidth_info(rdev);
875 void rs600_bandwidth_update(struct radeon_device *rdev)
877 struct drm_display_mode *mode0 = NULL;
878 struct drm_display_mode *mode1 = NULL;
879 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
880 /* FIXME: implement full support */
882 radeon_update_display_priority(rdev);
884 if (rdev->mode_info.crtcs[0]->base.enabled)
885 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
886 if (rdev->mode_info.crtcs[1]->base.enabled)
887 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
889 rs690_line_buffer_adjust(rdev, mode0, mode1);
891 if (rdev->disp_priority == 2) {
892 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
893 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
894 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
895 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
896 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
897 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
898 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
899 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
903 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
908 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
909 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
910 S_000070_MC_IND_CITF_ARB0(1));
911 r = RREG32(R_000074_MC_IND_DATA);
912 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
916 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
920 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
921 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
922 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
923 WREG32(R_000074_MC_IND_DATA, v);
924 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
927 static void rs600_debugfs(struct radeon_device *rdev)
929 if (r100_debugfs_rbbm_init(rdev))
930 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
933 void rs600_set_safe_registers(struct radeon_device *rdev)
935 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
936 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
939 static void rs600_mc_program(struct radeon_device *rdev)
941 struct rv515_mc_save save;
943 /* Stops all mc clients */
944 rv515_mc_stop(rdev, &save);
946 /* Wait for mc idle */
947 if (rs600_mc_wait_for_idle(rdev))
948 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
950 /* FIXME: What does AGP means for such chipset ? */
951 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
952 WREG32_MC(R_000006_AGP_BASE, 0);
953 WREG32_MC(R_000007_AGP_BASE_2, 0);
955 WREG32_MC(R_000004_MC_FB_LOCATION,
956 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
957 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
958 WREG32(R_000134_HDP_FB_LOCATION,
959 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
961 rv515_mc_resume(rdev, &save);
964 static int rs600_startup(struct radeon_device *rdev)
968 rs600_mc_program(rdev);
970 rv515_clock_startup(rdev);
971 /* Initialize GPU configuration (# pipes, ...) */
972 rs600_gpu_init(rdev);
973 /* Initialize GART (initialize after TTM so we can allocate
974 * memory through TTM but finalize after TTM) */
975 r = rs600_gart_enable(rdev);
979 /* allocate wb buffer */
980 r = radeon_wb_init(rdev);
984 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
986 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
991 if (!rdev->irq.installed) {
992 r = radeon_irq_kms_init(rdev);
998 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1000 r = r100_cp_init(rdev, 1024 * 1024);
1002 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1006 r = radeon_ib_pool_init(rdev);
1008 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1012 r = r600_audio_init(rdev);
1014 dev_err(rdev->dev, "failed initializing audio\n");
1021 int rs600_resume(struct radeon_device *rdev)
1025 /* Make sur GART are not working */
1026 rs600_gart_disable(rdev);
1027 /* Resume clock before doing reset */
1028 rv515_clock_startup(rdev);
1029 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1030 if (radeon_asic_reset(rdev)) {
1031 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1032 RREG32(R_000E40_RBBM_STATUS),
1033 RREG32(R_0007C0_CP_STAT));
1036 atom_asic_init(rdev->mode_info.atom_context);
1037 /* Resume clock after posting */
1038 rv515_clock_startup(rdev);
1039 /* Initialize surface registers */
1040 radeon_surface_init(rdev);
1042 rdev->accel_working = true;
1043 r = rs600_startup(rdev);
1045 rdev->accel_working = false;
1050 int rs600_suspend(struct radeon_device *rdev)
1052 radeon_pm_suspend(rdev);
1053 r600_audio_fini(rdev);
1054 r100_cp_disable(rdev);
1055 radeon_wb_disable(rdev);
1056 rs600_irq_disable(rdev);
1057 rs600_gart_disable(rdev);
1061 void rs600_fini(struct radeon_device *rdev)
1063 radeon_pm_fini(rdev);
1064 r600_audio_fini(rdev);
1066 radeon_wb_fini(rdev);
1067 radeon_ib_pool_fini(rdev);
1068 radeon_gem_fini(rdev);
1069 rs600_gart_fini(rdev);
1070 radeon_irq_kms_fini(rdev);
1071 radeon_fence_driver_fini(rdev);
1072 radeon_bo_fini(rdev);
1073 radeon_atombios_fini(rdev);
1078 int rs600_init(struct radeon_device *rdev)
1083 rv515_vga_render_disable(rdev);
1084 /* Initialize scratch registers */
1085 radeon_scratch_init(rdev);
1086 /* Initialize surface registers */
1087 radeon_surface_init(rdev);
1088 /* restore some register to sane defaults */
1089 r100_restore_sanity(rdev);
1091 if (!radeon_get_bios(rdev)) {
1092 if (ASIC_IS_AVIVO(rdev))
1095 if (rdev->is_atom_bios) {
1096 r = radeon_atombios_init(rdev);
1100 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1103 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1104 if (radeon_asic_reset(rdev)) {
1106 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1107 RREG32(R_000E40_RBBM_STATUS),
1108 RREG32(R_0007C0_CP_STAT));
1110 /* check if cards are posted or not */
1111 if (radeon_boot_test_post_card(rdev) == false)
1114 /* Initialize clocks */
1115 radeon_get_clock_info(rdev->ddev);
1116 /* initialize memory controller */
1117 rs600_mc_init(rdev);
1118 rs600_debugfs(rdev);
1120 r = radeon_fence_driver_init(rdev);
1123 /* Memory manager */
1124 r = radeon_bo_init(rdev);
1127 r = rs600_gart_init(rdev);
1130 rs600_set_safe_registers(rdev);
1132 /* Initialize power management */
1133 radeon_pm_init(rdev);
1135 rdev->accel_working = true;
1136 r = rs600_startup(rdev);
1138 /* Somethings want wront with the accel init stop accel */
1139 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1141 radeon_wb_fini(rdev);
1142 radeon_ib_pool_fini(rdev);
1143 rs600_gart_fini(rdev);
1144 radeon_irq_kms_fini(rdev);
1145 rdev->accel_working = false;