drivers/gpu/drm/radeon/rs600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 /* RS600 / Radeon X1250/X1270 integrated GPU
  29  *
  30  * This file gather function specific to RS600 which is the IGP of
  31  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33  * the avivo one, bios is an atombios, 3D block are the one of the
  34  * R4XX family. The GART is different from the RS400 one and is very
  35  * close to the one of the R600 family (R600 likely being an evolution
  36  * of the RS600 GART block).
  37  */
  38 #include <drm/drmP.h>
  39 #include "radeon.h"
  40 #include "radeon_asic.h"
  41 #include "atom.h"
  42 #include "rs600d.h"
  43
  44 #include "rs600_reg_safe.h"
  45
  46 static void rs600_gpu_init(struct radeon_device *rdev);
  47 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  48
  49 static const u32 crtc_offsets[2] =
  50 {
  51         0,
  52         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  53 };
  54
  55 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
  56 {
  57         int i;
  58
  59         if (crtc >= rdev->num_crtc)
  60                 return;
  61
  62         if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) {
  63                 for (i = 0; i < rdev->usec_timeout; i++) {
  64                         if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK))
  65                                 break;
  66                         udelay(1);
  67                 }
  68                 for (i = 0; i < rdev->usec_timeout; i++) {
  69                         if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
  70                                 break;
  71                         udelay(1);
  72                 }
  73         }
  74 }
  75
  76 void rs600_pre_page_flip(struct radeon_device *rdev, int crtc)
  77 {
  78         /* enable the pflip int */
  79         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  80 }
  81
  82 void rs600_post_page_flip(struct radeon_device *rdev, int crtc)
  83 {
  84         /* disable the pflip int */
  85         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  86 }
  87
  88 u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  89 {
  90         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  91         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
  92         int i;
  93
  94         /* Lock the graphics update lock */
  95         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  96         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  97
  98         /* update the scanout addresses */
  99         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 100                (u32)crtc_base);
 101         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 102                (u32)crtc_base);
 103
 104         /* Wait for update_pending to go high. */
 105         for (i = 0; i < rdev->usec_timeout; i++) {
 106                 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
 107                         break;
 108                 udelay(1);
 109         }
 110         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 111
 112         /* Unlock the lock, so double-buffering can take place inside vblank */
 113         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
 114         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 115
 116         /* Return current update_pending status: */
 117         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
 118 }
 119
 120 void rs600_pm_misc(struct radeon_device *rdev)
 121 {
 122         int requested_index = rdev->pm.requested_power_state_index;
 123         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 124         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 125         u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
 126         u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
 127
 128         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 129                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 130                         tmp = RREG32(voltage->gpio.reg);
 131                         if (voltage->active_high)
 132                                 tmp |= voltage->gpio.mask;
 133                         else
 134                                 tmp &= ~(voltage->gpio.mask);
 135                         WREG32(voltage->gpio.reg, tmp);
 136                         if (voltage->delay)
 137                                 udelay(voltage->delay);
 138                 } else {
 139                         tmp = RREG32(voltage->gpio.reg);
 140                         if (voltage->active_high)
 141                                 tmp &= ~voltage->gpio.mask;
 142                         else
 143                                 tmp |= voltage->gpio.mask;
 144                         WREG32(voltage->gpio.reg, tmp);
 145                         if (voltage->delay)
 146                                 udelay(voltage->delay);
 147                 }
 148         } else if (voltage->type == VOLTAGE_VDDC)
 149                 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
 150
 151         dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
 152         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
 153         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
 154         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 155                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
 156                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
 157                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
 158                 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
 159                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
 160                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
 161                 }
 162         } else {
 163                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
 164                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
 165         }
 166         WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
 167
 168         dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
 169         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 170                 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
 171                 if (voltage->delay) {
 172                         dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
 173                         dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
 174                 } else
 175                         dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
 176         } else
 177                 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
 178         WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
 179
 180         hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
 181         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 182                 hdp_dyn_cntl &= ~HDP_FORCEON;
 183         else
 184                 hdp_dyn_cntl |= HDP_FORCEON;
 185         WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
 186 #if 0
 187         /* mc_host_dyn seems to cause hangs from time to time */
 188         mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
 189         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
 190                 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
 191         else
 192                 mc_host_dyn_cntl |= MC_HOST_FORCEON;
 193         WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
 194 #endif
 195         dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
 196         if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
 197                 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
 198         else
 199                 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
 200         WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
 201
 202         /* set pcie lanes */
 203         if ((rdev->flags & RADEON_IS_PCIE) &&
 204             !(rdev->flags & RADEON_IS_IGP) &&
 205             rdev->asic->pm.set_pcie_lanes &&
 206             (ps->pcie_lanes !=
 207              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 208                 radeon_set_pcie_lanes(rdev,
 209                                       ps->pcie_lanes);
 210                 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
 211         }
 212 }
 213
 214 void rs600_pm_prepare(struct radeon_device *rdev)
 215 {
 216         struct drm_device *ddev = rdev->ddev;
 217         struct drm_crtc *crtc;
 218         struct radeon_crtc *radeon_crtc;
 219         u32 tmp;
 220
 221         /* disable any active CRTCs */
 222         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 223                 radeon_crtc = to_radeon_crtc(crtc);
 224                 if (radeon_crtc->enabled) {
 225                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 226                         tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 227                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 228                 }
 229         }
 230 }
 231
 232 void rs600_pm_finish(struct radeon_device *rdev)
 233 {
 234         struct drm_device *ddev = rdev->ddev;
 235         struct drm_crtc *crtc;
 236         struct radeon_crtc *radeon_crtc;
 237         u32 tmp;
 238
 239         /* enable any active CRTCs */
 240         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 241                 radeon_crtc = to_radeon_crtc(crtc);
 242                 if (radeon_crtc->enabled) {
 243                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 244                         tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 245                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 246                 }
 247         }
 248 }
 249
 250 /* hpd for digital panel detect/disconnect */
 251 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 252 {
 253         u32 tmp;
 254         bool connected = false;
 255
 256         switch (hpd) {
 257         case RADEON_HPD_1:
 258                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
 259                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
 260                         connected = true;
 261                 break;
 262         case RADEON_HPD_2:
 263                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
 264                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
 265                         connected = true;
 266                 break;
 267         default:
 268                 break;
 269         }
 270         return connected;
 271 }
 272
 273 void rs600_hpd_set_polarity(struct radeon_device *rdev,
 274                             enum radeon_hpd_id hpd)
 275 {
 276         u32 tmp;
 277         bool connected = rs600_hpd_sense(rdev, hpd);
 278
 279         switch (hpd) {
 280         case RADEON_HPD_1:
 281                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 282                 if (connected)
 283                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 284                 else
 285                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 286                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 287                 break;
 288         case RADEON_HPD_2:
 289                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 290                 if (connected)
 291                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 292                 else
 293                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 294                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 295                 break;
 296         default:
 297                 break;
 298         }
 299 }
 300
 301 void rs600_hpd_init(struct radeon_device *rdev)
 302 {
 303         struct drm_device *dev = rdev->ddev;
 304         struct drm_connector *connector;
 305         unsigned enable = 0;
 306
 307         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 308                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 309                 switch (radeon_connector->hpd.hpd) {
 310                 case RADEON_HPD_1:
 311                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 312                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
 313                         break;
 314                 case RADEON_HPD_2:
 315                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 316                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
 317                         break;
 318                 default:
 319                         break;
 320                 }
 321                 enable |= 1 << radeon_connector->hpd.hpd;
 322                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 323         }
 324         radeon_irq_kms_enable_hpd(rdev, enable);
 325 }
 326
 327 void rs600_hpd_fini(struct radeon_device *rdev)
 328 {
 329         struct drm_device *dev = rdev->ddev;
 330         struct drm_connector *connector;
 331         unsigned disable = 0;
 332
 333         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 334                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 335                 switch (radeon_connector->hpd.hpd) {
 336                 case RADEON_HPD_1:
 337                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 338                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
 339                         break;
 340                 case RADEON_HPD_2:
 341                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 342                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
 343                         break;
 344                 default:
 345                         break;
 346                 }
 347                 disable |= 1 << radeon_connector->hpd.hpd;
 348         }
 349         radeon_irq_kms_disable_hpd(rdev, disable);
 350 }
 351
 352 int rs600_asic_reset(struct radeon_device *rdev)
 353 {
 354         struct rv515_mc_save save;
 355         u32 status, tmp;
 356         int ret = 0;
 357
 358         status = RREG32(R_000E40_RBBM_STATUS);
 359         if (!G_000E40_GUI_ACTIVE(status)) {
 360                 return 0;
 361         }
 362         /* Stops all mc clients */
 363         rv515_mc_stop(rdev, &save);
 364         status = RREG32(R_000E40_RBBM_STATUS);
 365         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 366         /* stop CP */
 367         WREG32(RADEON_CP_CSQ_CNTL, 0);
 368         tmp = RREG32(RADEON_CP_RB_CNTL);
 369         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 370         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 371         WREG32(RADEON_CP_RB_WPTR, 0);
 372         WREG32(RADEON_CP_RB_CNTL, tmp);
 373         pci_save_state(rdev->pdev);
 374         /* disable bus mastering */
 375         pci_clear_master(rdev->pdev);
 376         mdelay(1);
 377         /* reset GA+VAP */
 378         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 379                                         S_0000F0_SOFT_RESET_GA(1));
 380         RREG32(R_0000F0_RBBM_SOFT_RESET);
 381         mdelay(500);
 382         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 383         mdelay(1);
 384         status = RREG32(R_000E40_RBBM_STATUS);
 385         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 386         /* reset CP */
 387         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 388         RREG32(R_0000F0_RBBM_SOFT_RESET);
 389         mdelay(500);
 390         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 391         mdelay(1);
 392         status = RREG32(R_000E40_RBBM_STATUS);
 393         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 394         /* reset MC */
 395         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
 396         RREG32(R_0000F0_RBBM_SOFT_RESET);
 397         mdelay(500);
 398         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 399         mdelay(1);
 400         status = RREG32(R_000E40_RBBM_STATUS);
 401         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 402         /* restore PCI & busmastering */
 403         pci_restore_state(rdev->pdev);
 404         /* Check if GPU is idle */
 405         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 406                 dev_err(rdev->dev, "failed to reset GPU\n");
 407                 ret = -1;
 408         } else
 409                 dev_info(rdev->dev, "GPU reset succeed\n");
 410         rv515_mc_resume(rdev, &save);
 411         return ret;
 412 }
 413
 414 /*
 415  * GART.
 416  */
 417 void rs600_gart_tlb_flush(struct radeon_device *rdev)
 418 {
 419         uint32_t tmp;
 420
 421         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 422         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 423         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 424
 425         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 426         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
 427         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 428
 429         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 430         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 431         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 432         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 433 }
 434
 435 static int rs600_gart_init(struct radeon_device *rdev)
 436 {
 437         int r;
 438
 439         if (rdev->gart.robj) {
 440                 WARN(1, "RS600 GART already initialized\n");
 441                 return 0;
 442         }
 443         /* Initialize common gart structure */
 444         r = radeon_gart_init(rdev);
 445         if (r) {
 446                 return r;
 447         }
 448         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 449         return radeon_gart_table_vram_alloc(rdev);
 450 }
 451
 452 static int rs600_gart_enable(struct radeon_device *rdev)
 453 {
 454         u32 tmp;
 455         int r, i;
 456
 457         if (rdev->gart.robj == NULL) {
 458                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 459                 return -EINVAL;
 460         }
 461         r = radeon_gart_table_vram_pin(rdev);
 462         if (r)
 463                 return r;
 464         radeon_gart_restore(rdev);
 465         /* Enable bus master */
 466         tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 467         WREG32(RADEON_BUS_CNTL, tmp);
 468         /* FIXME: setup default page */
 469         WREG32_MC(R_000100_MC_PT0_CNTL,
 470                   (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
 471                    S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
 472
 473         for (i = 0; i < 19; i++) {
 474                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
 475                           S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
 476                           S_00016C_SYSTEM_ACCESS_MODE_MASK(
 477                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
 478                           S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
 479                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
 480                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
 481                           S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
 482                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
 483         }
 484         /* enable first context */
 485         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
 486                   S_000102_ENABLE_PAGE_TABLE(1) |
 487                   S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
 488
 489         /* disable all other contexts */
 490         for (i = 1; i < 8; i++)
 491                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
 492
 493         /* setup the page table */
 494         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 495                   rdev->gart.table_addr);
 496         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
 497         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
 498         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 499
 500         /* System context maps to VRAM space */
 501         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
 502         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
 503
 504         /* enable page tables */
 505         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 506         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
 507         tmp = RREG32_MC(R_000009_MC_CNTL1);
 508         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
 509         rs600_gart_tlb_flush(rdev);
 510         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 511                  (unsigned)(rdev->mc.gtt_size >> 20),
 512                  (unsigned long long)rdev->gart.table_addr);
 513         rdev->gart.ready = true;
 514         return 0;
 515 }
 516
 517 static void rs600_gart_disable(struct radeon_device *rdev)
 518 {
 519         u32 tmp;
 520
 521         /* FIXME: disable out of gart access */
 522         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
 523         tmp = RREG32_MC(R_000009_MC_CNTL1);
 524         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
 525         radeon_gart_table_vram_unpin(rdev);
 526 }
 527
 528 static void rs600_gart_fini(struct radeon_device *rdev)
 529 {
 530         radeon_gart_fini(rdev);
 531         rs600_gart_disable(rdev);
 532         radeon_gart_table_vram_free(rdev);
 533 }
 534
 535 #define R600_PTE_VALID     (1 << 0)
 536 #define R600_PTE_SYSTEM    (1 << 1)
 537 #define R600_PTE_SNOOPED   (1 << 2)
 538 #define R600_PTE_READABLE  (1 << 5)
 539 #define R600_PTE_WRITEABLE (1 << 6)
 540
 541 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 542 {
 543         void __iomem *ptr = (void *)rdev->gart.ptr;
 544
 545         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 546                 return -EINVAL;
 547         }
 548         addr = addr & 0xFFFFFFFFFFFFF000ULL;
 549         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 550         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 551         writeq(addr, ptr + (i * 8));
 552         return 0;
 553 }
 554
 555 int rs600_irq_set(struct radeon_device *rdev)
 556 {
 557         uint32_t tmp = 0;
 558         uint32_t mode_int = 0;
 559         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
 560                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 561         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
 562                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 563         u32 hdmi0;
 564         if (ASIC_IS_DCE2(rdev))
 565                 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
 566                         ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 567         else
 568                 hdmi0 = 0;
 569
 570         if (!rdev->irq.installed) {
 571                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 572                 WREG32(R_000040_GEN_INT_CNTL, 0);
 573                 return -EINVAL;
 574         }
 575         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 576                 tmp |= S_000040_SW_INT_EN(1);
 577         }
 578         if (rdev->irq.crtc_vblank_int[0] ||
 579             atomic_read(&rdev->irq.pflip[0])) {
 580                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
 581         }
 582         if (rdev->irq.crtc_vblank_int[1] ||
 583             atomic_read(&rdev->irq.pflip[1])) {
 584                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
 585         }
 586         if (rdev->irq.hpd[0]) {
 587                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 588         }
 589         if (rdev->irq.hpd[1]) {
 590                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 591         }
 592         if (rdev->irq.afmt[0]) {
 593                 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 594         }
 595         WREG32(R_000040_GEN_INT_CNTL, tmp);
 596         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
 597         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
 598         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
 599         if (ASIC_IS_DCE2(rdev))
 600                 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 601         return 0;
 602 }
 603
 604 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
 605 {
 606         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
 607         uint32_t irq_mask = S_000044_SW_INT(1);
 608         u32 tmp;
 609
 610         if (G_000044_DISPLAY_INT_STAT(irqs)) {
 611                 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
 612                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 613                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
 614                                 S_006534_D1MODE_VBLANK_ACK(1));
 615                 }
 616                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 617                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
 618                                 S_006D34_D2MODE_VBLANK_ACK(1));
 619                 }
 620                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 621                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 622                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
 623                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 624                 }
 625                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 626                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 627                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
 628                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 629                 }
 630         } else {
 631                 rdev->irq.stat_regs.r500.disp_int = 0;
 632         }
 633
 634         if (ASIC_IS_DCE2(rdev)) {
 635                 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
 636                         S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
 637                 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
 638                         tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
 639                         tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
 640                         WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
 641                 }
 642         } else
 643                 rdev->irq.stat_regs.r500.hdmi0_status = 0;
 644
 645         if (irqs) {
 646                 WREG32(R_000044_GEN_INT_STATUS, irqs);
 647         }
 648         return irqs & irq_mask;
 649 }
 650
 651 void rs600_irq_disable(struct radeon_device *rdev)
 652 {
 653         u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
 654                 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 655         WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 656         WREG32(R_000040_GEN_INT_CNTL, 0);
 657         WREG32(R_006540_DxMODE_INT_MASK, 0);
 658         /* Wait and acknowledge irq */
 659         mdelay(1);
 660         rs600_irq_ack(rdev);
 661 }
 662
 663 int rs600_irq_process(struct radeon_device *rdev)
 664 {
 665         u32 status, msi_rearm;
 666         bool queue_hotplug = false;
 667         bool queue_hdmi = false;
 668
 669         status = rs600_irq_ack(rdev);
 670         if (!status &&
 671             !rdev->irq.stat_regs.r500.disp_int &&
 672             !rdev->irq.stat_regs.r500.hdmi0_status) {
 673                 return IRQ_NONE;
 674         }
 675         while (status ||
 676                rdev->irq.stat_regs.r500.disp_int ||
 677                rdev->irq.stat_regs.r500.hdmi0_status) {
 678                 /* SW interrupt */
 679                 if (G_000044_SW_INT(status)) {
 680                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 681                 }
 682                 /* Vertical blank interrupts */
 683                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 684                         if (rdev->irq.crtc_vblank_int[0]) {
 685                                 drm_handle_vblank(rdev->ddev, 0);
 686                                 rdev->pm.vblank_sync = true;
 687                                 wake_up(&rdev->irq.vblank_queue);
 688                         }
 689                         if (atomic_read(&rdev->irq.pflip[0]))
 690                                 radeon_crtc_handle_flip(rdev, 0);
 691                 }
 692                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 693                         if (rdev->irq.crtc_vblank_int[1]) {
 694                                 drm_handle_vblank(rdev->ddev, 1);
 695                                 rdev->pm.vblank_sync = true;
 696                                 wake_up(&rdev->irq.vblank_queue);
 697                         }
 698                         if (atomic_read(&rdev->irq.pflip[1]))
 699                                 radeon_crtc_handle_flip(rdev, 1);
 700                 }
 701                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 702                         queue_hotplug = true;
 703                         DRM_DEBUG("HPD1\n");
 704                 }
 705                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 706                         queue_hotplug = true;
 707                         DRM_DEBUG("HPD2\n");
 708                 }
 709                 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
 710                         queue_hdmi = true;
 711                         DRM_DEBUG("HDMI0\n");
 712                 }
 713                 status = rs600_irq_ack(rdev);
 714         }
 715         if (queue_hotplug)
 716                 schedule_work(&rdev->hotplug_work);
 717         if (queue_hdmi)
 718                 schedule_work(&rdev->audio_work);
 719         if (rdev->msi_enabled) {
 720                 switch (rdev->family) {
 721                 case CHIP_RS600:
 722                 case CHIP_RS690:
 723                 case CHIP_RS740:
 724                         msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
 725                         WREG32(RADEON_BUS_CNTL, msi_rearm);
 726                         WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
 727                         break;
 728                 default:
 729                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 730                         break;
 731                 }
 732         }
 733         return IRQ_HANDLED;
 734 }
 735
 736 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
 737 {
 738         if (crtc == 0)
 739                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
 740         else
 741                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
 742 }
 743
 744 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
 745 {
 746         unsigned i;
 747
 748         for (i = 0; i < rdev->usec_timeout; i++) {
 749                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
 750                         return 0;
 751                 udelay(1);
 752         }
 753         return -1;
 754 }
 755
 756 static void rs600_gpu_init(struct radeon_device *rdev)
 757 {
 758         r420_pipes_init(rdev);
 759         /* Wait for mc idle */
 760         if (rs600_mc_wait_for_idle(rdev))
 761                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 762 }
 763
 764 static void rs600_mc_init(struct radeon_device *rdev)
 765 {
 766         u64 base;
 767
 768         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
 769         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
 770         rdev->mc.vram_is_ddr = true;
 771         rdev->mc.vram_width = 128;
 772         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 773         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 774         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 775         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 776         base = RREG32_MC(R_000004_MC_FB_LOCATION);
 777         base = G_000004_MC_FB_START(base) << 16;
 778         radeon_vram_location(rdev, &rdev->mc, base);
 779         rdev->mc.gtt_base_align = 0;
 780         radeon_gtt_location(rdev, &rdev->mc);
 781         radeon_update_bandwidth_info(rdev);
 782 }
 783
 784 void rs600_bandwidth_update(struct radeon_device *rdev)
 785 {
 786         struct drm_display_mode *mode0 = NULL;
 787         struct drm_display_mode *mode1 = NULL;
 788         u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
 789         /* FIXME: implement full support */
 790
 791         radeon_update_display_priority(rdev);
 792
 793         if (rdev->mode_info.crtcs[0]->base.enabled)
 794                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 795         if (rdev->mode_info.crtcs[1]->base.enabled)
 796                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 797
 798         rs690_line_buffer_adjust(rdev, mode0, mode1);
 799
 800         if (rdev->disp_priority == 2) {
 801                 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
 802                 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
 803                 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 804                 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 805                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 806                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 807                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 808                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 809         }
 810 }
 811
 812 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 813 {
 814         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 815                 S_000070_MC_IND_CITF_ARB0(1));
 816         return RREG32(R_000074_MC_IND_DATA);
 817 }
 818
 819 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 820 {
 821         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 822                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
 823         WREG32(R_000074_MC_IND_DATA, v);
 824 }
 825
 826 static void rs600_debugfs(struct radeon_device *rdev)
 827 {
 828         if (r100_debugfs_rbbm_init(rdev))
 829                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 830 }
 831
 832 void rs600_set_safe_registers(struct radeon_device *rdev)
 833 {
 834         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
 835         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
 836 }
 837
 838 static void rs600_mc_program(struct radeon_device *rdev)
 839 {
 840         struct rv515_mc_save save;
 841
 842         /* Stops all mc clients */
 843         rv515_mc_stop(rdev, &save);
 844
 845         /* Wait for mc idle */
 846         if (rs600_mc_wait_for_idle(rdev))
 847                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 848
 849         /* FIXME: What does AGP means for such chipset ? */
 850         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
 851         WREG32_MC(R_000006_AGP_BASE, 0);
 852         WREG32_MC(R_000007_AGP_BASE_2, 0);
 853         /* Program MC */
 854         WREG32_MC(R_000004_MC_FB_LOCATION,
 855                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
 856                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
 857         WREG32(R_000134_HDP_FB_LOCATION,
 858                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 859
 860         rv515_mc_resume(rdev, &save);
 861 }
 862
 863 static int rs600_startup(struct radeon_device *rdev)
 864 {
 865         int r;
 866
 867         rs600_mc_program(rdev);
 868         /* Resume clock */
 869         rv515_clock_startup(rdev);
 870         /* Initialize GPU configuration (# pipes, ...) */
 871         rs600_gpu_init(rdev);
 872         /* Initialize GART (initialize after TTM so we can allocate
 873          * memory through TTM but finalize after TTM) */
 874         r = rs600_gart_enable(rdev);
 875         if (r)
 876                 return r;
 877
 878         /* allocate wb buffer */
 879         r = radeon_wb_init(rdev);
 880         if (r)
 881                 return r;
 882
 883         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 884         if (r) {
 885                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 886                 return r;
 887         }
 888
 889         /* Enable IRQ */
 890         rs600_irq_set(rdev);
 891         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 892         /* 1M ring buffer */
 893         r = r100_cp_init(rdev, 1024 * 1024);
 894         if (r) {
 895                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 896                 return r;
 897         }
 898
 899         r = radeon_ib_pool_init(rdev);
 900         if (r) {
 901                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 902                 return r;
 903         }
 904
 905         r = r600_audio_init(rdev);
 906         if (r) {
 907                 dev_err(rdev->dev, "failed initializing audio\n");
 908                 return r;
 909         }
 910
 911         return 0;
 912 }
 913
 914 int rs600_resume(struct radeon_device *rdev)
 915 {
 916         int r;
 917
 918         /* Make sur GART are not working */
 919         rs600_gart_disable(rdev);
 920         /* Resume clock before doing reset */
 921         rv515_clock_startup(rdev);
 922         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 923         if (radeon_asic_reset(rdev)) {
 924                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 925                         RREG32(R_000E40_RBBM_STATUS),
 926                         RREG32(R_0007C0_CP_STAT));
 927         }
 928         /* post */
 929         atom_asic_init(rdev->mode_info.atom_context);
 930         /* Resume clock after posting */
 931         rv515_clock_startup(rdev);
 932         /* Initialize surface registers */
 933         radeon_surface_init(rdev);
 934
 935         rdev->accel_working = true;
 936         r = rs600_startup(rdev);
 937         if (r) {
 938                 rdev->accel_working = false;
 939         }
 940         return r;
 941 }
 942
 943 int rs600_suspend(struct radeon_device *rdev)
 944 {
 945         r600_audio_fini(rdev);
 946         r100_cp_disable(rdev);
 947         radeon_wb_disable(rdev);
 948         rs600_irq_disable(rdev);
 949         rs600_gart_disable(rdev);
 950         return 0;
 951 }
 952
 953 void rs600_fini(struct radeon_device *rdev)
 954 {
 955         r600_audio_fini(rdev);
 956         r100_cp_fini(rdev);
 957         radeon_wb_fini(rdev);
 958         radeon_ib_pool_fini(rdev);
 959         radeon_gem_fini(rdev);
 960         rs600_gart_fini(rdev);
 961         radeon_irq_kms_fini(rdev);
 962         radeon_fence_driver_fini(rdev);
 963         radeon_bo_fini(rdev);
 964         radeon_atombios_fini(rdev);
 965         kfree(rdev->bios);
 966         rdev->bios = NULL;
 967 }
 968
 969 int rs600_init(struct radeon_device *rdev)
 970 {
 971         int r;
 972
 973         /* Disable VGA */
 974         rv515_vga_render_disable(rdev);
 975         /* Initialize scratch registers */
 976         radeon_scratch_init(rdev);
 977         /* Initialize surface registers */
 978         radeon_surface_init(rdev);
 979         /* restore some register to sane defaults */
 980         r100_restore_sanity(rdev);
 981         /* BIOS */
 982         if (!radeon_get_bios(rdev)) {
 983                 if (ASIC_IS_AVIVO(rdev))
 984                         return -EINVAL;
 985         }
 986         if (rdev->is_atom_bios) {
 987                 r = radeon_atombios_init(rdev);
 988                 if (r)
 989                         return r;
 990         } else {
 991                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
 992                 return -EINVAL;
 993         }
 994         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 995         if (radeon_asic_reset(rdev)) {
 996                 dev_warn(rdev->dev,
 997                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 998                         RREG32(R_000E40_RBBM_STATUS),
 999                         RREG32(R_0007C0_CP_STAT));
1000         }
1001         /* check if cards are posted or not */
1002         if (radeon_boot_test_post_card(rdev) == false)
1003                 return -EINVAL;
1004
1005         /* Initialize clocks */
1006         radeon_get_clock_info(rdev->ddev);
1007         /* initialize memory controller */
1008         rs600_mc_init(rdev);
1009         rs600_debugfs(rdev);
1010         /* Fence driver */
1011         r = radeon_fence_driver_init(rdev);
1012         if (r)
1013                 return r;
1014         r = radeon_irq_kms_init(rdev);
1015         if (r)
1016                 return r;
1017         /* Memory manager */
1018         r = radeon_bo_init(rdev);
1019         if (r)
1020                 return r;
1021         r = rs600_gart_init(rdev);
1022         if (r)
1023                 return r;
1024         rs600_set_safe_registers(rdev);
1025
1026         rdev->accel_working = true;
1027         r = rs600_startup(rdev);
1028         if (r) {
1029                 /* Somethings want wront with the accel init stop accel */
1030                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1031                 r100_cp_fini(rdev);
1032                 radeon_wb_fini(rdev);
1033                 radeon_ib_pool_fini(rdev);
1034                 rs600_gart_fini(rdev);
1035                 radeon_irq_kms_fini(rdev);
1036                 rdev->accel_working = false;
1037         }
1038         return 0;
1039 }