2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
35 static const char *radeon_pm_state_type_name[5] = {
43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47 static void radeon_pm_update_profile(struct radeon_device *rdev);
48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
50 int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
55 int found_instance = -1;
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
60 if (found_instance == instance)
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
71 if (rdev->pm.profile == PM_PROFILE_AUTO) {
72 mutex_lock(&rdev->pm.mutex);
73 radeon_pm_update_profile(rdev);
74 radeon_pm_set_clocks(rdev);
75 mutex_unlock(&rdev->pm.mutex);
80 static void radeon_pm_update_profile(struct radeon_device *rdev)
82 switch (rdev->pm.profile) {
83 case PM_PROFILE_DEFAULT:
84 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
87 if (power_supply_is_system_supplied() > 0) {
88 if (rdev->pm.active_crtc_count > 1)
89 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
91 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
93 if (rdev->pm.active_crtc_count > 1)
94 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
96 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
103 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
106 if (rdev->pm.active_crtc_count > 1)
107 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
109 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
111 case PM_PROFILE_HIGH:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
115 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
119 if (rdev->pm.active_crtc_count == 0) {
120 rdev->pm.requested_power_state_index =
121 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
122 rdev->pm.requested_clock_mode_index =
123 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
125 rdev->pm.requested_power_state_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
127 rdev->pm.requested_clock_mode_index =
128 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
132 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
134 struct radeon_bo *bo, *n;
136 if (list_empty(&rdev->gem.objects))
139 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
140 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
141 ttm_bo_unmap_virtual(&bo->tbo);
145 static void radeon_sync_with_vblank(struct radeon_device *rdev)
147 if (rdev->pm.active_crtcs) {
148 rdev->pm.vblank_sync = false;
150 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
151 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
155 static void radeon_set_power_state(struct radeon_device *rdev)
158 bool misc_after = false;
160 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
161 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
164 if (radeon_gui_idle(rdev)) {
165 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
166 clock_info[rdev->pm.requested_clock_mode_index].sclk;
167 if (sclk > rdev->pm.default_sclk)
168 sclk = rdev->pm.default_sclk;
170 /* starting with BTC, there is one state that is used for both
171 * MH and SH. Difference is that we always use the high clock index for
174 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
175 (rdev->family >= CHIP_BARTS) &&
176 rdev->pm.active_crtc_count &&
177 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
178 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
179 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
180 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
182 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].mclk;
185 if (mclk > rdev->pm.default_mclk)
186 mclk = rdev->pm.default_mclk;
188 /* upvolt before raising clocks, downvolt after lowering clocks */
189 if (sclk < rdev->pm.current_sclk)
192 radeon_sync_with_vblank(rdev);
194 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
195 if (!radeon_pm_in_vbl(rdev))
199 radeon_pm_prepare(rdev);
202 /* voltage, pcie lanes, etc.*/
203 radeon_pm_misc(rdev);
205 /* set engine clock */
206 if (sclk != rdev->pm.current_sclk) {
207 radeon_pm_debug_check_in_vbl(rdev, false);
208 radeon_set_engine_clock(rdev, sclk);
209 radeon_pm_debug_check_in_vbl(rdev, true);
210 rdev->pm.current_sclk = sclk;
211 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
214 /* set memory clock */
215 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_memory_clock(rdev, mclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_mclk = mclk;
220 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
224 /* voltage, pcie lanes, etc.*/
225 radeon_pm_misc(rdev);
227 radeon_pm_finish(rdev);
229 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
230 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
232 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
235 static void radeon_pm_set_clocks(struct radeon_device *rdev)
239 /* no need to take locks, etc. if nothing's going to change */
240 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
241 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
244 mutex_lock(&rdev->ddev->struct_mutex);
245 down_write(&rdev->pm.mclk_lock);
246 mutex_lock(&rdev->ring_lock);
248 /* wait for the rings to drain */
249 for (i = 0; i < RADEON_NUM_RINGS; i++) {
250 struct radeon_ring *ring = &rdev->ring[i];
254 r = radeon_fence_wait_empty_locked(rdev, i);
256 /* needs a GPU reset dont reset here */
257 mutex_unlock(&rdev->ring_lock);
258 up_write(&rdev->pm.mclk_lock);
259 mutex_unlock(&rdev->ddev->struct_mutex);
264 radeon_unmap_vram_bos(rdev);
266 if (rdev->irq.installed) {
267 for (i = 0; i < rdev->num_crtc; i++) {
268 if (rdev->pm.active_crtcs & (1 << i)) {
269 rdev->pm.req_vblank |= (1 << i);
270 drm_vblank_get(rdev->ddev, i);
275 radeon_set_power_state(rdev);
277 if (rdev->irq.installed) {
278 for (i = 0; i < rdev->num_crtc; i++) {
279 if (rdev->pm.req_vblank & (1 << i)) {
280 rdev->pm.req_vblank &= ~(1 << i);
281 drm_vblank_put(rdev->ddev, i);
286 /* update display watermarks based on new power state */
287 radeon_update_bandwidth_info(rdev);
288 if (rdev->pm.active_crtc_count)
289 radeon_bandwidth_update(rdev);
291 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
293 mutex_unlock(&rdev->ring_lock);
294 up_write(&rdev->pm.mclk_lock);
295 mutex_unlock(&rdev->ddev->struct_mutex);
298 static void radeon_pm_print_states(struct radeon_device *rdev)
301 struct radeon_power_state *power_state;
302 struct radeon_pm_clock_info *clock_info;
304 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
305 for (i = 0; i < rdev->pm.num_power_states; i++) {
306 power_state = &rdev->pm.power_state[i];
307 DRM_DEBUG_DRIVER("State %d: %s\n", i,
308 radeon_pm_state_type_name[power_state->type]);
309 if (i == rdev->pm.default_power_state_index)
310 DRM_DEBUG_DRIVER("\tDefault");
311 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
312 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
313 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
314 DRM_DEBUG_DRIVER("\tSingle display only\n");
315 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
316 for (j = 0; j < power_state->num_clock_modes; j++) {
317 clock_info = &(power_state->clock_info[j]);
318 if (rdev->flags & RADEON_IS_IGP)
319 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
321 clock_info->sclk * 10);
323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
325 clock_info->sclk * 10,
326 clock_info->mclk * 10,
327 clock_info->voltage.voltage);
332 static ssize_t radeon_get_pm_profile(struct device *dev,
333 struct device_attribute *attr,
336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
337 struct radeon_device *rdev = ddev->dev_private;
338 int cp = rdev->pm.profile;
340 return snprintf(buf, PAGE_SIZE, "%s\n",
341 (cp == PM_PROFILE_AUTO) ? "auto" :
342 (cp == PM_PROFILE_LOW) ? "low" :
343 (cp == PM_PROFILE_MID) ? "mid" :
344 (cp == PM_PROFILE_HIGH) ? "high" : "default");
347 static ssize_t radeon_set_pm_profile(struct device *dev,
348 struct device_attribute *attr,
352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
353 struct radeon_device *rdev = ddev->dev_private;
355 mutex_lock(&rdev->pm.mutex);
356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
357 if (strncmp("default", buf, strlen("default")) == 0)
358 rdev->pm.profile = PM_PROFILE_DEFAULT;
359 else if (strncmp("auto", buf, strlen("auto")) == 0)
360 rdev->pm.profile = PM_PROFILE_AUTO;
361 else if (strncmp("low", buf, strlen("low")) == 0)
362 rdev->pm.profile = PM_PROFILE_LOW;
363 else if (strncmp("mid", buf, strlen("mid")) == 0)
364 rdev->pm.profile = PM_PROFILE_MID;
365 else if (strncmp("high", buf, strlen("high")) == 0)
366 rdev->pm.profile = PM_PROFILE_HIGH;
371 radeon_pm_update_profile(rdev);
372 radeon_pm_set_clocks(rdev);
377 mutex_unlock(&rdev->pm.mutex);
382 static ssize_t radeon_get_pm_method(struct device *dev,
383 struct device_attribute *attr,
386 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
387 struct radeon_device *rdev = ddev->dev_private;
388 int pm = rdev->pm.pm_method;
390 return snprintf(buf, PAGE_SIZE, "%s\n",
391 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
394 static ssize_t radeon_set_pm_method(struct device *dev,
395 struct device_attribute *attr,
399 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
400 struct radeon_device *rdev = ddev->dev_private;
403 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
404 mutex_lock(&rdev->pm.mutex);
405 rdev->pm.pm_method = PM_METHOD_DYNPM;
406 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
407 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
408 mutex_unlock(&rdev->pm.mutex);
409 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
410 mutex_lock(&rdev->pm.mutex);
412 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
413 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
414 rdev->pm.pm_method = PM_METHOD_PROFILE;
415 mutex_unlock(&rdev->pm.mutex);
416 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
421 radeon_pm_compute_clocks(rdev);
426 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
427 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
429 static ssize_t radeon_hwmon_show_temp(struct device *dev,
430 struct device_attribute *attr,
433 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
434 struct radeon_device *rdev = ddev->dev_private;
437 switch (rdev->pm.int_thermal_type) {
438 case THERMAL_TYPE_RV6XX:
439 temp = rv6xx_get_temp(rdev);
441 case THERMAL_TYPE_RV770:
442 temp = rv770_get_temp(rdev);
444 case THERMAL_TYPE_EVERGREEN:
445 case THERMAL_TYPE_NI:
446 temp = evergreen_get_temp(rdev);
448 case THERMAL_TYPE_SUMO:
449 temp = sumo_get_temp(rdev);
451 case THERMAL_TYPE_SI:
452 temp = si_get_temp(rdev);
459 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
462 static ssize_t radeon_hwmon_show_name(struct device *dev,
463 struct device_attribute *attr,
466 return sprintf(buf, "radeon\n");
469 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
470 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
472 static struct attribute *hwmon_attributes[] = {
473 &sensor_dev_attr_temp1_input.dev_attr.attr,
474 &sensor_dev_attr_name.dev_attr.attr,
478 static const struct attribute_group hwmon_attrgroup = {
479 .attrs = hwmon_attributes,
482 static int radeon_hwmon_init(struct radeon_device *rdev)
486 rdev->pm.int_hwmon_dev = NULL;
488 switch (rdev->pm.int_thermal_type) {
489 case THERMAL_TYPE_RV6XX:
490 case THERMAL_TYPE_RV770:
491 case THERMAL_TYPE_EVERGREEN:
492 case THERMAL_TYPE_NI:
493 case THERMAL_TYPE_SUMO:
494 case THERMAL_TYPE_SI:
495 /* No support for TN yet */
496 if (rdev->family == CHIP_ARUBA)
498 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
499 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
500 err = PTR_ERR(rdev->pm.int_hwmon_dev);
502 "Unable to register hwmon device: %d\n", err);
505 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
506 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
510 "Unable to create hwmon sysfs file: %d\n", err);
511 hwmon_device_unregister(rdev->dev);
521 static void radeon_hwmon_fini(struct radeon_device *rdev)
523 if (rdev->pm.int_hwmon_dev) {
524 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
525 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
529 void radeon_pm_suspend(struct radeon_device *rdev)
531 mutex_lock(&rdev->pm.mutex);
532 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
533 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
534 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
536 mutex_unlock(&rdev->pm.mutex);
538 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
541 void radeon_pm_resume(struct radeon_device *rdev)
543 /* set up the default clocks if the MC ucode is loaded */
544 if ((rdev->family >= CHIP_BARTS) &&
545 (rdev->family <= CHIP_CAYMAN) &&
547 if (rdev->pm.default_vddc)
548 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
549 SET_VOLTAGE_TYPE_ASIC_VDDC);
550 if (rdev->pm.default_vddci)
551 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
552 SET_VOLTAGE_TYPE_ASIC_VDDCI);
553 if (rdev->pm.default_sclk)
554 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
555 if (rdev->pm.default_mclk)
556 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
558 /* asic init will reset the default power state */
559 mutex_lock(&rdev->pm.mutex);
560 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
561 rdev->pm.current_clock_mode_index = 0;
562 rdev->pm.current_sclk = rdev->pm.default_sclk;
563 rdev->pm.current_mclk = rdev->pm.default_mclk;
564 if (rdev->pm.power_state) {
565 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
566 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
568 if (rdev->pm.pm_method == PM_METHOD_DYNPM
569 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
570 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
571 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
572 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
574 mutex_unlock(&rdev->pm.mutex);
575 radeon_pm_compute_clocks(rdev);
578 int radeon_pm_init(struct radeon_device *rdev)
582 /* default to profile method */
583 rdev->pm.pm_method = PM_METHOD_PROFILE;
584 rdev->pm.profile = PM_PROFILE_DEFAULT;
585 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
586 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
587 rdev->pm.dynpm_can_upclock = true;
588 rdev->pm.dynpm_can_downclock = true;
589 rdev->pm.default_sclk = rdev->clock.default_sclk;
590 rdev->pm.default_mclk = rdev->clock.default_mclk;
591 rdev->pm.current_sclk = rdev->clock.default_sclk;
592 rdev->pm.current_mclk = rdev->clock.default_mclk;
593 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
596 if (rdev->is_atom_bios)
597 radeon_atombios_get_power_modes(rdev);
599 radeon_combios_get_power_modes(rdev);
600 radeon_pm_print_states(rdev);
601 radeon_pm_init_profile(rdev);
602 /* set up the default clocks if the MC ucode is loaded */
603 if ((rdev->family >= CHIP_BARTS) &&
604 (rdev->family <= CHIP_CAYMAN) &&
606 if (rdev->pm.default_vddc)
607 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
608 SET_VOLTAGE_TYPE_ASIC_VDDC);
609 if (rdev->pm.default_vddci)
610 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
611 SET_VOLTAGE_TYPE_ASIC_VDDCI);
612 if (rdev->pm.default_sclk)
613 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
614 if (rdev->pm.default_mclk)
615 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
619 /* set up the internal thermal sensor if applicable */
620 ret = radeon_hwmon_init(rdev);
624 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
626 if (rdev->pm.num_power_states > 1) {
627 /* where's the best place to put these? */
628 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
630 DRM_ERROR("failed to create device file for power profile\n");
631 ret = device_create_file(rdev->dev, &dev_attr_power_method);
633 DRM_ERROR("failed to create device file for power method\n");
635 if (radeon_debugfs_pm_init(rdev)) {
636 DRM_ERROR("Failed to register debugfs file for PM!\n");
639 DRM_INFO("radeon: power management initialized\n");
645 void radeon_pm_fini(struct radeon_device *rdev)
647 if (rdev->pm.num_power_states > 1) {
648 mutex_lock(&rdev->pm.mutex);
649 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
650 rdev->pm.profile = PM_PROFILE_DEFAULT;
651 radeon_pm_update_profile(rdev);
652 radeon_pm_set_clocks(rdev);
653 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
654 /* reset default clocks */
655 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
656 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
657 radeon_pm_set_clocks(rdev);
659 mutex_unlock(&rdev->pm.mutex);
661 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
663 device_remove_file(rdev->dev, &dev_attr_power_profile);
664 device_remove_file(rdev->dev, &dev_attr_power_method);
667 if (rdev->pm.power_state)
668 kfree(rdev->pm.power_state);
670 radeon_hwmon_fini(rdev);
673 void radeon_pm_compute_clocks(struct radeon_device *rdev)
675 struct drm_device *ddev = rdev->ddev;
676 struct drm_crtc *crtc;
677 struct radeon_crtc *radeon_crtc;
679 if (rdev->pm.num_power_states < 2)
682 mutex_lock(&rdev->pm.mutex);
684 rdev->pm.active_crtcs = 0;
685 rdev->pm.active_crtc_count = 0;
686 list_for_each_entry(crtc,
687 &ddev->mode_config.crtc_list, head) {
688 radeon_crtc = to_radeon_crtc(crtc);
689 if (radeon_crtc->enabled) {
690 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
691 rdev->pm.active_crtc_count++;
695 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
696 radeon_pm_update_profile(rdev);
697 radeon_pm_set_clocks(rdev);
698 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
699 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
700 if (rdev->pm.active_crtc_count > 1) {
701 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
702 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
704 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
705 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
706 radeon_pm_get_dynpm_state(rdev);
707 radeon_pm_set_clocks(rdev);
709 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
711 } else if (rdev->pm.active_crtc_count == 1) {
712 /* TODO: Increase clocks if needed for current mode */
714 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
715 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
716 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
717 radeon_pm_get_dynpm_state(rdev);
718 radeon_pm_set_clocks(rdev);
720 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
721 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
722 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
723 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
724 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
725 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
726 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
728 } else { /* count == 0 */
729 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
730 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
732 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
733 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
734 radeon_pm_get_dynpm_state(rdev);
735 radeon_pm_set_clocks(rdev);
741 mutex_unlock(&rdev->pm.mutex);
744 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
746 int crtc, vpos, hpos, vbl_status;
749 /* Iterate over all active crtc's. All crtc's must be in vblank,
750 * otherwise return in_vbl == false.
752 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
753 if (rdev->pm.active_crtcs & (1 << crtc)) {
754 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
755 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
756 !(vbl_status & DRM_SCANOUTPOS_INVBL))
764 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
767 bool in_vbl = radeon_pm_in_vbl(rdev);
770 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
771 finish ? "exit" : "entry");
775 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
777 struct radeon_device *rdev;
779 rdev = container_of(work, struct radeon_device,
780 pm.dynpm_idle_work.work);
782 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
783 mutex_lock(&rdev->pm.mutex);
784 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
785 int not_processed = 0;
788 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
789 struct radeon_ring *ring = &rdev->ring[i];
792 not_processed += radeon_fence_count_emitted(rdev, i);
793 if (not_processed >= 3)
798 if (not_processed >= 3) { /* should upclock */
799 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
800 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
801 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
802 rdev->pm.dynpm_can_upclock) {
803 rdev->pm.dynpm_planned_action =
804 DYNPM_ACTION_UPCLOCK;
805 rdev->pm.dynpm_action_timeout = jiffies +
806 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
808 } else if (not_processed == 0) { /* should downclock */
809 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
810 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
811 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
812 rdev->pm.dynpm_can_downclock) {
813 rdev->pm.dynpm_planned_action =
814 DYNPM_ACTION_DOWNCLOCK;
815 rdev->pm.dynpm_action_timeout = jiffies +
816 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
820 /* Note, radeon_pm_set_clocks is called with static_switch set
821 * to false since we want to wait for vbl to avoid flicker.
823 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
824 jiffies > rdev->pm.dynpm_action_timeout) {
825 radeon_pm_get_dynpm_state(rdev);
826 radeon_pm_set_clocks(rdev);
829 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
830 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
832 mutex_unlock(&rdev->pm.mutex);
833 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
839 #if defined(CONFIG_DEBUG_FS)
841 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
843 struct drm_info_node *node = (struct drm_info_node *) m->private;
844 struct drm_device *dev = node->minor->dev;
845 struct radeon_device *rdev = dev->dev_private;
847 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
848 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
849 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
850 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
852 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
853 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
854 if (rdev->asic->pm.get_memory_clock)
855 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
856 if (rdev->pm.current_vddc)
857 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
858 if (rdev->asic->pm.get_pcie_lanes)
859 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
864 static struct drm_info_list radeon_pm_info_list[] = {
865 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
869 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
871 #if defined(CONFIG_DEBUG_FS)
872 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));