2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
28 #include <linux/power_supply.h>
29 #include <linux/hwmon.h>
30 #include <linux/hwmon-sysfs.h>
32 #define RADEON_IDLE_LOOP_MS 100
33 #define RADEON_RECLOCK_DELAY_MS 200
34 #define RADEON_WAIT_VBLANK_TIMEOUT 200
36 static const char *radeon_pm_state_type_name[5] = {
44 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
45 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
46 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
47 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
48 static void radeon_pm_update_profile(struct radeon_device *rdev);
49 static void radeon_pm_set_clocks(struct radeon_device *rdev);
51 int radeon_pm_get_type_index(struct radeon_device *rdev,
52 enum radeon_pm_state_type ps_type,
56 int found_instance = -1;
58 for (i = 0; i < rdev->pm.num_power_states; i++) {
59 if (rdev->pm.power_state[i].type == ps_type) {
61 if (found_instance == instance)
65 /* return default if no match */
66 return rdev->pm.default_power_state_index;
69 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
71 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
72 mutex_lock(&rdev->pm.mutex);
73 if (power_supply_is_system_supplied() > 0)
74 rdev->pm.dpm.ac_power = true;
76 rdev->pm.dpm.ac_power = false;
77 if (rdev->family == CHIP_ARUBA) {
78 if (rdev->asic->dpm.enable_bapm)
79 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
81 mutex_unlock(&rdev->pm.mutex);
82 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
83 if (rdev->pm.profile == PM_PROFILE_AUTO) {
84 mutex_lock(&rdev->pm.mutex);
85 radeon_pm_update_profile(rdev);
86 radeon_pm_set_clocks(rdev);
87 mutex_unlock(&rdev->pm.mutex);
92 static void radeon_pm_update_profile(struct radeon_device *rdev)
94 switch (rdev->pm.profile) {
95 case PM_PROFILE_DEFAULT:
96 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
99 if (power_supply_is_system_supplied() > 0) {
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
103 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
105 if (rdev->pm.active_crtc_count > 1)
106 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
108 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
115 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
118 if (rdev->pm.active_crtc_count > 1)
119 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
121 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
123 case PM_PROFILE_HIGH:
124 if (rdev->pm.active_crtc_count > 1)
125 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
127 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
131 if (rdev->pm.active_crtc_count == 0) {
132 rdev->pm.requested_power_state_index =
133 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
134 rdev->pm.requested_clock_mode_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
137 rdev->pm.requested_power_state_index =
138 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
139 rdev->pm.requested_clock_mode_index =
140 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
144 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
146 struct radeon_bo *bo, *n;
148 if (list_empty(&rdev->gem.objects))
151 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
152 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
153 ttm_bo_unmap_virtual(&bo->tbo);
157 static void radeon_sync_with_vblank(struct radeon_device *rdev)
159 if (rdev->pm.active_crtcs) {
160 rdev->pm.vblank_sync = false;
162 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
163 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
167 static void radeon_set_power_state(struct radeon_device *rdev)
170 bool misc_after = false;
172 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
173 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
176 if (radeon_gui_idle(rdev)) {
177 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
178 clock_info[rdev->pm.requested_clock_mode_index].sclk;
179 if (sclk > rdev->pm.default_sclk)
180 sclk = rdev->pm.default_sclk;
182 /* starting with BTC, there is one state that is used for both
183 * MH and SH. Difference is that we always use the high clock index for
186 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
187 (rdev->family >= CHIP_BARTS) &&
188 rdev->pm.active_crtc_count &&
189 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
190 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
194 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
195 clock_info[rdev->pm.requested_clock_mode_index].mclk;
197 if (mclk > rdev->pm.default_mclk)
198 mclk = rdev->pm.default_mclk;
200 /* upvolt before raising clocks, downvolt after lowering clocks */
201 if (sclk < rdev->pm.current_sclk)
204 radeon_sync_with_vblank(rdev);
206 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
207 if (!radeon_pm_in_vbl(rdev))
211 radeon_pm_prepare(rdev);
214 /* voltage, pcie lanes, etc.*/
215 radeon_pm_misc(rdev);
217 /* set engine clock */
218 if (sclk != rdev->pm.current_sclk) {
219 radeon_pm_debug_check_in_vbl(rdev, false);
220 radeon_set_engine_clock(rdev, sclk);
221 radeon_pm_debug_check_in_vbl(rdev, true);
222 rdev->pm.current_sclk = sclk;
223 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
226 /* set memory clock */
227 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
228 radeon_pm_debug_check_in_vbl(rdev, false);
229 radeon_set_memory_clock(rdev, mclk);
230 radeon_pm_debug_check_in_vbl(rdev, true);
231 rdev->pm.current_mclk = mclk;
232 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
236 /* voltage, pcie lanes, etc.*/
237 radeon_pm_misc(rdev);
239 radeon_pm_finish(rdev);
241 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
242 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
244 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
247 static void radeon_pm_set_clocks(struct radeon_device *rdev)
251 /* no need to take locks, etc. if nothing's going to change */
252 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
253 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
256 mutex_lock(&rdev->ddev->struct_mutex);
257 down_write(&rdev->pm.mclk_lock);
258 mutex_lock(&rdev->ring_lock);
260 /* wait for the rings to drain */
261 for (i = 0; i < RADEON_NUM_RINGS; i++) {
262 struct radeon_ring *ring = &rdev->ring[i];
266 r = radeon_fence_wait_empty(rdev, i);
268 /* needs a GPU reset dont reset here */
269 mutex_unlock(&rdev->ring_lock);
270 up_write(&rdev->pm.mclk_lock);
271 mutex_unlock(&rdev->ddev->struct_mutex);
276 radeon_unmap_vram_bos(rdev);
278 if (rdev->irq.installed) {
279 for (i = 0; i < rdev->num_crtc; i++) {
280 if (rdev->pm.active_crtcs & (1 << i)) {
281 rdev->pm.req_vblank |= (1 << i);
282 drm_vblank_get(rdev->ddev, i);
287 radeon_set_power_state(rdev);
289 if (rdev->irq.installed) {
290 for (i = 0; i < rdev->num_crtc; i++) {
291 if (rdev->pm.req_vblank & (1 << i)) {
292 rdev->pm.req_vblank &= ~(1 << i);
293 drm_vblank_put(rdev->ddev, i);
298 /* update display watermarks based on new power state */
299 radeon_update_bandwidth_info(rdev);
300 if (rdev->pm.active_crtc_count)
301 radeon_bandwidth_update(rdev);
303 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
305 mutex_unlock(&rdev->ring_lock);
306 up_write(&rdev->pm.mclk_lock);
307 mutex_unlock(&rdev->ddev->struct_mutex);
310 static void radeon_pm_print_states(struct radeon_device *rdev)
313 struct radeon_power_state *power_state;
314 struct radeon_pm_clock_info *clock_info;
316 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
317 for (i = 0; i < rdev->pm.num_power_states; i++) {
318 power_state = &rdev->pm.power_state[i];
319 DRM_DEBUG_DRIVER("State %d: %s\n", i,
320 radeon_pm_state_type_name[power_state->type]);
321 if (i == rdev->pm.default_power_state_index)
322 DRM_DEBUG_DRIVER("\tDefault");
323 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
324 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
325 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
326 DRM_DEBUG_DRIVER("\tSingle display only\n");
327 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
328 for (j = 0; j < power_state->num_clock_modes; j++) {
329 clock_info = &(power_state->clock_info[j]);
330 if (rdev->flags & RADEON_IS_IGP)
331 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
333 clock_info->sclk * 10);
335 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
337 clock_info->sclk * 10,
338 clock_info->mclk * 10,
339 clock_info->voltage.voltage);
344 static ssize_t radeon_get_pm_profile(struct device *dev,
345 struct device_attribute *attr,
348 struct drm_device *ddev = dev_get_drvdata(dev);
349 struct radeon_device *rdev = ddev->dev_private;
350 int cp = rdev->pm.profile;
352 return snprintf(buf, PAGE_SIZE, "%s\n",
353 (cp == PM_PROFILE_AUTO) ? "auto" :
354 (cp == PM_PROFILE_LOW) ? "low" :
355 (cp == PM_PROFILE_MID) ? "mid" :
356 (cp == PM_PROFILE_HIGH) ? "high" : "default");
359 static ssize_t radeon_set_pm_profile(struct device *dev,
360 struct device_attribute *attr,
364 struct drm_device *ddev = dev_get_drvdata(dev);
365 struct radeon_device *rdev = ddev->dev_private;
367 /* Can't set profile when the card is off */
368 if ((rdev->flags & RADEON_IS_PX) &&
369 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
372 mutex_lock(&rdev->pm.mutex);
373 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
374 if (strncmp("default", buf, strlen("default")) == 0)
375 rdev->pm.profile = PM_PROFILE_DEFAULT;
376 else if (strncmp("auto", buf, strlen("auto")) == 0)
377 rdev->pm.profile = PM_PROFILE_AUTO;
378 else if (strncmp("low", buf, strlen("low")) == 0)
379 rdev->pm.profile = PM_PROFILE_LOW;
380 else if (strncmp("mid", buf, strlen("mid")) == 0)
381 rdev->pm.profile = PM_PROFILE_MID;
382 else if (strncmp("high", buf, strlen("high")) == 0)
383 rdev->pm.profile = PM_PROFILE_HIGH;
388 radeon_pm_update_profile(rdev);
389 radeon_pm_set_clocks(rdev);
394 mutex_unlock(&rdev->pm.mutex);
399 static ssize_t radeon_get_pm_method(struct device *dev,
400 struct device_attribute *attr,
403 struct drm_device *ddev = dev_get_drvdata(dev);
404 struct radeon_device *rdev = ddev->dev_private;
405 int pm = rdev->pm.pm_method;
407 return snprintf(buf, PAGE_SIZE, "%s\n",
408 (pm == PM_METHOD_DYNPM) ? "dynpm" :
409 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
412 static ssize_t radeon_set_pm_method(struct device *dev,
413 struct device_attribute *attr,
417 struct drm_device *ddev = dev_get_drvdata(dev);
418 struct radeon_device *rdev = ddev->dev_private;
420 /* Can't set method when the card is off */
421 if ((rdev->flags & RADEON_IS_PX) &&
422 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
427 /* we don't support the legacy modes with dpm */
428 if (rdev->pm.pm_method == PM_METHOD_DPM) {
433 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
434 mutex_lock(&rdev->pm.mutex);
435 rdev->pm.pm_method = PM_METHOD_DYNPM;
436 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
437 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
438 mutex_unlock(&rdev->pm.mutex);
439 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
440 mutex_lock(&rdev->pm.mutex);
442 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
443 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
444 rdev->pm.pm_method = PM_METHOD_PROFILE;
445 mutex_unlock(&rdev->pm.mutex);
446 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
451 radeon_pm_compute_clocks(rdev);
456 static ssize_t radeon_get_dpm_state(struct device *dev,
457 struct device_attribute *attr,
460 struct drm_device *ddev = dev_get_drvdata(dev);
461 struct radeon_device *rdev = ddev->dev_private;
462 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
464 return snprintf(buf, PAGE_SIZE, "%s\n",
465 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
466 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
469 static ssize_t radeon_set_dpm_state(struct device *dev,
470 struct device_attribute *attr,
474 struct drm_device *ddev = dev_get_drvdata(dev);
475 struct radeon_device *rdev = ddev->dev_private;
477 mutex_lock(&rdev->pm.mutex);
478 if (strncmp("battery", buf, strlen("battery")) == 0)
479 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
480 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
481 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
482 else if (strncmp("performance", buf, strlen("performance")) == 0)
483 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
485 mutex_unlock(&rdev->pm.mutex);
489 mutex_unlock(&rdev->pm.mutex);
491 /* Can't set dpm state when the card is off */
492 if (!(rdev->flags & RADEON_IS_PX) ||
493 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
494 radeon_pm_compute_clocks(rdev);
500 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
501 struct device_attribute *attr,
504 struct drm_device *ddev = dev_get_drvdata(dev);
505 struct radeon_device *rdev = ddev->dev_private;
506 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
508 if ((rdev->flags & RADEON_IS_PX) &&
509 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
510 return snprintf(buf, PAGE_SIZE, "off\n");
512 return snprintf(buf, PAGE_SIZE, "%s\n",
513 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
514 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
517 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
518 struct device_attribute *attr,
522 struct drm_device *ddev = dev_get_drvdata(dev);
523 struct radeon_device *rdev = ddev->dev_private;
524 enum radeon_dpm_forced_level level;
527 /* Can't force performance level when the card is off */
528 if ((rdev->flags & RADEON_IS_PX) &&
529 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
532 mutex_lock(&rdev->pm.mutex);
533 if (strncmp("low", buf, strlen("low")) == 0) {
534 level = RADEON_DPM_FORCED_LEVEL_LOW;
535 } else if (strncmp("high", buf, strlen("high")) == 0) {
536 level = RADEON_DPM_FORCED_LEVEL_HIGH;
537 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
538 level = RADEON_DPM_FORCED_LEVEL_AUTO;
543 if (rdev->asic->dpm.force_performance_level) {
544 if (rdev->pm.dpm.thermal_active) {
548 ret = radeon_dpm_force_performance_level(rdev, level);
553 mutex_unlock(&rdev->pm.mutex);
558 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev,
559 struct device_attribute *attr,
562 struct radeon_device *rdev = dev_get_drvdata(dev);
565 if (rdev->asic->dpm.fan_ctrl_get_mode)
566 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
568 /* never 0 (full-speed), fuse or smc-controlled always */
569 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
572 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev,
573 struct device_attribute *attr,
577 struct radeon_device *rdev = dev_get_drvdata(dev);
581 if(!rdev->asic->dpm.fan_ctrl_set_mode)
584 err = kstrtoint(buf, 10, &value);
589 case 1: /* manual, percent-based */
590 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
592 default: /* disable */
593 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
600 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev,
601 struct device_attribute *attr,
604 return sprintf(buf, "%i\n", 0);
607 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev,
608 struct device_attribute *attr,
611 return sprintf(buf, "%i\n", 255);
614 static ssize_t radeon_hwmon_set_pwm1(struct device *dev,
615 struct device_attribute *attr,
616 const char *buf, size_t count)
618 struct radeon_device *rdev = dev_get_drvdata(dev);
622 err = kstrtou32(buf, 10, &value);
626 value = (value * 100) / 255;
628 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
635 static ssize_t radeon_hwmon_get_pwm1(struct device *dev,
636 struct device_attribute *attr,
639 struct radeon_device *rdev = dev_get_drvdata(dev);
643 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
647 speed = (speed * 255) / 100;
649 return sprintf(buf, "%i\n", speed);
652 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
653 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
654 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
655 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
656 radeon_get_dpm_forced_performance_level,
657 radeon_set_dpm_forced_performance_level);
659 static ssize_t radeon_hwmon_show_temp(struct device *dev,
660 struct device_attribute *attr,
663 struct radeon_device *rdev = dev_get_drvdata(dev);
664 struct drm_device *ddev = rdev->ddev;
667 /* Can't get temperature when the card is off */
668 if ((rdev->flags & RADEON_IS_PX) &&
669 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
672 if (rdev->asic->pm.get_temperature)
673 temp = radeon_get_temperature(rdev);
677 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
680 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
681 struct device_attribute *attr,
684 struct radeon_device *rdev = dev_get_drvdata(dev);
685 int hyst = to_sensor_dev_attr(attr)->index;
689 temp = rdev->pm.dpm.thermal.min_temp;
691 temp = rdev->pm.dpm.thermal.max_temp;
693 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
696 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
697 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
698 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
699 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0);
700 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0);
701 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0);
702 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0);
705 static struct attribute *hwmon_attributes[] = {
706 &sensor_dev_attr_temp1_input.dev_attr.attr,
707 &sensor_dev_attr_temp1_crit.dev_attr.attr,
708 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
709 &sensor_dev_attr_pwm1.dev_attr.attr,
710 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
711 &sensor_dev_attr_pwm1_min.dev_attr.attr,
712 &sensor_dev_attr_pwm1_max.dev_attr.attr,
716 static umode_t hwmon_attributes_visible(struct kobject *kobj,
717 struct attribute *attr, int index)
719 struct device *dev = container_of(kobj, struct device, kobj);
720 struct radeon_device *rdev = dev_get_drvdata(dev);
721 umode_t effective_mode = attr->mode;
723 /* Skip limit attributes if DPM is not enabled */
724 if (rdev->pm.pm_method != PM_METHOD_DPM &&
725 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
726 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
729 /* Skip fan attributes if fan is not present */
730 if (rdev->pm.no_fan &&
731 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
732 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
733 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
734 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
737 /* mask fan attributes if we have no bindings for this asic to expose */
738 if ((!rdev->asic->dpm.get_fan_speed_percent &&
739 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
740 (!rdev->asic->dpm.fan_ctrl_get_mode &&
741 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
742 effective_mode &= ~S_IRUGO;
744 if ((!rdev->asic->dpm.set_fan_speed_percent &&
745 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
746 (!rdev->asic->dpm.fan_ctrl_set_mode &&
747 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
748 effective_mode &= ~S_IWUSR;
750 /* hide max/min values if we can't both query and manage the fan */
751 if ((!rdev->asic->dpm.set_fan_speed_percent &&
752 !rdev->asic->dpm.get_fan_speed_percent) &&
753 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
754 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
757 return effective_mode;
760 static const struct attribute_group hwmon_attrgroup = {
761 .attrs = hwmon_attributes,
762 .is_visible = hwmon_attributes_visible,
765 static const struct attribute_group *hwmon_groups[] = {
770 static int radeon_hwmon_init(struct radeon_device *rdev)
774 switch (rdev->pm.int_thermal_type) {
775 case THERMAL_TYPE_RV6XX:
776 case THERMAL_TYPE_RV770:
777 case THERMAL_TYPE_EVERGREEN:
778 case THERMAL_TYPE_NI:
779 case THERMAL_TYPE_SUMO:
780 case THERMAL_TYPE_SI:
781 case THERMAL_TYPE_CI:
782 case THERMAL_TYPE_KV:
783 if (rdev->asic->pm.get_temperature == NULL)
785 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
788 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
789 err = PTR_ERR(rdev->pm.int_hwmon_dev);
791 "Unable to register hwmon device: %d\n", err);
801 static void radeon_hwmon_fini(struct radeon_device *rdev)
803 if (rdev->pm.int_hwmon_dev)
804 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
807 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
809 struct radeon_device *rdev =
810 container_of(work, struct radeon_device,
811 pm.dpm.thermal.work);
812 /* switch to the thermal state */
813 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
815 if (!rdev->pm.dpm_enabled)
818 if (rdev->asic->pm.get_temperature) {
819 int temp = radeon_get_temperature(rdev);
821 if (temp < rdev->pm.dpm.thermal.min_temp)
822 /* switch back the user state */
823 dpm_state = rdev->pm.dpm.user_state;
825 if (rdev->pm.dpm.thermal.high_to_low)
826 /* switch back the user state */
827 dpm_state = rdev->pm.dpm.user_state;
829 mutex_lock(&rdev->pm.mutex);
830 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
831 rdev->pm.dpm.thermal_active = true;
833 rdev->pm.dpm.thermal_active = false;
834 rdev->pm.dpm.state = dpm_state;
835 mutex_unlock(&rdev->pm.mutex);
837 radeon_pm_compute_clocks(rdev);
840 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
841 enum radeon_pm_state_type dpm_state)
844 struct radeon_ps *ps;
846 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
849 /* check if the vblank period is too short to adjust the mclk */
850 if (single_display && rdev->asic->dpm.vblank_too_short) {
851 if (radeon_dpm_vblank_too_short(rdev))
852 single_display = false;
855 /* certain older asics have a separare 3D performance state,
856 * so try that first if the user selected performance
858 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
859 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
860 /* balanced states don't exist at the moment */
861 if (dpm_state == POWER_STATE_TYPE_BALANCED)
862 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
865 /* Pick the best power state based on current conditions */
866 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
867 ps = &rdev->pm.dpm.ps[i];
868 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
871 case POWER_STATE_TYPE_BATTERY:
872 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
873 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
880 case POWER_STATE_TYPE_BALANCED:
881 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
882 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
889 case POWER_STATE_TYPE_PERFORMANCE:
890 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
891 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
898 /* internal states */
899 case POWER_STATE_TYPE_INTERNAL_UVD:
900 if (rdev->pm.dpm.uvd_ps)
901 return rdev->pm.dpm.uvd_ps;
904 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
905 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
908 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
909 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
912 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
913 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
916 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
917 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
920 case POWER_STATE_TYPE_INTERNAL_BOOT:
921 return rdev->pm.dpm.boot_ps;
922 case POWER_STATE_TYPE_INTERNAL_THERMAL:
923 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
926 case POWER_STATE_TYPE_INTERNAL_ACPI:
927 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
930 case POWER_STATE_TYPE_INTERNAL_ULV:
931 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
934 case POWER_STATE_TYPE_INTERNAL_3DPERF:
935 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
942 /* use a fallback state if we didn't match */
944 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
945 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
947 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
948 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
949 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
950 if (rdev->pm.dpm.uvd_ps) {
951 return rdev->pm.dpm.uvd_ps;
953 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
956 case POWER_STATE_TYPE_INTERNAL_THERMAL:
957 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
959 case POWER_STATE_TYPE_INTERNAL_ACPI:
960 dpm_state = POWER_STATE_TYPE_BATTERY;
962 case POWER_STATE_TYPE_BATTERY:
963 case POWER_STATE_TYPE_BALANCED:
964 case POWER_STATE_TYPE_INTERNAL_3DPERF:
965 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
974 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
977 struct radeon_ps *ps;
978 enum radeon_pm_state_type dpm_state;
981 /* if dpm init failed */
982 if (!rdev->pm.dpm_enabled)
985 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
986 /* add other state override checks here */
987 if ((!rdev->pm.dpm.thermal_active) &&
988 (!rdev->pm.dpm.uvd_active))
989 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
991 dpm_state = rdev->pm.dpm.state;
993 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
995 rdev->pm.dpm.requested_ps = ps;
999 /* no need to reprogram if nothing changed unless we are on BTC+ */
1000 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1001 /* vce just modifies an existing state so force a change */
1002 if (ps->vce_active != rdev->pm.dpm.vce_active)
1004 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1005 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
1006 * all we need to do is update the display configuration.
1008 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1009 /* update display watermarks based on new power state */
1010 radeon_bandwidth_update(rdev);
1011 /* update displays */
1012 radeon_dpm_display_configuration_changed(rdev);
1013 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1014 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1018 /* for BTC+ if the num crtcs hasn't changed and state is the same,
1019 * nothing to do, if the num crtcs is > 1 and state is the same,
1020 * update display configuration.
1022 if (rdev->pm.dpm.new_active_crtcs ==
1023 rdev->pm.dpm.current_active_crtcs) {
1026 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1027 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1028 /* update display watermarks based on new power state */
1029 radeon_bandwidth_update(rdev);
1030 /* update displays */
1031 radeon_dpm_display_configuration_changed(rdev);
1032 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1033 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1041 if (radeon_dpm == 1) {
1042 printk("switching from power state:\n");
1043 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1044 printk("switching to power state:\n");
1045 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1048 mutex_lock(&rdev->ddev->struct_mutex);
1049 down_write(&rdev->pm.mclk_lock);
1050 mutex_lock(&rdev->ring_lock);
1052 /* update whether vce is active */
1053 ps->vce_active = rdev->pm.dpm.vce_active;
1055 ret = radeon_dpm_pre_set_power_state(rdev);
1059 /* update display watermarks based on new power state */
1060 radeon_bandwidth_update(rdev);
1061 /* update displays */
1062 radeon_dpm_display_configuration_changed(rdev);
1064 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1065 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1067 /* wait for the rings to drain */
1068 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1069 struct radeon_ring *ring = &rdev->ring[i];
1071 radeon_fence_wait_empty(rdev, i);
1074 /* program the new power state */
1075 radeon_dpm_set_power_state(rdev);
1077 /* update current power state */
1078 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1080 radeon_dpm_post_set_power_state(rdev);
1082 if (rdev->asic->dpm.force_performance_level) {
1083 if (rdev->pm.dpm.thermal_active) {
1084 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1085 /* force low perf level for thermal */
1086 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1087 /* save the user's level */
1088 rdev->pm.dpm.forced_level = level;
1090 /* otherwise, user selected level */
1091 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1096 mutex_unlock(&rdev->ring_lock);
1097 up_write(&rdev->pm.mclk_lock);
1098 mutex_unlock(&rdev->ddev->struct_mutex);
1101 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1103 enum radeon_pm_state_type dpm_state;
1105 if (rdev->asic->dpm.powergate_uvd) {
1106 mutex_lock(&rdev->pm.mutex);
1107 /* don't powergate anything if we
1108 have active but pause streams */
1109 enable |= rdev->pm.dpm.sd > 0;
1110 enable |= rdev->pm.dpm.hd > 0;
1111 /* enable/disable UVD */
1112 radeon_dpm_powergate_uvd(rdev, !enable);
1113 mutex_unlock(&rdev->pm.mutex);
1116 mutex_lock(&rdev->pm.mutex);
1117 rdev->pm.dpm.uvd_active = true;
1118 /* disable this for now */
1120 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1121 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1122 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1123 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1124 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1125 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1126 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1127 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1130 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1131 rdev->pm.dpm.state = dpm_state;
1132 mutex_unlock(&rdev->pm.mutex);
1134 mutex_lock(&rdev->pm.mutex);
1135 rdev->pm.dpm.uvd_active = false;
1136 mutex_unlock(&rdev->pm.mutex);
1139 radeon_pm_compute_clocks(rdev);
1143 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1146 mutex_lock(&rdev->pm.mutex);
1147 rdev->pm.dpm.vce_active = true;
1148 /* XXX select vce level based on ring/task */
1149 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1150 mutex_unlock(&rdev->pm.mutex);
1152 mutex_lock(&rdev->pm.mutex);
1153 rdev->pm.dpm.vce_active = false;
1154 mutex_unlock(&rdev->pm.mutex);
1157 radeon_pm_compute_clocks(rdev);
1160 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1162 mutex_lock(&rdev->pm.mutex);
1163 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1164 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1165 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1167 mutex_unlock(&rdev->pm.mutex);
1169 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1172 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1174 mutex_lock(&rdev->pm.mutex);
1176 radeon_dpm_disable(rdev);
1177 /* reset the power state */
1178 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1179 rdev->pm.dpm_enabled = false;
1180 mutex_unlock(&rdev->pm.mutex);
1183 void radeon_pm_suspend(struct radeon_device *rdev)
1185 if (rdev->pm.pm_method == PM_METHOD_DPM)
1186 radeon_pm_suspend_dpm(rdev);
1188 radeon_pm_suspend_old(rdev);
1191 static void radeon_pm_resume_old(struct radeon_device *rdev)
1193 /* set up the default clocks if the MC ucode is loaded */
1194 if ((rdev->family >= CHIP_BARTS) &&
1195 (rdev->family <= CHIP_CAYMAN) &&
1197 if (rdev->pm.default_vddc)
1198 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1199 SET_VOLTAGE_TYPE_ASIC_VDDC);
1200 if (rdev->pm.default_vddci)
1201 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1202 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1203 if (rdev->pm.default_sclk)
1204 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1205 if (rdev->pm.default_mclk)
1206 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1208 /* asic init will reset the default power state */
1209 mutex_lock(&rdev->pm.mutex);
1210 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1211 rdev->pm.current_clock_mode_index = 0;
1212 rdev->pm.current_sclk = rdev->pm.default_sclk;
1213 rdev->pm.current_mclk = rdev->pm.default_mclk;
1214 if (rdev->pm.power_state) {
1215 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1216 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1218 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1219 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1220 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1221 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1222 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1224 mutex_unlock(&rdev->pm.mutex);
1225 radeon_pm_compute_clocks(rdev);
1228 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1232 /* asic init will reset to the boot state */
1233 mutex_lock(&rdev->pm.mutex);
1234 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1235 radeon_dpm_setup_asic(rdev);
1236 ret = radeon_dpm_enable(rdev);
1237 mutex_unlock(&rdev->pm.mutex);
1239 goto dpm_resume_fail;
1240 rdev->pm.dpm_enabled = true;
1244 DRM_ERROR("radeon: dpm resume failed\n");
1245 if ((rdev->family >= CHIP_BARTS) &&
1246 (rdev->family <= CHIP_CAYMAN) &&
1248 if (rdev->pm.default_vddc)
1249 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1250 SET_VOLTAGE_TYPE_ASIC_VDDC);
1251 if (rdev->pm.default_vddci)
1252 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1253 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1254 if (rdev->pm.default_sclk)
1255 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1256 if (rdev->pm.default_mclk)
1257 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1261 void radeon_pm_resume(struct radeon_device *rdev)
1263 if (rdev->pm.pm_method == PM_METHOD_DPM)
1264 radeon_pm_resume_dpm(rdev);
1266 radeon_pm_resume_old(rdev);
1269 static int radeon_pm_init_old(struct radeon_device *rdev)
1273 rdev->pm.profile = PM_PROFILE_DEFAULT;
1274 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1275 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1276 rdev->pm.dynpm_can_upclock = true;
1277 rdev->pm.dynpm_can_downclock = true;
1278 rdev->pm.default_sclk = rdev->clock.default_sclk;
1279 rdev->pm.default_mclk = rdev->clock.default_mclk;
1280 rdev->pm.current_sclk = rdev->clock.default_sclk;
1281 rdev->pm.current_mclk = rdev->clock.default_mclk;
1282 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1285 if (rdev->is_atom_bios)
1286 radeon_atombios_get_power_modes(rdev);
1288 radeon_combios_get_power_modes(rdev);
1289 radeon_pm_print_states(rdev);
1290 radeon_pm_init_profile(rdev);
1291 /* set up the default clocks if the MC ucode is loaded */
1292 if ((rdev->family >= CHIP_BARTS) &&
1293 (rdev->family <= CHIP_CAYMAN) &&
1295 if (rdev->pm.default_vddc)
1296 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1297 SET_VOLTAGE_TYPE_ASIC_VDDC);
1298 if (rdev->pm.default_vddci)
1299 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1300 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1301 if (rdev->pm.default_sclk)
1302 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1303 if (rdev->pm.default_mclk)
1304 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1308 /* set up the internal thermal sensor if applicable */
1309 ret = radeon_hwmon_init(rdev);
1313 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1315 if (rdev->pm.num_power_states > 1) {
1316 /* where's the best place to put these? */
1317 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1319 DRM_ERROR("failed to create device file for power profile\n");
1320 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1322 DRM_ERROR("failed to create device file for power method\n");
1324 if (radeon_debugfs_pm_init(rdev)) {
1325 DRM_ERROR("Failed to register debugfs file for PM!\n");
1328 DRM_INFO("radeon: power management initialized\n");
1334 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1338 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1339 printk("== power state %d ==\n", i);
1340 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1344 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1348 /* default to balanced state */
1349 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1350 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1351 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1352 rdev->pm.default_sclk = rdev->clock.default_sclk;
1353 rdev->pm.default_mclk = rdev->clock.default_mclk;
1354 rdev->pm.current_sclk = rdev->clock.default_sclk;
1355 rdev->pm.current_mclk = rdev->clock.default_mclk;
1356 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1358 if (rdev->bios && rdev->is_atom_bios)
1359 radeon_atombios_get_power_modes(rdev);
1363 /* set up the internal thermal sensor if applicable */
1364 ret = radeon_hwmon_init(rdev);
1368 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1369 mutex_lock(&rdev->pm.mutex);
1370 radeon_dpm_init(rdev);
1371 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1372 if (radeon_dpm == 1)
1373 radeon_dpm_print_power_states(rdev);
1374 radeon_dpm_setup_asic(rdev);
1375 ret = radeon_dpm_enable(rdev);
1376 mutex_unlock(&rdev->pm.mutex);
1379 rdev->pm.dpm_enabled = true;
1381 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1383 DRM_ERROR("failed to create device file for dpm state\n");
1384 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1386 DRM_ERROR("failed to create device file for dpm state\n");
1387 /* XXX: these are noops for dpm but are here for backwards compat */
1388 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1390 DRM_ERROR("failed to create device file for power profile\n");
1391 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1393 DRM_ERROR("failed to create device file for power method\n");
1395 if (radeon_debugfs_pm_init(rdev)) {
1396 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1399 DRM_INFO("radeon: dpm initialized\n");
1404 rdev->pm.dpm_enabled = false;
1405 if ((rdev->family >= CHIP_BARTS) &&
1406 (rdev->family <= CHIP_CAYMAN) &&
1408 if (rdev->pm.default_vddc)
1409 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1410 SET_VOLTAGE_TYPE_ASIC_VDDC);
1411 if (rdev->pm.default_vddci)
1412 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1413 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1414 if (rdev->pm.default_sclk)
1415 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1416 if (rdev->pm.default_mclk)
1417 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1419 DRM_ERROR("radeon: dpm initialization failed\n");
1423 struct radeon_dpm_quirk {
1430 /* cards with dpm stability problems */
1431 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1432 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1433 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1434 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1435 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1439 int radeon_pm_init(struct radeon_device *rdev)
1441 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1442 bool disable_dpm = false;
1444 /* Apply dpm quirks */
1445 while (p && p->chip_device != 0) {
1446 if (rdev->pdev->vendor == p->chip_vendor &&
1447 rdev->pdev->device == p->chip_device &&
1448 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1449 rdev->pdev->subsystem_device == p->subsys_device) {
1456 /* enable dpm on rv6xx+ */
1457 switch (rdev->family) {
1466 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1468 rdev->pm.pm_method = PM_METHOD_PROFILE;
1469 else if ((rdev->family >= CHIP_RV770) &&
1470 (!(rdev->flags & RADEON_IS_IGP)) &&
1472 rdev->pm.pm_method = PM_METHOD_PROFILE;
1473 else if (radeon_dpm == 1)
1474 rdev->pm.pm_method = PM_METHOD_DPM;
1476 rdev->pm.pm_method = PM_METHOD_PROFILE;
1504 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1506 rdev->pm.pm_method = PM_METHOD_PROFILE;
1507 else if ((rdev->family >= CHIP_RV770) &&
1508 (!(rdev->flags & RADEON_IS_IGP)) &&
1510 rdev->pm.pm_method = PM_METHOD_PROFILE;
1511 else if (disable_dpm && (radeon_dpm == -1))
1512 rdev->pm.pm_method = PM_METHOD_PROFILE;
1513 else if (radeon_dpm == 0)
1514 rdev->pm.pm_method = PM_METHOD_PROFILE;
1516 rdev->pm.pm_method = PM_METHOD_DPM;
1519 /* default to profile method */
1520 rdev->pm.pm_method = PM_METHOD_PROFILE;
1524 if (rdev->pm.pm_method == PM_METHOD_DPM)
1525 return radeon_pm_init_dpm(rdev);
1527 return radeon_pm_init_old(rdev);
1530 int radeon_pm_late_init(struct radeon_device *rdev)
1534 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1535 mutex_lock(&rdev->pm.mutex);
1536 ret = radeon_dpm_late_enable(rdev);
1537 mutex_unlock(&rdev->pm.mutex);
1542 static void radeon_pm_fini_old(struct radeon_device *rdev)
1544 if (rdev->pm.num_power_states > 1) {
1545 mutex_lock(&rdev->pm.mutex);
1546 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1547 rdev->pm.profile = PM_PROFILE_DEFAULT;
1548 radeon_pm_update_profile(rdev);
1549 radeon_pm_set_clocks(rdev);
1550 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1551 /* reset default clocks */
1552 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1553 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1554 radeon_pm_set_clocks(rdev);
1556 mutex_unlock(&rdev->pm.mutex);
1558 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1560 device_remove_file(rdev->dev, &dev_attr_power_profile);
1561 device_remove_file(rdev->dev, &dev_attr_power_method);
1564 radeon_hwmon_fini(rdev);
1565 kfree(rdev->pm.power_state);
1568 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1570 if (rdev->pm.num_power_states > 1) {
1571 mutex_lock(&rdev->pm.mutex);
1572 radeon_dpm_disable(rdev);
1573 mutex_unlock(&rdev->pm.mutex);
1575 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1576 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1577 /* XXX backwards compat */
1578 device_remove_file(rdev->dev, &dev_attr_power_profile);
1579 device_remove_file(rdev->dev, &dev_attr_power_method);
1581 radeon_dpm_fini(rdev);
1583 radeon_hwmon_fini(rdev);
1584 kfree(rdev->pm.power_state);
1587 void radeon_pm_fini(struct radeon_device *rdev)
1589 if (rdev->pm.pm_method == PM_METHOD_DPM)
1590 radeon_pm_fini_dpm(rdev);
1592 radeon_pm_fini_old(rdev);
1595 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1597 struct drm_device *ddev = rdev->ddev;
1598 struct drm_crtc *crtc;
1599 struct radeon_crtc *radeon_crtc;
1601 if (rdev->pm.num_power_states < 2)
1604 mutex_lock(&rdev->pm.mutex);
1606 rdev->pm.active_crtcs = 0;
1607 rdev->pm.active_crtc_count = 0;
1608 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1609 list_for_each_entry(crtc,
1610 &ddev->mode_config.crtc_list, head) {
1611 radeon_crtc = to_radeon_crtc(crtc);
1612 if (radeon_crtc->enabled) {
1613 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1614 rdev->pm.active_crtc_count++;
1619 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1620 radeon_pm_update_profile(rdev);
1621 radeon_pm_set_clocks(rdev);
1622 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1623 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1624 if (rdev->pm.active_crtc_count > 1) {
1625 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1626 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1628 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1629 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1630 radeon_pm_get_dynpm_state(rdev);
1631 radeon_pm_set_clocks(rdev);
1633 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1635 } else if (rdev->pm.active_crtc_count == 1) {
1636 /* TODO: Increase clocks if needed for current mode */
1638 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1639 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1640 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1641 radeon_pm_get_dynpm_state(rdev);
1642 radeon_pm_set_clocks(rdev);
1644 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1645 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1646 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1647 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1648 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1649 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1650 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1652 } else { /* count == 0 */
1653 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1654 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1656 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1657 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1658 radeon_pm_get_dynpm_state(rdev);
1659 radeon_pm_set_clocks(rdev);
1665 mutex_unlock(&rdev->pm.mutex);
1668 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1670 struct drm_device *ddev = rdev->ddev;
1671 struct drm_crtc *crtc;
1672 struct radeon_crtc *radeon_crtc;
1674 if (!rdev->pm.dpm_enabled)
1677 mutex_lock(&rdev->pm.mutex);
1679 /* update active crtc counts */
1680 rdev->pm.dpm.new_active_crtcs = 0;
1681 rdev->pm.dpm.new_active_crtc_count = 0;
1682 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1683 list_for_each_entry(crtc,
1684 &ddev->mode_config.crtc_list, head) {
1685 radeon_crtc = to_radeon_crtc(crtc);
1686 if (crtc->enabled) {
1687 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1688 rdev->pm.dpm.new_active_crtc_count++;
1693 /* update battery/ac status */
1694 if (power_supply_is_system_supplied() > 0)
1695 rdev->pm.dpm.ac_power = true;
1697 rdev->pm.dpm.ac_power = false;
1699 radeon_dpm_change_power_state_locked(rdev);
1701 mutex_unlock(&rdev->pm.mutex);
1705 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1707 if (rdev->pm.pm_method == PM_METHOD_DPM)
1708 radeon_pm_compute_clocks_dpm(rdev);
1710 radeon_pm_compute_clocks_old(rdev);
1713 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1715 int crtc, vpos, hpos, vbl_status;
1718 /* Iterate over all active crtc's. All crtc's must be in vblank,
1719 * otherwise return in_vbl == false.
1721 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1722 if (rdev->pm.active_crtcs & (1 << crtc)) {
1723 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1724 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1725 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
1733 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1736 bool in_vbl = radeon_pm_in_vbl(rdev);
1738 if (in_vbl == false)
1739 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1740 finish ? "exit" : "entry");
1744 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1746 struct radeon_device *rdev;
1748 rdev = container_of(work, struct radeon_device,
1749 pm.dynpm_idle_work.work);
1751 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1752 mutex_lock(&rdev->pm.mutex);
1753 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1754 int not_processed = 0;
1757 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1758 struct radeon_ring *ring = &rdev->ring[i];
1761 not_processed += radeon_fence_count_emitted(rdev, i);
1762 if (not_processed >= 3)
1767 if (not_processed >= 3) { /* should upclock */
1768 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1769 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1770 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1771 rdev->pm.dynpm_can_upclock) {
1772 rdev->pm.dynpm_planned_action =
1773 DYNPM_ACTION_UPCLOCK;
1774 rdev->pm.dynpm_action_timeout = jiffies +
1775 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1777 } else if (not_processed == 0) { /* should downclock */
1778 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1779 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1780 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1781 rdev->pm.dynpm_can_downclock) {
1782 rdev->pm.dynpm_planned_action =
1783 DYNPM_ACTION_DOWNCLOCK;
1784 rdev->pm.dynpm_action_timeout = jiffies +
1785 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1789 /* Note, radeon_pm_set_clocks is called with static_switch set
1790 * to false since we want to wait for vbl to avoid flicker.
1792 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1793 jiffies > rdev->pm.dynpm_action_timeout) {
1794 radeon_pm_get_dynpm_state(rdev);
1795 radeon_pm_set_clocks(rdev);
1798 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1799 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1801 mutex_unlock(&rdev->pm.mutex);
1802 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1808 #if defined(CONFIG_DEBUG_FS)
1810 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1812 struct drm_info_node *node = (struct drm_info_node *) m->private;
1813 struct drm_device *dev = node->minor->dev;
1814 struct radeon_device *rdev = dev->dev_private;
1815 struct drm_device *ddev = rdev->ddev;
1817 if ((rdev->flags & RADEON_IS_PX) &&
1818 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1819 seq_printf(m, "PX asic powered off\n");
1820 } else if (rdev->pm.dpm_enabled) {
1821 mutex_lock(&rdev->pm.mutex);
1822 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1823 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1825 seq_printf(m, "Debugfs support not implemented for this asic\n");
1826 mutex_unlock(&rdev->pm.mutex);
1828 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1829 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1830 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1831 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1833 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1834 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1835 if (rdev->asic->pm.get_memory_clock)
1836 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1837 if (rdev->pm.current_vddc)
1838 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1839 if (rdev->asic->pm.get_pcie_lanes)
1840 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1846 static struct drm_info_list radeon_pm_info_list[] = {
1847 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1851 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1853 #if defined(CONFIG_DEBUG_FS)
1854 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));