2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include <drm/radeon_drm.h>
37 #include "radeon_trace.h"
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
49 void radeon_bo_clear_va(struct radeon_bo *bo)
51 struct radeon_bo_va *bo_va, *tmp;
53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54 /* remove from all vm address space */
55 radeon_vm_bo_rmv(bo->rdev, bo_va);
59 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
63 bo = container_of(tbo, struct radeon_bo, tbo);
64 mutex_lock(&bo->rdev->gem.mutex);
65 list_del_init(&bo->list);
66 mutex_unlock(&bo->rdev->gem.mutex);
67 radeon_bo_clear_surface_reg(bo);
68 radeon_bo_clear_va(bo);
69 drm_gem_object_release(&bo->gem_base);
73 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
75 if (bo->destroy == &radeon_ttm_bo_destroy)
80 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
84 rbo->placement.fpfn = 0;
85 rbo->placement.lpfn = 0;
86 rbo->placement.placement = rbo->placements;
87 rbo->placement.busy_placement = rbo->placements;
88 if (domain & RADEON_GEM_DOMAIN_VRAM)
89 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
91 if (domain & RADEON_GEM_DOMAIN_GTT) {
92 if (rbo->rdev->flags & RADEON_IS_AGP) {
93 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
95 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
98 if (domain & RADEON_GEM_DOMAIN_CPU) {
99 if (rbo->rdev->flags & RADEON_IS_AGP) {
100 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
102 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
106 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
107 rbo->placement.num_placement = c;
108 rbo->placement.num_busy_placement = c;
111 int radeon_bo_create(struct radeon_device *rdev,
112 unsigned long size, int byte_align, bool kernel, u32 domain,
113 struct sg_table *sg, struct radeon_bo **bo_ptr)
115 struct radeon_bo *bo;
116 enum ttm_bo_type type;
117 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
121 size = ALIGN(size, PAGE_SIZE);
123 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
125 type = ttm_bo_type_kernel;
127 type = ttm_bo_type_sg;
129 type = ttm_bo_type_device;
133 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
134 sizeof(struct radeon_bo));
136 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
139 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
145 bo->surface_reg = -1;
146 INIT_LIST_HEAD(&bo->list);
147 INIT_LIST_HEAD(&bo->va);
148 radeon_ttm_placement_from_domain(bo, domain);
149 /* Kernel allocation are uninterruptible */
150 down_read(&rdev->pm.mclk_lock);
151 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
152 &bo->placement, page_align, !kernel, NULL,
153 acc_size, sg, &radeon_ttm_bo_destroy);
154 up_read(&rdev->pm.mclk_lock);
155 if (unlikely(r != 0)) {
160 trace_radeon_bo_create(bo);
165 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
176 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
180 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
184 radeon_bo_check_tiling(bo, 0, 0);
188 void radeon_bo_kunmap(struct radeon_bo *bo)
190 if (bo->kptr == NULL)
193 radeon_bo_check_tiling(bo, 0, 0);
194 ttm_bo_kunmap(&bo->kmap);
197 void radeon_bo_unref(struct radeon_bo **bo)
199 struct ttm_buffer_object *tbo;
200 struct radeon_device *rdev;
206 down_read(&rdev->pm.mclk_lock);
208 up_read(&rdev->pm.mclk_lock);
213 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
221 *gpu_addr = radeon_bo_gpu_offset(bo);
223 if (max_offset != 0) {
226 if (domain == RADEON_GEM_DOMAIN_VRAM)
227 domain_start = bo->rdev->mc.vram_start;
229 domain_start = bo->rdev->mc.gtt_start;
230 WARN_ON_ONCE(max_offset <
231 (radeon_bo_gpu_offset(bo) - domain_start));
236 radeon_ttm_placement_from_domain(bo, domain);
237 if (domain == RADEON_GEM_DOMAIN_VRAM) {
238 /* force to pin into visible video ram */
239 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
242 u64 lpfn = max_offset >> PAGE_SHIFT;
244 if (!bo->placement.lpfn)
245 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
247 if (lpfn < bo->placement.lpfn)
248 bo->placement.lpfn = lpfn;
250 for (i = 0; i < bo->placement.num_placement; i++)
251 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
252 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
253 if (likely(r == 0)) {
255 if (gpu_addr != NULL)
256 *gpu_addr = radeon_bo_gpu_offset(bo);
258 if (unlikely(r != 0))
259 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
263 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
265 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
268 int radeon_bo_unpin(struct radeon_bo *bo)
272 if (!bo->pin_count) {
273 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
279 for (i = 0; i < bo->placement.num_placement; i++)
280 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
281 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
282 if (unlikely(r != 0))
283 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
287 int radeon_bo_evict_vram(struct radeon_device *rdev)
289 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
290 if (0 && (rdev->flags & RADEON_IS_IGP)) {
291 if (rdev->mc.igp_sideport_enabled == false)
292 /* Useless to evict on IGP chips */
295 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
298 void radeon_bo_force_delete(struct radeon_device *rdev)
300 struct radeon_bo *bo, *n;
302 if (list_empty(&rdev->gem.objects)) {
305 dev_err(rdev->dev, "Userspace still has active objects !\n");
306 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
307 mutex_lock(&rdev->ddev->struct_mutex);
308 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
309 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
310 *((unsigned long *)&bo->gem_base.refcount));
311 mutex_lock(&bo->rdev->gem.mutex);
312 list_del_init(&bo->list);
313 mutex_unlock(&bo->rdev->gem.mutex);
314 /* this should unref the ttm bo */
315 drm_gem_object_unreference(&bo->gem_base);
316 mutex_unlock(&rdev->ddev->struct_mutex);
320 int radeon_bo_init(struct radeon_device *rdev)
322 /* Add an MTRR for the VRAM */
323 if (!rdev->fastfb_working) {
324 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
327 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
328 rdev->mc.mc_vram_size >> 20,
329 (unsigned long long)rdev->mc.aper_size >> 20);
330 DRM_INFO("RAM width %dbits %cDR\n",
331 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
332 return radeon_ttm_init(rdev);
335 void radeon_bo_fini(struct radeon_device *rdev)
337 radeon_ttm_fini(rdev);
338 arch_phys_wc_del(rdev->mc.vram_mtrr);
341 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
342 struct list_head *head)
345 list_add(&lobj->tv.head, head);
347 list_add_tail(&lobj->tv.head, head);
351 int radeon_bo_list_validate(struct ww_acquire_ctx *ticket,
352 struct list_head *head, int ring)
354 struct radeon_bo_list *lobj;
355 struct radeon_bo *bo;
359 r = ttm_eu_reserve_buffers(ticket, head);
360 if (unlikely(r != 0)) {
363 list_for_each_entry(lobj, head, tv.head) {
365 if (!bo->pin_count) {
366 domain = lobj->domain;
369 radeon_ttm_placement_from_domain(bo, domain);
370 if (ring == R600_RING_TYPE_UVD_INDEX)
371 radeon_uvd_force_into_uvd_segment(bo);
372 r = ttm_bo_validate(&bo->tbo, &bo->placement,
375 if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
376 domain = lobj->alt_domain;
379 ttm_eu_backoff_reservation(ticket, head);
383 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
384 lobj->tiling_flags = bo->tiling_flags;
389 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
390 struct vm_area_struct *vma)
392 return ttm_fbdev_mmap(vma, &bo->tbo);
395 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
397 struct radeon_device *rdev = bo->rdev;
398 struct radeon_surface_reg *reg;
399 struct radeon_bo *old_object;
403 lockdep_assert_held(&bo->tbo.resv->lock.base);
405 if (!bo->tiling_flags)
408 if (bo->surface_reg >= 0) {
409 reg = &rdev->surface_regs[bo->surface_reg];
415 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
417 reg = &rdev->surface_regs[i];
421 old_object = reg->bo;
422 if (old_object->pin_count == 0)
426 /* if we are all out */
427 if (i == RADEON_GEM_MAX_SURFACES) {
430 /* find someone with a surface reg and nuke their BO */
431 reg = &rdev->surface_regs[steal];
432 old_object = reg->bo;
433 /* blow away the mapping */
434 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
435 ttm_bo_unmap_virtual(&old_object->tbo);
436 old_object->surface_reg = -1;
444 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
445 bo->tbo.mem.start << PAGE_SHIFT,
446 bo->tbo.num_pages << PAGE_SHIFT);
450 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
452 struct radeon_device *rdev = bo->rdev;
453 struct radeon_surface_reg *reg;
455 if (bo->surface_reg == -1)
458 reg = &rdev->surface_regs[bo->surface_reg];
459 radeon_clear_surface_reg(rdev, bo->surface_reg);
462 bo->surface_reg = -1;
465 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
466 uint32_t tiling_flags, uint32_t pitch)
468 struct radeon_device *rdev = bo->rdev;
471 if (rdev->family >= CHIP_CEDAR) {
472 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
474 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
475 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
476 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
477 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
478 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
512 if (stilesplit > 6) {
516 r = radeon_bo_reserve(bo, false);
517 if (unlikely(r != 0))
519 bo->tiling_flags = tiling_flags;
521 radeon_bo_unreserve(bo);
525 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
526 uint32_t *tiling_flags,
529 lockdep_assert_held(&bo->tbo.resv->lock.base);
532 *tiling_flags = bo->tiling_flags;
537 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
541 lockdep_assert_held(&bo->tbo.resv->lock.base);
543 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
547 radeon_bo_clear_surface_reg(bo);
551 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
555 if (bo->surface_reg >= 0)
556 radeon_bo_clear_surface_reg(bo);
560 if ((bo->surface_reg >= 0) && !has_moved)
563 return radeon_bo_get_surface_reg(bo);
566 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
567 struct ttm_mem_reg *mem)
569 struct radeon_bo *rbo;
570 if (!radeon_ttm_bo_is_radeon_bo(bo))
572 rbo = container_of(bo, struct radeon_bo, tbo);
573 radeon_bo_check_tiling(rbo, 0, 1);
574 radeon_vm_bo_invalidate(rbo->rdev, rbo);
577 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
579 struct radeon_device *rdev;
580 struct radeon_bo *rbo;
581 unsigned long offset, size;
584 if (!radeon_ttm_bo_is_radeon_bo(bo))
586 rbo = container_of(bo, struct radeon_bo, tbo);
587 radeon_bo_check_tiling(rbo, 0, 0);
589 if (bo->mem.mem_type == TTM_PL_VRAM) {
590 size = bo->mem.num_pages << PAGE_SHIFT;
591 offset = bo->mem.start << PAGE_SHIFT;
592 if ((offset + size) > rdev->mc.visible_vram_size) {
593 /* hurrah the memory is not visible ! */
594 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
595 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
596 r = ttm_bo_validate(bo, &rbo->placement, false, false);
597 if (unlikely(r != 0))
599 offset = bo->mem.start << PAGE_SHIFT;
600 /* this should not happen */
601 if ((offset + size) > rdev->mc.visible_vram_size)
608 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
612 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
613 if (unlikely(r != 0))
615 spin_lock(&bo->tbo.bdev->fence_lock);
617 *mem_type = bo->tbo.mem.mem_type;
618 if (bo->tbo.sync_obj)
619 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
620 spin_unlock(&bo->tbo.bdev->fence_lock);
621 ttm_bo_unreserve(&bo->tbo);