2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
33 static void radeon_overscan_setup(struct drm_crtc *crtc,
34 struct drm_display_mode *mode)
36 struct drm_device *dev = crtc->dev;
37 struct radeon_device *rdev = dev->dev_private;
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
46 struct drm_display_mode *mode)
48 struct drm_device *dev = crtc->dev;
49 struct radeon_device *rdev = dev->dev_private;
50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
51 int xres = mode->hdisplay;
52 int yres = mode->vdisplay;
53 bool hscale = true, vscale = true;
58 u32 scale, inc, crtc_more_cntl;
59 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
60 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
61 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
62 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
64 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
65 (RADEON_VERT_STRETCH_RESERVED |
66 RADEON_VERT_AUTO_RATIO_INC);
67 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
68 (RADEON_HORZ_FP_LOOP_STRETCH |
69 RADEON_HORZ_AUTO_RATIO_INC);
72 if ((rdev->family == CHIP_RS100) ||
73 (rdev->family == CHIP_RS200)) {
74 /* This is to workaround the asic bug for RMX, some versions
75 of BIOS dosen't have this register initialized correctly. */
76 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
80 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
81 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
83 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
86 hsync_start = mode->crtc_hsync_start - 8;
88 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
89 | ((hsync_wid & 0x3f) << 16)
90 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
91 ? RADEON_CRTC_H_SYNC_POL
94 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
95 | ((mode->crtc_vdisplay - 1) << 16));
97 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
101 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
102 | ((vsync_wid & 0x1f) << 16)
103 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
104 ? RADEON_CRTC_V_SYNC_POL
107 fp_horz_vert_active = 0;
109 if (native_mode->hdisplay == 0 ||
110 native_mode->vdisplay == 0) {
114 if (xres > native_mode->hdisplay)
115 xres = native_mode->hdisplay;
116 if (yres > native_mode->vdisplay)
117 yres = native_mode->vdisplay;
119 if (xres == native_mode->hdisplay)
121 if (yres == native_mode->vdisplay)
125 switch (radeon_crtc->rmx_type) {
129 fp_horz_stretch |= ((xres/8-1) << 16);
131 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
132 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
133 / native_mode->hdisplay + 1;
134 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
135 RADEON_HORZ_STRETCH_BLEND |
136 RADEON_HORZ_STRETCH_ENABLE |
137 ((native_mode->hdisplay/8-1) << 16));
141 fp_vert_stretch |= ((yres-1) << 12);
143 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
144 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
145 / native_mode->vdisplay + 1;
146 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
147 RADEON_VERT_STRETCH_ENABLE |
148 RADEON_VERT_STRETCH_BLEND |
149 ((native_mode->vdisplay-1) << 12));
153 fp_horz_stretch |= ((xres/8-1) << 16);
154 fp_vert_stretch |= ((yres-1) << 12);
156 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
157 RADEON_CRTC_AUTO_VERT_CENTER_EN);
159 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
160 if (blank_width > 110)
163 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
164 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
166 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
170 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
171 | ((hsync_wid & 0x3f) << 16)
172 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
173 ? RADEON_CRTC_H_SYNC_POL
176 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
177 | ((mode->crtc_vdisplay - 1) << 16));
179 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
183 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
184 | ((vsync_wid & 0x1f) << 16)
185 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
186 ? RADEON_CRTC_V_SYNC_POL
189 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
190 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
194 fp_horz_stretch |= ((xres/8-1) << 16);
195 fp_vert_stretch |= ((yres-1) << 12);
199 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
200 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
201 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
202 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
203 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
204 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
205 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
206 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
209 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
211 struct radeon_device *rdev = dev->dev_private;
214 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
215 the cause yet, but this workaround will mask the problem for now.
216 Other chips usually will pass at the very first test, so the
217 workaround shouldn't have any effect on them. */
220 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
224 static void radeon_pll_write_update(struct drm_device *dev)
226 struct radeon_device *rdev = dev->dev_private;
228 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
230 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
231 RADEON_PPLL_ATOMIC_UPDATE_W,
232 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
235 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
237 struct radeon_device *rdev = dev->dev_private;
241 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
242 the cause yet, but this workaround will mask the problem for now.
243 Other chips usually will pass at the very first test, so the
244 workaround shouldn't have any effect on them. */
247 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
251 static void radeon_pll2_write_update(struct drm_device *dev)
253 struct radeon_device *rdev = dev->dev_private;
255 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
257 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
258 RADEON_P2PLL_ATOMIC_UPDATE_W,
259 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
262 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
265 unsigned int vcoFreq;
270 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
273 * This is horribly crude: the VCO frequency range is divided into
274 * 3 parts, each part having a fixed PLL gain value.
276 if (vcoFreq >= 30000)
281 else if (vcoFreq >= 18000)
293 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
295 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
296 struct drm_device *dev = crtc->dev;
297 struct radeon_device *rdev = dev->dev_private;
298 uint32_t crtc_ext_cntl = 0;
301 if (radeon_crtc->crtc_id)
302 mask = (RADEON_CRTC2_DISP_DIS |
303 RADEON_CRTC2_VSYNC_DIS |
304 RADEON_CRTC2_HSYNC_DIS |
305 RADEON_CRTC2_DISP_REQ_EN_B);
307 mask = (RADEON_CRTC_DISPLAY_DIS |
308 RADEON_CRTC_VSYNC_DIS |
309 RADEON_CRTC_HSYNC_DIS);
312 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
313 * Therefore it is set in the DAC DMPS function.
314 * This is different for GPU's with a single CRTC but a primary and a
315 * TV DAC: here it controls the single CRTC no matter where it is
316 * routed. Therefore we set it here.
318 if (rdev->flags & RADEON_SINGLE_CRTC)
319 crtc_ext_cntl = RADEON_CRTC_CRT_ON;
322 case DRM_MODE_DPMS_ON:
323 radeon_crtc->enabled = true;
324 /* adjust pm to dpms changes BEFORE enabling crtcs */
325 radeon_pm_compute_clocks(rdev);
326 if (radeon_crtc->crtc_id)
327 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
329 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
330 RADEON_CRTC_DISP_REQ_EN_B));
331 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
333 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
334 /* Make sure vblank interrupt is still enabled if needed */
335 radeon_irq_set(rdev);
336 radeon_crtc_load_lut(crtc);
338 case DRM_MODE_DPMS_STANDBY:
339 case DRM_MODE_DPMS_SUSPEND:
340 case DRM_MODE_DPMS_OFF:
341 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
342 if (radeon_crtc->crtc_id)
343 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
345 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
346 RADEON_CRTC_DISP_REQ_EN_B));
347 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
349 radeon_crtc->enabled = false;
350 /* adjust pm to dpms changes AFTER disabling crtcs */
351 radeon_pm_compute_clocks(rdev);
356 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
357 struct drm_framebuffer *old_fb)
359 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
362 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
363 struct drm_framebuffer *fb,
364 int x, int y, enum mode_set_atomic state)
366 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
369 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
370 struct drm_framebuffer *fb,
371 int x, int y, int atomic)
373 struct drm_device *dev = crtc->dev;
374 struct radeon_device *rdev = dev->dev_private;
375 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
376 struct radeon_framebuffer *radeon_fb;
377 struct drm_framebuffer *target_fb;
378 struct drm_gem_object *obj;
379 struct radeon_bo *rbo;
381 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
382 uint32_t crtc_pitch, pitch_pixels;
383 uint32_t tiling_flags;
385 uint32_t gen_cntl_reg, gen_cntl_val;
390 if (!atomic && !crtc->primary->fb) {
391 DRM_DEBUG_KMS("No FB bound\n");
396 radeon_fb = to_radeon_framebuffer(fb);
400 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
401 target_fb = crtc->primary->fb;
404 switch (target_fb->bits_per_pixel) {
424 /* Pin framebuffer & get tilling informations */
425 obj = radeon_fb->obj;
426 rbo = gem_to_radeon_bo(obj);
428 r = radeon_bo_reserve(rbo, false);
429 if (unlikely(r != 0))
431 /* Only 27 bit offset for legacy CRTC */
432 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
434 if (unlikely(r != 0)) {
435 radeon_bo_unreserve(rbo);
437 /* On old GPU like RN50 with little vram pining can fails because
438 * current fb is taking all space needed. So instead of unpining
439 * the old buffer after pining the new one, first unpin old one
440 * and then retry pining new one.
442 * As only master can set mode only master can pin and it is
443 * unlikely the master client will race with itself especialy
444 * on those old gpu with single crtc.
446 * We don't shutdown the display controller because new buffer
447 * will end up in same spot.
449 if (!atomic && fb && fb != crtc->primary->fb) {
450 struct radeon_bo *old_rbo;
451 unsigned long nsize, osize;
453 old_rbo = gem_to_radeon_bo(to_radeon_framebuffer(fb)->obj);
454 osize = radeon_bo_size(old_rbo);
455 nsize = radeon_bo_size(rbo);
456 if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) {
457 radeon_bo_unpin(old_rbo);
458 radeon_bo_unreserve(old_rbo);
465 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
466 radeon_bo_unreserve(rbo);
467 if (tiling_flags & RADEON_TILING_MICRO)
468 DRM_ERROR("trying to scanout microtiled buffer\n");
470 /* if scanout was in GTT this really wouldn't work */
471 /* crtc offset is from display base addr not FB location */
472 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
474 base -= radeon_crtc->legacy_display_base_addr;
476 crtc_offset_cntl = 0;
478 pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
479 crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) +
480 ((target_fb->bits_per_pixel * 8) - 1)) /
481 (target_fb->bits_per_pixel * 8));
482 crtc_pitch |= crtc_pitch << 16;
484 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
485 if (tiling_flags & RADEON_TILING_MACRO) {
486 if (ASIC_IS_R300(rdev))
487 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
488 R300_CRTC_MICRO_TILE_BUFFER_DIS |
489 R300_CRTC_MACRO_TILE_EN);
491 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
493 if (ASIC_IS_R300(rdev))
494 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
495 R300_CRTC_MICRO_TILE_BUFFER_DIS |
496 R300_CRTC_MACRO_TILE_EN);
498 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
501 if (tiling_flags & RADEON_TILING_MACRO) {
502 if (ASIC_IS_R300(rdev)) {
503 crtc_tile_x0_y0 = x | (y << 16);
506 int byteshift = target_fb->bits_per_pixel >> 4;
507 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
508 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
509 crtc_offset_cntl |= (y % 16);
512 int offset = y * pitch_pixels + x;
513 switch (target_fb->bits_per_pixel) {
535 if (radeon_crtc->crtc_id == 1)
536 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
538 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
540 gen_cntl_val = RREG32(gen_cntl_reg);
541 gen_cntl_val &= ~(0xf << 8);
542 gen_cntl_val |= (format << 8);
543 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
544 WREG32(gen_cntl_reg, gen_cntl_val);
546 crtc_offset = (u32)base;
548 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
550 if (ASIC_IS_R300(rdev)) {
551 if (radeon_crtc->crtc_id)
552 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
554 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
556 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
557 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
558 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
560 if (!atomic && fb && fb != crtc->primary->fb) {
561 radeon_fb = to_radeon_framebuffer(fb);
562 rbo = gem_to_radeon_bo(radeon_fb->obj);
563 r = radeon_bo_reserve(rbo, false);
564 if (unlikely(r != 0))
566 radeon_bo_unpin(rbo);
567 radeon_bo_unreserve(rbo);
570 /* Bytes per pixel may have changed */
571 radeon_bandwidth_update(rdev);
576 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
578 struct drm_device *dev = crtc->dev;
579 struct radeon_device *rdev = dev->dev_private;
580 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
581 struct drm_encoder *encoder;
586 uint32_t crtc_h_total_disp;
587 uint32_t crtc_h_sync_strt_wid;
588 uint32_t crtc_v_total_disp;
589 uint32_t crtc_v_sync_strt_wid;
593 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
594 if (encoder->crtc == crtc) {
595 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
596 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
598 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
604 switch (crtc->primary->fb->bits_per_pixel) {
624 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
625 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
627 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
630 hsync_start = mode->crtc_hsync_start - 8;
632 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
633 | ((hsync_wid & 0x3f) << 16)
634 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
635 ? RADEON_CRTC_H_SYNC_POL
638 /* This works for double scan mode. */
639 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
640 | ((mode->crtc_vdisplay - 1) << 16));
642 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
646 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
647 | ((vsync_wid & 0x1f) << 16)
648 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
649 ? RADEON_CRTC_V_SYNC_POL
652 if (radeon_crtc->crtc_id) {
653 uint32_t crtc2_gen_cntl;
654 uint32_t disp2_merge_cntl;
656 /* if TV DAC is enabled for another crtc and keep it enabled */
657 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
658 crtc2_gen_cntl |= ((format << 8)
659 | RADEON_CRTC2_VSYNC_DIS
660 | RADEON_CRTC2_HSYNC_DIS
661 | RADEON_CRTC2_DISP_DIS
662 | RADEON_CRTC2_DISP_REQ_EN_B
663 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
664 ? RADEON_CRTC2_DBL_SCAN_EN
666 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
667 ? RADEON_CRTC2_CSYNC_EN
669 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
670 ? RADEON_CRTC2_INTERLACE_EN
673 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
674 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
675 crtc2_gen_cntl |= RADEON_CRTC2_EN;
677 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
678 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
680 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
681 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
683 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
684 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
686 uint32_t crtc_gen_cntl;
687 uint32_t crtc_ext_cntl;
688 uint32_t disp_merge_cntl;
690 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
691 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
693 | RADEON_CRTC_DISP_REQ_EN_B
694 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
695 ? RADEON_CRTC_DBL_SCAN_EN
697 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
698 ? RADEON_CRTC_CSYNC_EN
700 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
701 ? RADEON_CRTC_INTERLACE_EN
704 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
705 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
706 crtc_gen_cntl |= RADEON_CRTC_EN;
708 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
709 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
710 RADEON_CRTC_VSYNC_DIS |
711 RADEON_CRTC_HSYNC_DIS |
712 RADEON_CRTC_DISPLAY_DIS);
714 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
715 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
717 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
718 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
719 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
723 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
724 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
725 &crtc_v_sync_strt_wid);
727 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
728 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
729 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
730 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
735 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
737 struct drm_device *dev = crtc->dev;
738 struct radeon_device *rdev = dev->dev_private;
739 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
740 struct drm_encoder *encoder;
741 uint32_t feedback_div = 0;
742 uint32_t frac_fb_div = 0;
743 uint32_t reference_div = 0;
744 uint32_t post_divider = 0;
747 bool use_bios_divs = false;
749 uint32_t pll_ref_div = 0;
750 uint32_t pll_fb_post_div = 0;
751 uint32_t htotal_cntl = 0;
753 struct radeon_pll *pll;
758 } *post_div, post_divs[] = {
759 /* From RAGE 128 VR/RAGE 128 GL Register
760 * Reference Manual (Technical Reference
761 * Manual P/N RRG-G04100-C Rev. 0.04), page
762 * 3-17 (PLL_DIV_[3:0]).
764 { 1, 0 }, /* VCLK_SRC */
765 { 2, 1 }, /* VCLK_SRC/2 */
766 { 4, 2 }, /* VCLK_SRC/4 */
767 { 8, 3 }, /* VCLK_SRC/8 */
768 { 3, 4 }, /* VCLK_SRC/3 */
769 { 16, 5 }, /* VCLK_SRC/16 */
770 { 6, 6 }, /* VCLK_SRC/6 */
771 { 12, 7 }, /* VCLK_SRC/12 */
775 if (radeon_crtc->crtc_id)
776 pll = &rdev->clock.p2pll;
778 pll = &rdev->clock.p1pll;
780 pll->flags = RADEON_PLL_LEGACY;
782 if (mode->clock > 200000) /* range limits??? */
783 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
785 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
787 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
788 if (encoder->crtc == crtc) {
789 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
791 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
796 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
797 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
798 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
799 if (!rdev->is_atom_bios) {
800 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
801 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
803 if (lvds->use_bios_dividers) {
804 pll_ref_div = lvds->panel_ref_divider;
805 pll_fb_post_div = (lvds->panel_fb_divider |
806 (lvds->panel_post_divider << 16));
808 use_bios_divs = true;
812 pll->flags |= RADEON_PLL_USE_REF_DIV;
819 if (!use_bios_divs) {
820 radeon_compute_pll_legacy(pll, mode->clock,
821 &freq, &feedback_div, &frac_fb_div,
822 &reference_div, &post_divider);
824 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
825 if (post_div->divider == post_divider)
829 if (!post_div->divider)
830 post_div = &post_divs[0];
832 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
838 pll_ref_div = reference_div;
839 #if defined(__powerpc__) && (0) /* TODO */
840 /* apparently programming this otherwise causes a hang??? */
841 if (info->MacModel == RADEON_MAC_IBOOK)
842 pll_fb_post_div = 0x000600ad;
845 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
847 htotal_cntl = mode->htotal & 0x7;
851 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
853 pll_fb_post_div & 0x7ff);
855 if (radeon_crtc->crtc_id) {
856 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
857 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
858 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
861 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
862 &pll_ref_div, &pll_fb_post_div,
866 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
867 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
868 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
870 WREG32_PLL_P(RADEON_P2PLL_CNTL,
872 | RADEON_P2PLL_ATOMIC_UPDATE_EN
873 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
875 | RADEON_P2PLL_ATOMIC_UPDATE_EN
876 | RADEON_P2PLL_PVG_MASK));
878 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
880 ~RADEON_P2PLL_REF_DIV_MASK);
882 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
884 ~RADEON_P2PLL_FB0_DIV_MASK);
886 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
888 ~RADEON_P2PLL_POST0_DIV_MASK);
890 radeon_pll2_write_update(dev);
891 radeon_pll2_wait_for_read_update_complete(dev);
893 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
895 WREG32_PLL_P(RADEON_P2PLL_CNTL,
899 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
901 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
902 (unsigned)pll_ref_div,
903 (unsigned)pll_fb_post_div,
904 (unsigned)htotal_cntl,
905 RREG32_PLL(RADEON_P2PLL_CNTL));
906 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
907 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
908 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
909 (unsigned)((pll_fb_post_div &
910 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
912 mdelay(50); /* Let the clock to lock */
914 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
915 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
916 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
918 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
920 uint32_t pixclks_cntl;
924 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
925 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
926 &pll_fb_post_div, &pixclks_cntl);
929 if (rdev->flags & RADEON_IS_MOBILITY) {
930 /* A temporal workaround for the occasional blanking on certain laptop panels.
931 This appears to related to the PLL divider registers (fail to lock?).
932 It occurs even when all dividers are the same with their old settings.
933 In this case we really don't need to fiddle with PLL registers.
934 By doing this we can avoid the blanking problem with some panels.
936 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
937 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
938 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
939 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
941 ~(RADEON_PLL_DIV_SEL));
942 r100_pll_errata_after_index(rdev);
947 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
948 RADEON_VCLK_SRC_SEL_CPUCLK,
949 ~(RADEON_VCLK_SRC_SEL_MASK));
950 WREG32_PLL_P(RADEON_PPLL_CNTL,
952 | RADEON_PPLL_ATOMIC_UPDATE_EN
953 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
954 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
956 | RADEON_PPLL_ATOMIC_UPDATE_EN
957 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
958 | RADEON_PPLL_PVG_MASK));
960 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
962 ~(RADEON_PLL_DIV_SEL));
963 r100_pll_errata_after_index(rdev);
965 if (ASIC_IS_R300(rdev) ||
966 (rdev->family == CHIP_RS300) ||
967 (rdev->family == CHIP_RS400) ||
968 (rdev->family == CHIP_RS480)) {
969 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
970 /* When restoring console mode, use saved PPLL_REF_DIV
973 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
977 /* R300 uses ref_div_acc field as real ref divider */
978 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
979 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
980 ~R300_PPLL_REF_DIV_ACC_MASK);
983 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
985 ~RADEON_PPLL_REF_DIV_MASK);
987 WREG32_PLL_P(RADEON_PPLL_DIV_3,
989 ~RADEON_PPLL_FB3_DIV_MASK);
991 WREG32_PLL_P(RADEON_PPLL_DIV_3,
993 ~RADEON_PPLL_POST3_DIV_MASK);
995 radeon_pll_write_update(dev);
996 radeon_pll_wait_for_read_update_complete(dev);
998 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
1000 WREG32_PLL_P(RADEON_PPLL_CNTL,
1004 | RADEON_PPLL_ATOMIC_UPDATE_EN
1005 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1007 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
1010 (unsigned)htotal_cntl,
1011 RREG32_PLL(RADEON_PPLL_CNTL));
1012 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
1013 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1014 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1015 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1017 mdelay(50); /* Let the clock to lock */
1019 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1020 RADEON_VCLK_SRC_SEL_PPLLCLK,
1021 ~(RADEON_VCLK_SRC_SEL_MASK));
1024 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1028 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1029 const struct drm_display_mode *mode,
1030 struct drm_display_mode *adjusted_mode)
1032 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1037 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1038 struct drm_display_mode *mode,
1039 struct drm_display_mode *adjusted_mode,
1040 int x, int y, struct drm_framebuffer *old_fb)
1042 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1045 radeon_crtc_set_base(crtc, x, y, old_fb);
1046 radeon_set_crtc_timing(crtc, adjusted_mode);
1047 radeon_set_pll(crtc, adjusted_mode);
1048 radeon_overscan_setup(crtc, adjusted_mode);
1049 if (radeon_crtc->crtc_id == 0) {
1050 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1052 if (radeon_crtc->rmx_type != RMX_OFF) {
1053 /* FIXME: only first crtc has rmx what should we
1056 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1059 radeon_cursor_reset(crtc);
1063 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1065 struct drm_device *dev = crtc->dev;
1066 struct drm_crtc *crtci;
1069 * The hardware wedges sometimes if you reconfigure one CRTC
1070 * whilst another is running (see fdo bug #24611).
1072 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1073 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1076 static void radeon_crtc_commit(struct drm_crtc *crtc)
1078 struct drm_device *dev = crtc->dev;
1079 struct drm_crtc *crtci;
1082 * Reenable the CRTCs that should be running.
1084 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1086 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1090 static void radeon_crtc_disable(struct drm_crtc *crtc)
1092 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1093 if (crtc->primary->fb) {
1095 struct radeon_framebuffer *radeon_fb;
1096 struct radeon_bo *rbo;
1098 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1099 rbo = gem_to_radeon_bo(radeon_fb->obj);
1100 r = radeon_bo_reserve(rbo, false);
1102 DRM_ERROR("failed to reserve rbo before unpin\n");
1104 radeon_bo_unpin(rbo);
1105 radeon_bo_unreserve(rbo);
1110 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1111 .dpms = radeon_crtc_dpms,
1112 .mode_fixup = radeon_crtc_mode_fixup,
1113 .mode_set = radeon_crtc_mode_set,
1114 .mode_set_base = radeon_crtc_set_base,
1115 .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1116 .prepare = radeon_crtc_prepare,
1117 .commit = radeon_crtc_commit,
1118 .load_lut = radeon_crtc_load_lut,
1119 .disable = radeon_crtc_disable
1123 void radeon_legacy_init_crtc(struct drm_device *dev,
1124 struct radeon_crtc *radeon_crtc)
1126 if (radeon_crtc->crtc_id == 1)
1127 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1128 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);