drivers/gpu/drm/radeon/radeon_kfd.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/fdtable.h>
  25 #include <linux/uaccess.h>
  26 #include <drm/drmP.h>
  27 #include "radeon.h"
  28 #include "cikd.h"
  29 #include "cik_reg.h"
  30 #include "radeon_kfd.h"
  31 #include "radeon_ucode.h"
  32 #include <linux/firmware.h>
  33
  34 #define CIK_PIPE_PER_MEC        (4)
  35
  36 struct kgd_mem {
  37         struct radeon_sa_bo *sa_bo;
  38         uint64_t gpu_addr;
  39         void *ptr;
  40 };
  41
  42 static int init_sa_manager(struct kgd_dev *kgd, unsigned int size);
  43 static void fini_sa_manager(struct kgd_dev *kgd);
  44
  45 static int allocate_mem(struct kgd_dev *kgd, size_t size, size_t alignment,
  46                 enum kgd_memory_pool pool, struct kgd_mem **mem);
  47
  48 static void free_mem(struct kgd_dev *kgd, struct kgd_mem *mem);
  49
  50 static uint64_t get_vmem_size(struct kgd_dev *kgd);
  51 static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
  52
  53 static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
  54 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
  55
  56 /*
  57  * Register access functions
  58  */
  59
  60 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
  61                 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
  62                 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
  63
  64 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  65                                         unsigned int vmid);
  66
  67 static int kgd_init_memory(struct kgd_dev *kgd);
  68
  69 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
  70                                 uint32_t hpd_size, uint64_t hpd_gpu_addr);
  71
  72 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
  73                         uint32_t queue_id, uint32_t __user *wptr);
  74 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
  75 static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
  76                                 uint32_t pipe_id, uint32_t queue_id);
  77
  78 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
  79                                 unsigned int timeout, uint32_t pipe_id,
  80                                 uint32_t queue_id);
  81 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
  82 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
  83                                 unsigned int timeout);
  84
  85 static const struct kfd2kgd_calls kfd2kgd = {
  86         .init_sa_manager = init_sa_manager,
  87         .fini_sa_manager = fini_sa_manager,
  88         .allocate_mem = allocate_mem,
  89         .free_mem = free_mem,
  90         .get_vmem_size = get_vmem_size,
  91         .get_gpu_clock_counter = get_gpu_clock_counter,
  92         .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
  93         .program_sh_mem_settings = kgd_program_sh_mem_settings,
  94         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
  95         .init_memory = kgd_init_memory,
  96         .init_pipeline = kgd_init_pipeline,
  97         .hqd_load = kgd_hqd_load,
  98         .hqd_sdma_load = kgd_hqd_sdma_load,
  99         .hqd_is_occupies = kgd_hqd_is_occupies,
 100         .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
 101         .hqd_destroy = kgd_hqd_destroy,
 102         .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
 103         .get_fw_version = get_fw_version
 104 };
 105
 106 static const struct kgd2kfd_calls *kgd2kfd;
 107
 108 bool radeon_kfd_init(void)
 109 {
 110         bool (*kgd2kfd_init_p)(unsigned, const struct kfd2kgd_calls*,
 111                                 const struct kgd2kfd_calls**);
 112
 113         kgd2kfd_init_p = symbol_request(kgd2kfd_init);
 114
 115         if (kgd2kfd_init_p == NULL)
 116                 return false;
 117
 118         if (!kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
 119                 symbol_put(kgd2kfd_init);
 120                 kgd2kfd = NULL;
 121
 122                 return false;
 123         }
 124
 125         return true;
 126 }
 127
 128 void radeon_kfd_fini(void)
 129 {
 130         if (kgd2kfd) {
 131                 kgd2kfd->exit();
 132                 symbol_put(kgd2kfd_init);
 133         }
 134 }
 135
 136 void radeon_kfd_device_probe(struct radeon_device *rdev)
 137 {
 138         if (kgd2kfd)
 139                 rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev, rdev->pdev);
 140 }
 141
 142 void radeon_kfd_device_init(struct radeon_device *rdev)
 143 {
 144         if (rdev->kfd) {
 145                 struct kgd2kfd_shared_resources gpu_resources = {
 146                         .compute_vmid_bitmap = 0xFF00,
 147
 148                         .first_compute_pipe = 1,
 149                         .compute_pipe_count = 8 - 1,
 150                 };
 151
 152                 radeon_doorbell_get_kfd_info(rdev,
 153                                 &gpu_resources.doorbell_physical_address,
 154                                 &gpu_resources.doorbell_aperture_size,
 155                                 &gpu_resources.doorbell_start_offset);
 156
 157                 kgd2kfd->device_init(rdev->kfd, &gpu_resources);
 158         }
 159 }
 160
 161 void radeon_kfd_device_fini(struct radeon_device *rdev)
 162 {
 163         if (rdev->kfd) {
 164                 kgd2kfd->device_exit(rdev->kfd);
 165                 rdev->kfd = NULL;
 166         }
 167 }
 168
 169 void radeon_kfd_interrupt(struct radeon_device *rdev, const void *ih_ring_entry)
 170 {
 171         if (rdev->kfd)
 172                 kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);
 173 }
 174
 175 void radeon_kfd_suspend(struct radeon_device *rdev)
 176 {
 177         if (rdev->kfd)
 178                 kgd2kfd->suspend(rdev->kfd);
 179 }
 180
 181 int radeon_kfd_resume(struct radeon_device *rdev)
 182 {
 183         int r = 0;
 184
 185         if (rdev->kfd)
 186                 r = kgd2kfd->resume(rdev->kfd);
 187
 188         return r;
 189 }
 190
 191 static u32 pool_to_domain(enum kgd_memory_pool p)
 192 {
 193         switch (p) {
 194         case KGD_POOL_FRAMEBUFFER: return RADEON_GEM_DOMAIN_VRAM;
 195         default: return RADEON_GEM_DOMAIN_GTT;
 196         }
 197 }
 198
 199 static int init_sa_manager(struct kgd_dev *kgd, unsigned int size)
 200 {
 201         struct radeon_device *rdev = (struct radeon_device *)kgd;
 202         int r;
 203
 204         BUG_ON(kgd == NULL);
 205
 206         r = radeon_sa_bo_manager_init(rdev, &rdev->kfd_bo,
 207                                       size,
 208                                       RADEON_GPU_PAGE_SIZE,
 209                                       RADEON_GEM_DOMAIN_GTT,
 210                                       RADEON_GEM_GTT_WC);
 211
 212         if (r)
 213                 return r;
 214
 215         r = radeon_sa_bo_manager_start(rdev, &rdev->kfd_bo);
 216         if (r)
 217                 radeon_sa_bo_manager_fini(rdev, &rdev->kfd_bo);
 218
 219         return r;
 220 }
 221
 222 static void fini_sa_manager(struct kgd_dev *kgd)
 223 {
 224         struct radeon_device *rdev = (struct radeon_device *)kgd;
 225
 226         BUG_ON(kgd == NULL);
 227
 228         radeon_sa_bo_manager_suspend(rdev, &rdev->kfd_bo);
 229         radeon_sa_bo_manager_fini(rdev, &rdev->kfd_bo);
 230 }
 231
 232 static int allocate_mem(struct kgd_dev *kgd, size_t size, size_t alignment,
 233                 enum kgd_memory_pool pool, struct kgd_mem **mem)
 234 {
 235         struct radeon_device *rdev = (struct radeon_device *)kgd;
 236         u32 domain;
 237         int r;
 238
 239         BUG_ON(kgd == NULL);
 240
 241         domain = pool_to_domain(pool);
 242         if (domain != RADEON_GEM_DOMAIN_GTT) {
 243                 dev_err(rdev->dev,
 244                         "Only allowed to allocate gart memory for kfd\n");
 245                 return -EINVAL;
 246         }
 247
 248         *mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
 249         if ((*mem) == NULL)
 250                 return -ENOMEM;
 251
 252         r = radeon_sa_bo_new(rdev, &rdev->kfd_bo, &(*mem)->sa_bo, size,
 253                                 alignment);
 254         if (r) {
 255                 dev_err(rdev->dev, "failed to get memory for kfd (%d)\n", r);
 256                 return r;
 257         }
 258
 259         (*mem)->ptr = radeon_sa_bo_cpu_addr((*mem)->sa_bo);
 260         (*mem)->gpu_addr = radeon_sa_bo_gpu_addr((*mem)->sa_bo);
 261
 262         return 0;
 263 }
 264
 265 static void free_mem(struct kgd_dev *kgd, struct kgd_mem *mem)
 266 {
 267         struct radeon_device *rdev = (struct radeon_device *)kgd;
 268
 269         BUG_ON(kgd == NULL);
 270
 271         radeon_sa_bo_free(rdev, &mem->sa_bo, NULL);
 272         kfree(mem);
 273 }
 274
 275 static uint64_t get_vmem_size(struct kgd_dev *kgd)
 276 {
 277         struct radeon_device *rdev = (struct radeon_device *)kgd;
 278
 279         BUG_ON(kgd == NULL);
 280
 281         return rdev->mc.real_vram_size;
 282 }
 283
 284 static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
 285 {
 286         struct radeon_device *rdev = (struct radeon_device *)kgd;
 287
 288         return rdev->asic->get_gpu_clock_counter(rdev);
 289 }
 290
 291 static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
 292 {
 293         struct radeon_device *rdev = (struct radeon_device *)kgd;
 294
 295         /* The sclk is in quantas of 10kHz */
 296         return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
 297 }
 298
 299 static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd)
 300 {
 301         return (struct radeon_device *)kgd;
 302 }
 303
 304 static void write_register(struct kgd_dev *kgd, uint32_t offset, uint32_t value)
 305 {
 306         struct radeon_device *rdev = get_radeon_device(kgd);
 307
 308         writel(value, (void __iomem *)(rdev->rmmio + offset));
 309 }
 310
 311 static uint32_t read_register(struct kgd_dev *kgd, uint32_t offset)
 312 {
 313         struct radeon_device *rdev = get_radeon_device(kgd);
 314
 315         return readl((void __iomem *)(rdev->rmmio + offset));
 316 }
 317
 318 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
 319                         uint32_t queue, uint32_t vmid)
 320 {
 321         struct radeon_device *rdev = get_radeon_device(kgd);
 322         uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
 323
 324         mutex_lock(&rdev->srbm_mutex);
 325         write_register(kgd, SRBM_GFX_CNTL, value);
 326 }
 327
 328 static void unlock_srbm(struct kgd_dev *kgd)
 329 {
 330         struct radeon_device *rdev = get_radeon_device(kgd);
 331
 332         write_register(kgd, SRBM_GFX_CNTL, 0);
 333         mutex_unlock(&rdev->srbm_mutex);
 334 }
 335
 336 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 337                                 uint32_t queue_id)
 338 {
 339         uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
 340         uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
 341
 342         lock_srbm(kgd, mec, pipe, queue_id, 0);
 343 }
 344
 345 static void release_queue(struct kgd_dev *kgd)
 346 {
 347         unlock_srbm(kgd);
 348 }
 349
 350 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 351                                         uint32_t sh_mem_config,
 352                                         uint32_t sh_mem_ape1_base,
 353                                         uint32_t sh_mem_ape1_limit,
 354                                         uint32_t sh_mem_bases)
 355 {
 356         lock_srbm(kgd, 0, 0, 0, vmid);
 357
 358         write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
 359         write_register(kgd, SH_MEM_APE1_BASE, sh_mem_ape1_base);
 360         write_register(kgd, SH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
 361         write_register(kgd, SH_MEM_BASES, sh_mem_bases);
 362
 363         unlock_srbm(kgd);
 364 }
 365
 366 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 367                                         unsigned int vmid)
 368 {
 369         /*
 370          * We have to assume that there is no outstanding mapping.
 371          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0
 372          * because a mapping is in progress or because a mapping finished and
 373          * the SW cleared it.
 374          * So the protocol is to always wait & clear.
 375          */
 376         uint32_t pasid_mapping = (pasid == 0) ? 0 :
 377                                 (uint32_t)pasid | ATC_VMID_PASID_MAPPING_VALID;
 378
 379         write_register(kgd, ATC_VMID0_PASID_MAPPING + vmid*sizeof(uint32_t),
 380                         pasid_mapping);
 381
 382         while (!(read_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS) &
 383                                                                 (1U << vmid)))
 384                 cpu_relax();
 385         write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
 386
 387         return 0;
 388 }
 389
 390 static int kgd_init_memory(struct kgd_dev *kgd)
 391 {
 392         /*
 393          * Configure apertures:
 394          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
 395          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
 396          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
 397          */
 398         int i;
 399         uint32_t sh_mem_bases = PRIVATE_BASE(0x6000) | SHARED_BASE(0x6000);
 400
 401         for (i = 8; i < 16; i++) {
 402                 uint32_t sh_mem_config;
 403
 404                 lock_srbm(kgd, 0, 0, 0, i);
 405
 406                 sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
 407                 sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);
 408
 409                 write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
 410
 411                 write_register(kgd, SH_MEM_BASES, sh_mem_bases);
 412
 413                 /* Scratch aperture is not supported for now. */
 414                 write_register(kgd, SH_STATIC_MEM_CONFIG, 0);
 415
 416                 /* APE1 disabled for now. */
 417                 write_register(kgd, SH_MEM_APE1_BASE, 1);
 418                 write_register(kgd, SH_MEM_APE1_LIMIT, 0);
 419
 420                 unlock_srbm(kgd);
 421         }
 422
 423         return 0;
 424 }
 425
 426 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
 427                                 uint32_t hpd_size, uint64_t hpd_gpu_addr)
 428 {
 429         uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
 430         uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
 431
 432         lock_srbm(kgd, mec, pipe, 0, 0);
 433         write_register(kgd, CP_HPD_EOP_BASE_ADDR,
 434                         lower_32_bits(hpd_gpu_addr >> 8));
 435         write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI,
 436                         upper_32_bits(hpd_gpu_addr >> 8));
 437         write_register(kgd, CP_HPD_EOP_VMID, 0);
 438         write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size);
 439         unlock_srbm(kgd);
 440
 441         return 0;
 442 }
 443
 444 static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
 445 {
 446         uint32_t retval;
 447
 448         retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
 449                         m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
 450
 451         pr_debug("kfd: sdma base address: 0x%x\n", retval);
 452
 453         return retval;
 454 }
 455
 456 static inline struct cik_mqd *get_mqd(void *mqd)
 457 {
 458         return (struct cik_mqd *)mqd;
 459 }
 460
 461 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
 462 {
 463         return (struct cik_sdma_rlc_registers *)mqd;
 464 }
 465
 466 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 467                         uint32_t queue_id, uint32_t __user *wptr)
 468 {
 469         uint32_t wptr_shadow, is_wptr_shadow_valid;
 470         struct cik_mqd *m;
 471
 472         m = get_mqd(mqd);
 473
 474         is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
 475
 476         acquire_queue(kgd, pipe_id, queue_id);
 477         write_register(kgd, CP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
 478         write_register(kgd, CP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
 479         write_register(kgd, CP_MQD_CONTROL, m->cp_mqd_control);
 480
 481         write_register(kgd, CP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
 482         write_register(kgd, CP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
 483         write_register(kgd, CP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
 484
 485         write_register(kgd, CP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
 486         write_register(kgd, CP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
 487         write_register(kgd, CP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
 488
 489         write_register(kgd, CP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
 490
 491         write_register(kgd, CP_HQD_PERSISTENT_STATE,
 492                         m->cp_hqd_persistent_state);
 493         write_register(kgd, CP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
 494         write_register(kgd, CP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
 495
 496         write_register(kgd, CP_HQD_ATOMIC0_PREOP_LO,
 497                         m->cp_hqd_atomic0_preop_lo);
 498
 499         write_register(kgd, CP_HQD_ATOMIC0_PREOP_HI,
 500                         m->cp_hqd_atomic0_preop_hi);
 501
 502         write_register(kgd, CP_HQD_ATOMIC1_PREOP_LO,
 503                         m->cp_hqd_atomic1_preop_lo);
 504
 505         write_register(kgd, CP_HQD_ATOMIC1_PREOP_HI,
 506                         m->cp_hqd_atomic1_preop_hi);
 507
 508         write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR,
 509                         m->cp_hqd_pq_rptr_report_addr_lo);
 510
 511         write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
 512                         m->cp_hqd_pq_rptr_report_addr_hi);
 513
 514         write_register(kgd, CP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
 515
 516         write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR,
 517                         m->cp_hqd_pq_wptr_poll_addr_lo);
 518
 519         write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR_HI,
 520                         m->cp_hqd_pq_wptr_poll_addr_hi);
 521
 522         write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL,
 523                         m->cp_hqd_pq_doorbell_control);
 524
 525         write_register(kgd, CP_HQD_VMID, m->cp_hqd_vmid);
 526
 527         write_register(kgd, CP_HQD_QUANTUM, m->cp_hqd_quantum);
 528
 529         write_register(kgd, CP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
 530         write_register(kgd, CP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
 531
 532         write_register(kgd, CP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
 533
 534         if (is_wptr_shadow_valid)
 535                 write_register(kgd, CP_HQD_PQ_WPTR, wptr_shadow);
 536
 537         write_register(kgd, CP_HQD_ACTIVE, m->cp_hqd_active);
 538         release_queue(kgd);
 539
 540         return 0;
 541 }
 542
 543 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
 544 {
 545         struct cik_sdma_rlc_registers *m;
 546         uint32_t sdma_base_addr;
 547
 548         m = get_sdma_mqd(mqd);
 549         sdma_base_addr = get_sdma_base_addr(m);
 550
 551         write_register(kgd,
 552                         sdma_base_addr + SDMA0_RLC0_VIRTUAL_ADDR,
 553                         m->sdma_rlc_virtual_addr);
 554
 555         write_register(kgd,
 556                         sdma_base_addr + SDMA0_RLC0_RB_BASE,
 557                         m->sdma_rlc_rb_base);
 558
 559         write_register(kgd,
 560                         sdma_base_addr + SDMA0_RLC0_RB_BASE_HI,
 561                         m->sdma_rlc_rb_base_hi);
 562
 563         write_register(kgd,
 564                         sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_LO,
 565                         m->sdma_rlc_rb_rptr_addr_lo);
 566
 567         write_register(kgd,
 568                         sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_HI,
 569                         m->sdma_rlc_rb_rptr_addr_hi);
 570
 571         write_register(kgd,
 572                         sdma_base_addr + SDMA0_RLC0_DOORBELL,
 573                         m->sdma_rlc_doorbell);
 574
 575         write_register(kgd,
 576                         sdma_base_addr + SDMA0_RLC0_RB_CNTL,
 577                         m->sdma_rlc_rb_cntl);
 578
 579         return 0;
 580 }
 581
 582 static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
 583                                 uint32_t pipe_id, uint32_t queue_id)
 584 {
 585         uint32_t act;
 586         bool retval = false;
 587         uint32_t low, high;
 588
 589         acquire_queue(kgd, pipe_id, queue_id);
 590         act = read_register(kgd, CP_HQD_ACTIVE);
 591         if (act) {
 592                 low = lower_32_bits(queue_address >> 8);
 593                 high = upper_32_bits(queue_address >> 8);
 594
 595                 if (low == read_register(kgd, CP_HQD_PQ_BASE) &&
 596                                 high == read_register(kgd, CP_HQD_PQ_BASE_HI))
 597                         retval = true;
 598         }
 599         release_queue(kgd);
 600         return retval;
 601 }
 602
 603 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 604 {
 605         struct cik_sdma_rlc_registers *m;
 606         uint32_t sdma_base_addr;
 607         uint32_t sdma_rlc_rb_cntl;
 608
 609         m = get_sdma_mqd(mqd);
 610         sdma_base_addr = get_sdma_base_addr(m);
 611
 612         sdma_rlc_rb_cntl = read_register(kgd,
 613                                         sdma_base_addr + SDMA0_RLC0_RB_CNTL);
 614
 615         if (sdma_rlc_rb_cntl & SDMA_RB_ENABLE)
 616                 return true;
 617
 618         return false;
 619 }
 620
 621 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
 622                                 unsigned int timeout, uint32_t pipe_id,
 623                                 uint32_t queue_id)
 624 {
 625         uint32_t temp;
 626
 627         acquire_queue(kgd, pipe_id, queue_id);
 628         write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL, 0);
 629
 630         write_register(kgd, CP_HQD_DEQUEUE_REQUEST, reset_type);
 631
 632         while (true) {
 633                 temp = read_register(kgd, CP_HQD_ACTIVE);
 634                 if (temp & 0x1)
 635                         break;
 636                 if (timeout == 0) {
 637                         pr_err("kfd: cp queue preemption time out (%dms)\n",
 638                                 temp);
 639                         return -ETIME;
 640                 }
 641                 msleep(20);
 642                 timeout -= 20;
 643         }
 644
 645         release_queue(kgd);
 646         return 0;
 647 }
 648
 649 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 650                                 unsigned int timeout)
 651 {
 652         struct cik_sdma_rlc_registers *m;
 653         uint32_t sdma_base_addr;
 654         uint32_t temp;
 655
 656         m = get_sdma_mqd(mqd);
 657         sdma_base_addr = get_sdma_base_addr(m);
 658
 659         temp = read_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL);
 660         temp = temp & ~SDMA_RB_ENABLE;
 661         write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL, temp);
 662
 663         while (true) {
 664                 temp = read_register(kgd, sdma_base_addr +
 665                                                 SDMA0_RLC0_CONTEXT_STATUS);
 666                 if (temp & SDMA_RLC_IDLE)
 667                         break;
 668                 if (timeout == 0)
 669                         return -ETIME;
 670                 msleep(20);
 671                 timeout -= 20;
 672         }
 673
 674         write_register(kgd, sdma_base_addr + SDMA0_RLC0_DOORBELL, 0);
 675         write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_RPTR, 0);
 676         write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_WPTR, 0);
 677         write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_BASE, 0);
 678
 679         return 0;
 680 }
 681
 682 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 683 {
 684         struct radeon_device *rdev = (struct radeon_device *) kgd;
 685         const union radeon_firmware_header *hdr;
 686
 687         BUG_ON(kgd == NULL || rdev->mec_fw == NULL);
 688
 689         switch (type) {
 690         case KGD_ENGINE_PFP:
 691                 hdr = (const union radeon_firmware_header *) rdev->pfp_fw->data;
 692                 break;
 693
 694         case KGD_ENGINE_ME:
 695                 hdr = (const union radeon_firmware_header *) rdev->me_fw->data;
 696                 break;
 697
 698         case KGD_ENGINE_CE:
 699                 hdr = (const union radeon_firmware_header *) rdev->ce_fw->data;
 700                 break;
 701
 702         case KGD_ENGINE_MEC1:
 703                 hdr = (const union radeon_firmware_header *) rdev->mec_fw->data;
 704                 break;
 705
 706         case KGD_ENGINE_MEC2:
 707                 hdr = (const union radeon_firmware_header *)
 708                                                         rdev->mec2_fw->data;
 709                 break;
 710
 711         case KGD_ENGINE_RLC:
 712                 hdr = (const union radeon_firmware_header *) rdev->rlc_fw->data;
 713                 break;
 714
 715         case KGD_ENGINE_SDMA:
 716                 hdr = (const union radeon_firmware_header *)
 717                                                         rdev->sdma_fw->data;
 718                 break;
 719
 720         default:
 721                 return 0;
 722         }
 723
 724         if (hdr == NULL)
 725                 return 0;
 726
 727         /* Only 12 bit in use*/
 728         return hdr->common.ucode_version;
 729 }