2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
35 bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
37 u8 out_buf[] = { 0x0, 0x0};
40 struct i2c_msg msgs[] = {
55 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
64 static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
66 struct radeon_device *rdev = i2c->dev->dev_private;
67 struct radeon_i2c_bus_rec *rec = &i2c->rec;
70 /* RV410 appears to have a bug where the hw i2c in reset
71 * holds the i2c port in a bad state - switch hw i2c away before
72 * doing DDC - do this for all r200s/r300s/r400s for safety sake
74 if (rec->hw_capable) {
75 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
78 if (rdev->family >= CHIP_RV350)
79 reg = RADEON_GPIO_MONID;
80 else if ((rdev->family == CHIP_R300) ||
81 (rdev->family == CHIP_R350))
82 reg = RADEON_GPIO_DVI_DDC;
84 reg = RADEON_GPIO_CRT2_DDC;
86 mutex_lock(&rdev->dc_hw_i2c_mutex);
87 if (rec->a_clk_reg == reg) {
88 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
89 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
91 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
92 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
94 mutex_unlock(&rdev->dc_hw_i2c_mutex);
98 /* clear the output pin values */
99 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
100 WREG32(rec->a_clk_reg, temp);
102 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
103 WREG32(rec->a_data_reg, temp);
105 /* set the pins to input */
106 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
107 WREG32(rec->en_clk_reg, temp);
109 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
110 WREG32(rec->en_data_reg, temp);
112 /* mask the gpio pins for software use */
113 temp = RREG32(rec->mask_clk_reg);
115 temp |= rec->mask_clk_mask;
117 temp &= ~rec->mask_clk_mask;
118 WREG32(rec->mask_clk_reg, temp);
119 temp = RREG32(rec->mask_clk_reg);
121 temp = RREG32(rec->mask_data_reg);
123 temp |= rec->mask_data_mask;
125 temp &= ~rec->mask_data_mask;
126 WREG32(rec->mask_data_reg, temp);
127 temp = RREG32(rec->mask_data_reg);
130 static int get_clock(void *i2c_priv)
132 struct radeon_i2c_chan *i2c = i2c_priv;
133 struct radeon_device *rdev = i2c->dev->dev_private;
134 struct radeon_i2c_bus_rec *rec = &i2c->rec;
137 /* read the value off the pin */
138 val = RREG32(rec->y_clk_reg);
139 val &= rec->y_clk_mask;
145 static int get_data(void *i2c_priv)
147 struct radeon_i2c_chan *i2c = i2c_priv;
148 struct radeon_device *rdev = i2c->dev->dev_private;
149 struct radeon_i2c_bus_rec *rec = &i2c->rec;
152 /* read the value off the pin */
153 val = RREG32(rec->y_data_reg);
154 val &= rec->y_data_mask;
159 static void set_clock(void *i2c_priv, int clock)
161 struct radeon_i2c_chan *i2c = i2c_priv;
162 struct radeon_device *rdev = i2c->dev->dev_private;
163 struct radeon_i2c_bus_rec *rec = &i2c->rec;
166 /* set pin direction */
167 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
168 val |= clock ? 0 : rec->en_clk_mask;
169 WREG32(rec->en_clk_reg, val);
172 static void set_data(void *i2c_priv, int data)
174 struct radeon_i2c_chan *i2c = i2c_priv;
175 struct radeon_device *rdev = i2c->dev->dev_private;
176 struct radeon_i2c_bus_rec *rec = &i2c->rec;
179 /* set pin direction */
180 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
181 val |= data ? 0 : rec->en_data_mask;
182 WREG32(rec->en_data_reg, val);
185 static int pre_xfer(struct i2c_adapter *i2c_adap)
187 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
189 radeon_i2c_do_lock(i2c, 1);
194 static void post_xfer(struct i2c_adapter *i2c_adap)
196 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
198 radeon_i2c_do_lock(i2c, 0);
203 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
205 u32 sclk = radeon_get_engine_clock(rdev);
211 switch (rdev->family) {
225 nm = (sclk * 10) / (i2c_clock * 4);
226 for (loop = 1; loop < 255; loop++) {
227 if ((nm / loop) < loop)
232 prescale = m | (n << 8);
240 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
254 if (rdev->family == CHIP_R520)
255 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
257 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
283 DRM_ERROR("i2c: unhandled radeon chip\n");
290 /* hw i2c engine for r1xx-4xx hardware
291 * hw can buffer up to 15 bytes
293 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
294 struct i2c_msg *msgs, int num)
296 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
297 struct radeon_device *rdev = i2c->dev->dev_private;
298 struct radeon_i2c_bus_rec *rec = &i2c->rec;
300 int i, j, k, ret = num;
302 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
305 mutex_lock(&rdev->dc_hw_i2c_mutex);
306 /* take the pm lock since we need a constant sclk */
307 mutex_lock(&rdev->pm.mutex);
309 prescale = radeon_get_i2c_prescale(rdev);
311 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
312 RADEON_I2C_DRIVE_EN |
317 if (rdev->is_atom_bios) {
318 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
319 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
323 i2c_cntl_0 = RADEON_I2C_CNTL_0;
324 i2c_cntl_1 = RADEON_I2C_CNTL_1;
325 i2c_data = RADEON_I2C_DATA;
327 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
328 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
329 i2c_data = RADEON_DVI_I2C_DATA;
331 switch (rdev->family) {
338 switch (rec->mask_clk_reg) {
339 case RADEON_GPIO_DVI_DDC:
340 /* no gpio select bit */
343 DRM_ERROR("gpio not supported with hw i2c\n");
349 /* only bit 4 on r200 */
350 switch (rec->mask_clk_reg) {
351 case RADEON_GPIO_DVI_DDC:
352 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
354 case RADEON_GPIO_MONID:
355 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
358 DRM_ERROR("gpio not supported with hw i2c\n");
366 switch (rec->mask_clk_reg) {
367 case RADEON_GPIO_DVI_DDC:
368 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
370 case RADEON_GPIO_VGA_DDC:
371 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
373 case RADEON_GPIO_CRT2_DDC:
374 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
377 DRM_ERROR("gpio not supported with hw i2c\n");
384 /* only bit 4 on r300/r350 */
385 switch (rec->mask_clk_reg) {
386 case RADEON_GPIO_VGA_DDC:
387 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
389 case RADEON_GPIO_DVI_DDC:
390 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
393 DRM_ERROR("gpio not supported with hw i2c\n");
406 switch (rec->mask_clk_reg) {
407 case RADEON_GPIO_VGA_DDC:
408 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
410 case RADEON_GPIO_DVI_DDC:
411 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
413 case RADEON_GPIO_MONID:
414 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
417 DRM_ERROR("gpio not supported with hw i2c\n");
423 DRM_ERROR("unsupported asic\n");
430 /* check for bus probe */
432 if ((num == 1) && (p->len == 0)) {
433 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
436 RADEON_I2C_SOFT_RST));
437 WREG32(i2c_data, (p->addr << 1) & 0xff);
439 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
440 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
442 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
443 WREG32(i2c_cntl_0, reg);
444 for (k = 0; k < 32; k++) {
446 tmp = RREG32(i2c_cntl_0);
447 if (tmp & RADEON_I2C_GO)
449 tmp = RREG32(i2c_cntl_0);
450 if (tmp & RADEON_I2C_DONE)
453 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
454 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
462 for (i = 0; i < num; i++) {
464 for (j = 0; j < p->len; j++) {
465 if (p->flags & I2C_M_RD) {
466 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
469 RADEON_I2C_SOFT_RST));
470 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
471 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
472 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
474 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
475 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
476 for (k = 0; k < 32; k++) {
478 tmp = RREG32(i2c_cntl_0);
479 if (tmp & RADEON_I2C_GO)
481 tmp = RREG32(i2c_cntl_0);
482 if (tmp & RADEON_I2C_DONE)
485 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
486 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
491 p->buf[j] = RREG32(i2c_data) & 0xff;
493 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
496 RADEON_I2C_SOFT_RST));
497 WREG32(i2c_data, (p->addr << 1) & 0xff);
498 WREG32(i2c_data, p->buf[j]);
499 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
500 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
502 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
503 WREG32(i2c_cntl_0, reg);
504 for (k = 0; k < 32; k++) {
506 tmp = RREG32(i2c_cntl_0);
507 if (tmp & RADEON_I2C_GO)
509 tmp = RREG32(i2c_cntl_0);
510 if (tmp & RADEON_I2C_DONE)
513 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
514 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
524 WREG32(i2c_cntl_0, 0);
525 WREG32(i2c_cntl_1, 0);
526 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
529 RADEON_I2C_SOFT_RST));
531 if (rdev->is_atom_bios) {
532 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
533 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
534 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
537 mutex_unlock(&rdev->pm.mutex);
538 mutex_unlock(&rdev->dc_hw_i2c_mutex);
543 /* hw i2c engine for r5xx hardware
544 * hw can buffer up to 15 bytes
546 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
547 struct i2c_msg *msgs, int num)
549 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
550 struct radeon_device *rdev = i2c->dev->dev_private;
551 struct radeon_i2c_bus_rec *rec = &i2c->rec;
553 int i, j, remaining, current_count, buffer_offset, ret = num;
558 mutex_lock(&rdev->dc_hw_i2c_mutex);
559 /* take the pm lock since we need a constant sclk */
560 mutex_lock(&rdev->pm.mutex);
562 prescale = radeon_get_i2c_prescale(rdev);
564 /* clear gpio mask bits */
565 tmp = RREG32(rec->mask_clk_reg);
566 tmp &= ~rec->mask_clk_mask;
567 WREG32(rec->mask_clk_reg, tmp);
568 tmp = RREG32(rec->mask_clk_reg);
570 tmp = RREG32(rec->mask_data_reg);
571 tmp &= ~rec->mask_data_mask;
572 WREG32(rec->mask_data_reg, tmp);
573 tmp = RREG32(rec->mask_data_reg);
575 /* clear pin values */
576 tmp = RREG32(rec->a_clk_reg);
577 tmp &= ~rec->a_clk_mask;
578 WREG32(rec->a_clk_reg, tmp);
579 tmp = RREG32(rec->a_clk_reg);
581 tmp = RREG32(rec->a_data_reg);
582 tmp &= ~rec->a_data_mask;
583 WREG32(rec->a_data_reg, tmp);
584 tmp = RREG32(rec->a_data_reg);
586 /* set the pins to input */
587 tmp = RREG32(rec->en_clk_reg);
588 tmp &= ~rec->en_clk_mask;
589 WREG32(rec->en_clk_reg, tmp);
590 tmp = RREG32(rec->en_clk_reg);
592 tmp = RREG32(rec->en_data_reg);
593 tmp &= ~rec->en_data_mask;
594 WREG32(rec->en_data_reg, tmp);
595 tmp = RREG32(rec->en_data_reg);
598 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
599 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
600 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
601 saved2 = RREG32(0x494);
602 WREG32(0x494, saved2 | 0x1);
604 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
605 for (i = 0; i < 50; i++) {
607 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
611 DRM_ERROR("failed to get i2c bus\n");
616 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
617 switch (rec->mask_clk_reg) {
618 case AVIVO_DC_GPIO_DDC1_MASK:
619 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
621 case AVIVO_DC_GPIO_DDC2_MASK:
622 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
624 case AVIVO_DC_GPIO_DDC3_MASK:
625 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
628 DRM_ERROR("gpio not supported with hw i2c\n");
633 /* check for bus probe */
635 if ((num == 1) && (p->len == 0)) {
636 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
639 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
641 WREG32(AVIVO_DC_I2C_RESET, 0);
643 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
644 WREG32(AVIVO_DC_I2C_DATA, 0);
646 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
647 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
648 AVIVO_DC_I2C_DATA_COUNT(1) |
650 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
651 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
652 for (j = 0; j < 200; j++) {
654 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
655 if (tmp & AVIVO_DC_I2C_GO)
657 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
658 if (tmp & AVIVO_DC_I2C_DONE)
661 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
662 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
670 for (i = 0; i < num; i++) {
674 if (p->flags & I2C_M_RD) {
679 current_count = remaining;
680 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
683 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
685 WREG32(AVIVO_DC_I2C_RESET, 0);
687 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
688 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
689 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
690 AVIVO_DC_I2C_DATA_COUNT(current_count) |
692 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
693 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
694 for (j = 0; j < 200; j++) {
696 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
697 if (tmp & AVIVO_DC_I2C_GO)
699 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
700 if (tmp & AVIVO_DC_I2C_DONE)
703 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
704 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
709 for (j = 0; j < current_count; j++)
710 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
711 remaining -= current_count;
712 buffer_offset += current_count;
719 current_count = remaining;
720 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
723 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
725 WREG32(AVIVO_DC_I2C_RESET, 0);
727 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
728 for (j = 0; j < current_count; j++)
729 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
731 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
732 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
733 AVIVO_DC_I2C_DATA_COUNT(current_count) |
735 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
736 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
737 for (j = 0; j < 200; j++) {
739 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
740 if (tmp & AVIVO_DC_I2C_GO)
742 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
743 if (tmp & AVIVO_DC_I2C_DONE)
746 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
747 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
752 remaining -= current_count;
753 buffer_offset += current_count;
759 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
762 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
764 WREG32(AVIVO_DC_I2C_RESET, 0);
766 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
767 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
768 WREG32(0x494, saved2);
769 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
770 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
771 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
773 mutex_unlock(&rdev->pm.mutex);
774 mutex_unlock(&rdev->dc_hw_i2c_mutex);
779 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
780 struct i2c_msg *msgs, int num)
782 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
783 struct radeon_device *rdev = i2c->dev->dev_private;
784 struct radeon_i2c_bus_rec *rec = &i2c->rec;
787 switch (rdev->family) {
806 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
811 /* XXX fill in hw i2c implementation */
820 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
822 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
828 /* XXX fill in hw i2c implementation */
838 /* XXX fill in hw i2c implementation */
845 /* XXX fill in hw i2c implementation */
848 DRM_ERROR("i2c: unhandled radeon chip\n");
856 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
858 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
861 static const struct i2c_algorithm radeon_i2c_algo = {
862 .master_xfer = radeon_hw_i2c_xfer,
863 .functionality = radeon_hw_i2c_func,
866 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
867 struct radeon_i2c_bus_rec *rec,
870 struct radeon_device *rdev = dev->dev_private;
871 struct radeon_i2c_chan *i2c;
874 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
879 i2c->adapter.owner = THIS_MODULE;
881 i2c_set_adapdata(&i2c->adapter, i2c);
885 ((rdev->family <= CHIP_RS480) ||
886 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
887 /* set the radeon hw i2c adapter */
888 sprintf(i2c->adapter.name, "Radeon i2c hw bus %s", name);
889 i2c->adapter.algo = &radeon_i2c_algo;
890 ret = i2c_add_adapter(&i2c->adapter);
892 DRM_ERROR("Failed to register hw i2c %s\n", name);
896 /* set the radeon bit adapter */
897 sprintf(i2c->adapter.name, "Radeon i2c bit bus %s", name);
898 i2c->adapter.algo_data = &i2c->algo.bit;
899 i2c->algo.bit.pre_xfer = pre_xfer;
900 i2c->algo.bit.post_xfer = post_xfer;
901 i2c->algo.bit.setsda = set_data;
902 i2c->algo.bit.setscl = set_clock;
903 i2c->algo.bit.getsda = get_data;
904 i2c->algo.bit.getscl = get_clock;
905 i2c->algo.bit.udelay = 20;
906 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
907 * make this, 2 jiffies is a lot more reliable */
908 i2c->algo.bit.timeout = 2;
909 i2c->algo.bit.data = i2c;
910 ret = i2c_bit_add_bus(&i2c->adapter);
912 DRM_ERROR("Failed to register bit i2c %s\n", name);
924 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
925 struct radeon_i2c_bus_rec *rec,
928 struct radeon_i2c_chan *i2c;
931 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
936 i2c->adapter.owner = THIS_MODULE;
938 i2c_set_adapdata(&i2c->adapter, i2c);
939 i2c->adapter.algo_data = &i2c->algo.dp;
940 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
941 i2c->algo.dp.address = 0;
942 ret = i2c_dp_aux_add_bus(&i2c->adapter);
944 DRM_INFO("Failed to register i2c %s\n", name);
955 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
959 i2c_del_adapter(&i2c->adapter);
963 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
968 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
975 struct i2c_msg msgs[] = {
993 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
995 DRM_DEBUG("val = 0x%02x\n", *val);
997 DRM_ERROR("i2c 0x%02x 0x%02x read failed\n",
1002 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1008 struct i2c_msg msg = {
1018 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1019 DRM_ERROR("i2c 0x%02x 0x%02x write failed\n",