2 * Copyright 2015 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Dave Airlie
25 #include <drm/radeon_drm.h>
29 #define AUX_RX_ERROR_FLAGS (AUX_SW_RX_OVERFLOW | \
30 AUX_SW_RX_HPD_DISCON | \
31 AUX_SW_RX_PARTIAL_BYTE | \
32 AUX_SW_NON_AUX_MODE | \
33 AUX_SW_RX_SYNC_INVALID_L | \
34 AUX_SW_RX_SYNC_INVALID_H | \
35 AUX_SW_RX_INVALID_START | \
36 AUX_SW_RX_RECV_NO_DET | \
37 AUX_SW_RX_RECV_INVALID_H | \
38 AUX_SW_RX_RECV_INVALID_V)
40 #define AUX_SW_REPLY_GET_BYTE_COUNT(x) (((x) >> 24) & 0x1f)
42 #define BARE_ADDRESS_SIZE 3
44 static const u32 aux_offset[] =
55 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
57 struct radeon_i2c_chan *chan =
58 container_of(aux, struct radeon_i2c_chan, aux);
59 struct drm_device *dev = chan->dev;
60 struct radeon_device *rdev = dev->dev_private;
62 uint32_t tmp, ack = 0;
63 int instance = chan->rec.i2c_id & 0xf;
65 u8 *buf = msg->buffer;
69 bool is_write = false;
71 if (WARN_ON(msg->size > 16))
74 switch (msg->request & ~DP_AUX_I2C_MOT) {
75 case DP_AUX_NATIVE_WRITE:
76 case DP_AUX_I2C_WRITE:
79 case DP_AUX_NATIVE_READ:
86 /* work out two sizes required */
88 bytes = BARE_ADDRESS_SIZE;
90 msize = msg->size - 1;
96 mutex_lock(&chan->mutex);
98 /* switch the pad to aux mode */
99 tmp = RREG32(chan->rec.mask_clk_reg);
101 WREG32(chan->rec.mask_clk_reg, tmp);
103 /* setup AUX control register with correct HPD pin */
104 tmp = RREG32(AUX_CONTROL + aux_offset[instance]);
106 tmp &= AUX_HPD_SEL(0x7);
107 tmp |= AUX_HPD_SEL(chan->rec.hpd);
108 tmp |= AUX_EN | AUX_LS_READ_EN;
110 WREG32(AUX_CONTROL + aux_offset[instance], tmp);
112 /* atombios appears to write this twice lets copy it */
113 WREG32(AUX_SW_CONTROL + aux_offset[instance],
114 AUX_SW_WR_BYTES(bytes));
115 WREG32(AUX_SW_CONTROL + aux_offset[instance],
116 AUX_SW_WR_BYTES(bytes));
118 /* write the data header into the registers */
119 /* request, address, msg size */
120 byte = (msg->request << 4) | ((msg->address >> 16) & 0xf);
121 WREG32(AUX_SW_DATA + aux_offset[instance],
122 AUX_SW_DATA_MASK(byte) | AUX_SW_AUTOINCREMENT_DISABLE);
124 byte = (msg->address >> 8) & 0xff;
125 WREG32(AUX_SW_DATA + aux_offset[instance],
126 AUX_SW_DATA_MASK(byte));
128 byte = msg->address & 0xff;
129 WREG32(AUX_SW_DATA + aux_offset[instance],
130 AUX_SW_DATA_MASK(byte));
133 WREG32(AUX_SW_DATA + aux_offset[instance],
134 AUX_SW_DATA_MASK(byte));
136 /* if we are writing - write the msg buffer */
138 for (i = 0; i < msg->size; i++) {
139 WREG32(AUX_SW_DATA + aux_offset[instance],
140 AUX_SW_DATA_MASK(buf[i]));
145 WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK);
147 /* write the size and GO bits */
148 WREG32(AUX_SW_CONTROL + aux_offset[instance],
149 AUX_SW_WR_BYTES(bytes) | AUX_SW_GO);
151 /* poll the status registers - TODO irq support */
153 tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]);
154 if (tmp & AUX_SW_DONE) {
157 usleep_range(100, 200);
158 } while (retry_count++ < 1000);
160 if (retry_count >= 1000) {
161 DRM_ERROR("auxch hw never signalled completion, error %08x\n", tmp);
166 if (tmp & AUX_SW_RX_TIMEOUT) {
167 DRM_DEBUG_KMS("dp_aux_ch timed out\n");
171 if (tmp & AUX_RX_ERROR_FLAGS) {
172 DRM_DEBUG_KMS("dp_aux_ch flags not zero: %08x\n", tmp);
177 bytes = AUX_SW_REPLY_GET_BYTE_COUNT(tmp);
179 WREG32(AUX_SW_DATA + aux_offset[instance],
180 AUX_SW_DATA_RW | AUX_SW_AUTOINCREMENT_DISABLE);
182 tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
183 ack = (tmp >> 8) & 0xff;
185 for (i = 0; i < bytes - 1; i++) {
186 tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
188 buf[i] = (tmp >> 8) & 0xff;
194 WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK);
199 mutex_unlock(&chan->mutex);
202 msg->reply = ack >> 4;