drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_plane_helper.h>
  36 #include <drm/drm_edid.h>
  37
  38 #include <linux/gcd.h>
  39
  40 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  41 {
  42         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  43         struct drm_device *dev = crtc->dev;
  44         struct radeon_device *rdev = dev->dev_private;
  45         int i;
  46
  47         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  48         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  49
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  52         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  53
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  56         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  57
  58         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  59         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  60         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  61
  62         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  63         for (i = 0; i < 256; i++) {
  64                 WREG32(AVIVO_DC_LUT_30_COLOR,
  65                              (radeon_crtc->lut_r[i] << 20) |
  66                              (radeon_crtc->lut_g[i] << 10) |
  67                              (radeon_crtc->lut_b[i] << 0));
  68         }
  69
  70         /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
  71         WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
  72 }
  73
  74 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  75 {
  76         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  77         struct drm_device *dev = crtc->dev;
  78         struct radeon_device *rdev = dev->dev_private;
  79         int i;
  80
  81         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  82         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  83
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  85         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  86         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  87
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  89         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  90         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  91
  92         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  93         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  94
  95         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  96         for (i = 0; i < 256; i++) {
  97                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  98                        (radeon_crtc->lut_r[i] << 20) |
  99                        (radeon_crtc->lut_g[i] << 10) |
 100                        (radeon_crtc->lut_b[i] << 0));
 101         }
 102 }
 103
 104 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 105 {
 106         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 107         struct drm_device *dev = crtc->dev;
 108         struct radeon_device *rdev = dev->dev_private;
 109         int i;
 110
 111         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 112
 113         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 114                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 115                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 116         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 117                NI_GRPH_PRESCALE_BYPASS);
 118         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 119                NI_OVL_PRESCALE_BYPASS);
 120         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 121                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 122                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 123
 124         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 125
 126         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 127         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 128         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 129
 130         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 131         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 132         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 133
 134         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 135         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 136
 137         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 138         for (i = 0; i < 256; i++) {
 139                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 140                        (radeon_crtc->lut_r[i] << 20) |
 141                        (radeon_crtc->lut_g[i] << 10) |
 142                        (radeon_crtc->lut_b[i] << 0));
 143         }
 144
 145         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 146                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 147                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 148                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 149                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 150         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 151                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 152                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 153         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 154                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 155                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 156         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 157                (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
 158                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 159         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 160         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 161         if (ASIC_IS_DCE8(rdev)) {
 162                 /* XXX this only needs to be programmed once per crtc at startup,
 163                  * not sure where the best place for it is
 164                  */
 165                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 166                        CIK_CURSOR_ALPHA_BLND_ENA);
 167         }
 168 }
 169
 170 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 171 {
 172         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 173         struct drm_device *dev = crtc->dev;
 174         struct radeon_device *rdev = dev->dev_private;
 175         int i;
 176         uint32_t dac2_cntl;
 177
 178         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 179         if (radeon_crtc->crtc_id == 0)
 180                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 181         else
 182                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 183         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 184
 185         WREG8(RADEON_PALETTE_INDEX, 0);
 186         for (i = 0; i < 256; i++) {
 187                 WREG32(RADEON_PALETTE_30_DATA,
 188                              (radeon_crtc->lut_r[i] << 20) |
 189                              (radeon_crtc->lut_g[i] << 10) |
 190                              (radeon_crtc->lut_b[i] << 0));
 191         }
 192 }
 193
 194 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 195 {
 196         struct drm_device *dev = crtc->dev;
 197         struct radeon_device *rdev = dev->dev_private;
 198
 199         if (!crtc->enabled)
 200                 return;
 201
 202         if (ASIC_IS_DCE5(rdev))
 203                 dce5_crtc_load_lut(crtc);
 204         else if (ASIC_IS_DCE4(rdev))
 205                 dce4_crtc_load_lut(crtc);
 206         else if (ASIC_IS_AVIVO(rdev))
 207                 avivo_crtc_load_lut(crtc);
 208         else
 209                 legacy_crtc_load_lut(crtc);
 210 }
 211
 212 /** Sets the color ramps on behalf of fbcon */
 213 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 214                               u16 blue, int regno)
 215 {
 216         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 217
 218         radeon_crtc->lut_r[regno] = red >> 6;
 219         radeon_crtc->lut_g[regno] = green >> 6;
 220         radeon_crtc->lut_b[regno] = blue >> 6;
 221 }
 222
 223 /** Gets the color ramps on behalf of fbcon */
 224 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 225                               u16 *blue, int regno)
 226 {
 227         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 228
 229         *red = radeon_crtc->lut_r[regno] << 6;
 230         *green = radeon_crtc->lut_g[regno] << 6;
 231         *blue = radeon_crtc->lut_b[regno] << 6;
 232 }
 233
 234 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 235                                   u16 *blue, uint32_t start, uint32_t size)
 236 {
 237         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 238         int end = (start + size > 256) ? 256 : start + size, i;
 239
 240         /* userspace palettes are always correct as is */
 241         for (i = start; i < end; i++) {
 242                 radeon_crtc->lut_r[i] = red[i] >> 6;
 243                 radeon_crtc->lut_g[i] = green[i] >> 6;
 244                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 245         }
 246         radeon_crtc_load_lut(crtc);
 247 }
 248
 249 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 250 {
 251         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 252
 253         drm_crtc_cleanup(crtc);
 254         destroy_workqueue(radeon_crtc->flip_queue);
 255         kfree(radeon_crtc);
 256 }
 257
 258 /**
 259  * radeon_unpin_work_func - unpin old buffer object
 260  *
 261  * @__work - kernel work item
 262  *
 263  * Unpin the old frame buffer object outside of the interrupt handler
 264  */
 265 static void radeon_unpin_work_func(struct work_struct *__work)
 266 {
 267         struct radeon_flip_work *work =
 268                 container_of(__work, struct radeon_flip_work, unpin_work);
 269         int r;
 270
 271         /* unpin of the old buffer */
 272         r = radeon_bo_reserve(work->old_rbo, false);
 273         if (likely(r == 0)) {
 274                 r = radeon_bo_unpin(work->old_rbo);
 275                 if (unlikely(r != 0)) {
 276                         DRM_ERROR("failed to unpin buffer after flip\n");
 277                 }
 278                 radeon_bo_unreserve(work->old_rbo);
 279         } else
 280                 DRM_ERROR("failed to reserve buffer after flip\n");
 281
 282         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 283         kfree(work);
 284 }
 285
 286 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
 287 {
 288         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 289         unsigned long flags;
 290         u32 update_pending;
 291         int vpos, hpos;
 292
 293         /* can happen during initialization */
 294         if (radeon_crtc == NULL)
 295                 return;
 296
 297         /* Skip the pageflip completion check below (based on polling) on
 298          * asics which reliably support hw pageflip completion irqs. pflip
 299          * irqs are a reliable and race-free method of handling pageflip
 300          * completion detection. A use_pflipirq module parameter < 2 allows
 301          * to override this in case of asics with faulty pflip irqs.
 302          * A module parameter of 0 would only use this polling based path,
 303          * a parameter of 1 would use pflip irq only as a backup to this
 304          * path, as in Linux 3.16.
 305          */
 306         if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
 307                 return;
 308
 309         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 310         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 311                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 312                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 313                                  radeon_crtc->flip_status,
 314                                  RADEON_FLIP_SUBMITTED);
 315                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 316                 return;
 317         }
 318
 319         update_pending = radeon_page_flip_pending(rdev, crtc_id);
 320
 321         /* Has the pageflip already completed in crtc, or is it certain
 322          * to complete in this vblank?
 323          */
 324         if (update_pending &&
 325             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
 326                                                                &vpos, &hpos, NULL, NULL,
 327                                                                &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
 328             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 329              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 330                 /* crtc didn't flip in this target vblank interval,
 331                  * but flip is pending in crtc. Based on the current
 332                  * scanout position we know that the current frame is
 333                  * (nearly) complete and the flip will (likely)
 334                  * complete before the start of the next frame.
 335                  */
 336                 update_pending = 0;
 337         }
 338         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 339         if (!update_pending)
 340                 radeon_crtc_handle_flip(rdev, crtc_id);
 341 }
 342
 343 /**
 344  * radeon_crtc_handle_flip - page flip completed
 345  *
 346  * @rdev: radeon device pointer
 347  * @crtc_id: crtc number this event is for
 348  *
 349  * Called when we are sure that a page flip for this crtc is completed.
 350  */
 351 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 352 {
 353         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 354         struct radeon_flip_work *work;
 355         unsigned long flags;
 356
 357         /* this can happen at init */
 358         if (radeon_crtc == NULL)
 359                 return;
 360
 361         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 362         work = radeon_crtc->flip_work;
 363         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 364                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 365                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 366                                  radeon_crtc->flip_status,
 367                                  RADEON_FLIP_SUBMITTED);
 368                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 369                 return;
 370         }
 371
 372         /* Pageflip completed. Clean up. */
 373         radeon_crtc->flip_status = RADEON_FLIP_NONE;
 374         radeon_crtc->flip_work = NULL;
 375
 376         /* wakeup userspace */
 377         if (work->event)
 378                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 379
 380         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 381
 382         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 383         radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
 384         queue_work(radeon_crtc->flip_queue, &work->unpin_work);
 385 }
 386
 387 /**
 388  * radeon_flip_work_func - page flip framebuffer
 389  *
 390  * @work - kernel work item
 391  *
 392  * Wait for the buffer object to become idle and do the actual page flip
 393  */
 394 static void radeon_flip_work_func(struct work_struct *__work)
 395 {
 396         struct radeon_flip_work *work =
 397                 container_of(__work, struct radeon_flip_work, flip_work);
 398         struct radeon_device *rdev = work->rdev;
 399         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
 400
 401         struct drm_crtc *crtc = &radeon_crtc->base;
 402         unsigned long flags;
 403         int r;
 404
 405         down_read(&rdev->exclusive_lock);
 406         if (work->fence) {
 407                 struct radeon_fence *fence;
 408
 409                 fence = to_radeon_fence(work->fence);
 410                 if (fence && fence->rdev == rdev) {
 411                         r = radeon_fence_wait(fence, false);
 412                         if (r == -EDEADLK) {
 413                                 up_read(&rdev->exclusive_lock);
 414                                 do {
 415                                         r = radeon_gpu_reset(rdev);
 416                                 } while (r == -EAGAIN);
 417                                 down_read(&rdev->exclusive_lock);
 418                         }
 419                 } else
 420                         r = fence_wait(work->fence, false);
 421
 422                 if (r)
 423                         DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
 424
 425                 /* We continue with the page flip even if we failed to wait on
 426                  * the fence, otherwise the DRM core and userspace will be
 427                  * confused about which BO the CRTC is scanning out
 428                  */
 429
 430                 fence_put(work->fence);
 431                 work->fence = NULL;
 432         }
 433
 434         /* We borrow the event spin lock for protecting flip_status */
 435         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 436
 437         /* set the proper interrupt */
 438         radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
 439
 440         /* do the flip (mmio) */
 441         radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base);
 442
 443         radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
 444         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 445         up_read(&rdev->exclusive_lock);
 446 }
 447
 448 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 449                                  struct drm_framebuffer *fb,
 450                                  struct drm_pending_vblank_event *event,
 451                                  uint32_t page_flip_flags)
 452 {
 453         struct drm_device *dev = crtc->dev;
 454         struct radeon_device *rdev = dev->dev_private;
 455         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 456         struct radeon_framebuffer *old_radeon_fb;
 457         struct radeon_framebuffer *new_radeon_fb;
 458         struct drm_gem_object *obj;
 459         struct radeon_flip_work *work;
 460         struct radeon_bo *new_rbo;
 461         uint32_t tiling_flags, pitch_pixels;
 462         uint64_t base;
 463         unsigned long flags;
 464         int r;
 465
 466         work = kzalloc(sizeof *work, GFP_KERNEL);
 467         if (work == NULL)
 468                 return -ENOMEM;
 469
 470         INIT_WORK(&work->flip_work, radeon_flip_work_func);
 471         INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
 472
 473         work->rdev = rdev;
 474         work->crtc_id = radeon_crtc->crtc_id;
 475         work->event = event;
 476
 477         /* schedule unpin of the old buffer */
 478         old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 479         obj = old_radeon_fb->obj;
 480
 481         /* take a reference to the old object */
 482         drm_gem_object_reference(obj);
 483         work->old_rbo = gem_to_radeon_bo(obj);
 484
 485         new_radeon_fb = to_radeon_framebuffer(fb);
 486         obj = new_radeon_fb->obj;
 487         new_rbo = gem_to_radeon_bo(obj);
 488
 489         /* pin the new buffer */
 490         DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
 491                          work->old_rbo, new_rbo);
 492
 493         r = radeon_bo_reserve(new_rbo, false);
 494         if (unlikely(r != 0)) {
 495                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 496                 goto cleanup;
 497         }
 498         /* Only 27 bit offset for legacy CRTC */
 499         r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
 500                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 501         if (unlikely(r != 0)) {
 502                 radeon_bo_unreserve(new_rbo);
 503                 r = -EINVAL;
 504                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 505                 goto cleanup;
 506         }
 507         work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
 508         radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
 509         radeon_bo_unreserve(new_rbo);
 510
 511         if (!ASIC_IS_AVIVO(rdev)) {
 512                 /* crtc offset is from display base addr not FB location */
 513                 base -= radeon_crtc->legacy_display_base_addr;
 514                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 515
 516                 if (tiling_flags & RADEON_TILING_MACRO) {
 517                         if (ASIC_IS_R300(rdev)) {
 518                                 base &= ~0x7ff;
 519                         } else {
 520                                 int byteshift = fb->bits_per_pixel >> 4;
 521                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 522                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 523                         }
 524                 } else {
 525                         int offset = crtc->y * pitch_pixels + crtc->x;
 526                         switch (fb->bits_per_pixel) {
 527                         case 8:
 528                         default:
 529                                 offset *= 1;
 530                                 break;
 531                         case 15:
 532                         case 16:
 533                                 offset *= 2;
 534                                 break;
 535                         case 24:
 536                                 offset *= 3;
 537                                 break;
 538                         case 32:
 539                                 offset *= 4;
 540                                 break;
 541                         }
 542                         base += offset;
 543                 }
 544                 base &= ~7;
 545         }
 546         work->base = base;
 547
 548         r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
 549         if (r) {
 550                 DRM_ERROR("failed to get vblank before flip\n");
 551                 goto pflip_cleanup;
 552         }
 553
 554         /* We borrow the event spin lock for protecting flip_work */
 555         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 556
 557         if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
 558                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 559                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 560                 r = -EBUSY;
 561                 goto vblank_cleanup;
 562         }
 563         radeon_crtc->flip_status = RADEON_FLIP_PENDING;
 564         radeon_crtc->flip_work = work;
 565
 566         /* update crtc fb */
 567         crtc->primary->fb = fb;
 568
 569         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 570
 571         queue_work(radeon_crtc->flip_queue, &work->flip_work);
 572         return 0;
 573
 574 vblank_cleanup:
 575         drm_vblank_put(crtc->dev, radeon_crtc->crtc_id);
 576
 577 pflip_cleanup:
 578         if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
 579                 DRM_ERROR("failed to reserve new rbo in error path\n");
 580                 goto cleanup;
 581         }
 582         if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
 583                 DRM_ERROR("failed to unpin new rbo in error path\n");
 584         }
 585         radeon_bo_unreserve(new_rbo);
 586
 587 cleanup:
 588         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 589         fence_put(work->fence);
 590         kfree(work);
 591         return r;
 592 }
 593
 594 static int
 595 radeon_crtc_set_config(struct drm_mode_set *set)
 596 {
 597         struct drm_device *dev;
 598         struct radeon_device *rdev;
 599         struct drm_crtc *crtc;
 600         bool active = false;
 601         int ret;
 602
 603         if (!set || !set->crtc)
 604                 return -EINVAL;
 605
 606         dev = set->crtc->dev;
 607
 608         ret = pm_runtime_get_sync(dev->dev);
 609         if (ret < 0)
 610                 return ret;
 611
 612         ret = drm_crtc_helper_set_config(set);
 613
 614         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 615                 if (crtc->enabled)
 616                         active = true;
 617
 618         pm_runtime_mark_last_busy(dev->dev);
 619
 620         rdev = dev->dev_private;
 621         /* if we have active crtcs and we don't have a power ref,
 622            take the current one */
 623         if (active && !rdev->have_disp_power_ref) {
 624                 rdev->have_disp_power_ref = true;
 625                 return ret;
 626         }
 627         /* if we have no active crtcs, then drop the power ref
 628            we got before */
 629         if (!active && rdev->have_disp_power_ref) {
 630                 pm_runtime_put_autosuspend(dev->dev);
 631                 rdev->have_disp_power_ref = false;
 632         }
 633
 634         /* drop the power reference we got coming in here */
 635         pm_runtime_put_autosuspend(dev->dev);
 636         return ret;
 637 }
 638 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 639         .cursor_set2 = radeon_crtc_cursor_set2,
 640         .cursor_move = radeon_crtc_cursor_move,
 641         .gamma_set = radeon_crtc_gamma_set,
 642         .set_config = radeon_crtc_set_config,
 643         .destroy = radeon_crtc_destroy,
 644         .page_flip = radeon_crtc_page_flip,
 645 };
 646
 647 static void radeon_crtc_init(struct drm_device *dev, int index)
 648 {
 649         struct radeon_device *rdev = dev->dev_private;
 650         struct radeon_crtc *radeon_crtc;
 651         int i;
 652
 653         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 654         if (radeon_crtc == NULL)
 655                 return;
 656
 657         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 658
 659         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 660         radeon_crtc->crtc_id = index;
 661         radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
 662         rdev->mode_info.crtcs[index] = radeon_crtc;
 663
 664         if (rdev->family >= CHIP_BONAIRE) {
 665                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 666                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 667         } else {
 668                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 669                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 670         }
 671         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 672         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 673
 674 #if 0
 675         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 676         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 677         radeon_crtc->mode_set.num_connectors = 0;
 678 #endif
 679
 680         for (i = 0; i < 256; i++) {
 681                 radeon_crtc->lut_r[i] = i << 2;
 682                 radeon_crtc->lut_g[i] = i << 2;
 683                 radeon_crtc->lut_b[i] = i << 2;
 684         }
 685
 686         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 687                 radeon_atombios_init_crtc(dev, radeon_crtc);
 688         else
 689                 radeon_legacy_init_crtc(dev, radeon_crtc);
 690 }
 691
 692 static const char *encoder_names[38] = {
 693         "NONE",
 694         "INTERNAL_LVDS",
 695         "INTERNAL_TMDS1",
 696         "INTERNAL_TMDS2",
 697         "INTERNAL_DAC1",
 698         "INTERNAL_DAC2",
 699         "INTERNAL_SDVOA",
 700         "INTERNAL_SDVOB",
 701         "SI170B",
 702         "CH7303",
 703         "CH7301",
 704         "INTERNAL_DVO1",
 705         "EXTERNAL_SDVOA",
 706         "EXTERNAL_SDVOB",
 707         "TITFP513",
 708         "INTERNAL_LVTM1",
 709         "VT1623",
 710         "HDMI_SI1930",
 711         "HDMI_INTERNAL",
 712         "INTERNAL_KLDSCP_TMDS1",
 713         "INTERNAL_KLDSCP_DVO1",
 714         "INTERNAL_KLDSCP_DAC1",
 715         "INTERNAL_KLDSCP_DAC2",
 716         "SI178",
 717         "MVPU_FPGA",
 718         "INTERNAL_DDI",
 719         "VT1625",
 720         "HDMI_SI1932",
 721         "DP_AN9801",
 722         "DP_DP501",
 723         "INTERNAL_UNIPHY",
 724         "INTERNAL_KLDSCP_LVTMA",
 725         "INTERNAL_UNIPHY1",
 726         "INTERNAL_UNIPHY2",
 727         "NUTMEG",
 728         "TRAVIS",
 729         "INTERNAL_VCE",
 730         "INTERNAL_UNIPHY3",
 731 };
 732
 733 static const char *hpd_names[6] = {
 734         "HPD1",
 735         "HPD2",
 736         "HPD3",
 737         "HPD4",
 738         "HPD5",
 739         "HPD6",
 740 };
 741
 742 static void radeon_print_display_setup(struct drm_device *dev)
 743 {
 744         struct drm_connector *connector;
 745         struct radeon_connector *radeon_connector;
 746         struct drm_encoder *encoder;
 747         struct radeon_encoder *radeon_encoder;
 748         uint32_t devices;
 749         int i = 0;
 750
 751         DRM_INFO("Radeon Display Connectors\n");
 752         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 753                 radeon_connector = to_radeon_connector(connector);
 754                 DRM_INFO("Connector %d:\n", i);
 755                 DRM_INFO("  %s\n", connector->name);
 756                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 757                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 758                 if (radeon_connector->ddc_bus) {
 759                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 760                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 761                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 762                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 763                                  radeon_connector->ddc_bus->rec.a_data_reg,
 764                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 765                                  radeon_connector->ddc_bus->rec.en_data_reg,
 766                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 767                                  radeon_connector->ddc_bus->rec.y_data_reg);
 768                         if (radeon_connector->router.ddc_valid)
 769                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 770                                          radeon_connector->router.ddc_mux_control_pin,
 771                                          radeon_connector->router.ddc_mux_state);
 772                         if (radeon_connector->router.cd_valid)
 773                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 774                                          radeon_connector->router.cd_mux_control_pin,
 775                                          radeon_connector->router.cd_mux_state);
 776                 } else {
 777                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 778                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 779                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 780                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 781                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 782                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 783                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 784                 }
 785                 DRM_INFO("  Encoders:\n");
 786                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 787                         radeon_encoder = to_radeon_encoder(encoder);
 788                         devices = radeon_encoder->devices & radeon_connector->devices;
 789                         if (devices) {
 790                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 791                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 792                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 793                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 794                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 795                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 796                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 797                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 798                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 799                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 800                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 801                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 802                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 803                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 804                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 805                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 806                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 807                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 808                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 809                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 810                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 811                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 812                         }
 813                 }
 814                 i++;
 815         }
 816 }
 817
 818 static bool radeon_setup_enc_conn(struct drm_device *dev)
 819 {
 820         struct radeon_device *rdev = dev->dev_private;
 821         bool ret = false;
 822
 823         if (rdev->bios) {
 824                 if (rdev->is_atom_bios) {
 825                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 826                         if (ret == false)
 827                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 828                 } else {
 829                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 830                         if (ret == false)
 831                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 832                 }
 833         } else {
 834                 if (!ASIC_IS_AVIVO(rdev))
 835                         ret = radeon_get_legacy_connector_info_from_table(dev);
 836         }
 837         if (ret) {
 838                 radeon_setup_encoder_clones(dev);
 839                 radeon_print_display_setup(dev);
 840         }
 841
 842         return ret;
 843 }
 844
 845 /* avivo */
 846
 847 /**
 848  * avivo_reduce_ratio - fractional number reduction
 849  *
 850  * @nom: nominator
 851  * @den: denominator
 852  * @nom_min: minimum value for nominator
 853  * @den_min: minimum value for denominator
 854  *
 855  * Find the greatest common divisor and apply it on both nominator and
 856  * denominator, but make nominator and denominator are at least as large
 857  * as their minimum values.
 858  */
 859 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 860                                unsigned nom_min, unsigned den_min)
 861 {
 862         unsigned tmp;
 863
 864         /* reduce the numbers to a simpler ratio */
 865         tmp = gcd(*nom, *den);
 866         *nom /= tmp;
 867         *den /= tmp;
 868
 869         /* make sure nominator is large enough */
 870         if (*nom < nom_min) {
 871                 tmp = DIV_ROUND_UP(nom_min, *nom);
 872                 *nom *= tmp;
 873                 *den *= tmp;
 874         }
 875
 876         /* make sure the denominator is large enough */
 877         if (*den < den_min) {
 878                 tmp = DIV_ROUND_UP(den_min, *den);
 879                 *nom *= tmp;
 880                 *den *= tmp;
 881         }
 882 }
 883
 884 /**
 885  * avivo_get_fb_ref_div - feedback and ref divider calculation
 886  *
 887  * @nom: nominator
 888  * @den: denominator
 889  * @post_div: post divider
 890  * @fb_div_max: feedback divider maximum
 891  * @ref_div_max: reference divider maximum
 892  * @fb_div: resulting feedback divider
 893  * @ref_div: resulting reference divider
 894  *
 895  * Calculate feedback and reference divider for a given post divider. Makes
 896  * sure we stay within the limits.
 897  */
 898 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 899                                  unsigned fb_div_max, unsigned ref_div_max,
 900                                  unsigned *fb_div, unsigned *ref_div)
 901 {
 902         /* limit reference * post divider to a maximum */
 903         ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
 904
 905         /* get matching reference and feedback divider */
 906         *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
 907         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 908
 909         /* limit fb divider to its maximum */
 910         if (*fb_div > fb_div_max) {
 911                 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
 912                 *fb_div = fb_div_max;
 913         }
 914 }
 915
 916 /**
 917  * radeon_compute_pll_avivo - compute PLL paramaters
 918  *
 919  * @pll: information about the PLL
 920  * @dot_clock_p: resulting pixel clock
 921  * fb_div_p: resulting feedback divider
 922  * frac_fb_div_p: fractional part of the feedback divider
 923  * ref_div_p: resulting reference divider
 924  * post_div_p: resulting reference divider
 925  *
 926  * Try to calculate the PLL parameters to generate the given frequency:
 927  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 928  */
 929 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 930                               u32 freq,
 931                               u32 *dot_clock_p,
 932                               u32 *fb_div_p,
 933                               u32 *frac_fb_div_p,
 934                               u32 *ref_div_p,
 935                               u32 *post_div_p)
 936 {
 937         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 938                 freq : freq / 10;
 939
 940         unsigned fb_div_min, fb_div_max, fb_div;
 941         unsigned post_div_min, post_div_max, post_div;
 942         unsigned ref_div_min, ref_div_max, ref_div;
 943         unsigned post_div_best, diff_best;
 944         unsigned nom, den;
 945
 946         /* determine allowed feedback divider range */
 947         fb_div_min = pll->min_feedback_div;
 948         fb_div_max = pll->max_feedback_div;
 949
 950         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 951                 fb_div_min *= 10;
 952                 fb_div_max *= 10;
 953         }
 954
 955         /* determine allowed ref divider range */
 956         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 957                 ref_div_min = pll->reference_div;
 958         else
 959                 ref_div_min = pll->min_ref_div;
 960
 961         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
 962             pll->flags & RADEON_PLL_USE_REF_DIV)
 963                 ref_div_max = pll->reference_div;
 964         else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 965                 /* fix for problems on RS880 */
 966                 ref_div_max = min(pll->max_ref_div, 7u);
 967         else
 968                 ref_div_max = pll->max_ref_div;
 969
 970         /* determine allowed post divider range */
 971         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 972                 post_div_min = pll->post_div;
 973                 post_div_max = pll->post_div;
 974         } else {
 975                 unsigned vco_min, vco_max;
 976
 977                 if (pll->flags & RADEON_PLL_IS_LCD) {
 978                         vco_min = pll->lcd_pll_out_min;
 979                         vco_max = pll->lcd_pll_out_max;
 980                 } else {
 981                         vco_min = pll->pll_out_min;
 982                         vco_max = pll->pll_out_max;
 983                 }
 984
 985                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 986                         vco_min *= 10;
 987                         vco_max *= 10;
 988                 }
 989
 990                 post_div_min = vco_min / target_clock;
 991                 if ((target_clock * post_div_min) < vco_min)
 992                         ++post_div_min;
 993                 if (post_div_min < pll->min_post_div)
 994                         post_div_min = pll->min_post_div;
 995
 996                 post_div_max = vco_max / target_clock;
 997                 if ((target_clock * post_div_max) > vco_max)
 998                         --post_div_max;
 999                 if (post_div_max > pll->max_post_div)
1000                         post_div_max = pll->max_post_div;
1001         }
1002
1003         /* represent the searched ratio as fractional number */
1004         nom = target_clock;
1005         den = pll->reference_freq;
1006
1007         /* reduce the numbers to a simpler ratio */
1008         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1009
1010         /* now search for a post divider */
1011         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1012                 post_div_best = post_div_min;
1013         else
1014                 post_div_best = post_div_max;
1015         diff_best = ~0;
1016
1017         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1018                 unsigned diff;
1019                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1020                                      ref_div_max, &fb_div, &ref_div);
1021                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1022                         (ref_div * post_div));
1023
1024                 if (diff < diff_best || (diff == diff_best &&
1025                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1026
1027                         post_div_best = post_div;
1028                         diff_best = diff;
1029                 }
1030         }
1031         post_div = post_div_best;
1032
1033         /* get the feedback and reference divider for the optimal value */
1034         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1035                              &fb_div, &ref_div);
1036
1037         /* reduce the numbers to a simpler ratio once more */
1038         /* this also makes sure that the reference divider is large enough */
1039         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1040
1041         /* avoid high jitter with small fractional dividers */
1042         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1043                 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1044                 if (fb_div < fb_div_min) {
1045                         unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1046                         fb_div *= tmp;
1047                         ref_div *= tmp;
1048                 }
1049         }
1050
1051         /* and finally save the result */
1052         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1053                 *fb_div_p = fb_div / 10;
1054                 *frac_fb_div_p = fb_div % 10;
1055         } else {
1056                 *fb_div_p = fb_div;
1057                 *frac_fb_div_p = 0;
1058         }
1059
1060         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1061                         (pll->reference_freq * *frac_fb_div_p)) /
1062                        (ref_div * post_div * 10);
1063         *ref_div_p = ref_div;
1064         *post_div_p = post_div;
1065
1066         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1067                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1068                       ref_div, post_div);
1069 }
1070
1071 /* pre-avivo */
1072 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1073 {
1074         uint64_t mod;
1075
1076         n += d / 2;
1077
1078         mod = do_div(n, d);
1079         return n;
1080 }
1081
1082 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1083                                uint64_t freq,
1084                                uint32_t *dot_clock_p,
1085                                uint32_t *fb_div_p,
1086                                uint32_t *frac_fb_div_p,
1087                                uint32_t *ref_div_p,
1088                                uint32_t *post_div_p)
1089 {
1090         uint32_t min_ref_div = pll->min_ref_div;
1091         uint32_t max_ref_div = pll->max_ref_div;
1092         uint32_t min_post_div = pll->min_post_div;
1093         uint32_t max_post_div = pll->max_post_div;
1094         uint32_t min_fractional_feed_div = 0;
1095         uint32_t max_fractional_feed_div = 0;
1096         uint32_t best_vco = pll->best_vco;
1097         uint32_t best_post_div = 1;
1098         uint32_t best_ref_div = 1;
1099         uint32_t best_feedback_div = 1;
1100         uint32_t best_frac_feedback_div = 0;
1101         uint32_t best_freq = -1;
1102         uint32_t best_error = 0xffffffff;
1103         uint32_t best_vco_diff = 1;
1104         uint32_t post_div;
1105         u32 pll_out_min, pll_out_max;
1106
1107         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1108         freq = freq * 1000;
1109
1110         if (pll->flags & RADEON_PLL_IS_LCD) {
1111                 pll_out_min = pll->lcd_pll_out_min;
1112                 pll_out_max = pll->lcd_pll_out_max;
1113         } else {
1114                 pll_out_min = pll->pll_out_min;
1115                 pll_out_max = pll->pll_out_max;
1116         }
1117
1118         if (pll_out_min > 64800)
1119                 pll_out_min = 64800;
1120
1121         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1122                 min_ref_div = max_ref_div = pll->reference_div;
1123         else {
1124                 while (min_ref_div < max_ref_div-1) {
1125                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1126                         uint32_t pll_in = pll->reference_freq / mid;
1127                         if (pll_in < pll->pll_in_min)
1128                                 max_ref_div = mid;
1129                         else if (pll_in > pll->pll_in_max)
1130                                 min_ref_div = mid;
1131                         else
1132                                 break;
1133                 }
1134         }
1135
1136         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1137                 min_post_div = max_post_div = pll->post_div;
1138
1139         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1140                 min_fractional_feed_div = pll->min_frac_feedback_div;
1141                 max_fractional_feed_div = pll->max_frac_feedback_div;
1142         }
1143
1144         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1145                 uint32_t ref_div;
1146
1147                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1148                         continue;
1149
1150                 /* legacy radeons only have a few post_divs */
1151                 if (pll->flags & RADEON_PLL_LEGACY) {
1152                         if ((post_div == 5) ||
1153                             (post_div == 7) ||
1154                             (post_div == 9) ||
1155                             (post_div == 10) ||
1156                             (post_div == 11) ||
1157                             (post_div == 13) ||
1158                             (post_div == 14) ||
1159                             (post_div == 15))
1160                                 continue;
1161                 }
1162
1163                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1164                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1165                         uint32_t pll_in = pll->reference_freq / ref_div;
1166                         uint32_t min_feed_div = pll->min_feedback_div;
1167                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1168
1169                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1170                                 continue;
1171
1172                         while (min_feed_div < max_feed_div) {
1173                                 uint32_t vco;
1174                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1175                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1176                                 uint32_t frac_feedback_div;
1177                                 uint64_t tmp;
1178
1179                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1180
1181                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1182                                 vco = radeon_div(tmp, ref_div);
1183
1184                                 if (vco < pll_out_min) {
1185                                         min_feed_div = feedback_div + 1;
1186                                         continue;
1187                                 } else if (vco > pll_out_max) {
1188                                         max_feed_div = feedback_div;
1189                                         continue;
1190                                 }
1191
1192                                 while (min_frac_feed_div < max_frac_feed_div) {
1193                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1194                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1195                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1196                                         current_freq = radeon_div(tmp, ref_div * post_div);
1197
1198                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1199                                                 if (freq < current_freq)
1200                                                         error = 0xffffffff;
1201                                                 else
1202                                                         error = freq - current_freq;
1203                                         } else
1204                                                 error = abs(current_freq - freq);
1205                                         vco_diff = abs(vco - best_vco);
1206
1207                                         if ((best_vco == 0 && error < best_error) ||
1208                                             (best_vco != 0 &&
1209                                              ((best_error > 100 && error < best_error - 100) ||
1210                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1211                                                 best_post_div = post_div;
1212                                                 best_ref_div = ref_div;
1213                                                 best_feedback_div = feedback_div;
1214                                                 best_frac_feedback_div = frac_feedback_div;
1215                                                 best_freq = current_freq;
1216                                                 best_error = error;
1217                                                 best_vco_diff = vco_diff;
1218                                         } else if (current_freq == freq) {
1219                                                 if (best_freq == -1) {
1220                                                         best_post_div = post_div;
1221                                                         best_ref_div = ref_div;
1222                                                         best_feedback_div = feedback_div;
1223                                                         best_frac_feedback_div = frac_feedback_div;
1224                                                         best_freq = current_freq;
1225                                                         best_error = error;
1226                                                         best_vco_diff = vco_diff;
1227                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1228                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1229                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1230                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1231                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1232                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1233                                                         best_post_div = post_div;
1234                                                         best_ref_div = ref_div;
1235                                                         best_feedback_div = feedback_div;
1236                                                         best_frac_feedback_div = frac_feedback_div;
1237                                                         best_freq = current_freq;
1238                                                         best_error = error;
1239                                                         best_vco_diff = vco_diff;
1240                                                 }
1241                                         }
1242                                         if (current_freq < freq)
1243                                                 min_frac_feed_div = frac_feedback_div + 1;
1244                                         else
1245                                                 max_frac_feed_div = frac_feedback_div;
1246                                 }
1247                                 if (current_freq < freq)
1248                                         min_feed_div = feedback_div + 1;
1249                                 else
1250                                         max_feed_div = feedback_div;
1251                         }
1252                 }
1253         }
1254
1255         *dot_clock_p = best_freq / 10000;
1256         *fb_div_p = best_feedback_div;
1257         *frac_fb_div_p = best_frac_feedback_div;
1258         *ref_div_p = best_ref_div;
1259         *post_div_p = best_post_div;
1260         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1261                       (long long)freq,
1262                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1263                       best_ref_div, best_post_div);
1264
1265 }
1266
1267 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1268 {
1269         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1270
1271         if (radeon_fb->obj) {
1272                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1273         }
1274         drm_framebuffer_cleanup(fb);
1275         kfree(radeon_fb);
1276 }
1277
1278 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1279                                                   struct drm_file *file_priv,
1280                                                   unsigned int *handle)
1281 {
1282         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1283
1284         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1285 }
1286
1287 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1288         .destroy = radeon_user_framebuffer_destroy,
1289         .create_handle = radeon_user_framebuffer_create_handle,
1290 };
1291
1292 int
1293 radeon_framebuffer_init(struct drm_device *dev,
1294                         struct radeon_framebuffer *rfb,
1295                         struct drm_mode_fb_cmd2 *mode_cmd,
1296                         struct drm_gem_object *obj)
1297 {
1298         int ret;
1299         rfb->obj = obj;
1300         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1301         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1302         if (ret) {
1303                 rfb->obj = NULL;
1304                 return ret;
1305         }
1306         return 0;
1307 }
1308
1309 static struct drm_framebuffer *
1310 radeon_user_framebuffer_create(struct drm_device *dev,
1311                                struct drm_file *file_priv,
1312                                struct drm_mode_fb_cmd2 *mode_cmd)
1313 {
1314         struct drm_gem_object *obj;
1315         struct radeon_framebuffer *radeon_fb;
1316         int ret;
1317
1318         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1319         if (obj ==  NULL) {
1320                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1321                         "can't create framebuffer\n", mode_cmd->handles[0]);
1322                 return ERR_PTR(-ENOENT);
1323         }
1324
1325         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1326         if (radeon_fb == NULL) {
1327                 drm_gem_object_unreference_unlocked(obj);
1328                 return ERR_PTR(-ENOMEM);
1329         }
1330
1331         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1332         if (ret) {
1333                 kfree(radeon_fb);
1334                 drm_gem_object_unreference_unlocked(obj);
1335                 return ERR_PTR(ret);
1336         }
1337
1338         return &radeon_fb->base;
1339 }
1340
1341 static void radeon_output_poll_changed(struct drm_device *dev)
1342 {
1343         struct radeon_device *rdev = dev->dev_private;
1344         radeon_fb_output_poll_changed(rdev);
1345 }
1346
1347 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1348         .fb_create = radeon_user_framebuffer_create,
1349         .output_poll_changed = radeon_output_poll_changed
1350 };
1351
1352 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1353 {       { 0, "driver" },
1354         { 1, "bios" },
1355 };
1356
1357 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1358 {       { TV_STD_NTSC, "ntsc" },
1359         { TV_STD_PAL, "pal" },
1360         { TV_STD_PAL_M, "pal-m" },
1361         { TV_STD_PAL_60, "pal-60" },
1362         { TV_STD_NTSC_J, "ntsc-j" },
1363         { TV_STD_SCART_PAL, "scart-pal" },
1364         { TV_STD_PAL_CN, "pal-cn" },
1365         { TV_STD_SECAM, "secam" },
1366 };
1367
1368 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1369 {       { UNDERSCAN_OFF, "off" },
1370         { UNDERSCAN_ON, "on" },
1371         { UNDERSCAN_AUTO, "auto" },
1372 };
1373
1374 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1375 {       { RADEON_AUDIO_DISABLE, "off" },
1376         { RADEON_AUDIO_ENABLE, "on" },
1377         { RADEON_AUDIO_AUTO, "auto" },
1378 };
1379
1380 /* XXX support different dither options? spatial, temporal, both, etc. */
1381 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1382 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1383         { RADEON_FMT_DITHER_ENABLE, "on" },
1384 };
1385
1386 static struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1387 {       { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1388         { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1389         { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1390         { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1391 };
1392
1393 static int radeon_modeset_create_props(struct radeon_device *rdev)
1394 {
1395         int sz;
1396
1397         if (rdev->is_atom_bios) {
1398                 rdev->mode_info.coherent_mode_property =
1399                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1400                 if (!rdev->mode_info.coherent_mode_property)
1401                         return -ENOMEM;
1402         }
1403
1404         if (!ASIC_IS_AVIVO(rdev)) {
1405                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1406                 rdev->mode_info.tmds_pll_property =
1407                         drm_property_create_enum(rdev->ddev, 0,
1408                                             "tmds_pll",
1409                                             radeon_tmds_pll_enum_list, sz);
1410         }
1411
1412         rdev->mode_info.load_detect_property =
1413                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1414         if (!rdev->mode_info.load_detect_property)
1415                 return -ENOMEM;
1416
1417         drm_mode_create_scaling_mode_property(rdev->ddev);
1418
1419         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1420         rdev->mode_info.tv_std_property =
1421                 drm_property_create_enum(rdev->ddev, 0,
1422                                     "tv standard",
1423                                     radeon_tv_std_enum_list, sz);
1424
1425         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1426         rdev->mode_info.underscan_property =
1427                 drm_property_create_enum(rdev->ddev, 0,
1428                                     "underscan",
1429                                     radeon_underscan_enum_list, sz);
1430
1431         rdev->mode_info.underscan_hborder_property =
1432                 drm_property_create_range(rdev->ddev, 0,
1433                                         "underscan hborder", 0, 128);
1434         if (!rdev->mode_info.underscan_hborder_property)
1435                 return -ENOMEM;
1436
1437         rdev->mode_info.underscan_vborder_property =
1438                 drm_property_create_range(rdev->ddev, 0,
1439                                         "underscan vborder", 0, 128);
1440         if (!rdev->mode_info.underscan_vborder_property)
1441                 return -ENOMEM;
1442
1443         sz = ARRAY_SIZE(radeon_audio_enum_list);
1444         rdev->mode_info.audio_property =
1445                 drm_property_create_enum(rdev->ddev, 0,
1446                                          "audio",
1447                                          radeon_audio_enum_list, sz);
1448
1449         sz = ARRAY_SIZE(radeon_dither_enum_list);
1450         rdev->mode_info.dither_property =
1451                 drm_property_create_enum(rdev->ddev, 0,
1452                                          "dither",
1453                                          radeon_dither_enum_list, sz);
1454
1455         sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1456         rdev->mode_info.output_csc_property =
1457                 drm_property_create_enum(rdev->ddev, 0,
1458                                          "output_csc",
1459                                          radeon_output_csc_enum_list, sz);
1460
1461         return 0;
1462 }
1463
1464 void radeon_update_display_priority(struct radeon_device *rdev)
1465 {
1466         /* adjustment options for the display watermarks */
1467         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1468                 /* set display priority to high for r3xx, rv515 chips
1469                  * this avoids flickering due to underflow to the
1470                  * display controllers during heavy acceleration.
1471                  * Don't force high on rs4xx igp chips as it seems to
1472                  * affect the sound card.  See kernel bug 15982.
1473                  */
1474                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1475                     !(rdev->flags & RADEON_IS_IGP))
1476                         rdev->disp_priority = 2;
1477                 else
1478                         rdev->disp_priority = 0;
1479         } else
1480                 rdev->disp_priority = radeon_disp_priority;
1481
1482 }
1483
1484 /*
1485  * Allocate hdmi structs and determine register offsets
1486  */
1487 static void radeon_afmt_init(struct radeon_device *rdev)
1488 {
1489         int i;
1490
1491         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1492                 rdev->mode_info.afmt[i] = NULL;
1493
1494         if (ASIC_IS_NODCE(rdev)) {
1495                 /* nothing to do */
1496         } else if (ASIC_IS_DCE4(rdev)) {
1497                 static uint32_t eg_offsets[] = {
1498                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1499                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1500                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1501                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1502                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1503                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1504                         0x13830 - 0x7030,
1505                 };
1506                 int num_afmt;
1507
1508                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1509                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1510                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1511                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1512                 if (ASIC_IS_DCE8(rdev))
1513                         num_afmt = 7;
1514                 else if (ASIC_IS_DCE6(rdev))
1515                         num_afmt = 6;
1516                 else if (ASIC_IS_DCE5(rdev))
1517                         num_afmt = 6;
1518                 else if (ASIC_IS_DCE41(rdev))
1519                         num_afmt = 2;
1520                 else /* DCE4 */
1521                         num_afmt = 6;
1522
1523                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1524                 for (i = 0; i < num_afmt; i++) {
1525                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1526                         if (rdev->mode_info.afmt[i]) {
1527                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1528                                 rdev->mode_info.afmt[i]->id = i;
1529                         }
1530                 }
1531         } else if (ASIC_IS_DCE3(rdev)) {
1532                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1533                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1534                 if (rdev->mode_info.afmt[0]) {
1535                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1536                         rdev->mode_info.afmt[0]->id = 0;
1537                 }
1538                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1539                 if (rdev->mode_info.afmt[1]) {
1540                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1541                         rdev->mode_info.afmt[1]->id = 1;
1542                 }
1543         } else if (ASIC_IS_DCE2(rdev)) {
1544                 /* DCE2 has at least 1 routable audio block */
1545                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1546                 if (rdev->mode_info.afmt[0]) {
1547                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1548                         rdev->mode_info.afmt[0]->id = 0;
1549                 }
1550                 /* r6xx has 2 routable audio blocks */
1551                 if (rdev->family >= CHIP_R600) {
1552                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1553                         if (rdev->mode_info.afmt[1]) {
1554                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1555                                 rdev->mode_info.afmt[1]->id = 1;
1556                         }
1557                 }
1558         }
1559 }
1560
1561 static void radeon_afmt_fini(struct radeon_device *rdev)
1562 {
1563         int i;
1564
1565         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1566                 kfree(rdev->mode_info.afmt[i]);
1567                 rdev->mode_info.afmt[i] = NULL;
1568         }
1569 }
1570
1571 int radeon_modeset_init(struct radeon_device *rdev)
1572 {
1573         int i;
1574         int ret;
1575
1576         drm_mode_config_init(rdev->ddev);
1577         rdev->mode_info.mode_config_initialized = true;
1578
1579         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1580
1581         if (ASIC_IS_DCE5(rdev)) {
1582                 rdev->ddev->mode_config.max_width = 16384;
1583                 rdev->ddev->mode_config.max_height = 16384;
1584         } else if (ASIC_IS_AVIVO(rdev)) {
1585                 rdev->ddev->mode_config.max_width = 8192;
1586                 rdev->ddev->mode_config.max_height = 8192;
1587         } else {
1588                 rdev->ddev->mode_config.max_width = 4096;
1589                 rdev->ddev->mode_config.max_height = 4096;
1590         }
1591
1592         rdev->ddev->mode_config.preferred_depth = 24;
1593         rdev->ddev->mode_config.prefer_shadow = 1;
1594
1595         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1596
1597         ret = radeon_modeset_create_props(rdev);
1598         if (ret) {
1599                 return ret;
1600         }
1601
1602         /* init i2c buses */
1603         radeon_i2c_init(rdev);
1604
1605         /* check combios for a valid hardcoded EDID - Sun servers */
1606         if (!rdev->is_atom_bios) {
1607                 /* check for hardcoded EDID in BIOS */
1608                 radeon_combios_check_hardcoded_edid(rdev);
1609         }
1610
1611         /* allocate crtcs */
1612         for (i = 0; i < rdev->num_crtc; i++) {
1613                 radeon_crtc_init(rdev->ddev, i);
1614         }
1615
1616         /* okay we should have all the bios connectors */
1617         ret = radeon_setup_enc_conn(rdev->ddev);
1618         if (!ret) {
1619                 return ret;
1620         }
1621
1622         /* init dig PHYs, disp eng pll */
1623         if (rdev->is_atom_bios) {
1624                 radeon_atom_encoder_init(rdev);
1625                 radeon_atom_disp_eng_pll_init(rdev);
1626         }
1627
1628         /* initialize hpd */
1629         radeon_hpd_init(rdev);
1630
1631         /* setup afmt */
1632         radeon_afmt_init(rdev);
1633
1634         radeon_fbdev_init(rdev);
1635         drm_kms_helper_poll_init(rdev->ddev);
1636
1637         /* do pm late init */
1638         ret = radeon_pm_late_init(rdev);
1639
1640         return 0;
1641 }
1642
1643 void radeon_modeset_fini(struct radeon_device *rdev)
1644 {
1645         radeon_fbdev_fini(rdev);
1646         kfree(rdev->mode_info.bios_hardcoded_edid);
1647
1648         if (rdev->mode_info.mode_config_initialized) {
1649                 radeon_afmt_fini(rdev);
1650                 drm_kms_helper_poll_fini(rdev->ddev);
1651                 radeon_hpd_fini(rdev);
1652                 drm_mode_config_cleanup(rdev->ddev);
1653                 rdev->mode_info.mode_config_initialized = false;
1654         }
1655         /* free i2c buses */
1656         radeon_i2c_fini(rdev);
1657 }
1658
1659 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1660 {
1661         /* try and guess if this is a tv or a monitor */
1662         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1663             (mode->vdisplay == 576) || /* 576p */
1664             (mode->vdisplay == 720) || /* 720p */
1665             (mode->vdisplay == 1080)) /* 1080p */
1666                 return true;
1667         else
1668                 return false;
1669 }
1670
1671 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1672                                 const struct drm_display_mode *mode,
1673                                 struct drm_display_mode *adjusted_mode)
1674 {
1675         struct drm_device *dev = crtc->dev;
1676         struct radeon_device *rdev = dev->dev_private;
1677         struct drm_encoder *encoder;
1678         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1679         struct radeon_encoder *radeon_encoder;
1680         struct drm_connector *connector;
1681         struct radeon_connector *radeon_connector;
1682         bool first = true;
1683         u32 src_v = 1, dst_v = 1;
1684         u32 src_h = 1, dst_h = 1;
1685
1686         radeon_crtc->h_border = 0;
1687         radeon_crtc->v_border = 0;
1688
1689         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1690                 if (encoder->crtc != crtc)
1691                         continue;
1692                 radeon_encoder = to_radeon_encoder(encoder);
1693                 connector = radeon_get_connector_for_encoder(encoder);
1694                 radeon_connector = to_radeon_connector(connector);
1695
1696                 if (first) {
1697                         /* set scaling */
1698                         if (radeon_encoder->rmx_type == RMX_OFF)
1699                                 radeon_crtc->rmx_type = RMX_OFF;
1700                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1701                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1702                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1703                         else
1704                                 radeon_crtc->rmx_type = RMX_OFF;
1705                         /* copy native mode */
1706                         memcpy(&radeon_crtc->native_mode,
1707                                &radeon_encoder->native_mode,
1708                                 sizeof(struct drm_display_mode));
1709                         src_v = crtc->mode.vdisplay;
1710                         dst_v = radeon_crtc->native_mode.vdisplay;
1711                         src_h = crtc->mode.hdisplay;
1712                         dst_h = radeon_crtc->native_mode.hdisplay;
1713
1714                         /* fix up for overscan on hdmi */
1715                         if (ASIC_IS_AVIVO(rdev) &&
1716                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1717                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1718                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1719                               drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1720                               is_hdtv_mode(mode)))) {
1721                                 if (radeon_encoder->underscan_hborder != 0)
1722                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1723                                 else
1724                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1725                                 if (radeon_encoder->underscan_vborder != 0)
1726                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1727                                 else
1728                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1729                                 radeon_crtc->rmx_type = RMX_FULL;
1730                                 src_v = crtc->mode.vdisplay;
1731                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1732                                 src_h = crtc->mode.hdisplay;
1733                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1734                         }
1735                         first = false;
1736                 } else {
1737                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1738                                 /* WARNING: Right now this can't happen but
1739                                  * in the future we need to check that scaling
1740                                  * are consistent across different encoder
1741                                  * (ie all encoder can work with the same
1742                                  *  scaling).
1743                                  */
1744                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1745                                 return false;
1746                         }
1747                 }
1748         }
1749         if (radeon_crtc->rmx_type != RMX_OFF) {
1750                 fixed20_12 a, b;
1751                 a.full = dfixed_const(src_v);
1752                 b.full = dfixed_const(dst_v);
1753                 radeon_crtc->vsc.full = dfixed_div(a, b);
1754                 a.full = dfixed_const(src_h);
1755                 b.full = dfixed_const(dst_h);
1756                 radeon_crtc->hsc.full = dfixed_div(a, b);
1757         } else {
1758                 radeon_crtc->vsc.full = dfixed_const(1);
1759                 radeon_crtc->hsc.full = dfixed_const(1);
1760         }
1761         return true;
1762 }
1763
1764 /*
1765  * Retrieve current video scanout position of crtc on a given gpu, and
1766  * an optional accurate timestamp of when query happened.
1767  *
1768  * \param dev Device to query.
1769  * \param crtc Crtc to query.
1770  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1771  * \param *vpos Location where vertical scanout position should be stored.
1772  * \param *hpos Location where horizontal scanout position should go.
1773  * \param *stime Target location for timestamp taken immediately before
1774  *               scanout position query. Can be NULL to skip timestamp.
1775  * \param *etime Target location for timestamp taken immediately after
1776  *               scanout position query. Can be NULL to skip timestamp.
1777  *
1778  * Returns vpos as a positive number while in active scanout area.
1779  * Returns vpos as a negative number inside vblank, counting the number
1780  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1781  * until start of active scanout / end of vblank."
1782  *
1783  * \return Flags, or'ed together as follows:
1784  *
1785  * DRM_SCANOUTPOS_VALID = Query successful.
1786  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1787  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1788  * this flag means that returned position may be offset by a constant but
1789  * unknown small number of scanlines wrt. real scanout position.
1790  *
1791  */
1792 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1793                                unsigned int flags, int *vpos, int *hpos,
1794                                ktime_t *stime, ktime_t *etime,
1795                                const struct drm_display_mode *mode)
1796 {
1797         u32 stat_crtc = 0, vbl = 0, position = 0;
1798         int vbl_start, vbl_end, vtotal, ret = 0;
1799         bool in_vbl = true;
1800
1801         struct radeon_device *rdev = dev->dev_private;
1802
1803         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1804
1805         /* Get optional system timestamp before query. */
1806         if (stime)
1807                 *stime = ktime_get();
1808
1809         if (ASIC_IS_DCE4(rdev)) {
1810                 if (pipe == 0) {
1811                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1812                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1813                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1814                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1815                         ret |= DRM_SCANOUTPOS_VALID;
1816                 }
1817                 if (pipe == 1) {
1818                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1819                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1820                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1821                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1822                         ret |= DRM_SCANOUTPOS_VALID;
1823                 }
1824                 if (pipe == 2) {
1825                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1826                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1827                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1828                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1829                         ret |= DRM_SCANOUTPOS_VALID;
1830                 }
1831                 if (pipe == 3) {
1832                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1833                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1834                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1835                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1836                         ret |= DRM_SCANOUTPOS_VALID;
1837                 }
1838                 if (pipe == 4) {
1839                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1840                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1841                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1842                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1843                         ret |= DRM_SCANOUTPOS_VALID;
1844                 }
1845                 if (pipe == 5) {
1846                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1847                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1848                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1849                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1850                         ret |= DRM_SCANOUTPOS_VALID;
1851                 }
1852         } else if (ASIC_IS_AVIVO(rdev)) {
1853                 if (pipe == 0) {
1854                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1855                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1856                         ret |= DRM_SCANOUTPOS_VALID;
1857                 }
1858                 if (pipe == 1) {
1859                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1860                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1861                         ret |= DRM_SCANOUTPOS_VALID;
1862                 }
1863         } else {
1864                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1865                 if (pipe == 0) {
1866                         /* Assume vbl_end == 0, get vbl_start from
1867                          * upper 16 bits.
1868                          */
1869                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1870                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1871                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1872                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1873                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1874                         if (!(stat_crtc & 1))
1875                                 in_vbl = false;
1876
1877                         ret |= DRM_SCANOUTPOS_VALID;
1878                 }
1879                 if (pipe == 1) {
1880                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1881                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1882                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1883                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1884                         if (!(stat_crtc & 1))
1885                                 in_vbl = false;
1886
1887                         ret |= DRM_SCANOUTPOS_VALID;
1888                 }
1889         }
1890
1891         /* Get optional system timestamp after query. */
1892         if (etime)
1893                 *etime = ktime_get();
1894
1895         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1896
1897         /* Decode into vertical and horizontal scanout position. */
1898         *vpos = position & 0x1fff;
1899         *hpos = (position >> 16) & 0x1fff;
1900
1901         /* Valid vblank area boundaries from gpu retrieved? */
1902         if (vbl > 0) {
1903                 /* Yes: Decode. */
1904                 ret |= DRM_SCANOUTPOS_ACCURATE;
1905                 vbl_start = vbl & 0x1fff;
1906                 vbl_end = (vbl >> 16) & 0x1fff;
1907         }
1908         else {
1909                 /* No: Fake something reasonable which gives at least ok results. */
1910                 vbl_start = mode->crtc_vdisplay;
1911                 vbl_end = 0;
1912         }
1913
1914         /* Test scanout position against vblank region. */
1915         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1916                 in_vbl = false;
1917
1918         /* Check if inside vblank area and apply corrective offsets:
1919          * vpos will then be >=0 in video scanout area, but negative
1920          * within vblank area, counting down the number of lines until
1921          * start of scanout.
1922          */
1923
1924         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1925         if (in_vbl && (*vpos >= vbl_start)) {
1926                 vtotal = mode->crtc_vtotal;
1927                 *vpos = *vpos - vtotal;
1928         }
1929
1930         /* Correct for shifted end of vbl at vbl_end. */
1931         *vpos = *vpos - vbl_end;
1932
1933         /* In vblank? */
1934         if (in_vbl)
1935                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1936
1937         /* Is vpos outside nominal vblank area, but less than
1938          * 1/100 of a frame height away from start of vblank?
1939          * If so, assume this isn't a massively delayed vblank
1940          * interrupt, but a vblank interrupt that fired a few
1941          * microseconds before true start of vblank. Compensate
1942          * by adding a full frame duration to the final timestamp.
1943          * Happens, e.g., on ATI R500, R600.
1944          *
1945          * We only do this if DRM_CALLED_FROM_VBLIRQ.
1946          */
1947         if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1948                 vbl_start = mode->crtc_vdisplay;
1949                 vtotal = mode->crtc_vtotal;
1950
1951                 if (vbl_start - *vpos < vtotal / 100) {
1952                         *vpos -= vtotal;
1953
1954                         /* Signal this correction as "applied". */
1955                         ret |= 0x8;
1956                 }
1957         }
1958
1959         return ret;
1960 }