2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
40 static const char radeon_family_name[][16] = {
105 #if defined(CONFIG_VGA_SWITCHEROO)
106 bool radeon_is_px(void);
108 static inline bool radeon_is_px(void) { return false; }
112 * radeon_program_register_sequence - program an array of registers.
114 * @rdev: radeon_device pointer
115 * @registers: pointer to the register array
116 * @array_size: size of the register array
118 * Programs an array or registers with and and or masks.
119 * This is a helper for setting golden registers.
121 void radeon_program_register_sequence(struct radeon_device *rdev,
122 const u32 *registers,
123 const u32 array_size)
125 u32 tmp, reg, and_mask, or_mask;
131 for (i = 0; i < array_size; i +=3) {
132 reg = registers[i + 0];
133 and_mask = registers[i + 1];
134 or_mask = registers[i + 2];
136 if (and_mask == 0xffffffff) {
148 * radeon_surface_init - Clear GPU surface registers.
150 * @rdev: radeon_device pointer
152 * Clear GPU surface registers (r1xx-r5xx).
154 void radeon_surface_init(struct radeon_device *rdev)
156 /* FIXME: check this out */
157 if (rdev->family < CHIP_R600) {
160 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
161 if (rdev->surface_regs[i].bo)
162 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
164 radeon_clear_surface_reg(rdev, i);
166 /* enable surfaces */
167 WREG32(RADEON_SURFACE_CNTL, 0);
172 * GPU scratch registers helpers function.
175 * radeon_scratch_init - Init scratch register driver information.
177 * @rdev: radeon_device pointer
179 * Init CP scratch register driver information (r1xx-r5xx)
181 void radeon_scratch_init(struct radeon_device *rdev)
185 /* FIXME: check this out */
186 if (rdev->family < CHIP_R300) {
187 rdev->scratch.num_reg = 5;
189 rdev->scratch.num_reg = 7;
191 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
192 for (i = 0; i < rdev->scratch.num_reg; i++) {
193 rdev->scratch.free[i] = true;
194 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
199 * radeon_scratch_get - Allocate a scratch register
201 * @rdev: radeon_device pointer
202 * @reg: scratch register mmio offset
204 * Allocate a CP scratch register for use by the driver (all asics).
205 * Returns 0 on success or -EINVAL on failure.
207 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
211 for (i = 0; i < rdev->scratch.num_reg; i++) {
212 if (rdev->scratch.free[i]) {
213 rdev->scratch.free[i] = false;
214 *reg = rdev->scratch.reg[i];
222 * radeon_scratch_free - Free a scratch register
224 * @rdev: radeon_device pointer
225 * @reg: scratch register mmio offset
227 * Free a CP scratch register allocated for use by the driver (all asics)
229 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
233 for (i = 0; i < rdev->scratch.num_reg; i++) {
234 if (rdev->scratch.reg[i] == reg) {
235 rdev->scratch.free[i] = true;
242 * GPU doorbell aperture helpers function.
245 * radeon_doorbell_init - Init doorbell driver information.
247 * @rdev: radeon_device pointer
249 * Init doorbell driver information (CIK)
250 * Returns 0 on success, error on failure.
252 int radeon_doorbell_init(struct radeon_device *rdev)
254 /* doorbell bar mapping */
255 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
256 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
258 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
259 if (rdev->doorbell.num_doorbells == 0)
262 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
263 if (rdev->doorbell.ptr == NULL) {
266 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
267 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
269 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
275 * radeon_doorbell_fini - Tear down doorbell driver information.
277 * @rdev: radeon_device pointer
279 * Tear down doorbell driver information (CIK)
281 void radeon_doorbell_fini(struct radeon_device *rdev)
283 iounmap(rdev->doorbell.ptr);
284 rdev->doorbell.ptr = NULL;
288 * radeon_doorbell_get - Allocate a doorbell entry
290 * @rdev: radeon_device pointer
291 * @doorbell: doorbell index
293 * Allocate a doorbell for use by the driver (all asics).
294 * Returns 0 on success or -EINVAL on failure.
296 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
298 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
299 if (offset < rdev->doorbell.num_doorbells) {
300 __set_bit(offset, rdev->doorbell.used);
309 * radeon_doorbell_free - Free a doorbell entry
311 * @rdev: radeon_device pointer
312 * @doorbell: doorbell index
314 * Free a doorbell allocated for use by the driver (all asics)
316 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
318 if (doorbell < rdev->doorbell.num_doorbells)
319 __clear_bit(doorbell, rdev->doorbell.used);
324 * Writeback is the the method by which the the GPU updates special pages
325 * in memory with the status of certain GPU events (fences, ring pointers,
330 * radeon_wb_disable - Disable Writeback
332 * @rdev: radeon_device pointer
334 * Disables Writeback (all asics). Used for suspend.
336 void radeon_wb_disable(struct radeon_device *rdev)
338 rdev->wb.enabled = false;
342 * radeon_wb_fini - Disable Writeback and free memory
344 * @rdev: radeon_device pointer
346 * Disables Writeback and frees the Writeback memory (all asics).
347 * Used at driver shutdown.
349 void radeon_wb_fini(struct radeon_device *rdev)
351 radeon_wb_disable(rdev);
352 if (rdev->wb.wb_obj) {
353 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
354 radeon_bo_kunmap(rdev->wb.wb_obj);
355 radeon_bo_unpin(rdev->wb.wb_obj);
356 radeon_bo_unreserve(rdev->wb.wb_obj);
358 radeon_bo_unref(&rdev->wb.wb_obj);
360 rdev->wb.wb_obj = NULL;
365 * radeon_wb_init- Init Writeback driver info and allocate memory
367 * @rdev: radeon_device pointer
369 * Disables Writeback and frees the Writeback memory (all asics).
370 * Used at driver startup.
371 * Returns 0 on success or an -error on failure.
373 int radeon_wb_init(struct radeon_device *rdev)
377 if (rdev->wb.wb_obj == NULL) {
378 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
379 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
381 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
384 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
385 if (unlikely(r != 0)) {
386 radeon_wb_fini(rdev);
389 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
392 radeon_bo_unreserve(rdev->wb.wb_obj);
393 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
394 radeon_wb_fini(rdev);
397 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
398 radeon_bo_unreserve(rdev->wb.wb_obj);
400 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
401 radeon_wb_fini(rdev);
406 /* clear wb memory */
407 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
408 /* disable event_write fences */
409 rdev->wb.use_event = false;
410 /* disabled via module param */
411 if (radeon_no_wb == 1) {
412 rdev->wb.enabled = false;
414 if (rdev->flags & RADEON_IS_AGP) {
415 /* often unreliable on AGP */
416 rdev->wb.enabled = false;
417 } else if (rdev->family < CHIP_R300) {
418 /* often unreliable on pre-r300 */
419 rdev->wb.enabled = false;
421 rdev->wb.enabled = true;
422 /* event_write fences are only available on r600+ */
423 if (rdev->family >= CHIP_R600) {
424 rdev->wb.use_event = true;
428 /* always use writeback/events on NI, APUs */
429 if (rdev->family >= CHIP_PALM) {
430 rdev->wb.enabled = true;
431 rdev->wb.use_event = true;
434 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
440 * radeon_vram_location - try to find VRAM location
441 * @rdev: radeon device structure holding all necessary informations
442 * @mc: memory controller structure holding memory informations
443 * @base: base address at which to put VRAM
445 * Function will place try to place VRAM at base address provided
446 * as parameter (which is so far either PCI aperture address or
447 * for IGP TOM base address).
449 * If there is not enough space to fit the unvisible VRAM in the 32bits
450 * address space then we limit the VRAM size to the aperture.
452 * If we are using AGP and if the AGP aperture doesn't allow us to have
453 * room for all the VRAM than we restrict the VRAM to the PCI aperture
454 * size and print a warning.
456 * This function will never fails, worst case are limiting VRAM.
458 * Note: GTT start, end, size should be initialized before calling this
459 * function on AGP platform.
461 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
462 * this shouldn't be a problem as we are using the PCI aperture as a reference.
463 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
466 * Note: we use mc_vram_size as on some board we need to program the mc to
467 * cover the whole aperture even if VRAM size is inferior to aperture size
468 * Novell bug 204882 + along with lots of ubuntu ones
470 * Note: when limiting vram it's safe to overwritte real_vram_size because
471 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
472 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
475 * Note: IGP TOM addr should be the same as the aperture addr, we don't
476 * explicitly check for that thought.
478 * FIXME: when reducing VRAM size align new size on power of 2.
480 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
482 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
484 mc->vram_start = base;
485 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
486 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
487 mc->real_vram_size = mc->aper_size;
488 mc->mc_vram_size = mc->aper_size;
490 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
491 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
492 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
493 mc->real_vram_size = mc->aper_size;
494 mc->mc_vram_size = mc->aper_size;
496 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
497 if (limit && limit < mc->real_vram_size)
498 mc->real_vram_size = limit;
499 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
500 mc->mc_vram_size >> 20, mc->vram_start,
501 mc->vram_end, mc->real_vram_size >> 20);
505 * radeon_gtt_location - try to find GTT location
506 * @rdev: radeon device structure holding all necessary informations
507 * @mc: memory controller structure holding memory informations
509 * Function will place try to place GTT before or after VRAM.
511 * If GTT size is bigger than space left then we ajust GTT size.
512 * Thus function will never fails.
514 * FIXME: when reducing GTT size align new size on power of 2.
516 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
518 u64 size_af, size_bf;
520 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
521 size_bf = mc->vram_start & ~mc->gtt_base_align;
522 if (size_bf > size_af) {
523 if (mc->gtt_size > size_bf) {
524 dev_warn(rdev->dev, "limiting GTT\n");
525 mc->gtt_size = size_bf;
527 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
529 if (mc->gtt_size > size_af) {
530 dev_warn(rdev->dev, "limiting GTT\n");
531 mc->gtt_size = size_af;
533 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
535 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
536 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
537 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
541 * GPU helpers function.
544 * radeon_card_posted - check if the hw has already been initialized
546 * @rdev: radeon_device pointer
548 * Check if the asic has been initialized (all asics).
549 * Used at driver startup.
550 * Returns true if initialized or false if not.
552 bool radeon_card_posted(struct radeon_device *rdev)
556 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
557 if (efi_enabled(EFI_BOOT) &&
558 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
559 (rdev->family < CHIP_R600))
562 if (ASIC_IS_NODCE(rdev))
565 /* first check CRTCs */
566 if (ASIC_IS_DCE4(rdev)) {
567 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
568 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
569 if (rdev->num_crtc >= 4) {
570 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
571 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
573 if (rdev->num_crtc >= 6) {
574 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
575 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
577 if (reg & EVERGREEN_CRTC_MASTER_EN)
579 } else if (ASIC_IS_AVIVO(rdev)) {
580 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
581 RREG32(AVIVO_D2CRTC_CONTROL);
582 if (reg & AVIVO_CRTC_EN) {
586 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
587 RREG32(RADEON_CRTC2_GEN_CNTL);
588 if (reg & RADEON_CRTC_EN) {
594 /* then check MEM_SIZE, in case the crtcs are off */
595 if (rdev->family >= CHIP_R600)
596 reg = RREG32(R600_CONFIG_MEMSIZE);
598 reg = RREG32(RADEON_CONFIG_MEMSIZE);
608 * radeon_update_bandwidth_info - update display bandwidth params
610 * @rdev: radeon_device pointer
612 * Used when sclk/mclk are switched or display modes are set.
613 * params are used to calculate display watermarks (all asics)
615 void radeon_update_bandwidth_info(struct radeon_device *rdev)
618 u32 sclk = rdev->pm.current_sclk;
619 u32 mclk = rdev->pm.current_mclk;
621 /* sclk/mclk in Mhz */
622 a.full = dfixed_const(100);
623 rdev->pm.sclk.full = dfixed_const(sclk);
624 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
625 rdev->pm.mclk.full = dfixed_const(mclk);
626 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
628 if (rdev->flags & RADEON_IS_IGP) {
629 a.full = dfixed_const(16);
630 /* core_bandwidth = sclk(Mhz) * 16 */
631 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
636 * radeon_boot_test_post_card - check and possibly initialize the hw
638 * @rdev: radeon_device pointer
640 * Check if the asic is initialized and if not, attempt to initialize
642 * Returns true if initialized or false if not.
644 bool radeon_boot_test_post_card(struct radeon_device *rdev)
646 if (radeon_card_posted(rdev))
650 DRM_INFO("GPU not posted. posting now...\n");
651 if (rdev->is_atom_bios)
652 atom_asic_init(rdev->mode_info.atom_context);
654 radeon_combios_asic_init(rdev->ddev);
657 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
663 * radeon_dummy_page_init - init dummy page used by the driver
665 * @rdev: radeon_device pointer
667 * Allocate the dummy page used by the driver (all asics).
668 * This dummy page is used by the driver as a filler for gart entries
669 * when pages are taken out of the GART
670 * Returns 0 on sucess, -ENOMEM on failure.
672 int radeon_dummy_page_init(struct radeon_device *rdev)
674 if (rdev->dummy_page.page)
676 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
677 if (rdev->dummy_page.page == NULL)
679 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
680 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
681 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
682 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
683 __free_page(rdev->dummy_page.page);
684 rdev->dummy_page.page = NULL;
691 * radeon_dummy_page_fini - free dummy page used by the driver
693 * @rdev: radeon_device pointer
695 * Frees the dummy page used by the driver (all asics).
697 void radeon_dummy_page_fini(struct radeon_device *rdev)
699 if (rdev->dummy_page.page == NULL)
701 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
702 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
703 __free_page(rdev->dummy_page.page);
704 rdev->dummy_page.page = NULL;
708 /* ATOM accessor methods */
710 * ATOM is an interpreted byte code stored in tables in the vbios. The
711 * driver registers callbacks to access registers and the interpreter
712 * in the driver parses the tables and executes then to program specific
713 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
714 * atombios.h, and atom.c
718 * cail_pll_read - read PLL register
720 * @info: atom card_info pointer
721 * @reg: PLL register offset
723 * Provides a PLL register accessor for the atom interpreter (r4xx+).
724 * Returns the value of the PLL register.
726 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
728 struct radeon_device *rdev = info->dev->dev_private;
731 r = rdev->pll_rreg(rdev, reg);
736 * cail_pll_write - write PLL register
738 * @info: atom card_info pointer
739 * @reg: PLL register offset
740 * @val: value to write to the pll register
742 * Provides a PLL register accessor for the atom interpreter (r4xx+).
744 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
746 struct radeon_device *rdev = info->dev->dev_private;
748 rdev->pll_wreg(rdev, reg, val);
752 * cail_mc_read - read MC (Memory Controller) register
754 * @info: atom card_info pointer
755 * @reg: MC register offset
757 * Provides an MC register accessor for the atom interpreter (r4xx+).
758 * Returns the value of the MC register.
760 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
762 struct radeon_device *rdev = info->dev->dev_private;
765 r = rdev->mc_rreg(rdev, reg);
770 * cail_mc_write - write MC (Memory Controller) register
772 * @info: atom card_info pointer
773 * @reg: MC register offset
774 * @val: value to write to the pll register
776 * Provides a MC register accessor for the atom interpreter (r4xx+).
778 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
780 struct radeon_device *rdev = info->dev->dev_private;
782 rdev->mc_wreg(rdev, reg, val);
786 * cail_reg_write - write MMIO register
788 * @info: atom card_info pointer
789 * @reg: MMIO register offset
790 * @val: value to write to the pll register
792 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
794 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
796 struct radeon_device *rdev = info->dev->dev_private;
802 * cail_reg_read - read MMIO register
804 * @info: atom card_info pointer
805 * @reg: MMIO register offset
807 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
808 * Returns the value of the MMIO register.
810 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
812 struct radeon_device *rdev = info->dev->dev_private;
820 * cail_ioreg_write - write IO register
822 * @info: atom card_info pointer
823 * @reg: IO register offset
824 * @val: value to write to the pll register
826 * Provides a IO register accessor for the atom interpreter (r4xx+).
828 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
830 struct radeon_device *rdev = info->dev->dev_private;
832 WREG32_IO(reg*4, val);
836 * cail_ioreg_read - read IO register
838 * @info: atom card_info pointer
839 * @reg: IO register offset
841 * Provides an IO register accessor for the atom interpreter (r4xx+).
842 * Returns the value of the IO register.
844 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
846 struct radeon_device *rdev = info->dev->dev_private;
849 r = RREG32_IO(reg*4);
854 * radeon_atombios_init - init the driver info and callbacks for atombios
856 * @rdev: radeon_device pointer
858 * Initializes the driver info and register access callbacks for the
859 * ATOM interpreter (r4xx+).
860 * Returns 0 on sucess, -ENOMEM on failure.
861 * Called at driver startup.
863 int radeon_atombios_init(struct radeon_device *rdev)
865 struct card_info *atom_card_info =
866 kzalloc(sizeof(struct card_info), GFP_KERNEL);
871 rdev->mode_info.atom_card_info = atom_card_info;
872 atom_card_info->dev = rdev->ddev;
873 atom_card_info->reg_read = cail_reg_read;
874 atom_card_info->reg_write = cail_reg_write;
875 /* needed for iio ops */
877 atom_card_info->ioreg_read = cail_ioreg_read;
878 atom_card_info->ioreg_write = cail_ioreg_write;
880 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
881 atom_card_info->ioreg_read = cail_reg_read;
882 atom_card_info->ioreg_write = cail_reg_write;
884 atom_card_info->mc_read = cail_mc_read;
885 atom_card_info->mc_write = cail_mc_write;
886 atom_card_info->pll_read = cail_pll_read;
887 atom_card_info->pll_write = cail_pll_write;
889 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
890 if (!rdev->mode_info.atom_context) {
891 radeon_atombios_fini(rdev);
895 mutex_init(&rdev->mode_info.atom_context->mutex);
896 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
897 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
902 * radeon_atombios_fini - free the driver info and callbacks for atombios
904 * @rdev: radeon_device pointer
906 * Frees the driver info and register access callbacks for the ATOM
907 * interpreter (r4xx+).
908 * Called at driver shutdown.
910 void radeon_atombios_fini(struct radeon_device *rdev)
912 if (rdev->mode_info.atom_context) {
913 kfree(rdev->mode_info.atom_context->scratch);
915 kfree(rdev->mode_info.atom_context);
916 rdev->mode_info.atom_context = NULL;
917 kfree(rdev->mode_info.atom_card_info);
918 rdev->mode_info.atom_card_info = NULL;
923 * COMBIOS is the bios format prior to ATOM. It provides
924 * command tables similar to ATOM, but doesn't have a unified
925 * parser. See radeon_combios.c
929 * radeon_combios_init - init the driver info for combios
931 * @rdev: radeon_device pointer
933 * Initializes the driver info for combios (r1xx-r3xx).
934 * Returns 0 on sucess.
935 * Called at driver startup.
937 int radeon_combios_init(struct radeon_device *rdev)
939 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
944 * radeon_combios_fini - free the driver info for combios
946 * @rdev: radeon_device pointer
948 * Frees the driver info for combios (r1xx-r3xx).
949 * Called at driver shutdown.
951 void radeon_combios_fini(struct radeon_device *rdev)
955 /* if we get transitioned to only one device, take VGA back */
957 * radeon_vga_set_decode - enable/disable vga decode
959 * @cookie: radeon_device pointer
960 * @state: enable/disable vga decode
962 * Enable/disable vga decode (all asics).
963 * Returns VGA resource flags.
965 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
967 struct radeon_device *rdev = cookie;
968 radeon_vga_set_state(rdev, state);
970 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
971 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
973 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
977 * radeon_check_pot_argument - check that argument is a power of two
979 * @arg: value to check
981 * Validates that a certain argument is a power of two (all asics).
982 * Returns true if argument is valid.
984 static bool radeon_check_pot_argument(int arg)
986 return (arg & (arg - 1)) == 0;
990 * radeon_check_arguments - validate module params
992 * @rdev: radeon_device pointer
994 * Validates certain module parameters and updates
995 * the associated values used by the driver (all asics).
997 static void radeon_check_arguments(struct radeon_device *rdev)
999 /* vramlimit must be a power of two */
1000 if (!radeon_check_pot_argument(radeon_vram_limit)) {
1001 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1003 radeon_vram_limit = 0;
1006 if (radeon_gart_size == -1) {
1007 /* default to a larger gart size on newer asics */
1008 if (rdev->family >= CHIP_RV770)
1009 radeon_gart_size = 1024;
1011 radeon_gart_size = 512;
1013 /* gtt size must be power of two and greater or equal to 32M */
1014 if (radeon_gart_size < 32) {
1015 dev_warn(rdev->dev, "gart size (%d) too small\n",
1017 if (rdev->family >= CHIP_RV770)
1018 radeon_gart_size = 1024;
1020 radeon_gart_size = 512;
1021 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1022 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1024 if (rdev->family >= CHIP_RV770)
1025 radeon_gart_size = 1024;
1027 radeon_gart_size = 512;
1029 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1031 /* AGP mode can only be -1, 1, 2, 4, 8 */
1032 switch (radeon_agpmode) {
1041 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1042 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1049 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
1050 * needed for waking up.
1052 * @pdev: pci dev pointer
1054 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
1057 /* 6600m in a macbook pro */
1058 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1059 pdev->subsystem_device == 0x00e2) {
1060 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
1068 * radeon_switcheroo_set_state - set switcheroo state
1070 * @pdev: pci dev pointer
1071 * @state: vga switcheroo state
1073 * Callback for the switcheroo driver. Suspends or resumes the
1074 * the asics before or after it is powered up using ACPI methods.
1076 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1078 struct drm_device *dev = pci_get_drvdata(pdev);
1080 if (radeon_is_px() && state == VGA_SWITCHEROO_OFF)
1083 if (state == VGA_SWITCHEROO_ON) {
1084 unsigned d3_delay = dev->pdev->d3_delay;
1086 printk(KERN_INFO "radeon: switched on\n");
1087 /* don't suspend or resume card normally */
1088 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1090 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
1091 dev->pdev->d3_delay = 20;
1093 radeon_resume_kms(dev, true, true);
1095 dev->pdev->d3_delay = d3_delay;
1097 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1098 drm_kms_helper_poll_enable(dev);
1100 printk(KERN_INFO "radeon: switched off\n");
1101 drm_kms_helper_poll_disable(dev);
1102 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1103 radeon_suspend_kms(dev, true, true);
1104 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1109 * radeon_switcheroo_can_switch - see if switcheroo state can change
1111 * @pdev: pci dev pointer
1113 * Callback for the switcheroo driver. Check of the switcheroo
1114 * state can be changed.
1115 * Returns true if the state can be changed, false if not.
1117 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1119 struct drm_device *dev = pci_get_drvdata(pdev);
1122 spin_lock(&dev->count_lock);
1123 can_switch = (dev->open_count == 0);
1124 spin_unlock(&dev->count_lock);
1128 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1129 .set_gpu_state = radeon_switcheroo_set_state,
1131 .can_switch = radeon_switcheroo_can_switch,
1135 * radeon_device_init - initialize the driver
1137 * @rdev: radeon_device pointer
1138 * @pdev: drm dev pointer
1139 * @pdev: pci dev pointer
1140 * @flags: driver flags
1142 * Initializes the driver info and hw (all asics).
1143 * Returns 0 for success or an error on failure.
1144 * Called at driver startup.
1146 int radeon_device_init(struct radeon_device *rdev,
1147 struct drm_device *ddev,
1148 struct pci_dev *pdev,
1153 bool runtime = false;
1155 rdev->shutdown = false;
1156 rdev->dev = &pdev->dev;
1159 rdev->flags = flags;
1160 rdev->family = flags & RADEON_FAMILY_MASK;
1161 rdev->is_atom_bios = false;
1162 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1163 rdev->mc.gtt_size = 512 * 1024 * 1024;
1164 rdev->accel_working = false;
1165 /* set up ring ids */
1166 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1167 rdev->ring[i].idx = i;
1170 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1171 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1172 pdev->subsystem_vendor, pdev->subsystem_device);
1174 /* mutex initialization are all done here so we
1175 * can recall function without having locking issues */
1176 mutex_init(&rdev->ring_lock);
1177 mutex_init(&rdev->dc_hw_i2c_mutex);
1178 atomic_set(&rdev->ih.lock, 0);
1179 mutex_init(&rdev->gem.mutex);
1180 mutex_init(&rdev->pm.mutex);
1181 mutex_init(&rdev->gpu_clock_mutex);
1182 mutex_init(&rdev->srbm_mutex);
1183 init_rwsem(&rdev->pm.mclk_lock);
1184 init_rwsem(&rdev->exclusive_lock);
1185 init_waitqueue_head(&rdev->irq.vblank_queue);
1186 r = radeon_gem_init(rdev);
1189 /* initialize vm here */
1190 mutex_init(&rdev->vm_manager.lock);
1191 /* Adjust VM size here.
1192 * Currently set to 4GB ((1 << 20) 4k pages).
1193 * Max GPUVM size for cayman and SI is 40 bits.
1195 rdev->vm_manager.max_pfn = 1 << 20;
1196 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1198 /* Set asic functions */
1199 r = radeon_asic_init(rdev);
1202 radeon_check_arguments(rdev);
1204 /* all of the newer IGP chips have an internal gart
1205 * However some rs4xx report as AGP, so remove that here.
1207 if ((rdev->family >= CHIP_RS400) &&
1208 (rdev->flags & RADEON_IS_IGP)) {
1209 rdev->flags &= ~RADEON_IS_AGP;
1212 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1213 radeon_agp_disable(rdev);
1216 /* Set the internal MC address mask
1217 * This is the max address of the GPU's
1218 * internal address space.
1220 if (rdev->family >= CHIP_CAYMAN)
1221 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1222 else if (rdev->family >= CHIP_CEDAR)
1223 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1225 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1227 /* set DMA mask + need_dma32 flags.
1228 * PCIE - can handle 40-bits.
1229 * IGP - can handle 40-bits
1230 * AGP - generally dma32 is safest
1231 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1233 rdev->need_dma32 = false;
1234 if (rdev->flags & RADEON_IS_AGP)
1235 rdev->need_dma32 = true;
1236 if ((rdev->flags & RADEON_IS_PCI) &&
1237 (rdev->family <= CHIP_RS740))
1238 rdev->need_dma32 = true;
1240 dma_bits = rdev->need_dma32 ? 32 : 40;
1241 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1243 rdev->need_dma32 = true;
1245 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1247 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1249 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1250 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1253 /* Registers mapping */
1254 /* TODO: block userspace mapping of io register */
1255 spin_lock_init(&rdev->mmio_idx_lock);
1256 spin_lock_init(&rdev->smc_idx_lock);
1257 spin_lock_init(&rdev->pll_idx_lock);
1258 spin_lock_init(&rdev->mc_idx_lock);
1259 spin_lock_init(&rdev->pcie_idx_lock);
1260 spin_lock_init(&rdev->pciep_idx_lock);
1261 spin_lock_init(&rdev->pif_idx_lock);
1262 spin_lock_init(&rdev->cg_idx_lock);
1263 spin_lock_init(&rdev->uvd_idx_lock);
1264 spin_lock_init(&rdev->rcu_idx_lock);
1265 spin_lock_init(&rdev->didt_idx_lock);
1266 spin_lock_init(&rdev->end_idx_lock);
1267 if (rdev->family >= CHIP_BONAIRE) {
1268 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1269 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1271 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1272 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1274 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1275 if (rdev->rmmio == NULL) {
1278 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1279 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1281 /* doorbell bar mapping */
1282 if (rdev->family >= CHIP_BONAIRE)
1283 radeon_doorbell_init(rdev);
1285 /* io port mapping */
1286 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1287 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1288 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1289 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1293 if (rdev->rio_mem == NULL)
1294 DRM_ERROR("Unable to find PCI I/O BAR\n");
1296 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1297 /* this will fail for cards that aren't VGA class devices, just
1299 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1301 if (radeon_runtime_pm == 1)
1303 if ((radeon_runtime_pm == -1) && radeon_is_px())
1305 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1307 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1309 r = radeon_init(rdev);
1313 r = radeon_ib_ring_tests(rdev);
1315 DRM_ERROR("ib ring test failed (%d).\n", r);
1317 r = radeon_gem_debugfs_init(rdev);
1319 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1322 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1323 /* Acceleration not working on AGP card try again
1324 * with fallback to PCI or PCIE GART
1326 radeon_asic_reset(rdev);
1328 radeon_agp_disable(rdev);
1329 r = radeon_init(rdev);
1333 if ((radeon_testing & 1)) {
1334 if (rdev->accel_working)
1335 radeon_test_moves(rdev);
1337 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1339 if ((radeon_testing & 2)) {
1340 if (rdev->accel_working)
1341 radeon_test_syncing(rdev);
1343 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1345 if (radeon_benchmarking) {
1346 if (rdev->accel_working)
1347 radeon_benchmark(rdev, radeon_benchmarking);
1349 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1354 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1357 * radeon_device_fini - tear down the driver
1359 * @rdev: radeon_device pointer
1361 * Tear down the driver info (all asics).
1362 * Called at driver shutdown.
1364 void radeon_device_fini(struct radeon_device *rdev)
1366 DRM_INFO("radeon: finishing device.\n");
1367 rdev->shutdown = true;
1368 /* evict vram memory */
1369 radeon_bo_evict_vram(rdev);
1371 vga_switcheroo_unregister_client(rdev->pdev);
1372 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1374 pci_iounmap(rdev->pdev, rdev->rio_mem);
1375 rdev->rio_mem = NULL;
1376 iounmap(rdev->rmmio);
1378 if (rdev->family >= CHIP_BONAIRE)
1379 radeon_doorbell_fini(rdev);
1380 radeon_debugfs_remove_files(rdev);
1388 * radeon_suspend_kms - initiate device suspend
1390 * @pdev: drm dev pointer
1391 * @state: suspend state
1393 * Puts the hw in the suspend state (all asics).
1394 * Returns 0 for success or an error on failure.
1395 * Called at driver suspend.
1397 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1399 struct radeon_device *rdev;
1400 struct drm_crtc *crtc;
1401 struct drm_connector *connector;
1403 bool force_completion = false;
1405 if (dev == NULL || dev->dev_private == NULL) {
1409 rdev = dev->dev_private;
1411 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1414 drm_kms_helper_poll_disable(dev);
1416 /* turn off display hw */
1417 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1418 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1421 /* unpin the front buffers */
1422 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1423 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
1424 struct radeon_bo *robj;
1426 if (rfb == NULL || rfb->obj == NULL) {
1429 robj = gem_to_radeon_bo(rfb->obj);
1430 /* don't unpin kernel fb objects */
1431 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1432 r = radeon_bo_reserve(robj, false);
1434 radeon_bo_unpin(robj);
1435 radeon_bo_unreserve(robj);
1439 /* evict vram memory */
1440 radeon_bo_evict_vram(rdev);
1442 mutex_lock(&rdev->ring_lock);
1443 /* wait for gpu to finish processing current batch */
1444 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1445 r = radeon_fence_wait_empty_locked(rdev, i);
1447 /* delay GPU reset to resume */
1448 force_completion = true;
1451 if (force_completion) {
1452 radeon_fence_driver_force_completion(rdev);
1454 mutex_unlock(&rdev->ring_lock);
1456 radeon_save_bios_scratch_regs(rdev);
1458 radeon_pm_suspend(rdev);
1459 radeon_suspend(rdev);
1460 radeon_hpd_fini(rdev);
1461 /* evict remaining vram memory */
1462 radeon_bo_evict_vram(rdev);
1464 radeon_agp_suspend(rdev);
1466 pci_save_state(dev->pdev);
1468 /* Shut down the device */
1469 pci_disable_device(dev->pdev);
1470 pci_set_power_state(dev->pdev, PCI_D3hot);
1475 radeon_fbdev_set_suspend(rdev, 1);
1482 * radeon_resume_kms - initiate device resume
1484 * @pdev: drm dev pointer
1486 * Bring the hw back to operating state (all asics).
1487 * Returns 0 for success or an error on failure.
1488 * Called at driver resume.
1490 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1492 struct drm_connector *connector;
1493 struct radeon_device *rdev = dev->dev_private;
1496 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1503 pci_set_power_state(dev->pdev, PCI_D0);
1504 pci_restore_state(dev->pdev);
1505 if (pci_enable_device(dev->pdev)) {
1511 /* resume AGP if in use */
1512 radeon_agp_resume(rdev);
1513 radeon_resume(rdev);
1515 r = radeon_ib_ring_tests(rdev);
1517 DRM_ERROR("ib ring test failed (%d).\n", r);
1519 radeon_pm_resume(rdev);
1520 radeon_restore_bios_scratch_regs(rdev);
1523 radeon_fbdev_set_suspend(rdev, 0);
1527 /* init dig PHYs, disp eng pll */
1528 if (rdev->is_atom_bios) {
1529 radeon_atom_encoder_init(rdev);
1530 radeon_atom_disp_eng_pll_init(rdev);
1531 /* turn on the BL */
1532 if (rdev->mode_info.bl_encoder) {
1533 u8 bl_level = radeon_get_backlight_level(rdev,
1534 rdev->mode_info.bl_encoder);
1535 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1539 /* reset hpd state */
1540 radeon_hpd_init(rdev);
1541 /* blat the mode back in */
1542 drm_helper_resume_force_mode(dev);
1543 /* turn on display hw */
1544 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1545 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1548 drm_kms_helper_poll_enable(dev);
1553 * radeon_gpu_reset - reset the asic
1555 * @rdev: radeon device pointer
1557 * Attempt the reset the GPU if it has hung (all asics).
1558 * Returns 0 for success or an error on failure.
1560 int radeon_gpu_reset(struct radeon_device *rdev)
1562 unsigned ring_sizes[RADEON_NUM_RINGS];
1563 uint32_t *ring_data[RADEON_NUM_RINGS];
1570 down_write(&rdev->exclusive_lock);
1572 if (!rdev->needs_reset) {
1573 up_write(&rdev->exclusive_lock);
1577 rdev->needs_reset = false;
1579 radeon_save_bios_scratch_regs(rdev);
1581 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1582 radeon_pm_suspend(rdev);
1583 radeon_suspend(rdev);
1585 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1586 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1588 if (ring_sizes[i]) {
1590 dev_info(rdev->dev, "Saved %d dwords of commands "
1591 "on ring %d.\n", ring_sizes[i], i);
1596 r = radeon_asic_reset(rdev);
1598 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1599 radeon_resume(rdev);
1602 radeon_restore_bios_scratch_regs(rdev);
1605 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1606 radeon_ring_restore(rdev, &rdev->ring[i],
1607 ring_sizes[i], ring_data[i]);
1609 ring_data[i] = NULL;
1612 r = radeon_ib_ring_tests(rdev);
1614 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1617 radeon_suspend(rdev);
1622 radeon_fence_driver_force_completion(rdev);
1623 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1624 kfree(ring_data[i]);
1628 radeon_pm_resume(rdev);
1629 drm_helper_resume_force_mode(rdev->ddev);
1631 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1633 /* bad news, how to tell it to userspace ? */
1634 dev_info(rdev->dev, "GPU reset failed\n");
1637 up_write(&rdev->exclusive_lock);
1645 int radeon_debugfs_add_files(struct radeon_device *rdev,
1646 struct drm_info_list *files,
1651 for (i = 0; i < rdev->debugfs_count; i++) {
1652 if (rdev->debugfs[i].files == files) {
1653 /* Already registered */
1658 i = rdev->debugfs_count + 1;
1659 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1660 DRM_ERROR("Reached maximum number of debugfs components.\n");
1661 DRM_ERROR("Report so we increase "
1662 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1665 rdev->debugfs[rdev->debugfs_count].files = files;
1666 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1667 rdev->debugfs_count = i;
1668 #if defined(CONFIG_DEBUG_FS)
1669 drm_debugfs_create_files(files, nfiles,
1670 rdev->ddev->control->debugfs_root,
1671 rdev->ddev->control);
1672 drm_debugfs_create_files(files, nfiles,
1673 rdev->ddev->primary->debugfs_root,
1674 rdev->ddev->primary);
1679 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1681 #if defined(CONFIG_DEBUG_FS)
1684 for (i = 0; i < rdev->debugfs_count; i++) {
1685 drm_debugfs_remove_files(rdev->debugfs[i].files,
1686 rdev->debugfs[i].num_files,
1687 rdev->ddev->control);
1688 drm_debugfs_remove_files(rdev->debugfs[i].files,
1689 rdev->debugfs[i].num_files,
1690 rdev->ddev->primary);
1695 #if defined(CONFIG_DEBUG_FS)
1696 int radeon_debugfs_init(struct drm_minor *minor)
1701 void radeon_debugfs_cleanup(struct drm_minor *minor)