2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include <drm/radeon_drm.h>
29 #include "radeon_reg.h"
32 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
34 struct drm_device *ddev = p->rdev->ddev;
35 struct radeon_cs_chunk *chunk;
39 if (p->chunk_relocs_idx == -1) {
42 chunk = &p->chunks[p->chunk_relocs_idx];
44 /* FIXME: we assume that each relocs use 4 dwords */
45 p->nrelocs = chunk->length_dw / 4;
46 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
47 if (p->relocs_ptr == NULL) {
50 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
51 if (p->relocs == NULL) {
54 for (i = 0; i < p->nrelocs; i++) {
55 struct drm_radeon_cs_reloc *r;
58 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
59 for (j = 0; j < i; j++) {
60 if (r->handle == p->relocs[j].handle) {
61 p->relocs_ptr[i] = &p->relocs[j];
67 p->relocs[i].handle = 0;
71 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
73 if (p->relocs[i].gobj == NULL) {
74 DRM_ERROR("gem object lookup failed 0x%x\n",
78 p->relocs_ptr[i] = &p->relocs[i];
79 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
80 p->relocs[i].lobj.bo = p->relocs[i].robj;
81 p->relocs[i].lobj.written = !!r->write_domain;
83 /* the first reloc of an UVD job is the msg and that must be in
84 VRAM, also but everything into VRAM on AGP cards to avoid
86 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
87 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
88 /* TODO: is this still needed for NI+ ? */
89 p->relocs[i].lobj.domain =
90 RADEON_GEM_DOMAIN_VRAM;
92 p->relocs[i].lobj.alt_domain =
93 RADEON_GEM_DOMAIN_VRAM;
96 uint32_t domain = r->write_domain ?
97 r->write_domain : r->read_domains;
99 p->relocs[i].lobj.domain = domain;
100 if (domain == RADEON_GEM_DOMAIN_VRAM)
101 domain |= RADEON_GEM_DOMAIN_GTT;
102 p->relocs[i].lobj.alt_domain = domain;
105 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
106 p->relocs[i].handle = r->handle;
108 radeon_bo_list_add_object(&p->relocs[i].lobj,
111 return radeon_bo_list_validate(&p->validated, p->ring);
114 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
116 p->priority = priority;
120 DRM_ERROR("unknown ring id: %d\n", ring);
122 case RADEON_CS_RING_GFX:
123 p->ring = RADEON_RING_TYPE_GFX_INDEX;
125 case RADEON_CS_RING_COMPUTE:
126 if (p->rdev->family >= CHIP_TAHITI) {
128 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
130 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
132 p->ring = RADEON_RING_TYPE_GFX_INDEX;
134 case RADEON_CS_RING_DMA:
135 if (p->rdev->family >= CHIP_CAYMAN) {
137 p->ring = R600_RING_TYPE_DMA_INDEX;
139 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
140 } else if (p->rdev->family >= CHIP_R600) {
141 p->ring = R600_RING_TYPE_DMA_INDEX;
146 case RADEON_CS_RING_UVD:
147 p->ring = R600_RING_TYPE_UVD_INDEX;
153 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
157 for (i = 0; i < p->nrelocs; i++) {
158 if (!p->relocs[i].robj)
161 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj);
165 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
166 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
168 struct drm_radeon_cs *cs = data;
169 uint64_t *chunk_array_ptr;
171 u32 ring = RADEON_CS_RING_GFX;
174 if (!cs->num_chunks) {
178 INIT_LIST_HEAD(&p->validated);
181 p->ib.semaphore = NULL;
182 p->const_ib.sa_bo = NULL;
183 p->const_ib.semaphore = NULL;
184 p->chunk_ib_idx = -1;
185 p->chunk_relocs_idx = -1;
186 p->chunk_flags_idx = -1;
187 p->chunk_const_ib_idx = -1;
188 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
189 if (p->chunks_array == NULL) {
192 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
193 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
194 sizeof(uint64_t)*cs->num_chunks)) {
198 p->nchunks = cs->num_chunks;
199 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
200 if (p->chunks == NULL) {
203 for (i = 0; i < p->nchunks; i++) {
204 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
205 struct drm_radeon_cs_chunk user_chunk;
206 uint32_t __user *cdata;
208 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
209 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
210 sizeof(struct drm_radeon_cs_chunk))) {
213 p->chunks[i].length_dw = user_chunk.length_dw;
214 p->chunks[i].kdata = NULL;
215 p->chunks[i].chunk_id = user_chunk.chunk_id;
216 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
217 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
218 p->chunk_relocs_idx = i;
220 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
222 /* zero length IB isn't useful */
223 if (p->chunks[i].length_dw == 0)
226 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
227 p->chunk_const_ib_idx = i;
228 /* zero length CONST IB isn't useful */
229 if (p->chunks[i].length_dw == 0)
232 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
233 p->chunk_flags_idx = i;
234 /* zero length flags aren't useful */
235 if (p->chunks[i].length_dw == 0)
239 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
240 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
241 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
242 size = p->chunks[i].length_dw * sizeof(uint32_t);
243 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
244 if (p->chunks[i].kdata == NULL) {
247 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
248 p->chunks[i].user_ptr, size)) {
251 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
252 p->cs_flags = p->chunks[i].kdata[0];
253 if (p->chunks[i].length_dw > 1)
254 ring = p->chunks[i].kdata[1];
255 if (p->chunks[i].length_dw > 2)
256 priority = (s32)p->chunks[i].kdata[2];
261 /* these are KMS only */
263 if ((p->cs_flags & RADEON_CS_USE_VM) &&
264 !p->rdev->vm_manager.enabled) {
265 DRM_ERROR("VM not active on asic!\n");
269 if (radeon_cs_get_ring(p, ring, priority))
272 /* we only support VM on some SI+ rings */
273 if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) &&
274 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
275 DRM_ERROR("Ring %d requires VM!\n", p->ring);
280 /* deal with non-vm */
281 if ((p->chunk_ib_idx != -1) &&
282 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
283 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
284 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
285 DRM_ERROR("cs IB too big: %d\n",
286 p->chunks[p->chunk_ib_idx].length_dw);
289 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) {
290 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
291 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
292 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
293 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
294 kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
295 kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
296 p->chunks[p->chunk_ib_idx].kpage[0] = NULL;
297 p->chunks[p->chunk_ib_idx].kpage[1] = NULL;
301 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
302 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
303 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
304 p->chunks[p->chunk_ib_idx].last_page_index =
305 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
312 * cs_parser_fini() - clean parser states
313 * @parser: parser structure holding parsing context.
314 * @error: error number
316 * If error is set than unvalidate buffer, otherwise just free memory
317 * used by parsing context.
319 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
324 ttm_eu_fence_buffer_objects(&parser->validated,
327 ttm_eu_backoff_reservation(&parser->validated);
330 if (parser->relocs != NULL) {
331 for (i = 0; i < parser->nrelocs; i++) {
332 if (parser->relocs[i].gobj)
333 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
336 kfree(parser->track);
337 kfree(parser->relocs);
338 kfree(parser->relocs_ptr);
339 for (i = 0; i < parser->nchunks; i++) {
340 kfree(parser->chunks[i].kdata);
341 if ((parser->rdev->flags & RADEON_IS_AGP)) {
342 kfree(parser->chunks[i].kpage[0]);
343 kfree(parser->chunks[i].kpage[1]);
346 kfree(parser->chunks);
347 kfree(parser->chunks_array);
348 radeon_ib_free(parser->rdev, &parser->ib);
349 radeon_ib_free(parser->rdev, &parser->const_ib);
352 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
353 struct radeon_cs_parser *parser)
355 struct radeon_cs_chunk *ib_chunk;
358 if (parser->chunk_ib_idx == -1)
361 if (parser->cs_flags & RADEON_CS_USE_VM)
364 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
365 /* Copy the packet into the IB, the parser will read from the
366 * input memory (cached) and write to the IB (which can be
369 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
370 NULL, ib_chunk->length_dw * 4);
372 DRM_ERROR("Failed to get ib !\n");
375 parser->ib.length_dw = ib_chunk->length_dw;
376 r = radeon_cs_parse(rdev, parser->ring, parser);
377 if (r || parser->parser_error) {
378 DRM_ERROR("Invalid command stream !\n");
381 r = radeon_cs_finish_pages(parser);
383 DRM_ERROR("Invalid command stream !\n");
386 radeon_cs_sync_rings(parser);
387 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
389 DRM_ERROR("Failed to schedule IB !\n");
394 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
395 struct radeon_vm *vm)
397 struct radeon_device *rdev = parser->rdev;
398 struct radeon_bo_list *lobj;
399 struct radeon_bo *bo;
402 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
406 list_for_each_entry(lobj, &parser->validated, tv.head) {
408 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
416 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
417 struct radeon_cs_parser *parser)
419 struct radeon_cs_chunk *ib_chunk;
420 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
421 struct radeon_vm *vm = &fpriv->vm;
424 if (parser->chunk_ib_idx == -1)
426 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
429 if ((rdev->family >= CHIP_TAHITI) &&
430 (parser->chunk_const_ib_idx != -1)) {
431 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
432 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
433 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
436 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
437 vm, ib_chunk->length_dw * 4);
439 DRM_ERROR("Failed to get const ib !\n");
442 parser->const_ib.is_const_ib = true;
443 parser->const_ib.length_dw = ib_chunk->length_dw;
444 /* Copy the packet into the IB */
445 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
446 ib_chunk->length_dw * 4)) {
449 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
455 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
456 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
457 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
460 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
461 vm, ib_chunk->length_dw * 4);
463 DRM_ERROR("Failed to get ib !\n");
466 parser->ib.length_dw = ib_chunk->length_dw;
467 /* Copy the packet into the IB */
468 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
469 ib_chunk->length_dw * 4)) {
472 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
477 mutex_lock(&rdev->vm_manager.lock);
478 mutex_lock(&vm->mutex);
479 r = radeon_vm_alloc_pt(rdev, vm);
483 r = radeon_bo_vm_update_pte(parser, vm);
487 radeon_cs_sync_rings(parser);
488 radeon_ib_sync_to(&parser->ib, vm->fence);
489 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id(
490 rdev, vm, parser->ring));
492 if ((rdev->family >= CHIP_TAHITI) &&
493 (parser->chunk_const_ib_idx != -1)) {
494 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
496 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
500 radeon_vm_fence(rdev, vm, parser->ib.fence);
504 radeon_vm_add_to_lru(rdev, vm);
505 mutex_unlock(&vm->mutex);
506 mutex_unlock(&rdev->vm_manager.lock);
510 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
513 r = radeon_gpu_reset(rdev);
520 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
522 struct radeon_device *rdev = dev->dev_private;
523 struct radeon_cs_parser parser;
526 down_read(&rdev->exclusive_lock);
527 if (!rdev->accel_working) {
528 up_read(&rdev->exclusive_lock);
531 /* initialize parser */
532 memset(&parser, 0, sizeof(struct radeon_cs_parser));
535 parser.dev = rdev->dev;
536 parser.family = rdev->family;
537 r = radeon_cs_parser_init(&parser, data);
539 DRM_ERROR("Failed to initialize parser !\n");
540 radeon_cs_parser_fini(&parser, r);
541 up_read(&rdev->exclusive_lock);
542 r = radeon_cs_handle_lockup(rdev, r);
545 r = radeon_cs_parser_relocs(&parser);
547 if (r != -ERESTARTSYS)
548 DRM_ERROR("Failed to parse relocation %d!\n", r);
549 radeon_cs_parser_fini(&parser, r);
550 up_read(&rdev->exclusive_lock);
551 r = radeon_cs_handle_lockup(rdev, r);
555 if (parser.ring == R600_RING_TYPE_UVD_INDEX)
556 radeon_uvd_note_usage(rdev);
558 r = radeon_cs_ib_chunk(rdev, &parser);
562 r = radeon_cs_ib_vm_chunk(rdev, &parser);
567 radeon_cs_parser_fini(&parser, r);
568 up_read(&rdev->exclusive_lock);
569 r = radeon_cs_handle_lockup(rdev, r);
573 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
575 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
577 int size = PAGE_SIZE;
579 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
580 if (i == ibc->last_page_index) {
581 size = (ibc->length_dw * 4) % PAGE_SIZE;
586 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
587 ibc->user_ptr + (i * PAGE_SIZE),
594 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
597 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
599 int size = PAGE_SIZE;
600 bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ?
603 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
604 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
605 ibc->user_ptr + (i * PAGE_SIZE),
607 p->parser_error = -EFAULT;
612 if (pg_idx == ibc->last_page_index) {
613 size = (ibc->length_dw * 4) % PAGE_SIZE;
618 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
620 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
622 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
623 ibc->user_ptr + (pg_idx * PAGE_SIZE),
625 p->parser_error = -EFAULT;
629 /* copy to IB for non single case */
631 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
633 ibc->last_copied_page = pg_idx;
634 ibc->kpage_idx[new_page] = pg_idx;
639 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
641 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
642 u32 pg_idx, pg_offset;
646 pg_idx = (idx * 4) / PAGE_SIZE;
647 pg_offset = (idx * 4) % PAGE_SIZE;
649 if (ibc->kpage_idx[0] == pg_idx)
650 return ibc->kpage[0][pg_offset/4];
651 if (ibc->kpage_idx[1] == pg_idx)
652 return ibc->kpage[1][pg_offset/4];
654 new_page = radeon_cs_update_pages(p, pg_idx);
656 p->parser_error = new_page;
660 idx_value = ibc->kpage[new_page][pg_offset/4];
665 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
666 * @parser: parser structure holding parsing context.
667 * @pkt: where to store packet information
669 * Assume that chunk_ib_index is properly set. Will return -EINVAL
670 * if packet is bigger than remaining ib size. or if packets is unknown.
672 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
673 struct radeon_cs_packet *pkt,
676 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
677 struct radeon_device *rdev = p->rdev;
680 if (idx >= ib_chunk->length_dw) {
681 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
682 idx, ib_chunk->length_dw);
685 header = radeon_get_ib_value(p, idx);
687 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
688 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
691 case RADEON_PACKET_TYPE0:
692 if (rdev->family < CHIP_R600) {
693 pkt->reg = R100_CP_PACKET0_GET_REG(header);
695 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
697 pkt->reg = R600_CP_PACKET0_GET_REG(header);
699 case RADEON_PACKET_TYPE3:
700 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
702 case RADEON_PACKET_TYPE2:
706 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
709 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
710 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
711 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
718 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
719 * @p: structure holding the parser context.
721 * Check if the next packet is NOP relocation packet3.
723 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
725 struct radeon_cs_packet p3reloc;
728 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
731 if (p3reloc.type != RADEON_PACKET_TYPE3)
733 if (p3reloc.opcode != RADEON_PACKET3_NOP)
739 * radeon_cs_dump_packet() - dump raw packet context
740 * @p: structure holding the parser context.
741 * @pkt: structure holding the packet.
743 * Used mostly for debugging and error reporting.
745 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
746 struct radeon_cs_packet *pkt)
748 volatile uint32_t *ib;
754 for (i = 0; i <= (pkt->count + 1); i++, idx++)
755 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
759 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
760 * @parser: parser structure holding parsing context.
761 * @data: pointer to relocation data
762 * @offset_start: starting offset
763 * @offset_mask: offset mask (to align start offset on)
764 * @reloc: reloc informations
766 * Check if next packet is relocation packet3, do bo validation and compute
767 * GPU offset using the provided start.
769 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
770 struct radeon_cs_reloc **cs_reloc,
773 struct radeon_cs_chunk *relocs_chunk;
774 struct radeon_cs_packet p3reloc;
778 if (p->chunk_relocs_idx == -1) {
779 DRM_ERROR("No relocation chunk !\n");
783 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
784 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
787 p->idx += p3reloc.count + 2;
788 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
789 p3reloc.opcode != RADEON_PACKET3_NOP) {
790 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
792 radeon_cs_dump_packet(p, &p3reloc);
795 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
796 if (idx >= relocs_chunk->length_dw) {
797 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
798 idx, relocs_chunk->length_dw);
799 radeon_cs_dump_packet(p, &p3reloc);
802 /* FIXME: we assume reloc size is 4 dwords */
804 *cs_reloc = p->relocs;
805 (*cs_reloc)->lobj.gpu_offset =
806 (u64)relocs_chunk->kdata[idx + 3] << 32;
807 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
809 *cs_reloc = p->relocs_ptr[(idx / 4)];