2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include "radeon_drm.h"
29 #include "radeon_reg.h"
32 void r100_cs_dump_packet(struct radeon_cs_parser *p,
33 struct radeon_cs_packet *pkt);
35 int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
37 struct drm_device *ddev = p->rdev->ddev;
38 struct radeon_cs_chunk *chunk;
42 if (p->chunk_relocs_idx == -1) {
45 chunk = &p->chunks[p->chunk_relocs_idx];
46 /* FIXME: we assume that each relocs use 4 dwords */
47 p->nrelocs = chunk->length_dw / 4;
48 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
49 if (p->relocs_ptr == NULL) {
52 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
53 if (p->relocs == NULL) {
56 for (i = 0; i < p->nrelocs; i++) {
57 struct drm_radeon_cs_reloc *r;
60 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
61 for (j = 0; j < i; j++) {
62 if (r->handle == p->relocs[j].handle) {
63 p->relocs_ptr[i] = &p->relocs[j];
69 p->relocs[i].gobj = drm_gem_object_lookup(ddev,
72 if (p->relocs[i].gobj == NULL) {
73 DRM_ERROR("gem object lookup failed 0x%x\n",
77 p->relocs_ptr[i] = &p->relocs[i];
78 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
79 p->relocs[i].lobj.bo = p->relocs[i].robj;
80 p->relocs[i].lobj.wdomain = r->write_domain;
81 p->relocs[i].lobj.rdomain = r->read_domains;
82 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
83 p->relocs[i].handle = r->handle;
84 p->relocs[i].flags = r->flags;
85 radeon_bo_list_add_object(&p->relocs[i].lobj,
89 p->relocs[i].handle = 0;
91 return radeon_bo_list_validate(&p->validated);
94 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
96 p->priority = priority;
100 DRM_ERROR("unknown ring id: %d\n", ring);
102 case RADEON_CS_RING_GFX:
103 p->ring = RADEON_RING_TYPE_GFX_INDEX;
105 case RADEON_CS_RING_COMPUTE:
106 if (p->rdev->family >= CHIP_TAHITI) {
108 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
110 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
112 p->ring = RADEON_RING_TYPE_GFX_INDEX;
118 static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
120 bool sync_to_ring[RADEON_NUM_RINGS] = { };
123 for (i = 0; i < p->nrelocs; i++) {
124 if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
127 if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
128 struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
129 if (!radeon_fence_signaled(fence)) {
130 sync_to_ring[fence->ring] = true;
135 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
136 /* no need to sync to our own or unused rings */
137 if (i == p->ring || !sync_to_ring[i] || !p->rdev->ring[i].ready)
140 if (!p->ib->fence->semaphore) {
141 r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
146 r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3);
149 radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore);
150 radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]);
152 r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3);
155 radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore);
156 radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]);
161 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
163 struct drm_radeon_cs *cs = data;
164 uint64_t *chunk_array_ptr;
166 u32 ring = RADEON_CS_RING_GFX;
169 if (!cs->num_chunks) {
173 INIT_LIST_HEAD(&p->validated);
175 p->chunk_ib_idx = -1;
176 p->chunk_relocs_idx = -1;
177 p->chunk_flags_idx = -1;
178 p->chunk_const_ib_idx = -1;
179 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
180 if (p->chunks_array == NULL) {
183 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
184 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
185 sizeof(uint64_t)*cs->num_chunks)) {
189 p->nchunks = cs->num_chunks;
190 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
191 if (p->chunks == NULL) {
194 for (i = 0; i < p->nchunks; i++) {
195 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
196 struct drm_radeon_cs_chunk user_chunk;
197 uint32_t __user *cdata;
199 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
200 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
201 sizeof(struct drm_radeon_cs_chunk))) {
204 p->chunks[i].length_dw = user_chunk.length_dw;
205 p->chunks[i].kdata = NULL;
206 p->chunks[i].chunk_id = user_chunk.chunk_id;
208 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
209 p->chunk_relocs_idx = i;
211 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
213 /* zero length IB isn't useful */
214 if (p->chunks[i].length_dw == 0)
217 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
218 p->chunk_const_ib_idx = i;
219 /* zero length CONST IB isn't useful */
220 if (p->chunks[i].length_dw == 0)
223 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
224 p->chunk_flags_idx = i;
225 /* zero length flags aren't useful */
226 if (p->chunks[i].length_dw == 0)
230 p->chunks[i].length_dw = user_chunk.length_dw;
231 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
233 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
234 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
235 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
236 size = p->chunks[i].length_dw * sizeof(uint32_t);
237 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
238 if (p->chunks[i].kdata == NULL) {
241 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
242 p->chunks[i].user_ptr, size)) {
245 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
246 p->cs_flags = p->chunks[i].kdata[0];
247 if (p->chunks[i].length_dw > 1)
248 ring = p->chunks[i].kdata[1];
249 if (p->chunks[i].length_dw > 2)
250 priority = (s32)p->chunks[i].kdata[2];
255 if ((p->cs_flags & RADEON_CS_USE_VM) &&
256 !p->rdev->vm_manager.enabled) {
257 DRM_ERROR("VM not active on asic!\n");
261 /* we only support VM on SI+ */
262 if ((p->rdev->family >= CHIP_TAHITI) &&
263 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
264 DRM_ERROR("VM required on SI+!\n");
268 if (radeon_cs_get_ring(p, ring, priority))
272 /* deal with non-vm */
273 if ((p->chunk_ib_idx != -1) &&
274 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
275 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
276 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
277 DRM_ERROR("cs IB too big: %d\n",
278 p->chunks[p->chunk_ib_idx].length_dw);
281 if ((p->rdev->flags & RADEON_IS_AGP)) {
282 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
283 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
284 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
285 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
286 kfree(p->chunks[i].kpage[0]);
287 kfree(p->chunks[i].kpage[1]);
291 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
292 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
293 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
294 p->chunks[p->chunk_ib_idx].last_page_index =
295 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
302 * cs_parser_fini() - clean parser states
303 * @parser: parser structure holding parsing context.
304 * @error: error number
306 * If error is set than unvalidate buffer, otherwise just free memory
307 * used by parsing context.
309 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
314 if (!error && parser->ib)
315 ttm_eu_fence_buffer_objects(&parser->validated,
318 ttm_eu_backoff_reservation(&parser->validated);
320 if (parser->relocs != NULL) {
321 for (i = 0; i < parser->nrelocs; i++) {
322 if (parser->relocs[i].gobj)
323 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
326 kfree(parser->track);
327 kfree(parser->relocs);
328 kfree(parser->relocs_ptr);
329 for (i = 0; i < parser->nchunks; i++) {
330 kfree(parser->chunks[i].kdata);
331 if ((parser->rdev->flags & RADEON_IS_AGP)) {
332 kfree(parser->chunks[i].kpage[0]);
333 kfree(parser->chunks[i].kpage[1]);
336 kfree(parser->chunks);
337 kfree(parser->chunks_array);
338 radeon_ib_free(parser->rdev, &parser->ib);
341 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
342 struct radeon_cs_parser *parser)
344 struct radeon_cs_chunk *ib_chunk;
347 if (parser->chunk_ib_idx == -1)
350 if (parser->cs_flags & RADEON_CS_USE_VM)
353 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
354 /* Copy the packet into the IB, the parser will read from the
355 * input memory (cached) and write to the IB (which can be
358 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
359 ib_chunk->length_dw * 4);
361 DRM_ERROR("Failed to get ib !\n");
364 parser->ib->length_dw = ib_chunk->length_dw;
365 r = radeon_cs_parse(rdev, parser->ring, parser);
366 if (r || parser->parser_error) {
367 DRM_ERROR("Invalid command stream !\n");
370 r = radeon_cs_finish_pages(parser);
372 DRM_ERROR("Invalid command stream !\n");
375 r = radeon_cs_sync_rings(parser);
377 DRM_ERROR("Failed to synchronize rings !\n");
379 parser->ib->vm_id = 0;
380 r = radeon_ib_schedule(rdev, parser->ib);
382 DRM_ERROR("Failed to schedule IB !\n");
387 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
388 struct radeon_vm *vm)
390 struct radeon_bo_list *lobj;
391 struct radeon_bo *bo;
394 list_for_each_entry(lobj, &parser->validated, tv.head) {
396 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
404 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
405 struct radeon_cs_parser *parser)
407 struct radeon_cs_chunk *ib_chunk;
408 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
409 struct radeon_vm *vm = &fpriv->vm;
412 if (parser->chunk_ib_idx == -1)
415 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
418 if ((rdev->family >= CHIP_TAHITI) &&
419 (parser->chunk_const_ib_idx != -1)) {
420 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
421 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
422 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
425 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
426 ib_chunk->length_dw * 4);
428 DRM_ERROR("Failed to get const ib !\n");
431 parser->const_ib->is_const_ib = true;
432 parser->const_ib->length_dw = ib_chunk->length_dw;
433 /* Copy the packet into the IB */
434 if (DRM_COPY_FROM_USER(parser->const_ib->ptr, ib_chunk->user_ptr,
435 ib_chunk->length_dw * 4)) {
438 r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib);
444 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
445 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
446 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
449 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
450 ib_chunk->length_dw * 4);
452 DRM_ERROR("Failed to get ib !\n");
455 parser->ib->length_dw = ib_chunk->length_dw;
456 /* Copy the packet into the IB */
457 if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
458 ib_chunk->length_dw * 4)) {
461 r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
466 mutex_lock(&vm->mutex);
467 r = radeon_vm_bind(rdev, vm);
471 r = radeon_bo_vm_update_pte(parser, vm);
475 r = radeon_cs_sync_rings(parser);
477 DRM_ERROR("Failed to synchronize rings !\n");
480 if ((rdev->family >= CHIP_TAHITI) &&
481 (parser->chunk_const_ib_idx != -1)) {
482 parser->const_ib->vm_id = vm->id;
483 /* ib pool is bind at 0 in virtual address space to gpu_addr is the
484 * offset inside the pool bo
486 parser->const_ib->gpu_addr = parser->const_ib->sa_bo.offset;
487 r = radeon_ib_schedule(rdev, parser->const_ib);
492 parser->ib->vm_id = vm->id;
493 /* ib pool is bind at 0 in virtual address space to gpu_addr is the
494 * offset inside the pool bo
496 parser->ib->gpu_addr = parser->ib->sa_bo.offset;
497 parser->ib->is_const_ib = false;
498 r = radeon_ib_schedule(rdev, parser->ib);
502 radeon_fence_unref(&vm->fence);
504 vm->fence = radeon_fence_ref(parser->ib->fence);
506 mutex_unlock(&fpriv->vm.mutex);
510 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
512 struct radeon_device *rdev = dev->dev_private;
513 struct radeon_cs_parser parser;
516 radeon_mutex_lock(&rdev->cs_mutex);
517 if (!rdev->accel_working) {
518 radeon_mutex_unlock(&rdev->cs_mutex);
521 /* initialize parser */
522 memset(&parser, 0, sizeof(struct radeon_cs_parser));
525 parser.dev = rdev->dev;
526 parser.family = rdev->family;
527 r = radeon_cs_parser_init(&parser, data);
529 DRM_ERROR("Failed to initialize parser !\n");
530 radeon_cs_parser_fini(&parser, r);
531 radeon_mutex_unlock(&rdev->cs_mutex);
534 r = radeon_cs_parser_relocs(&parser);
536 if (r != -ERESTARTSYS)
537 DRM_ERROR("Failed to parse relocation %d!\n", r);
538 radeon_cs_parser_fini(&parser, r);
539 radeon_mutex_unlock(&rdev->cs_mutex);
542 r = radeon_cs_ib_chunk(rdev, &parser);
546 r = radeon_cs_ib_vm_chunk(rdev, &parser);
551 radeon_cs_parser_fini(&parser, r);
552 radeon_mutex_unlock(&rdev->cs_mutex);
556 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
558 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
560 int size = PAGE_SIZE;
562 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
563 if (i == ibc->last_page_index) {
564 size = (ibc->length_dw * 4) % PAGE_SIZE;
569 if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
570 ibc->user_ptr + (i * PAGE_SIZE),
577 int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
580 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
582 int size = PAGE_SIZE;
583 bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
585 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
586 if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
587 ibc->user_ptr + (i * PAGE_SIZE),
589 p->parser_error = -EFAULT;
594 if (pg_idx == ibc->last_page_index) {
595 size = (ibc->length_dw * 4) % PAGE_SIZE;
600 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
602 ibc->kpage[new_page] = p->ib->ptr + (pg_idx * (PAGE_SIZE / 4));
604 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
605 ibc->user_ptr + (pg_idx * PAGE_SIZE),
607 p->parser_error = -EFAULT;
611 /* copy to IB for non single case */
613 memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
615 ibc->last_copied_page = pg_idx;
616 ibc->kpage_idx[new_page] = pg_idx;