2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include <drm/radeon_drm.h>
29 #include "radeon_reg.h"
32 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
34 struct drm_device *ddev = p->rdev->ddev;
35 struct radeon_cs_chunk *chunk;
39 if (p->chunk_relocs_idx == -1) {
42 chunk = &p->chunks[p->chunk_relocs_idx];
44 /* FIXME: we assume that each relocs use 4 dwords */
45 p->nrelocs = chunk->length_dw / 4;
46 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
47 if (p->relocs_ptr == NULL) {
50 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
51 if (p->relocs == NULL) {
54 for (i = 0; i < p->nrelocs; i++) {
55 struct drm_radeon_cs_reloc *r;
58 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
59 for (j = 0; j < i; j++) {
60 if (r->handle == p->relocs[j].handle) {
61 p->relocs_ptr[i] = &p->relocs[j];
67 p->relocs[i].handle = 0;
71 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
73 if (p->relocs[i].gobj == NULL) {
74 DRM_ERROR("gem object lookup failed 0x%x\n",
78 p->relocs_ptr[i] = &p->relocs[i];
79 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
80 p->relocs[i].lobj.bo = p->relocs[i].robj;
81 p->relocs[i].lobj.written = !!r->write_domain;
83 /* the first reloc of an UVD job is the msg and that must be in
84 VRAM, also but everything into VRAM on AGP cards to avoid
86 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
87 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
88 /* TODO: is this still needed for NI+ ? */
89 p->relocs[i].lobj.domain =
90 RADEON_GEM_DOMAIN_VRAM;
92 p->relocs[i].lobj.alt_domain =
93 RADEON_GEM_DOMAIN_VRAM;
96 uint32_t domain = r->write_domain ?
97 r->write_domain : r->read_domains;
99 if (domain & RADEON_GEM_DOMAIN_CPU) {
100 DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "
101 "for command submission\n");
105 p->relocs[i].lobj.domain = domain;
106 if (domain == RADEON_GEM_DOMAIN_VRAM)
107 domain |= RADEON_GEM_DOMAIN_GTT;
108 p->relocs[i].lobj.alt_domain = domain;
111 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
112 p->relocs[i].handle = r->handle;
114 radeon_bo_list_add_object(&p->relocs[i].lobj,
117 return radeon_bo_list_validate(&p->validated, p->ring);
120 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
122 p->priority = priority;
126 DRM_ERROR("unknown ring id: %d\n", ring);
128 case RADEON_CS_RING_GFX:
129 p->ring = RADEON_RING_TYPE_GFX_INDEX;
131 case RADEON_CS_RING_COMPUTE:
132 if (p->rdev->family >= CHIP_TAHITI) {
134 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
136 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
138 p->ring = RADEON_RING_TYPE_GFX_INDEX;
140 case RADEON_CS_RING_DMA:
141 if (p->rdev->family >= CHIP_CAYMAN) {
143 p->ring = R600_RING_TYPE_DMA_INDEX;
145 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
146 } else if (p->rdev->family >= CHIP_R600) {
147 p->ring = R600_RING_TYPE_DMA_INDEX;
152 case RADEON_CS_RING_UVD:
153 p->ring = R600_RING_TYPE_UVD_INDEX;
159 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
163 for (i = 0; i < p->nrelocs; i++) {
164 if (!p->relocs[i].robj)
167 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj);
171 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
172 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
174 struct drm_radeon_cs *cs = data;
175 uint64_t *chunk_array_ptr;
177 u32 ring = RADEON_CS_RING_GFX;
180 INIT_LIST_HEAD(&p->validated);
182 if (!cs->num_chunks) {
189 p->ib.semaphore = NULL;
190 p->const_ib.sa_bo = NULL;
191 p->const_ib.semaphore = NULL;
192 p->chunk_ib_idx = -1;
193 p->chunk_relocs_idx = -1;
194 p->chunk_flags_idx = -1;
195 p->chunk_const_ib_idx = -1;
196 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
197 if (p->chunks_array == NULL) {
200 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
201 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
202 sizeof(uint64_t)*cs->num_chunks)) {
206 p->nchunks = cs->num_chunks;
207 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
208 if (p->chunks == NULL) {
211 for (i = 0; i < p->nchunks; i++) {
212 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
213 struct drm_radeon_cs_chunk user_chunk;
214 uint32_t __user *cdata;
216 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
217 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
218 sizeof(struct drm_radeon_cs_chunk))) {
221 p->chunks[i].length_dw = user_chunk.length_dw;
222 p->chunks[i].kdata = NULL;
223 p->chunks[i].chunk_id = user_chunk.chunk_id;
224 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
225 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
226 p->chunk_relocs_idx = i;
228 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
230 /* zero length IB isn't useful */
231 if (p->chunks[i].length_dw == 0)
234 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
235 p->chunk_const_ib_idx = i;
236 /* zero length CONST IB isn't useful */
237 if (p->chunks[i].length_dw == 0)
240 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
241 p->chunk_flags_idx = i;
242 /* zero length flags aren't useful */
243 if (p->chunks[i].length_dw == 0)
247 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
248 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
249 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
250 size = p->chunks[i].length_dw * sizeof(uint32_t);
251 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
252 if (p->chunks[i].kdata == NULL) {
255 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
256 p->chunks[i].user_ptr, size)) {
259 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
260 p->cs_flags = p->chunks[i].kdata[0];
261 if (p->chunks[i].length_dw > 1)
262 ring = p->chunks[i].kdata[1];
263 if (p->chunks[i].length_dw > 2)
264 priority = (s32)p->chunks[i].kdata[2];
269 /* these are KMS only */
271 if ((p->cs_flags & RADEON_CS_USE_VM) &&
272 !p->rdev->vm_manager.enabled) {
273 DRM_ERROR("VM not active on asic!\n");
277 if (radeon_cs_get_ring(p, ring, priority))
280 /* we only support VM on some SI+ rings */
281 if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) &&
282 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
283 DRM_ERROR("Ring %d requires VM!\n", p->ring);
288 /* deal with non-vm */
289 if ((p->chunk_ib_idx != -1) &&
290 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
291 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
292 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
293 DRM_ERROR("cs IB too big: %d\n",
294 p->chunks[p->chunk_ib_idx].length_dw);
297 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) {
298 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
299 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
300 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
301 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
302 kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
303 kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
304 p->chunks[p->chunk_ib_idx].kpage[0] = NULL;
305 p->chunks[p->chunk_ib_idx].kpage[1] = NULL;
309 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
310 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
311 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
312 p->chunks[p->chunk_ib_idx].last_page_index =
313 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
320 * cs_parser_fini() - clean parser states
321 * @parser: parser structure holding parsing context.
322 * @error: error number
324 * If error is set than unvalidate buffer, otherwise just free memory
325 * used by parsing context.
327 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
332 ttm_eu_fence_buffer_objects(&parser->validated,
335 ttm_eu_backoff_reservation(&parser->validated);
338 if (parser->relocs != NULL) {
339 for (i = 0; i < parser->nrelocs; i++) {
340 if (parser->relocs[i].gobj)
341 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
344 kfree(parser->track);
345 kfree(parser->relocs);
346 kfree(parser->relocs_ptr);
347 for (i = 0; i < parser->nchunks; i++) {
348 kfree(parser->chunks[i].kdata);
349 if ((parser->rdev->flags & RADEON_IS_AGP)) {
350 kfree(parser->chunks[i].kpage[0]);
351 kfree(parser->chunks[i].kpage[1]);
354 kfree(parser->chunks);
355 kfree(parser->chunks_array);
356 radeon_ib_free(parser->rdev, &parser->ib);
357 radeon_ib_free(parser->rdev, &parser->const_ib);
360 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
361 struct radeon_cs_parser *parser)
363 struct radeon_cs_chunk *ib_chunk;
366 if (parser->chunk_ib_idx == -1)
369 if (parser->cs_flags & RADEON_CS_USE_VM)
372 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
373 /* Copy the packet into the IB, the parser will read from the
374 * input memory (cached) and write to the IB (which can be
377 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
378 NULL, ib_chunk->length_dw * 4);
380 DRM_ERROR("Failed to get ib !\n");
383 parser->ib.length_dw = ib_chunk->length_dw;
384 r = radeon_cs_parse(rdev, parser->ring, parser);
385 if (r || parser->parser_error) {
386 DRM_ERROR("Invalid command stream !\n");
389 r = radeon_cs_finish_pages(parser);
391 DRM_ERROR("Invalid command stream !\n");
394 radeon_cs_sync_rings(parser);
395 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
397 DRM_ERROR("Failed to schedule IB !\n");
402 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
403 struct radeon_vm *vm)
405 struct radeon_device *rdev = parser->rdev;
406 struct radeon_bo_list *lobj;
407 struct radeon_bo *bo;
410 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
414 list_for_each_entry(lobj, &parser->validated, tv.head) {
416 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
424 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
425 struct radeon_cs_parser *parser)
427 struct radeon_cs_chunk *ib_chunk;
428 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
429 struct radeon_vm *vm = &fpriv->vm;
432 if (parser->chunk_ib_idx == -1)
434 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
437 if ((rdev->family >= CHIP_TAHITI) &&
438 (parser->chunk_const_ib_idx != -1)) {
439 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
440 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
441 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
444 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
445 vm, ib_chunk->length_dw * 4);
447 DRM_ERROR("Failed to get const ib !\n");
450 parser->const_ib.is_const_ib = true;
451 parser->const_ib.length_dw = ib_chunk->length_dw;
452 /* Copy the packet into the IB */
453 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
454 ib_chunk->length_dw * 4)) {
457 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
463 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
464 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
465 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
468 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
469 vm, ib_chunk->length_dw * 4);
471 DRM_ERROR("Failed to get ib !\n");
474 parser->ib.length_dw = ib_chunk->length_dw;
475 /* Copy the packet into the IB */
476 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
477 ib_chunk->length_dw * 4)) {
480 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
485 mutex_lock(&rdev->vm_manager.lock);
486 mutex_lock(&vm->mutex);
487 r = radeon_vm_alloc_pt(rdev, vm);
491 r = radeon_bo_vm_update_pte(parser, vm);
495 radeon_cs_sync_rings(parser);
496 radeon_ib_sync_to(&parser->ib, vm->fence);
497 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id(
498 rdev, vm, parser->ring));
500 if ((rdev->family >= CHIP_TAHITI) &&
501 (parser->chunk_const_ib_idx != -1)) {
502 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
504 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
508 radeon_vm_fence(rdev, vm, parser->ib.fence);
512 radeon_vm_add_to_lru(rdev, vm);
513 mutex_unlock(&vm->mutex);
514 mutex_unlock(&rdev->vm_manager.lock);
518 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
521 r = radeon_gpu_reset(rdev);
528 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
530 struct radeon_device *rdev = dev->dev_private;
531 struct radeon_cs_parser parser;
534 down_read(&rdev->exclusive_lock);
535 if (!rdev->accel_working) {
536 up_read(&rdev->exclusive_lock);
539 /* initialize parser */
540 memset(&parser, 0, sizeof(struct radeon_cs_parser));
543 parser.dev = rdev->dev;
544 parser.family = rdev->family;
545 r = radeon_cs_parser_init(&parser, data);
547 DRM_ERROR("Failed to initialize parser !\n");
548 radeon_cs_parser_fini(&parser, r);
549 up_read(&rdev->exclusive_lock);
550 r = radeon_cs_handle_lockup(rdev, r);
553 r = radeon_cs_parser_relocs(&parser);
555 if (r != -ERESTARTSYS)
556 DRM_ERROR("Failed to parse relocation %d!\n", r);
557 radeon_cs_parser_fini(&parser, r);
558 up_read(&rdev->exclusive_lock);
559 r = radeon_cs_handle_lockup(rdev, r);
563 if (parser.ring == R600_RING_TYPE_UVD_INDEX)
564 radeon_uvd_note_usage(rdev);
566 r = radeon_cs_ib_chunk(rdev, &parser);
570 r = radeon_cs_ib_vm_chunk(rdev, &parser);
575 radeon_cs_parser_fini(&parser, r);
576 up_read(&rdev->exclusive_lock);
577 r = radeon_cs_handle_lockup(rdev, r);
581 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
583 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
585 int size = PAGE_SIZE;
587 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
588 if (i == ibc->last_page_index) {
589 size = (ibc->length_dw * 4) % PAGE_SIZE;
594 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
595 ibc->user_ptr + (i * PAGE_SIZE),
602 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
605 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
607 int size = PAGE_SIZE;
608 bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ?
611 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
612 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
613 ibc->user_ptr + (i * PAGE_SIZE),
615 p->parser_error = -EFAULT;
620 if (pg_idx == ibc->last_page_index) {
621 size = (ibc->length_dw * 4) % PAGE_SIZE;
626 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
628 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
630 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
631 ibc->user_ptr + (pg_idx * PAGE_SIZE),
633 p->parser_error = -EFAULT;
637 /* copy to IB for non single case */
639 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
641 ibc->last_copied_page = pg_idx;
642 ibc->kpage_idx[new_page] = pg_idx;
647 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
649 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
650 u32 pg_idx, pg_offset;
654 pg_idx = (idx * 4) / PAGE_SIZE;
655 pg_offset = (idx * 4) % PAGE_SIZE;
657 if (ibc->kpage_idx[0] == pg_idx)
658 return ibc->kpage[0][pg_offset/4];
659 if (ibc->kpage_idx[1] == pg_idx)
660 return ibc->kpage[1][pg_offset/4];
662 new_page = radeon_cs_update_pages(p, pg_idx);
664 p->parser_error = new_page;
668 idx_value = ibc->kpage[new_page][pg_offset/4];
673 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
674 * @parser: parser structure holding parsing context.
675 * @pkt: where to store packet information
677 * Assume that chunk_ib_index is properly set. Will return -EINVAL
678 * if packet is bigger than remaining ib size. or if packets is unknown.
680 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
681 struct radeon_cs_packet *pkt,
684 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
685 struct radeon_device *rdev = p->rdev;
688 if (idx >= ib_chunk->length_dw) {
689 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
690 idx, ib_chunk->length_dw);
693 header = radeon_get_ib_value(p, idx);
695 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
696 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
699 case RADEON_PACKET_TYPE0:
700 if (rdev->family < CHIP_R600) {
701 pkt->reg = R100_CP_PACKET0_GET_REG(header);
703 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
705 pkt->reg = R600_CP_PACKET0_GET_REG(header);
707 case RADEON_PACKET_TYPE3:
708 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
710 case RADEON_PACKET_TYPE2:
714 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
717 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
718 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
719 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
726 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
727 * @p: structure holding the parser context.
729 * Check if the next packet is NOP relocation packet3.
731 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
733 struct radeon_cs_packet p3reloc;
736 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
739 if (p3reloc.type != RADEON_PACKET_TYPE3)
741 if (p3reloc.opcode != RADEON_PACKET3_NOP)
747 * radeon_cs_dump_packet() - dump raw packet context
748 * @p: structure holding the parser context.
749 * @pkt: structure holding the packet.
751 * Used mostly for debugging and error reporting.
753 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
754 struct radeon_cs_packet *pkt)
756 volatile uint32_t *ib;
762 for (i = 0; i <= (pkt->count + 1); i++, idx++)
763 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
767 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
768 * @parser: parser structure holding parsing context.
769 * @data: pointer to relocation data
770 * @offset_start: starting offset
771 * @offset_mask: offset mask (to align start offset on)
772 * @reloc: reloc informations
774 * Check if next packet is relocation packet3, do bo validation and compute
775 * GPU offset using the provided start.
777 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
778 struct radeon_cs_reloc **cs_reloc,
781 struct radeon_cs_chunk *relocs_chunk;
782 struct radeon_cs_packet p3reloc;
786 if (p->chunk_relocs_idx == -1) {
787 DRM_ERROR("No relocation chunk !\n");
791 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
792 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
795 p->idx += p3reloc.count + 2;
796 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
797 p3reloc.opcode != RADEON_PACKET3_NOP) {
798 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
800 radeon_cs_dump_packet(p, &p3reloc);
803 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
804 if (idx >= relocs_chunk->length_dw) {
805 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
806 idx, relocs_chunk->length_dw);
807 radeon_cs_dump_packet(p, &p3reloc);
810 /* FIXME: we assume reloc size is 4 dwords */
812 *cs_reloc = p->relocs;
813 (*cs_reloc)->lobj.gpu_offset =
814 (u64)relocs_chunk->kdata[idx + 3] << 32;
815 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
817 *cs_reloc = p->relocs_ptr[(idx / 4)];