drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include <drm/drmP.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  43                         uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev, size;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = 0xc;
 160                 break;
 161         case COMBIOS_BIOS_SUPPORT_TABLE:
 162                 check_offset = 0x14;
 163                 break;
 164         case COMBIOS_DAC_PROGRAMMING_TABLE:
 165                 check_offset = 0x2a;
 166                 break;
 167         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 168                 check_offset = 0x2c;
 169                 break;
 170         case COMBIOS_CRTC_INFO_TABLE:
 171                 check_offset = 0x2e;
 172                 break;
 173         case COMBIOS_PLL_INFO_TABLE:
 174                 check_offset = 0x30;
 175                 break;
 176         case COMBIOS_TV_INFO_TABLE:
 177                 check_offset = 0x32;
 178                 break;
 179         case COMBIOS_DFP_INFO_TABLE:
 180                 check_offset = 0x34;
 181                 break;
 182         case COMBIOS_HW_CONFIG_INFO_TABLE:
 183                 check_offset = 0x36;
 184                 break;
 185         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 186                 check_offset = 0x38;
 187                 break;
 188         case COMBIOS_TV_STD_PATCH_TABLE:
 189                 check_offset = 0x3e;
 190                 break;
 191         case COMBIOS_LCD_INFO_TABLE:
 192                 check_offset = 0x40;
 193                 break;
 194         case COMBIOS_MOBILE_INFO_TABLE:
 195                 check_offset = 0x42;
 196                 break;
 197         case COMBIOS_PLL_INIT_TABLE:
 198                 check_offset = 0x46;
 199                 break;
 200         case COMBIOS_MEM_CONFIG_TABLE:
 201                 check_offset = 0x48;
 202                 break;
 203         case COMBIOS_SAVE_MASK_TABLE:
 204                 check_offset = 0x4a;
 205                 break;
 206         case COMBIOS_HARDCODED_EDID_TABLE:
 207                 check_offset = 0x4c;
 208                 break;
 209         case COMBIOS_ASIC_INIT_2_TABLE:
 210                 check_offset = 0x4e;
 211                 break;
 212         case COMBIOS_CONNECTOR_INFO_TABLE:
 213                 check_offset = 0x50;
 214                 break;
 215         case COMBIOS_DYN_CLK_1_TABLE:
 216                 check_offset = 0x52;
 217                 break;
 218         case COMBIOS_RESERVED_MEM_TABLE:
 219                 check_offset = 0x54;
 220                 break;
 221         case COMBIOS_EXT_TMDS_INFO_TABLE:
 222                 check_offset = 0x58;
 223                 break;
 224         case COMBIOS_MEM_CLK_INFO_TABLE:
 225                 check_offset = 0x5a;
 226                 break;
 227         case COMBIOS_EXT_DAC_INFO_TABLE:
 228                 check_offset = 0x5c;
 229                 break;
 230         case COMBIOS_MISC_INFO_TABLE:
 231                 check_offset = 0x5e;
 232                 break;
 233         case COMBIOS_CRT_INFO_TABLE:
 234                 check_offset = 0x60;
 235                 break;
 236         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 237                 check_offset = 0x62;
 238                 break;
 239         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 240                 check_offset = 0x64;
 241                 break;
 242         case COMBIOS_FAN_SPEED_INFO_TABLE:
 243                 check_offset = 0x66;
 244                 break;
 245         case COMBIOS_OVERDRIVE_INFO_TABLE:
 246                 check_offset = 0x68;
 247                 break;
 248         case COMBIOS_OEM_INFO_TABLE:
 249                 check_offset = 0x6a;
 250                 break;
 251         case COMBIOS_DYN_CLK_2_TABLE:
 252                 check_offset = 0x6c;
 253                 break;
 254         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 255                 check_offset = 0x6e;
 256                 break;
 257         case COMBIOS_I2C_INFO_TABLE:
 258                 check_offset = 0x70;
 259                 break;
 260                 /* relative offset tables */
 261         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 262                 check_offset =
 263                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 264                 if (check_offset) {
 265                         rev = RBIOS8(check_offset);
 266                         if (rev > 0) {
 267                                 check_offset = RBIOS16(check_offset + 0x3);
 268                                 if (check_offset)
 269                                         offset = check_offset;
 270                         }
 271                 }
 272                 break;
 273         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 274                 check_offset =
 275                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 276                 if (check_offset) {
 277                         rev = RBIOS8(check_offset);
 278                         if (rev > 0) {
 279                                 check_offset = RBIOS16(check_offset + 0x5);
 280                                 if (check_offset)
 281                                         offset = check_offset;
 282                         }
 283                 }
 284                 break;
 285         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 286                 check_offset =
 287                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 288                 if (check_offset) {
 289                         rev = RBIOS8(check_offset);
 290                         if (rev > 0) {
 291                                 check_offset = RBIOS16(check_offset + 0x7);
 292                                 if (check_offset)
 293                                         offset = check_offset;
 294                         }
 295                 }
 296                 break;
 297         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 298                 check_offset =
 299                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 300                 if (check_offset) {
 301                         rev = RBIOS8(check_offset);
 302                         if (rev == 2) {
 303                                 check_offset = RBIOS16(check_offset + 0x9);
 304                                 if (check_offset)
 305                                         offset = check_offset;
 306                         }
 307                 }
 308                 break;
 309         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 310                 check_offset =
 311                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 312                 if (check_offset) {
 313                         while (RBIOS8(check_offset++));
 314                         check_offset += 2;
 315                         if (check_offset)
 316                                 offset = check_offset;
 317                 }
 318                 break;
 319         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 320                 check_offset =
 321                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 322                 if (check_offset) {
 323                         check_offset = RBIOS16(check_offset + 0x11);
 324                         if (check_offset)
 325                                 offset = check_offset;
 326                 }
 327                 break;
 328         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 329                 check_offset =
 330                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 331                 if (check_offset) {
 332                         check_offset = RBIOS16(check_offset + 0x13);
 333                         if (check_offset)
 334                                 offset = check_offset;
 335                 }
 336                 break;
 337         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 338                 check_offset =
 339                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 340                 if (check_offset) {
 341                         check_offset = RBIOS16(check_offset + 0x15);
 342                         if (check_offset)
 343                                 offset = check_offset;
 344                 }
 345                 break;
 346         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 347                 check_offset =
 348                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 349                 if (check_offset) {
 350                         check_offset = RBIOS16(check_offset + 0x17);
 351                         if (check_offset)
 352                                 offset = check_offset;
 353                 }
 354                 break;
 355         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 356                 check_offset =
 357                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 358                 if (check_offset) {
 359                         check_offset = RBIOS16(check_offset + 0x2);
 360                         if (check_offset)
 361                                 offset = check_offset;
 362                 }
 363                 break;
 364         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 365                 check_offset =
 366                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 367                 if (check_offset) {
 368                         check_offset = RBIOS16(check_offset + 0x4);
 369                         if (check_offset)
 370                                 offset = check_offset;
 371                 }
 372                 break;
 373         default:
 374                 check_offset = 0;
 375                 break;
 376         }
 377
 378         size = RBIOS8(rdev->bios_header_start + 0x6);
 379         /* check absolute offset tables */
 380         if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
 381                 offset = RBIOS16(rdev->bios_header_start + check_offset);
 382
 383         return offset;
 384 }
 385
 386 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 387 {
 388         int edid_info, size;
 389         struct edid *edid;
 390         unsigned char *raw;
 391         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 392         if (!edid_info)
 393                 return false;
 394
 395         raw = rdev->bios + edid_info;
 396         size = EDID_LENGTH * (raw[0x7e] + 1);
 397         edid = kmalloc(size, GFP_KERNEL);
 398         if (edid == NULL)
 399                 return false;
 400
 401         memcpy((unsigned char *)edid, raw, size);
 402
 403         if (!drm_edid_is_valid(edid)) {
 404                 kfree(edid);
 405                 return false;
 406         }
 407
 408         rdev->mode_info.bios_hardcoded_edid = edid;
 409         rdev->mode_info.bios_hardcoded_edid_size = size;
 410         return true;
 411 }
 412
 413 /* this is used for atom LCDs as well */
 414 struct edid *
 415 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 416 {
 417         struct edid *edid;
 418
 419         if (rdev->mode_info.bios_hardcoded_edid) {
 420                 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 421                 if (edid) {
 422                         memcpy((unsigned char *)edid,
 423                                (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 424                                rdev->mode_info.bios_hardcoded_edid_size);
 425                         return edid;
 426                 }
 427         }
 428         return NULL;
 429 }
 430
 431 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 432                                                        enum radeon_combios_ddc ddc,
 433                                                        u32 clk_mask,
 434                                                        u32 data_mask)
 435 {
 436         struct radeon_i2c_bus_rec i2c;
 437         int ddc_line = 0;
 438
 439         /* ddc id            = mask reg
 440          * DDC_NONE_DETECTED = none
 441          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 442          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 443          * DDC_LCD           = RADEON_GPIOPAD_MASK
 444          * DDC_GPIO          = RADEON_MDGPIO_MASK
 445          * r1xx
 446          * DDC_MONID         = RADEON_GPIO_MONID
 447          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 448          * r200
 449          * DDC_MONID         = RADEON_GPIO_MONID
 450          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 451          * r300/r350
 452          * DDC_MONID         = RADEON_GPIO_DVI_DDC
 453          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 454          * rv2xx/rv3xx
 455          * DDC_MONID         = RADEON_GPIO_MONID
 456          * DDC_CRT2          = RADEON_GPIO_MONID
 457          * rs3xx/rs4xx
 458          * DDC_MONID         = RADEON_GPIOPAD_MASK
 459          * DDC_CRT2          = RADEON_GPIO_MONID
 460          */
 461         switch (ddc) {
 462         case DDC_NONE_DETECTED:
 463         default:
 464                 ddc_line = 0;
 465                 break;
 466         case DDC_DVI:
 467                 ddc_line = RADEON_GPIO_DVI_DDC;
 468                 break;
 469         case DDC_VGA:
 470                 ddc_line = RADEON_GPIO_VGA_DDC;
 471                 break;
 472         case DDC_LCD:
 473                 ddc_line = RADEON_GPIOPAD_MASK;
 474                 break;
 475         case DDC_GPIO:
 476                 ddc_line = RADEON_MDGPIO_MASK;
 477                 break;
 478         case DDC_MONID:
 479                 if (rdev->family == CHIP_RS300 ||
 480                     rdev->family == CHIP_RS400 ||
 481                     rdev->family == CHIP_RS480)
 482                         ddc_line = RADEON_GPIOPAD_MASK;
 483                 else if (rdev->family == CHIP_R300 ||
 484                          rdev->family == CHIP_R350) {
 485                         ddc_line = RADEON_GPIO_DVI_DDC;
 486                         ddc = DDC_DVI;
 487                 } else
 488                         ddc_line = RADEON_GPIO_MONID;
 489                 break;
 490         case DDC_CRT2:
 491                 if (rdev->family == CHIP_R200 ||
 492                     rdev->family == CHIP_R300 ||
 493                     rdev->family == CHIP_R350) {
 494                         ddc_line = RADEON_GPIO_DVI_DDC;
 495                         ddc = DDC_DVI;
 496                 } else if (rdev->family == CHIP_RS300 ||
 497                            rdev->family == CHIP_RS400 ||
 498                            rdev->family == CHIP_RS480)
 499                         ddc_line = RADEON_GPIO_MONID;
 500                 else if (rdev->family >= CHIP_RV350) {
 501                         ddc_line = RADEON_GPIO_MONID;
 502                         ddc = DDC_MONID;
 503                 } else
 504                         ddc_line = RADEON_GPIO_CRT2_DDC;
 505                 break;
 506         }
 507
 508         if (ddc_line == RADEON_GPIOPAD_MASK) {
 509                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 510                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 511                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 512                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 513                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 514                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 515                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 516                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 517         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 518                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 519                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 520                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 521                 i2c.a_data_reg = RADEON_MDGPIO_A;
 522                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 523                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 524                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 525                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 526         } else {
 527                 i2c.mask_clk_reg = ddc_line;
 528                 i2c.mask_data_reg = ddc_line;
 529                 i2c.a_clk_reg = ddc_line;
 530                 i2c.a_data_reg = ddc_line;
 531                 i2c.en_clk_reg = ddc_line;
 532                 i2c.en_data_reg = ddc_line;
 533                 i2c.y_clk_reg = ddc_line;
 534                 i2c.y_data_reg = ddc_line;
 535         }
 536
 537         if (clk_mask && data_mask) {
 538                 /* system specific masks */
 539                 i2c.mask_clk_mask = clk_mask;
 540                 i2c.mask_data_mask = data_mask;
 541                 i2c.a_clk_mask = clk_mask;
 542                 i2c.a_data_mask = data_mask;
 543                 i2c.en_clk_mask = clk_mask;
 544                 i2c.en_data_mask = data_mask;
 545                 i2c.y_clk_mask = clk_mask;
 546                 i2c.y_data_mask = data_mask;
 547         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 548                    (ddc_line == RADEON_MDGPIO_MASK)) {
 549                 /* default gpiopad masks */
 550                 i2c.mask_clk_mask = (0x20 << 8);
 551                 i2c.mask_data_mask = 0x80;
 552                 i2c.a_clk_mask = (0x20 << 8);
 553                 i2c.a_data_mask = 0x80;
 554                 i2c.en_clk_mask = (0x20 << 8);
 555                 i2c.en_data_mask = 0x80;
 556                 i2c.y_clk_mask = (0x20 << 8);
 557                 i2c.y_data_mask = 0x80;
 558         } else {
 559                 /* default masks for ddc pads */
 560                 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
 561                 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
 562                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 563                 i2c.a_data_mask = RADEON_GPIO_A_0;
 564                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 565                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 566                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 567                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 568         }
 569
 570         switch (rdev->family) {
 571         case CHIP_R100:
 572         case CHIP_RV100:
 573         case CHIP_RS100:
 574         case CHIP_RV200:
 575         case CHIP_RS200:
 576         case CHIP_RS300:
 577                 switch (ddc_line) {
 578                 case RADEON_GPIO_DVI_DDC:
 579                         i2c.hw_capable = true;
 580                         break;
 581                 default:
 582                         i2c.hw_capable = false;
 583                         break;
 584                 }
 585                 break;
 586         case CHIP_R200:
 587                 switch (ddc_line) {
 588                 case RADEON_GPIO_DVI_DDC:
 589                 case RADEON_GPIO_MONID:
 590                         i2c.hw_capable = true;
 591                         break;
 592                 default:
 593                         i2c.hw_capable = false;
 594                         break;
 595                 }
 596                 break;
 597         case CHIP_RV250:
 598         case CHIP_RV280:
 599                 switch (ddc_line) {
 600                 case RADEON_GPIO_VGA_DDC:
 601                 case RADEON_GPIO_DVI_DDC:
 602                 case RADEON_GPIO_CRT2_DDC:
 603                         i2c.hw_capable = true;
 604                         break;
 605                 default:
 606                         i2c.hw_capable = false;
 607                         break;
 608                 }
 609                 break;
 610         case CHIP_R300:
 611         case CHIP_R350:
 612                 switch (ddc_line) {
 613                 case RADEON_GPIO_VGA_DDC:
 614                 case RADEON_GPIO_DVI_DDC:
 615                         i2c.hw_capable = true;
 616                         break;
 617                 default:
 618                         i2c.hw_capable = false;
 619                         break;
 620                 }
 621                 break;
 622         case CHIP_RV350:
 623         case CHIP_RV380:
 624         case CHIP_RS400:
 625         case CHIP_RS480:
 626                 switch (ddc_line) {
 627                 case RADEON_GPIO_VGA_DDC:
 628                 case RADEON_GPIO_DVI_DDC:
 629                         i2c.hw_capable = true;
 630                         break;
 631                 case RADEON_GPIO_MONID:
 632                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 633                          * reliably on some pre-r4xx hardware; not sure why.
 634                          */
 635                         i2c.hw_capable = false;
 636                         break;
 637                 default:
 638                         i2c.hw_capable = false;
 639                         break;
 640                 }
 641                 break;
 642         default:
 643                 i2c.hw_capable = false;
 644                 break;
 645         }
 646         i2c.mm_i2c = false;
 647
 648         i2c.i2c_id = ddc;
 649         i2c.hpd = RADEON_HPD_NONE;
 650
 651         if (ddc_line)
 652                 i2c.valid = true;
 653         else
 654                 i2c.valid = false;
 655
 656         return i2c;
 657 }
 658
 659 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
 660 {
 661         struct drm_device *dev = rdev->ddev;
 662         struct radeon_i2c_bus_rec i2c;
 663         u16 offset;
 664         u8 id, blocks, clk, data;
 665         int i;
 666
 667         i2c.valid = false;
 668
 669         offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 670         if (offset) {
 671                 blocks = RBIOS8(offset + 2);
 672                 for (i = 0; i < blocks; i++) {
 673                         id = RBIOS8(offset + 3 + (i * 5) + 0);
 674                         if (id == 136) {
 675                                 clk = RBIOS8(offset + 3 + (i * 5) + 3);
 676                                 data = RBIOS8(offset + 3 + (i * 5) + 4);
 677                                 /* gpiopad */
 678                                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 679                                                             (1 << clk), (1 << data));
 680                                 break;
 681                         }
 682                 }
 683         }
 684         return i2c;
 685 }
 686
 687 void radeon_combios_i2c_init(struct radeon_device *rdev)
 688 {
 689         struct drm_device *dev = rdev->ddev;
 690         struct radeon_i2c_bus_rec i2c;
 691
 692         /* actual hw pads
 693          * r1xx/rs2xx/rs3xx
 694          * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
 695          * r200
 696          * 0x60, 0x64, 0x68, mm
 697          * r300/r350
 698          * 0x60, 0x64, mm
 699          * rv2xx/rv3xx/rs4xx
 700          * 0x60, 0x64, 0x68, gpiopads, mm
 701          */
 702
 703         /* 0x60 */
 704         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 705         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 706         /* 0x64 */
 707         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 708         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 709
 710         /* mm i2c */
 711         i2c.valid = true;
 712         i2c.hw_capable = true;
 713         i2c.mm_i2c = true;
 714         i2c.i2c_id = 0xa0;
 715         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 716
 717         if (rdev->family == CHIP_R300 ||
 718             rdev->family == CHIP_R350) {
 719                 /* only 2 sw i2c pads */
 720         } else if (rdev->family == CHIP_RS300 ||
 721                    rdev->family == CHIP_RS400 ||
 722                    rdev->family == CHIP_RS480) {
 723                 /* 0x68 */
 724                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 725                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 726
 727                 /* gpiopad */
 728                 i2c = radeon_combios_get_i2c_info_from_table(rdev);
 729                 if (i2c.valid)
 730                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 731         } else if ((rdev->family == CHIP_R200) ||
 732                    (rdev->family >= CHIP_R300)) {
 733                 /* 0x68 */
 734                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 735                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 736         } else {
 737                 /* 0x68 */
 738                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 739                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 740                 /* 0x6c */
 741                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 742                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 743         }
 744 }
 745
 746 bool radeon_combios_get_clock_info(struct drm_device *dev)
 747 {
 748         struct radeon_device *rdev = dev->dev_private;
 749         uint16_t pll_info;
 750         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 751         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 752         struct radeon_pll *spll = &rdev->clock.spll;
 753         struct radeon_pll *mpll = &rdev->clock.mpll;
 754         int8_t rev;
 755         uint16_t sclk, mclk;
 756
 757         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 758         if (pll_info) {
 759                 rev = RBIOS8(pll_info);
 760
 761                 /* pixel clocks */
 762                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 763                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 764                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 765                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 766                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 767                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 768
 769                 if (rev > 9) {
 770                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 771                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 772                 } else {
 773                         p1pll->pll_in_min = 40;
 774                         p1pll->pll_in_max = 500;
 775                 }
 776                 *p2pll = *p1pll;
 777
 778                 /* system clock */
 779                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 780                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 781                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 782                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 783
 784                 if (rev > 10) {
 785                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 786                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 787                 } else {
 788                         /* ??? */
 789                         spll->pll_in_min = 40;
 790                         spll->pll_in_max = 500;
 791                 }
 792
 793                 /* memory clock */
 794                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 795                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 796                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 797                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 798
 799                 if (rev > 10) {
 800                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 801                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 802                 } else {
 803                         /* ??? */
 804                         mpll->pll_in_min = 40;
 805                         mpll->pll_in_max = 500;
 806                 }
 807
 808                 /* default sclk/mclk */
 809                 sclk = RBIOS16(pll_info + 0xa);
 810                 mclk = RBIOS16(pll_info + 0x8);
 811                 if (sclk == 0)
 812                         sclk = 200 * 100;
 813                 if (mclk == 0)
 814                         mclk = 200 * 100;
 815
 816                 rdev->clock.default_sclk = sclk;
 817                 rdev->clock.default_mclk = mclk;
 818
 819                 if (RBIOS32(pll_info + 0x16))
 820                         rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
 821                 else
 822                         rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
 823
 824                 return true;
 825         }
 826         return false;
 827 }
 828
 829 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 830 {
 831         struct drm_device *dev = rdev->ddev;
 832         u16 igp_info;
 833
 834         /* sideport is AMD only */
 835         if (rdev->family == CHIP_RS400)
 836                 return false;
 837
 838         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 839
 840         if (igp_info) {
 841                 if (RBIOS16(igp_info + 0x4))
 842                         return true;
 843         }
 844         return false;
 845 }
 846
 847 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 848         0x00000808,             /* r100  */
 849         0x00000808,             /* rv100 */
 850         0x00000808,             /* rs100 */
 851         0x00000808,             /* rv200 */
 852         0x00000808,             /* rs200 */
 853         0x00000808,             /* r200  */
 854         0x00000808,             /* rv250 */
 855         0x00000000,             /* rs300 */
 856         0x00000808,             /* rv280 */
 857         0x00000808,             /* r300  */
 858         0x00000808,             /* r350  */
 859         0x00000808,             /* rv350 */
 860         0x00000808,             /* rv380 */
 861         0x00000808,             /* r420  */
 862         0x00000808,             /* r423  */
 863         0x00000808,             /* rv410 */
 864         0x00000000,             /* rs400 */
 865         0x00000000,             /* rs480 */
 866 };
 867
 868 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 869                                                           struct radeon_encoder_primary_dac *p_dac)
 870 {
 871         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 872         return;
 873 }
 874
 875 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 876                                                                        radeon_encoder
 877                                                                        *encoder)
 878 {
 879         struct drm_device *dev = encoder->base.dev;
 880         struct radeon_device *rdev = dev->dev_private;
 881         uint16_t dac_info;
 882         uint8_t rev, bg, dac;
 883         struct radeon_encoder_primary_dac *p_dac = NULL;
 884         int found = 0;
 885
 886         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 887                         GFP_KERNEL);
 888
 889         if (!p_dac)
 890                 return NULL;
 891
 892         /* check CRT table */
 893         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 894         if (dac_info) {
 895                 rev = RBIOS8(dac_info) & 0x3;
 896                 if (rev < 2) {
 897                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 898                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 899                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 900                 } else {
 901                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 902                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 903                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 904                 }
 905                 /* if the values are zeros, use the table */
 906                 if ((dac == 0) || (bg == 0))
 907                         found = 0;
 908                 else
 909                         found = 1;
 910         }
 911
 912         /* quirks */
 913         /* Radeon 7000 (RV100) */
 914         if (((dev->pdev->device == 0x5159) &&
 915             (dev->pdev->subsystem_vendor == 0x174B) &&
 916             (dev->pdev->subsystem_device == 0x7c28)) ||
 917         /* Radeon 9100 (R200) */
 918            ((dev->pdev->device == 0x514D) &&
 919             (dev->pdev->subsystem_vendor == 0x174B) &&
 920             (dev->pdev->subsystem_device == 0x7149))) {
 921                 /* vbios value is bad, use the default */
 922                 found = 0;
 923         }
 924
 925         if (!found) /* fallback to defaults */
 926                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 927
 928         return p_dac;
 929 }
 930
 931 enum radeon_tv_std
 932 radeon_combios_get_tv_info(struct radeon_device *rdev)
 933 {
 934         struct drm_device *dev = rdev->ddev;
 935         uint16_t tv_info;
 936         enum radeon_tv_std tv_std = TV_STD_NTSC;
 937
 938         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 939         if (tv_info) {
 940                 if (RBIOS8(tv_info + 6) == 'T') {
 941                         switch (RBIOS8(tv_info + 7) & 0xf) {
 942                         case 1:
 943                                 tv_std = TV_STD_NTSC;
 944                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 945                                 break;
 946                         case 2:
 947                                 tv_std = TV_STD_PAL;
 948                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
 949                                 break;
 950                         case 3:
 951                                 tv_std = TV_STD_PAL_M;
 952                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 953                                 break;
 954                         case 4:
 955                                 tv_std = TV_STD_PAL_60;
 956                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
 957                                 break;
 958                         case 5:
 959                                 tv_std = TV_STD_NTSC_J;
 960                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
 961                                 break;
 962                         case 6:
 963                                 tv_std = TV_STD_SCART_PAL;
 964                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
 965                                 break;
 966                         default:
 967                                 tv_std = TV_STD_NTSC;
 968                                 DRM_DEBUG_KMS
 969                                     ("Unknown TV standard; defaulting to NTSC\n");
 970                                 break;
 971                         }
 972
 973                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 974                         case 0:
 975                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
 976                                 break;
 977                         case 1:
 978                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
 979                                 break;
 980                         case 2:
 981                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
 982                                 break;
 983                         case 3:
 984                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
 985                                 break;
 986                         default:
 987                                 break;
 988                         }
 989                 }
 990         }
 991         return tv_std;
 992 }
 993
 994 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 995         0x00000000,             /* r100  */
 996         0x00280000,             /* rv100 */
 997         0x00000000,             /* rs100 */
 998         0x00880000,             /* rv200 */
 999         0x00000000,             /* rs200 */
1000         0x00000000,             /* r200  */
1001         0x00770000,             /* rv250 */
1002         0x00290000,             /* rs300 */
1003         0x00560000,             /* rv280 */
1004         0x00780000,             /* r300  */
1005         0x00770000,             /* r350  */
1006         0x00780000,             /* rv350 */
1007         0x00780000,             /* rv380 */
1008         0x01080000,             /* r420  */
1009         0x01080000,             /* r423  */
1010         0x01080000,             /* rv410 */
1011         0x00780000,             /* rs400 */
1012         0x00780000,             /* rs480 */
1013 };
1014
1015 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1016                                                      struct radeon_encoder_tv_dac *tv_dac)
1017 {
1018         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1019         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1020                 tv_dac->ps2_tvdac_adj = 0x00880000;
1021         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1022         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1023         return;
1024 }
1025
1026 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1027                                                              radeon_encoder
1028                                                              *encoder)
1029 {
1030         struct drm_device *dev = encoder->base.dev;
1031         struct radeon_device *rdev = dev->dev_private;
1032         uint16_t dac_info;
1033         uint8_t rev, bg, dac;
1034         struct radeon_encoder_tv_dac *tv_dac = NULL;
1035         int found = 0;
1036
1037         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1038         if (!tv_dac)
1039                 return NULL;
1040
1041         /* first check TV table */
1042         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1043         if (dac_info) {
1044                 rev = RBIOS8(dac_info + 0x3);
1045                 if (rev > 4) {
1046                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1047                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1048                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1049
1050                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1051                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1052                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1053
1054                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1055                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1056                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1057                         /* if the values are all zeros, use the table */
1058                         if (tv_dac->ps2_tvdac_adj)
1059                                 found = 1;
1060                 } else if (rev > 1) {
1061                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1062                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1063                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1064
1065                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1066                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1067                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1068
1069                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1070                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1071                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1072                         /* if the values are all zeros, use the table */
1073                         if (tv_dac->ps2_tvdac_adj)
1074                                 found = 1;
1075                 }
1076                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1077         }
1078         if (!found) {
1079                 /* then check CRT table */
1080                 dac_info =
1081                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1082                 if (dac_info) {
1083                         rev = RBIOS8(dac_info) & 0x3;
1084                         if (rev < 2) {
1085                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1086                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1087                                 tv_dac->ps2_tvdac_adj =
1088                                     (bg << 16) | (dac << 20);
1089                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1090                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1091                                 /* if the values are all zeros, use the table */
1092                                 if (tv_dac->ps2_tvdac_adj)
1093                                         found = 1;
1094                         } else {
1095                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1096                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1097                                 tv_dac->ps2_tvdac_adj =
1098                                     (bg << 16) | (dac << 20);
1099                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1100                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1101                                 /* if the values are all zeros, use the table */
1102                                 if (tv_dac->ps2_tvdac_adj)
1103                                         found = 1;
1104                         }
1105                 } else {
1106                         DRM_INFO("No TV DAC info found in BIOS\n");
1107                 }
1108         }
1109
1110         if (!found) /* fallback to defaults */
1111                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1112
1113         return tv_dac;
1114 }
1115
1116 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1117                                                                          radeon_device
1118                                                                          *rdev)
1119 {
1120         struct radeon_encoder_lvds *lvds = NULL;
1121         uint32_t fp_vert_stretch, fp_horz_stretch;
1122         uint32_t ppll_div_sel, ppll_val;
1123         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1124
1125         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1126
1127         if (!lvds)
1128                 return NULL;
1129
1130         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1131         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1132
1133         /* These should be fail-safe defaults, fingers crossed */
1134         lvds->panel_pwr_delay = 200;
1135         lvds->panel_vcc_delay = 2000;
1136
1137         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1138         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1139         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1140
1141         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1142                 lvds->native_mode.vdisplay =
1143                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1144                      RADEON_VERT_PANEL_SHIFT) + 1;
1145         else
1146                 lvds->native_mode.vdisplay =
1147                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1148
1149         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1150                 lvds->native_mode.hdisplay =
1151                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1152                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1153         else
1154                 lvds->native_mode.hdisplay =
1155                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1156
1157         if ((lvds->native_mode.hdisplay < 640) ||
1158             (lvds->native_mode.vdisplay < 480)) {
1159                 lvds->native_mode.hdisplay = 640;
1160                 lvds->native_mode.vdisplay = 480;
1161         }
1162
1163         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1164         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1165         if ((ppll_val & 0x000707ff) == 0x1bb)
1166                 lvds->use_bios_dividers = false;
1167         else {
1168                 lvds->panel_ref_divider =
1169                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1170                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1171                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1172
1173                 if ((lvds->panel_ref_divider != 0) &&
1174                     (lvds->panel_fb_divider > 3))
1175                         lvds->use_bios_dividers = true;
1176         }
1177         lvds->panel_vcc_delay = 200;
1178
1179         DRM_INFO("Panel info derived from registers\n");
1180         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1181                  lvds->native_mode.vdisplay);
1182
1183         return lvds;
1184 }
1185
1186 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1187                                                          *encoder)
1188 {
1189         struct drm_device *dev = encoder->base.dev;
1190         struct radeon_device *rdev = dev->dev_private;
1191         uint16_t lcd_info;
1192         uint32_t panel_setup;
1193         char stmp[30];
1194         int tmp, i;
1195         struct radeon_encoder_lvds *lvds = NULL;
1196
1197         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1198
1199         if (lcd_info) {
1200                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1201
1202                 if (!lvds)
1203                         return NULL;
1204
1205                 for (i = 0; i < 24; i++)
1206                         stmp[i] = RBIOS8(lcd_info + i + 1);
1207                 stmp[24] = 0;
1208
1209                 DRM_INFO("Panel ID String: %s\n", stmp);
1210
1211                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1212                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1213
1214                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1215                          lvds->native_mode.vdisplay);
1216
1217                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1218                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1219
1220                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1221                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1222                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1223
1224                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1225                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1226                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1227                 if ((lvds->panel_ref_divider != 0) &&
1228                     (lvds->panel_fb_divider > 3))
1229                         lvds->use_bios_dividers = true;
1230
1231                 panel_setup = RBIOS32(lcd_info + 0x39);
1232                 lvds->lvds_gen_cntl = 0xff00;
1233                 if (panel_setup & 0x1)
1234                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1235
1236                 if ((panel_setup >> 4) & 0x1)
1237                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1238
1239                 switch ((panel_setup >> 8) & 0x7) {
1240                 case 0:
1241                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1242                         break;
1243                 case 1:
1244                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1245                         break;
1246                 case 2:
1247                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1248                         break;
1249                 default:
1250                         break;
1251                 }
1252
1253                 if ((panel_setup >> 16) & 0x1)
1254                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1255
1256                 if ((panel_setup >> 17) & 0x1)
1257                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1258
1259                 if ((panel_setup >> 18) & 0x1)
1260                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1261
1262                 if ((panel_setup >> 23) & 0x1)
1263                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1264
1265                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1266
1267                 for (i = 0; i < 32; i++) {
1268                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1269                         if (tmp == 0)
1270                                 break;
1271
1272                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1273                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1274                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1275                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1276                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1277                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1278                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1279                                         (RBIOS8(tmp + 23) * 8);
1280
1281                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1282                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1283                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1284                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1285                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1286                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1287
1288                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1289                                 lvds->native_mode.flags = 0;
1290                                 /* set crtc values */
1291                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1292
1293                         }
1294                 }
1295         } else {
1296                 DRM_INFO("No panel info found in BIOS\n");
1297                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1298         }
1299
1300         if (lvds)
1301                 encoder->native_mode = lvds->native_mode;
1302         return lvds;
1303 }
1304
1305 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1306         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1307         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1308         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1309         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1310         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1311         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1312         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1313         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1314         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1315         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1316         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1317         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1318         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1319         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1320         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1321         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1322         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1323         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1324 };
1325
1326 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1327                                             struct radeon_encoder_int_tmds *tmds)
1328 {
1329         struct drm_device *dev = encoder->base.dev;
1330         struct radeon_device *rdev = dev->dev_private;
1331         int i;
1332
1333         for (i = 0; i < 4; i++) {
1334                 tmds->tmds_pll[i].value =
1335                         default_tmds_pll[rdev->family][i].value;
1336                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1337         }
1338
1339         return true;
1340 }
1341
1342 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1343                                               struct radeon_encoder_int_tmds *tmds)
1344 {
1345         struct drm_device *dev = encoder->base.dev;
1346         struct radeon_device *rdev = dev->dev_private;
1347         uint16_t tmds_info;
1348         int i, n;
1349         uint8_t ver;
1350
1351         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1352
1353         if (tmds_info) {
1354                 ver = RBIOS8(tmds_info);
1355                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1356                 if (ver == 3) {
1357                         n = RBIOS8(tmds_info + 5) + 1;
1358                         if (n > 4)
1359                                 n = 4;
1360                         for (i = 0; i < n; i++) {
1361                                 tmds->tmds_pll[i].value =
1362                                     RBIOS32(tmds_info + i * 10 + 0x08);
1363                                 tmds->tmds_pll[i].freq =
1364                                     RBIOS16(tmds_info + i * 10 + 0x10);
1365                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1366                                           tmds->tmds_pll[i].freq,
1367                                           tmds->tmds_pll[i].value);
1368                         }
1369                 } else if (ver == 4) {
1370                         int stride = 0;
1371                         n = RBIOS8(tmds_info + 5) + 1;
1372                         if (n > 4)
1373                                 n = 4;
1374                         for (i = 0; i < n; i++) {
1375                                 tmds->tmds_pll[i].value =
1376                                     RBIOS32(tmds_info + stride + 0x08);
1377                                 tmds->tmds_pll[i].freq =
1378                                     RBIOS16(tmds_info + stride + 0x10);
1379                                 if (i == 0)
1380                                         stride += 10;
1381                                 else
1382                                         stride += 6;
1383                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1384                                           tmds->tmds_pll[i].freq,
1385                                           tmds->tmds_pll[i].value);
1386                         }
1387                 }
1388         } else {
1389                 DRM_INFO("No TMDS info found in BIOS\n");
1390                 return false;
1391         }
1392         return true;
1393 }
1394
1395 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1396                                                 struct radeon_encoder_ext_tmds *tmds)
1397 {
1398         struct drm_device *dev = encoder->base.dev;
1399         struct radeon_device *rdev = dev->dev_private;
1400         struct radeon_i2c_bus_rec i2c_bus;
1401
1402         /* default for macs */
1403         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1404         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1405
1406         /* XXX some macs have duallink chips */
1407         switch (rdev->mode_info.connector_table) {
1408         case CT_POWERBOOK_EXTERNAL:
1409         case CT_MINI_EXTERNAL:
1410         default:
1411                 tmds->dvo_chip = DVO_SIL164;
1412                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1413                 break;
1414         }
1415
1416         return true;
1417 }
1418
1419 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1420                                                   struct radeon_encoder_ext_tmds *tmds)
1421 {
1422         struct drm_device *dev = encoder->base.dev;
1423         struct radeon_device *rdev = dev->dev_private;
1424         uint16_t offset;
1425         uint8_t ver;
1426         enum radeon_combios_ddc gpio;
1427         struct radeon_i2c_bus_rec i2c_bus;
1428
1429         tmds->i2c_bus = NULL;
1430         if (rdev->flags & RADEON_IS_IGP) {
1431                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1432                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1433                 tmds->dvo_chip = DVO_SIL164;
1434                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1435         } else {
1436                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1437                 if (offset) {
1438                         ver = RBIOS8(offset);
1439                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1440                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1441                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1442                         gpio = RBIOS8(offset + 4 + 3);
1443                         if (gpio == DDC_LCD) {
1444                                 /* MM i2c */
1445                                 i2c_bus.valid = true;
1446                                 i2c_bus.hw_capable = true;
1447                                 i2c_bus.mm_i2c = true;
1448                                 i2c_bus.i2c_id = 0xa0;
1449                         } else
1450                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1451                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1452                 }
1453         }
1454
1455         if (!tmds->i2c_bus) {
1456                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1457                 return false;
1458         }
1459
1460         return true;
1461 }
1462
1463 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1464 {
1465         struct radeon_device *rdev = dev->dev_private;
1466         struct radeon_i2c_bus_rec ddc_i2c;
1467         struct radeon_hpd hpd;
1468
1469         rdev->mode_info.connector_table = radeon_connector_table;
1470         if (rdev->mode_info.connector_table == CT_NONE) {
1471 #ifdef CONFIG_PPC_PMAC
1472                 if (of_machine_is_compatible("PowerBook3,3")) {
1473                         /* powerbook with VGA */
1474                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1475                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1476                            of_machine_is_compatible("PowerBook3,5")) {
1477                         /* powerbook with internal tmds */
1478                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1479                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1480                            of_machine_is_compatible("PowerBook5,2") ||
1481                            of_machine_is_compatible("PowerBook5,3") ||
1482                            of_machine_is_compatible("PowerBook5,4") ||
1483                            of_machine_is_compatible("PowerBook5,5")) {
1484                         /* powerbook with external single link tmds (sil164) */
1485                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1486                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1487                         /* powerbook with external dual or single link tmds */
1488                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1489                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1490                            of_machine_is_compatible("PowerBook5,8") ||
1491                            of_machine_is_compatible("PowerBook5,9")) {
1492                         /* PowerBook6,2 ? */
1493                         /* powerbook with external dual link tmds (sil1178?) */
1494                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1495                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1496                            of_machine_is_compatible("PowerBook4,2") ||
1497                            of_machine_is_compatible("PowerBook4,3") ||
1498                            of_machine_is_compatible("PowerBook6,3") ||
1499                            of_machine_is_compatible("PowerBook6,5") ||
1500                            of_machine_is_compatible("PowerBook6,7")) {
1501                         /* ibook */
1502                         rdev->mode_info.connector_table = CT_IBOOK;
1503                 } else if (of_machine_is_compatible("PowerMac3,5")) {
1504                         /* PowerMac G4 Silver radeon 7500 */
1505                         rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1506                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1507                         /* emac */
1508                         rdev->mode_info.connector_table = CT_EMAC;
1509                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1510                         /* mini with internal tmds */
1511                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1512                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1513                         /* mini with external tmds */
1514                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1515                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1516                         /* PowerMac8,1 ? */
1517                         /* imac g5 isight */
1518                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1519                 } else if ((rdev->pdev->device == 0x4a48) &&
1520                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1521                            (rdev->pdev->subsystem_device == 0x4a48)) {
1522                         /* Mac X800 */
1523                         rdev->mode_info.connector_table = CT_MAC_X800;
1524                 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1525                             of_machine_is_compatible("PowerMac7,3")) &&
1526                            (rdev->pdev->device == 0x4150) &&
1527                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1528                            (rdev->pdev->subsystem_device == 0x4150)) {
1529                         /* Mac G5 tower 9600 */
1530                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1531                 } else if ((rdev->pdev->device == 0x4c66) &&
1532                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1533                            (rdev->pdev->subsystem_device == 0x4c66)) {
1534                         /* SAM440ep RV250 embedded board */
1535                         rdev->mode_info.connector_table = CT_SAM440EP;
1536                 } else
1537 #endif /* CONFIG_PPC_PMAC */
1538 #ifdef CONFIG_PPC64
1539                 if (ASIC_IS_RN50(rdev))
1540                         rdev->mode_info.connector_table = CT_RN50_POWER;
1541                 else
1542 #endif
1543                         rdev->mode_info.connector_table = CT_GENERIC;
1544         }
1545
1546         switch (rdev->mode_info.connector_table) {
1547         case CT_GENERIC:
1548                 DRM_INFO("Connector Table: %d (generic)\n",
1549                          rdev->mode_info.connector_table);
1550                 /* these are the most common settings */
1551                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1552                         /* VGA - primary dac */
1553                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1554                         hpd.hpd = RADEON_HPD_NONE;
1555                         radeon_add_legacy_encoder(dev,
1556                                                   radeon_get_encoder_enum(dev,
1557                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1558                                                                         1),
1559                                                   ATOM_DEVICE_CRT1_SUPPORT);
1560                         radeon_add_legacy_connector(dev, 0,
1561                                                     ATOM_DEVICE_CRT1_SUPPORT,
1562                                                     DRM_MODE_CONNECTOR_VGA,
1563                                                     &ddc_i2c,
1564                                                     CONNECTOR_OBJECT_ID_VGA,
1565                                                     &hpd);
1566                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1567                         /* LVDS */
1568                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1569                         hpd.hpd = RADEON_HPD_NONE;
1570                         radeon_add_legacy_encoder(dev,
1571                                                   radeon_get_encoder_enum(dev,
1572                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1573                                                                         0),
1574                                                   ATOM_DEVICE_LCD1_SUPPORT);
1575                         radeon_add_legacy_connector(dev, 0,
1576                                                     ATOM_DEVICE_LCD1_SUPPORT,
1577                                                     DRM_MODE_CONNECTOR_LVDS,
1578                                                     &ddc_i2c,
1579                                                     CONNECTOR_OBJECT_ID_LVDS,
1580                                                     &hpd);
1581
1582                         /* VGA - primary dac */
1583                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1584                         hpd.hpd = RADEON_HPD_NONE;
1585                         radeon_add_legacy_encoder(dev,
1586                                                   radeon_get_encoder_enum(dev,
1587                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1588                                                                         1),
1589                                                   ATOM_DEVICE_CRT1_SUPPORT);
1590                         radeon_add_legacy_connector(dev, 1,
1591                                                     ATOM_DEVICE_CRT1_SUPPORT,
1592                                                     DRM_MODE_CONNECTOR_VGA,
1593                                                     &ddc_i2c,
1594                                                     CONNECTOR_OBJECT_ID_VGA,
1595                                                     &hpd);
1596                 } else {
1597                         /* DVI-I - tv dac, int tmds */
1598                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1599                         hpd.hpd = RADEON_HPD_1;
1600                         radeon_add_legacy_encoder(dev,
1601                                                   radeon_get_encoder_enum(dev,
1602                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1603                                                                         0),
1604                                                   ATOM_DEVICE_DFP1_SUPPORT);
1605                         radeon_add_legacy_encoder(dev,
1606                                                   radeon_get_encoder_enum(dev,
1607                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1608                                                                         2),
1609                                                   ATOM_DEVICE_CRT2_SUPPORT);
1610                         radeon_add_legacy_connector(dev, 0,
1611                                                     ATOM_DEVICE_DFP1_SUPPORT |
1612                                                     ATOM_DEVICE_CRT2_SUPPORT,
1613                                                     DRM_MODE_CONNECTOR_DVII,
1614                                                     &ddc_i2c,
1615                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1616                                                     &hpd);
1617
1618                         /* VGA - primary dac */
1619                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1620                         hpd.hpd = RADEON_HPD_NONE;
1621                         radeon_add_legacy_encoder(dev,
1622                                                   radeon_get_encoder_enum(dev,
1623                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1624                                                                         1),
1625                                                   ATOM_DEVICE_CRT1_SUPPORT);
1626                         radeon_add_legacy_connector(dev, 1,
1627                                                     ATOM_DEVICE_CRT1_SUPPORT,
1628                                                     DRM_MODE_CONNECTOR_VGA,
1629                                                     &ddc_i2c,
1630                                                     CONNECTOR_OBJECT_ID_VGA,
1631                                                     &hpd);
1632                 }
1633
1634                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1635                         /* TV - tv dac */
1636                         ddc_i2c.valid = false;
1637                         hpd.hpd = RADEON_HPD_NONE;
1638                         radeon_add_legacy_encoder(dev,
1639                                                   radeon_get_encoder_enum(dev,
1640                                                                         ATOM_DEVICE_TV1_SUPPORT,
1641                                                                         2),
1642                                                   ATOM_DEVICE_TV1_SUPPORT);
1643                         radeon_add_legacy_connector(dev, 2,
1644                                                     ATOM_DEVICE_TV1_SUPPORT,
1645                                                     DRM_MODE_CONNECTOR_SVIDEO,
1646                                                     &ddc_i2c,
1647                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1648                                                     &hpd);
1649                 }
1650                 break;
1651         case CT_IBOOK:
1652                 DRM_INFO("Connector Table: %d (ibook)\n",
1653                          rdev->mode_info.connector_table);
1654                 /* LVDS */
1655                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1656                 hpd.hpd = RADEON_HPD_NONE;
1657                 radeon_add_legacy_encoder(dev,
1658                                           radeon_get_encoder_enum(dev,
1659                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1660                                                                 0),
1661                                           ATOM_DEVICE_LCD1_SUPPORT);
1662                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1663                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1664                                             CONNECTOR_OBJECT_ID_LVDS,
1665                                             &hpd);
1666                 /* VGA - TV DAC */
1667                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1668                 hpd.hpd = RADEON_HPD_NONE;
1669                 radeon_add_legacy_encoder(dev,
1670                                           radeon_get_encoder_enum(dev,
1671                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1672                                                                 2),
1673                                           ATOM_DEVICE_CRT2_SUPPORT);
1674                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1675                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1676                                             CONNECTOR_OBJECT_ID_VGA,
1677                                             &hpd);
1678                 /* TV - TV DAC */
1679                 ddc_i2c.valid = false;
1680                 hpd.hpd = RADEON_HPD_NONE;
1681                 radeon_add_legacy_encoder(dev,
1682                                           radeon_get_encoder_enum(dev,
1683                                                                 ATOM_DEVICE_TV1_SUPPORT,
1684                                                                 2),
1685                                           ATOM_DEVICE_TV1_SUPPORT);
1686                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1687                                             DRM_MODE_CONNECTOR_SVIDEO,
1688                                             &ddc_i2c,
1689                                             CONNECTOR_OBJECT_ID_SVIDEO,
1690                                             &hpd);
1691                 break;
1692         case CT_POWERBOOK_EXTERNAL:
1693                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1694                          rdev->mode_info.connector_table);
1695                 /* LVDS */
1696                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1697                 hpd.hpd = RADEON_HPD_NONE;
1698                 radeon_add_legacy_encoder(dev,
1699                                           radeon_get_encoder_enum(dev,
1700                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1701                                                                 0),
1702                                           ATOM_DEVICE_LCD1_SUPPORT);
1703                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1704                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1705                                             CONNECTOR_OBJECT_ID_LVDS,
1706                                             &hpd);
1707                 /* DVI-I - primary dac, ext tmds */
1708                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1709                 hpd.hpd = RADEON_HPD_2; /* ??? */
1710                 radeon_add_legacy_encoder(dev,
1711                                           radeon_get_encoder_enum(dev,
1712                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1713                                                                 0),
1714                                           ATOM_DEVICE_DFP2_SUPPORT);
1715                 radeon_add_legacy_encoder(dev,
1716                                           radeon_get_encoder_enum(dev,
1717                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1718                                                                 1),
1719                                           ATOM_DEVICE_CRT1_SUPPORT);
1720                 /* XXX some are SL */
1721                 radeon_add_legacy_connector(dev, 1,
1722                                             ATOM_DEVICE_DFP2_SUPPORT |
1723                                             ATOM_DEVICE_CRT1_SUPPORT,
1724                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1725                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1726                                             &hpd);
1727                 /* TV - TV DAC */
1728                 ddc_i2c.valid = false;
1729                 hpd.hpd = RADEON_HPD_NONE;
1730                 radeon_add_legacy_encoder(dev,
1731                                           radeon_get_encoder_enum(dev,
1732                                                                 ATOM_DEVICE_TV1_SUPPORT,
1733                                                                 2),
1734                                           ATOM_DEVICE_TV1_SUPPORT);
1735                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1736                                             DRM_MODE_CONNECTOR_SVIDEO,
1737                                             &ddc_i2c,
1738                                             CONNECTOR_OBJECT_ID_SVIDEO,
1739                                             &hpd);
1740                 break;
1741         case CT_POWERBOOK_INTERNAL:
1742                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1743                          rdev->mode_info.connector_table);
1744                 /* LVDS */
1745                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1746                 hpd.hpd = RADEON_HPD_NONE;
1747                 radeon_add_legacy_encoder(dev,
1748                                           radeon_get_encoder_enum(dev,
1749                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1750                                                                 0),
1751                                           ATOM_DEVICE_LCD1_SUPPORT);
1752                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1753                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1754                                             CONNECTOR_OBJECT_ID_LVDS,
1755                                             &hpd);
1756                 /* DVI-I - primary dac, int tmds */
1757                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1758                 hpd.hpd = RADEON_HPD_1; /* ??? */
1759                 radeon_add_legacy_encoder(dev,
1760                                           radeon_get_encoder_enum(dev,
1761                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1762                                                                 0),
1763                                           ATOM_DEVICE_DFP1_SUPPORT);
1764                 radeon_add_legacy_encoder(dev,
1765                                           radeon_get_encoder_enum(dev,
1766                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1767                                                                 1),
1768                                           ATOM_DEVICE_CRT1_SUPPORT);
1769                 radeon_add_legacy_connector(dev, 1,
1770                                             ATOM_DEVICE_DFP1_SUPPORT |
1771                                             ATOM_DEVICE_CRT1_SUPPORT,
1772                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1773                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1774                                             &hpd);
1775                 /* TV - TV DAC */
1776                 ddc_i2c.valid = false;
1777                 hpd.hpd = RADEON_HPD_NONE;
1778                 radeon_add_legacy_encoder(dev,
1779                                           radeon_get_encoder_enum(dev,
1780                                                                 ATOM_DEVICE_TV1_SUPPORT,
1781                                                                 2),
1782                                           ATOM_DEVICE_TV1_SUPPORT);
1783                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1784                                             DRM_MODE_CONNECTOR_SVIDEO,
1785                                             &ddc_i2c,
1786                                             CONNECTOR_OBJECT_ID_SVIDEO,
1787                                             &hpd);
1788                 break;
1789         case CT_POWERBOOK_VGA:
1790                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1791                          rdev->mode_info.connector_table);
1792                 /* LVDS */
1793                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1794                 hpd.hpd = RADEON_HPD_NONE;
1795                 radeon_add_legacy_encoder(dev,
1796                                           radeon_get_encoder_enum(dev,
1797                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1798                                                                 0),
1799                                           ATOM_DEVICE_LCD1_SUPPORT);
1800                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1801                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1802                                             CONNECTOR_OBJECT_ID_LVDS,
1803                                             &hpd);
1804                 /* VGA - primary dac */
1805                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1806                 hpd.hpd = RADEON_HPD_NONE;
1807                 radeon_add_legacy_encoder(dev,
1808                                           radeon_get_encoder_enum(dev,
1809                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1810                                                                 1),
1811                                           ATOM_DEVICE_CRT1_SUPPORT);
1812                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1813                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1814                                             CONNECTOR_OBJECT_ID_VGA,
1815                                             &hpd);
1816                 /* TV - TV DAC */
1817                 ddc_i2c.valid = false;
1818                 hpd.hpd = RADEON_HPD_NONE;
1819                 radeon_add_legacy_encoder(dev,
1820                                           radeon_get_encoder_enum(dev,
1821                                                                 ATOM_DEVICE_TV1_SUPPORT,
1822                                                                 2),
1823                                           ATOM_DEVICE_TV1_SUPPORT);
1824                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1825                                             DRM_MODE_CONNECTOR_SVIDEO,
1826                                             &ddc_i2c,
1827                                             CONNECTOR_OBJECT_ID_SVIDEO,
1828                                             &hpd);
1829                 break;
1830         case CT_MINI_EXTERNAL:
1831                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1832                          rdev->mode_info.connector_table);
1833                 /* DVI-I - tv dac, ext tmds */
1834                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1835                 hpd.hpd = RADEON_HPD_2; /* ??? */
1836                 radeon_add_legacy_encoder(dev,
1837                                           radeon_get_encoder_enum(dev,
1838                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1839                                                                 0),
1840                                           ATOM_DEVICE_DFP2_SUPPORT);
1841                 radeon_add_legacy_encoder(dev,
1842                                           radeon_get_encoder_enum(dev,
1843                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1844                                                                 2),
1845                                           ATOM_DEVICE_CRT2_SUPPORT);
1846                 /* XXX are any DL? */
1847                 radeon_add_legacy_connector(dev, 0,
1848                                             ATOM_DEVICE_DFP2_SUPPORT |
1849                                             ATOM_DEVICE_CRT2_SUPPORT,
1850                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1851                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1852                                             &hpd);
1853                 /* TV - TV DAC */
1854                 ddc_i2c.valid = false;
1855                 hpd.hpd = RADEON_HPD_NONE;
1856                 radeon_add_legacy_encoder(dev,
1857                                           radeon_get_encoder_enum(dev,
1858                                                                 ATOM_DEVICE_TV1_SUPPORT,
1859                                                                 2),
1860                                           ATOM_DEVICE_TV1_SUPPORT);
1861                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1862                                             DRM_MODE_CONNECTOR_SVIDEO,
1863                                             &ddc_i2c,
1864                                             CONNECTOR_OBJECT_ID_SVIDEO,
1865                                             &hpd);
1866                 break;
1867         case CT_MINI_INTERNAL:
1868                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1869                          rdev->mode_info.connector_table);
1870                 /* DVI-I - tv dac, int tmds */
1871                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1872                 hpd.hpd = RADEON_HPD_1; /* ??? */
1873                 radeon_add_legacy_encoder(dev,
1874                                           radeon_get_encoder_enum(dev,
1875                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1876                                                                 0),
1877                                           ATOM_DEVICE_DFP1_SUPPORT);
1878                 radeon_add_legacy_encoder(dev,
1879                                           radeon_get_encoder_enum(dev,
1880                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1881                                                                 2),
1882                                           ATOM_DEVICE_CRT2_SUPPORT);
1883                 radeon_add_legacy_connector(dev, 0,
1884                                             ATOM_DEVICE_DFP1_SUPPORT |
1885                                             ATOM_DEVICE_CRT2_SUPPORT,
1886                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1887                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1888                                             &hpd);
1889                 /* TV - TV DAC */
1890                 ddc_i2c.valid = false;
1891                 hpd.hpd = RADEON_HPD_NONE;
1892                 radeon_add_legacy_encoder(dev,
1893                                           radeon_get_encoder_enum(dev,
1894                                                                 ATOM_DEVICE_TV1_SUPPORT,
1895                                                                 2),
1896                                           ATOM_DEVICE_TV1_SUPPORT);
1897                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1898                                             DRM_MODE_CONNECTOR_SVIDEO,
1899                                             &ddc_i2c,
1900                                             CONNECTOR_OBJECT_ID_SVIDEO,
1901                                             &hpd);
1902                 break;
1903         case CT_IMAC_G5_ISIGHT:
1904                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1905                          rdev->mode_info.connector_table);
1906                 /* DVI-D - int tmds */
1907                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1908                 hpd.hpd = RADEON_HPD_1; /* ??? */
1909                 radeon_add_legacy_encoder(dev,
1910                                           radeon_get_encoder_enum(dev,
1911                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1912                                                                 0),
1913                                           ATOM_DEVICE_DFP1_SUPPORT);
1914                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1915                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1916                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1917                                             &hpd);
1918                 /* VGA - tv dac */
1919                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1920                 hpd.hpd = RADEON_HPD_NONE;
1921                 radeon_add_legacy_encoder(dev,
1922                                           radeon_get_encoder_enum(dev,
1923                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1924                                                                 2),
1925                                           ATOM_DEVICE_CRT2_SUPPORT);
1926                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1927                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1928                                             CONNECTOR_OBJECT_ID_VGA,
1929                                             &hpd);
1930                 /* TV - TV DAC */
1931                 ddc_i2c.valid = false;
1932                 hpd.hpd = RADEON_HPD_NONE;
1933                 radeon_add_legacy_encoder(dev,
1934                                           radeon_get_encoder_enum(dev,
1935                                                                 ATOM_DEVICE_TV1_SUPPORT,
1936                                                                 2),
1937                                           ATOM_DEVICE_TV1_SUPPORT);
1938                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1939                                             DRM_MODE_CONNECTOR_SVIDEO,
1940                                             &ddc_i2c,
1941                                             CONNECTOR_OBJECT_ID_SVIDEO,
1942                                             &hpd);
1943                 break;
1944         case CT_EMAC:
1945                 DRM_INFO("Connector Table: %d (emac)\n",
1946                          rdev->mode_info.connector_table);
1947                 /* VGA - primary dac */
1948                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1949                 hpd.hpd = RADEON_HPD_NONE;
1950                 radeon_add_legacy_encoder(dev,
1951                                           radeon_get_encoder_enum(dev,
1952                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1953                                                                 1),
1954                                           ATOM_DEVICE_CRT1_SUPPORT);
1955                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1956                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1957                                             CONNECTOR_OBJECT_ID_VGA,
1958                                             &hpd);
1959                 /* VGA - tv dac */
1960                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1961                 hpd.hpd = RADEON_HPD_NONE;
1962                 radeon_add_legacy_encoder(dev,
1963                                           radeon_get_encoder_enum(dev,
1964                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1965                                                                 2),
1966                                           ATOM_DEVICE_CRT2_SUPPORT);
1967                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1968                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1969                                             CONNECTOR_OBJECT_ID_VGA,
1970                                             &hpd);
1971                 /* TV - TV DAC */
1972                 ddc_i2c.valid = false;
1973                 hpd.hpd = RADEON_HPD_NONE;
1974                 radeon_add_legacy_encoder(dev,
1975                                           radeon_get_encoder_enum(dev,
1976                                                                 ATOM_DEVICE_TV1_SUPPORT,
1977                                                                 2),
1978                                           ATOM_DEVICE_TV1_SUPPORT);
1979                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1980                                             DRM_MODE_CONNECTOR_SVIDEO,
1981                                             &ddc_i2c,
1982                                             CONNECTOR_OBJECT_ID_SVIDEO,
1983                                             &hpd);
1984                 break;
1985         case CT_RN50_POWER:
1986                 DRM_INFO("Connector Table: %d (rn50-power)\n",
1987                          rdev->mode_info.connector_table);
1988                 /* VGA - primary dac */
1989                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1990                 hpd.hpd = RADEON_HPD_NONE;
1991                 radeon_add_legacy_encoder(dev,
1992                                           radeon_get_encoder_enum(dev,
1993                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1994                                                                 1),
1995                                           ATOM_DEVICE_CRT1_SUPPORT);
1996                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1997                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1998                                             CONNECTOR_OBJECT_ID_VGA,
1999                                             &hpd);
2000                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2001                 hpd.hpd = RADEON_HPD_NONE;
2002                 radeon_add_legacy_encoder(dev,
2003                                           radeon_get_encoder_enum(dev,
2004                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2005                                                                 2),
2006                                           ATOM_DEVICE_CRT2_SUPPORT);
2007                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2008                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2009                                             CONNECTOR_OBJECT_ID_VGA,
2010                                             &hpd);
2011                 break;
2012         case CT_MAC_X800:
2013                 DRM_INFO("Connector Table: %d (mac x800)\n",
2014                          rdev->mode_info.connector_table);
2015                 /* DVI - primary dac, internal tmds */
2016                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2017                 hpd.hpd = RADEON_HPD_1; /* ??? */
2018                 radeon_add_legacy_encoder(dev,
2019                                           radeon_get_encoder_enum(dev,
2020                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2021                                                                   0),
2022                                           ATOM_DEVICE_DFP1_SUPPORT);
2023                 radeon_add_legacy_encoder(dev,
2024                                           radeon_get_encoder_enum(dev,
2025                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2026                                                                   1),
2027                                           ATOM_DEVICE_CRT1_SUPPORT);
2028                 radeon_add_legacy_connector(dev, 0,
2029                                             ATOM_DEVICE_DFP1_SUPPORT |
2030                                             ATOM_DEVICE_CRT1_SUPPORT,
2031                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2032                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2033                                             &hpd);
2034                 /* DVI - tv dac, dvo */
2035                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2036                 hpd.hpd = RADEON_HPD_2; /* ??? */
2037                 radeon_add_legacy_encoder(dev,
2038                                           radeon_get_encoder_enum(dev,
2039                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2040                                                                   0),
2041                                           ATOM_DEVICE_DFP2_SUPPORT);
2042                 radeon_add_legacy_encoder(dev,
2043                                           radeon_get_encoder_enum(dev,
2044                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2045                                                                   2),
2046                                           ATOM_DEVICE_CRT2_SUPPORT);
2047                 radeon_add_legacy_connector(dev, 1,
2048                                             ATOM_DEVICE_DFP2_SUPPORT |
2049                                             ATOM_DEVICE_CRT2_SUPPORT,
2050                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2051                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2052                                             &hpd);
2053                 break;
2054         case CT_MAC_G5_9600:
2055                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2056                          rdev->mode_info.connector_table);
2057                 /* DVI - tv dac, dvo */
2058                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2059                 hpd.hpd = RADEON_HPD_1; /* ??? */
2060                 radeon_add_legacy_encoder(dev,
2061                                           radeon_get_encoder_enum(dev,
2062                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2063                                                                   0),
2064                                           ATOM_DEVICE_DFP2_SUPPORT);
2065                 radeon_add_legacy_encoder(dev,
2066                                           radeon_get_encoder_enum(dev,
2067                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2068                                                                   2),
2069                                           ATOM_DEVICE_CRT2_SUPPORT);
2070                 radeon_add_legacy_connector(dev, 0,
2071                                             ATOM_DEVICE_DFP2_SUPPORT |
2072                                             ATOM_DEVICE_CRT2_SUPPORT,
2073                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2074                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2075                                             &hpd);
2076                 /* ADC - primary dac, internal tmds */
2077                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2078                 hpd.hpd = RADEON_HPD_2; /* ??? */
2079                 radeon_add_legacy_encoder(dev,
2080                                           radeon_get_encoder_enum(dev,
2081                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2082                                                                   0),
2083                                           ATOM_DEVICE_DFP1_SUPPORT);
2084                 radeon_add_legacy_encoder(dev,
2085                                           radeon_get_encoder_enum(dev,
2086                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2087                                                                   1),
2088                                           ATOM_DEVICE_CRT1_SUPPORT);
2089                 radeon_add_legacy_connector(dev, 1,
2090                                             ATOM_DEVICE_DFP1_SUPPORT |
2091                                             ATOM_DEVICE_CRT1_SUPPORT,
2092                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2093                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2094                                             &hpd);
2095                 /* TV - TV DAC */
2096                 ddc_i2c.valid = false;
2097                 hpd.hpd = RADEON_HPD_NONE;
2098                 radeon_add_legacy_encoder(dev,
2099                                           radeon_get_encoder_enum(dev,
2100                                                                 ATOM_DEVICE_TV1_SUPPORT,
2101                                                                 2),
2102                                           ATOM_DEVICE_TV1_SUPPORT);
2103                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2104                                             DRM_MODE_CONNECTOR_SVIDEO,
2105                                             &ddc_i2c,
2106                                             CONNECTOR_OBJECT_ID_SVIDEO,
2107                                             &hpd);
2108                 break;
2109         case CT_SAM440EP:
2110                 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2111                          rdev->mode_info.connector_table);
2112                 /* LVDS */
2113                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2114                 hpd.hpd = RADEON_HPD_NONE;
2115                 radeon_add_legacy_encoder(dev,
2116                                           radeon_get_encoder_enum(dev,
2117                                                                 ATOM_DEVICE_LCD1_SUPPORT,
2118                                                                 0),
2119                                           ATOM_DEVICE_LCD1_SUPPORT);
2120                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2121                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2122                                             CONNECTOR_OBJECT_ID_LVDS,
2123                                             &hpd);
2124                 /* DVI-I - secondary dac, int tmds */
2125                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2126                 hpd.hpd = RADEON_HPD_1; /* ??? */
2127                 radeon_add_legacy_encoder(dev,
2128                                           radeon_get_encoder_enum(dev,
2129                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2130                                                                 0),
2131                                           ATOM_DEVICE_DFP1_SUPPORT);
2132                 radeon_add_legacy_encoder(dev,
2133                                           radeon_get_encoder_enum(dev,
2134                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2135                                                                 2),
2136                                           ATOM_DEVICE_CRT2_SUPPORT);
2137                 radeon_add_legacy_connector(dev, 1,
2138                                             ATOM_DEVICE_DFP1_SUPPORT |
2139                                             ATOM_DEVICE_CRT2_SUPPORT,
2140                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2141                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2142                                             &hpd);
2143                 /* VGA - primary dac */
2144                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2145                 hpd.hpd = RADEON_HPD_NONE;
2146                 radeon_add_legacy_encoder(dev,
2147                                           radeon_get_encoder_enum(dev,
2148                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2149                                                                 1),
2150                                           ATOM_DEVICE_CRT1_SUPPORT);
2151                 radeon_add_legacy_connector(dev, 2,
2152                                             ATOM_DEVICE_CRT1_SUPPORT,
2153                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2154                                             CONNECTOR_OBJECT_ID_VGA,
2155                                             &hpd);
2156                 /* TV - TV DAC */
2157                 ddc_i2c.valid = false;
2158                 hpd.hpd = RADEON_HPD_NONE;
2159                 radeon_add_legacy_encoder(dev,
2160                                           radeon_get_encoder_enum(dev,
2161                                                                 ATOM_DEVICE_TV1_SUPPORT,
2162                                                                 2),
2163                                           ATOM_DEVICE_TV1_SUPPORT);
2164                 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2165                                             DRM_MODE_CONNECTOR_SVIDEO,
2166                                             &ddc_i2c,
2167                                             CONNECTOR_OBJECT_ID_SVIDEO,
2168                                             &hpd);
2169                 break;
2170         case CT_MAC_G4_SILVER:
2171                 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2172                          rdev->mode_info.connector_table);
2173                 /* DVI-I - tv dac, int tmds */
2174                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2175                 hpd.hpd = RADEON_HPD_1; /* ??? */
2176                 radeon_add_legacy_encoder(dev,
2177                                           radeon_get_encoder_enum(dev,
2178                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2179                                                                 0),
2180                                           ATOM_DEVICE_DFP1_SUPPORT);
2181                 radeon_add_legacy_encoder(dev,
2182                                           radeon_get_encoder_enum(dev,
2183                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2184                                                                 2),
2185                                           ATOM_DEVICE_CRT2_SUPPORT);
2186                 radeon_add_legacy_connector(dev, 0,
2187                                             ATOM_DEVICE_DFP1_SUPPORT |
2188                                             ATOM_DEVICE_CRT2_SUPPORT,
2189                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2190                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2191                                             &hpd);
2192                 /* VGA - primary dac */
2193                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2194                 hpd.hpd = RADEON_HPD_NONE;
2195                 radeon_add_legacy_encoder(dev,
2196                                           radeon_get_encoder_enum(dev,
2197                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2198                                                                 1),
2199                                           ATOM_DEVICE_CRT1_SUPPORT);
2200                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2201                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2202                                             CONNECTOR_OBJECT_ID_VGA,
2203                                             &hpd);
2204                 /* TV - TV DAC */
2205                 ddc_i2c.valid = false;
2206                 hpd.hpd = RADEON_HPD_NONE;
2207                 radeon_add_legacy_encoder(dev,
2208                                           radeon_get_encoder_enum(dev,
2209                                                                 ATOM_DEVICE_TV1_SUPPORT,
2210                                                                 2),
2211                                           ATOM_DEVICE_TV1_SUPPORT);
2212                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2213                                             DRM_MODE_CONNECTOR_SVIDEO,
2214                                             &ddc_i2c,
2215                                             CONNECTOR_OBJECT_ID_SVIDEO,
2216                                             &hpd);
2217                 break;
2218         default:
2219                 DRM_INFO("Connector table: %d (invalid)\n",
2220                          rdev->mode_info.connector_table);
2221                 return false;
2222         }
2223
2224         radeon_link_encoder_connector(dev);
2225
2226         return true;
2227 }
2228
2229 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2230                                        int bios_index,
2231                                        enum radeon_combios_connector
2232                                        *legacy_connector,
2233                                        struct radeon_i2c_bus_rec *ddc_i2c,
2234                                        struct radeon_hpd *hpd)
2235 {
2236
2237         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2238            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2239         if (dev->pdev->device == 0x515e &&
2240             dev->pdev->subsystem_vendor == 0x1014) {
2241                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2242                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2243                         return false;
2244         }
2245
2246         /* X300 card with extra non-existent DVI port */
2247         if (dev->pdev->device == 0x5B60 &&
2248             dev->pdev->subsystem_vendor == 0x17af &&
2249             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2250                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2251                         return false;
2252         }
2253
2254         return true;
2255 }
2256
2257 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2258 {
2259         /* Acer 5102 has non-existent TV port */
2260         if (dev->pdev->device == 0x5975 &&
2261             dev->pdev->subsystem_vendor == 0x1025 &&
2262             dev->pdev->subsystem_device == 0x009f)
2263                 return false;
2264
2265         /* HP dc5750 has non-existent TV port */
2266         if (dev->pdev->device == 0x5974 &&
2267             dev->pdev->subsystem_vendor == 0x103c &&
2268             dev->pdev->subsystem_device == 0x280a)
2269                 return false;
2270
2271         /* MSI S270 has non-existent TV port */
2272         if (dev->pdev->device == 0x5955 &&
2273             dev->pdev->subsystem_vendor == 0x1462 &&
2274             dev->pdev->subsystem_device == 0x0131)
2275                 return false;
2276
2277         return true;
2278 }
2279
2280 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2281 {
2282         struct radeon_device *rdev = dev->dev_private;
2283         uint32_t ext_tmds_info;
2284
2285         if (rdev->flags & RADEON_IS_IGP) {
2286                 if (is_dvi_d)
2287                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2288                 else
2289                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2290         }
2291         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2292         if (ext_tmds_info) {
2293                 uint8_t rev = RBIOS8(ext_tmds_info);
2294                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2295                 if (rev >= 3) {
2296                         if (is_dvi_d)
2297                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2298                         else
2299                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2300                 } else {
2301                         if (flags & 1) {
2302                                 if (is_dvi_d)
2303                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2304                                 else
2305                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2306                         }
2307                 }
2308         }
2309         if (is_dvi_d)
2310                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2311         else
2312                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2313 }
2314
2315 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2316 {
2317         struct radeon_device *rdev = dev->dev_private;
2318         uint32_t conn_info, entry, devices;
2319         uint16_t tmp, connector_object_id;
2320         enum radeon_combios_ddc ddc_type;
2321         enum radeon_combios_connector connector;
2322         int i = 0;
2323         struct radeon_i2c_bus_rec ddc_i2c;
2324         struct radeon_hpd hpd;
2325
2326         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2327         if (conn_info) {
2328                 for (i = 0; i < 4; i++) {
2329                         entry = conn_info + 2 + i * 2;
2330
2331                         if (!RBIOS16(entry))
2332                                 break;
2333
2334                         tmp = RBIOS16(entry);
2335
2336                         connector = (tmp >> 12) & 0xf;
2337
2338                         ddc_type = (tmp >> 8) & 0xf;
2339                         if (ddc_type == 5)
2340                                 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2341                         else
2342                                 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2343
2344                         switch (connector) {
2345                         case CONNECTOR_PROPRIETARY_LEGACY:
2346                         case CONNECTOR_DVI_I_LEGACY:
2347                         case CONNECTOR_DVI_D_LEGACY:
2348                                 if ((tmp >> 4) & 0x1)
2349                                         hpd.hpd = RADEON_HPD_2;
2350                                 else
2351                                         hpd.hpd = RADEON_HPD_1;
2352                                 break;
2353                         default:
2354                                 hpd.hpd = RADEON_HPD_NONE;
2355                                 break;
2356                         }
2357
2358                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2359                                                         &ddc_i2c, &hpd))
2360                                 continue;
2361
2362                         switch (connector) {
2363                         case CONNECTOR_PROPRIETARY_LEGACY:
2364                                 if ((tmp >> 4) & 0x1)
2365                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2366                                 else
2367                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2368                                 radeon_add_legacy_encoder(dev,
2369                                                           radeon_get_encoder_enum
2370                                                           (dev, devices, 0),
2371                                                           devices);
2372                                 radeon_add_legacy_connector(dev, i, devices,
2373                                                             legacy_connector_convert
2374                                                             [connector],
2375                                                             &ddc_i2c,
2376                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2377                                                             &hpd);
2378                                 break;
2379                         case CONNECTOR_CRT_LEGACY:
2380                                 if (tmp & 0x1) {
2381                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2382                                         radeon_add_legacy_encoder(dev,
2383                                                                   radeon_get_encoder_enum
2384                                                                   (dev,
2385                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2386                                                                    2),
2387                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2388                                 } else {
2389                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2390                                         radeon_add_legacy_encoder(dev,
2391                                                                   radeon_get_encoder_enum
2392                                                                   (dev,
2393                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2394                                                                    1),
2395                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2396                                 }
2397                                 radeon_add_legacy_connector(dev,
2398                                                             i,
2399                                                             devices,
2400                                                             legacy_connector_convert
2401                                                             [connector],
2402                                                             &ddc_i2c,
2403                                                             CONNECTOR_OBJECT_ID_VGA,
2404                                                             &hpd);
2405                                 break;
2406                         case CONNECTOR_DVI_I_LEGACY:
2407                                 devices = 0;
2408                                 if (tmp & 0x1) {
2409                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2410                                         radeon_add_legacy_encoder(dev,
2411                                                                   radeon_get_encoder_enum
2412                                                                   (dev,
2413                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2414                                                                    2),
2415                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2416                                 } else {
2417                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2418                                         radeon_add_legacy_encoder(dev,
2419                                                                   radeon_get_encoder_enum
2420                                                                   (dev,
2421                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2422                                                                    1),
2423                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2424                                 }
2425                                 /* RV100 board with external TDMS bit mis-set.
2426                                  * Actually uses internal TMDS, clear the bit.
2427                                  */
2428                                 if (dev->pdev->device == 0x5159 &&
2429                                     dev->pdev->subsystem_vendor == 0x1014 &&
2430                                     dev->pdev->subsystem_device == 0x029A) {
2431                                         tmp &= ~(1 << 4);
2432                                 }
2433                                 if ((tmp >> 4) & 0x1) {
2434                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2435                                         radeon_add_legacy_encoder(dev,
2436                                                                   radeon_get_encoder_enum
2437                                                                   (dev,
2438                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2439                                                                    0),
2440                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2441                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2442                                 } else {
2443                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2444                                         radeon_add_legacy_encoder(dev,
2445                                                                   radeon_get_encoder_enum
2446                                                                   (dev,
2447                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2448                                                                    0),
2449                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2450                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2451                                 }
2452                                 radeon_add_legacy_connector(dev,
2453                                                             i,
2454                                                             devices,
2455                                                             legacy_connector_convert
2456                                                             [connector],
2457                                                             &ddc_i2c,
2458                                                             connector_object_id,
2459                                                             &hpd);
2460                                 break;
2461                         case CONNECTOR_DVI_D_LEGACY:
2462                                 if ((tmp >> 4) & 0x1) {
2463                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2464                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2465                                 } else {
2466                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2467                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2468                                 }
2469                                 radeon_add_legacy_encoder(dev,
2470                                                           radeon_get_encoder_enum
2471                                                           (dev, devices, 0),
2472                                                           devices);
2473                                 radeon_add_legacy_connector(dev, i, devices,
2474                                                             legacy_connector_convert
2475                                                             [connector],
2476                                                             &ddc_i2c,
2477                                                             connector_object_id,
2478                                                             &hpd);
2479                                 break;
2480                         case CONNECTOR_CTV_LEGACY:
2481                         case CONNECTOR_STV_LEGACY:
2482                                 radeon_add_legacy_encoder(dev,
2483                                                           radeon_get_encoder_enum
2484                                                           (dev,
2485                                                            ATOM_DEVICE_TV1_SUPPORT,
2486                                                            2),
2487                                                           ATOM_DEVICE_TV1_SUPPORT);
2488                                 radeon_add_legacy_connector(dev, i,
2489                                                             ATOM_DEVICE_TV1_SUPPORT,
2490                                                             legacy_connector_convert
2491                                                             [connector],
2492                                                             &ddc_i2c,
2493                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2494                                                             &hpd);
2495                                 break;
2496                         default:
2497                                 DRM_ERROR("Unknown connector type: %d\n",
2498                                           connector);
2499                                 continue;
2500                         }
2501
2502                 }
2503         } else {
2504                 uint16_t tmds_info =
2505                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2506                 if (tmds_info) {
2507                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2508
2509                         radeon_add_legacy_encoder(dev,
2510                                                   radeon_get_encoder_enum(dev,
2511                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2512                                                                         1),
2513                                                   ATOM_DEVICE_CRT1_SUPPORT);
2514                         radeon_add_legacy_encoder(dev,
2515                                                   radeon_get_encoder_enum(dev,
2516                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2517                                                                         0),
2518                                                   ATOM_DEVICE_DFP1_SUPPORT);
2519
2520                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2521                         hpd.hpd = RADEON_HPD_1;
2522                         radeon_add_legacy_connector(dev,
2523                                                     0,
2524                                                     ATOM_DEVICE_CRT1_SUPPORT |
2525                                                     ATOM_DEVICE_DFP1_SUPPORT,
2526                                                     DRM_MODE_CONNECTOR_DVII,
2527                                                     &ddc_i2c,
2528                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2529                                                     &hpd);
2530                 } else {
2531                         uint16_t crt_info =
2532                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2533                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2534                         if (crt_info) {
2535                                 radeon_add_legacy_encoder(dev,
2536                                                           radeon_get_encoder_enum(dev,
2537                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2538                                                                                 1),
2539                                                           ATOM_DEVICE_CRT1_SUPPORT);
2540                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2541                                 hpd.hpd = RADEON_HPD_NONE;
2542                                 radeon_add_legacy_connector(dev,
2543                                                             0,
2544                                                             ATOM_DEVICE_CRT1_SUPPORT,
2545                                                             DRM_MODE_CONNECTOR_VGA,
2546                                                             &ddc_i2c,
2547                                                             CONNECTOR_OBJECT_ID_VGA,
2548                                                             &hpd);
2549                         } else {
2550                                 DRM_DEBUG_KMS("No connector info found\n");
2551                                 return false;
2552                         }
2553                 }
2554         }
2555
2556         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2557                 uint16_t lcd_info =
2558                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2559                 if (lcd_info) {
2560                         uint16_t lcd_ddc_info =
2561                             combios_get_table_offset(dev,
2562                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2563
2564                         radeon_add_legacy_encoder(dev,
2565                                                   radeon_get_encoder_enum(dev,
2566                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2567                                                                         0),
2568                                                   ATOM_DEVICE_LCD1_SUPPORT);
2569
2570                         if (lcd_ddc_info) {
2571                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2572                                 switch (ddc_type) {
2573                                 case DDC_LCD:
2574                                         ddc_i2c =
2575                                                 combios_setup_i2c_bus(rdev,
2576                                                                       DDC_LCD,
2577                                                                       RBIOS32(lcd_ddc_info + 3),
2578                                                                       RBIOS32(lcd_ddc_info + 7));
2579                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2580                                         break;
2581                                 case DDC_GPIO:
2582                                         ddc_i2c =
2583                                                 combios_setup_i2c_bus(rdev,
2584                                                                       DDC_GPIO,
2585                                                                       RBIOS32(lcd_ddc_info + 3),
2586                                                                       RBIOS32(lcd_ddc_info + 7));
2587                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2588                                         break;
2589                                 default:
2590                                         ddc_i2c =
2591                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2592                                         break;
2593                                 }
2594                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2595                         } else
2596                                 ddc_i2c.valid = false;
2597
2598                         hpd.hpd = RADEON_HPD_NONE;
2599                         radeon_add_legacy_connector(dev,
2600                                                     5,
2601                                                     ATOM_DEVICE_LCD1_SUPPORT,
2602                                                     DRM_MODE_CONNECTOR_LVDS,
2603                                                     &ddc_i2c,
2604                                                     CONNECTOR_OBJECT_ID_LVDS,
2605                                                     &hpd);
2606                 }
2607         }
2608
2609         /* check TV table */
2610         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2611                 uint32_t tv_info =
2612                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2613                 if (tv_info) {
2614                         if (RBIOS8(tv_info + 6) == 'T') {
2615                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2616                                         hpd.hpd = RADEON_HPD_NONE;
2617                                         ddc_i2c.valid = false;
2618                                         radeon_add_legacy_encoder(dev,
2619                                                                   radeon_get_encoder_enum
2620                                                                   (dev,
2621                                                                    ATOM_DEVICE_TV1_SUPPORT,
2622                                                                    2),
2623                                                                   ATOM_DEVICE_TV1_SUPPORT);
2624                                         radeon_add_legacy_connector(dev, 6,
2625                                                                     ATOM_DEVICE_TV1_SUPPORT,
2626                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2627                                                                     &ddc_i2c,
2628                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2629                                                                     &hpd);
2630                                 }
2631                         }
2632                 }
2633         }
2634
2635         radeon_link_encoder_connector(dev);
2636
2637         return true;
2638 }
2639
2640 static const char *thermal_controller_names[] = {
2641         "NONE",
2642         "lm63",
2643         "adm1032",
2644 };
2645
2646 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2647 {
2648         struct drm_device *dev = rdev->ddev;
2649         u16 offset, misc, misc2 = 0;
2650         u8 rev, blocks, tmp;
2651         int state_index = 0;
2652         struct radeon_i2c_bus_rec i2c_bus;
2653
2654         rdev->pm.default_power_state_index = -1;
2655
2656         /* allocate 2 power states */
2657         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2658         if (rdev->pm.power_state) {
2659                 /* allocate 1 clock mode per state */
2660                 rdev->pm.power_state[0].clock_info =
2661                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2662                 rdev->pm.power_state[1].clock_info =
2663                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2664                 if (!rdev->pm.power_state[0].clock_info ||
2665                     !rdev->pm.power_state[1].clock_info)
2666                         goto pm_failed;
2667         } else
2668                 goto pm_failed;
2669
2670         /* check for a thermal chip */
2671         offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2672         if (offset) {
2673                 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2674
2675                 rev = RBIOS8(offset);
2676
2677                 if (rev == 0) {
2678                         thermal_controller = RBIOS8(offset + 3);
2679                         gpio = RBIOS8(offset + 4) & 0x3f;
2680                         i2c_addr = RBIOS8(offset + 5);
2681                 } else if (rev == 1) {
2682                         thermal_controller = RBIOS8(offset + 4);
2683                         gpio = RBIOS8(offset + 5) & 0x3f;
2684                         i2c_addr = RBIOS8(offset + 6);
2685                 } else if (rev == 2) {
2686                         thermal_controller = RBIOS8(offset + 4);
2687                         gpio = RBIOS8(offset + 5) & 0x3f;
2688                         i2c_addr = RBIOS8(offset + 6);
2689                         clk_bit = RBIOS8(offset + 0xa);
2690                         data_bit = RBIOS8(offset + 0xb);
2691                 }
2692                 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2693                         DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2694                                  thermal_controller_names[thermal_controller],
2695                                  i2c_addr >> 1);
2696                         if (gpio == DDC_LCD) {
2697                                 /* MM i2c */
2698                                 i2c_bus.valid = true;
2699                                 i2c_bus.hw_capable = true;
2700                                 i2c_bus.mm_i2c = true;
2701                                 i2c_bus.i2c_id = 0xa0;
2702                         } else if (gpio == DDC_GPIO)
2703                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2704                         else
2705                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2706                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2707                         if (rdev->pm.i2c_bus) {
2708                                 struct i2c_board_info info = { };
2709                                 const char *name = thermal_controller_names[thermal_controller];
2710                                 info.addr = i2c_addr >> 1;
2711                                 strlcpy(info.type, name, sizeof(info.type));
2712                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2713                         }
2714                 }
2715         } else {
2716                 /* boards with a thermal chip, but no overdrive table */
2717
2718                 /* Asus 9600xt has an f75375 on the monid bus */
2719                 if ((dev->pdev->device == 0x4152) &&
2720                     (dev->pdev->subsystem_vendor == 0x1043) &&
2721                     (dev->pdev->subsystem_device == 0xc002)) {
2722                         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2723                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2724                         if (rdev->pm.i2c_bus) {
2725                                 struct i2c_board_info info = { };
2726                                 const char *name = "f75375";
2727                                 info.addr = 0x28;
2728                                 strlcpy(info.type, name, sizeof(info.type));
2729                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2730                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2731                                          name, info.addr);
2732                         }
2733                 }
2734         }
2735
2736         if (rdev->flags & RADEON_IS_MOBILITY) {
2737                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2738                 if (offset) {
2739                         rev = RBIOS8(offset);
2740                         blocks = RBIOS8(offset + 0x2);
2741                         /* power mode 0 tends to be the only valid one */
2742                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2743                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2744                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2745                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2746                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2747                                 goto default_mode;
2748                         rdev->pm.power_state[state_index].type =
2749                                 POWER_STATE_TYPE_BATTERY;
2750                         misc = RBIOS16(offset + 0x5 + 0x0);
2751                         if (rev > 4)
2752                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2753                         rdev->pm.power_state[state_index].misc = misc;
2754                         rdev->pm.power_state[state_index].misc2 = misc2;
2755                         if (misc & 0x4) {
2756                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2757                                 if (misc & 0x8)
2758                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2759                                                 true;
2760                                 else
2761                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2762                                                 false;
2763                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2764                                 if (rev < 6) {
2765                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2766                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2767                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2768                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2769                                 } else {
2770                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2771                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2772                                         if (entries && voltage_table_offset) {
2773                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2774                                                         RBIOS16(voltage_table_offset) * 4;
2775                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2776                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2777                                         } else
2778                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2779                                 }
2780                                 switch ((misc2 & 0x700) >> 8) {
2781                                 case 0:
2782                                 default:
2783                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2784                                         break;
2785                                 case 1:
2786                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2787                                         break;
2788                                 case 2:
2789                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2790                                         break;
2791                                 case 3:
2792                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2793                                         break;
2794                                 case 4:
2795                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2796                                         break;
2797                                 }
2798                         } else
2799                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2800                         if (rev > 6)
2801                                 rdev->pm.power_state[state_index].pcie_lanes =
2802                                         RBIOS8(offset + 0x5 + 0x10);
2803                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2804                         state_index++;
2805                 } else {
2806                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2807                 }
2808         } else {
2809                 /* XXX figure out some good default low power mode for desktop cards */
2810         }
2811
2812 default_mode:
2813         /* add the default mode */
2814         rdev->pm.power_state[state_index].type =
2815                 POWER_STATE_TYPE_DEFAULT;
2816         rdev->pm.power_state[state_index].num_clock_modes = 1;
2817         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2818         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2819         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2820         if ((state_index > 0) &&
2821             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2822                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2823                         rdev->pm.power_state[0].clock_info[0].voltage;
2824         else
2825                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2826         rdev->pm.power_state[state_index].pcie_lanes = 16;
2827         rdev->pm.power_state[state_index].flags = 0;
2828         rdev->pm.default_power_state_index = state_index;
2829         rdev->pm.num_power_states = state_index + 1;
2830
2831         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2832         rdev->pm.current_clock_mode_index = 0;
2833         return;
2834
2835 pm_failed:
2836         rdev->pm.default_power_state_index = state_index;
2837         rdev->pm.num_power_states = 0;
2838
2839         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2840         rdev->pm.current_clock_mode_index = 0;
2841 }
2842
2843 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2844 {
2845         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2846         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2847
2848         if (!tmds)
2849                 return;
2850
2851         switch (tmds->dvo_chip) {
2852         case DVO_SIL164:
2853                 /* sil 164 */
2854                 radeon_i2c_put_byte(tmds->i2c_bus,
2855                                     tmds->slave_addr,
2856                                     0x08, 0x30);
2857                 radeon_i2c_put_byte(tmds->i2c_bus,
2858                                        tmds->slave_addr,
2859                                        0x09, 0x00);
2860                 radeon_i2c_put_byte(tmds->i2c_bus,
2861                                     tmds->slave_addr,
2862                                     0x0a, 0x90);
2863                 radeon_i2c_put_byte(tmds->i2c_bus,
2864                                     tmds->slave_addr,
2865                                     0x0c, 0x89);
2866                 radeon_i2c_put_byte(tmds->i2c_bus,
2867                                        tmds->slave_addr,
2868                                        0x08, 0x3b);
2869                 break;
2870         case DVO_SIL1178:
2871                 /* sil 1178 - untested */
2872                 /*
2873                  * 0x0f, 0x44
2874                  * 0x0f, 0x4c
2875                  * 0x0e, 0x01
2876                  * 0x0a, 0x80
2877                  * 0x09, 0x30
2878                  * 0x0c, 0xc9
2879                  * 0x0d, 0x70
2880                  * 0x08, 0x32
2881                  * 0x08, 0x33
2882                  */
2883                 break;
2884         default:
2885                 break;
2886         }
2887
2888 }
2889
2890 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2891 {
2892         struct drm_device *dev = encoder->dev;
2893         struct radeon_device *rdev = dev->dev_private;
2894         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2895         uint16_t offset;
2896         uint8_t blocks, slave_addr, rev;
2897         uint32_t index, id;
2898         uint32_t reg, val, and_mask, or_mask;
2899         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2900
2901         if (!tmds)
2902                 return false;
2903
2904         if (rdev->flags & RADEON_IS_IGP) {
2905                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2906                 rev = RBIOS8(offset);
2907                 if (offset) {
2908                         rev = RBIOS8(offset);
2909                         if (rev > 1) {
2910                                 blocks = RBIOS8(offset + 3);
2911                                 index = offset + 4;
2912                                 while (blocks > 0) {
2913                                         id = RBIOS16(index);
2914                                         index += 2;
2915                                         switch (id >> 13) {
2916                                         case 0:
2917                                                 reg = (id & 0x1fff) * 4;
2918                                                 val = RBIOS32(index);
2919                                                 index += 4;
2920                                                 WREG32(reg, val);
2921                                                 break;
2922                                         case 2:
2923                                                 reg = (id & 0x1fff) * 4;
2924                                                 and_mask = RBIOS32(index);
2925                                                 index += 4;
2926                                                 or_mask = RBIOS32(index);
2927                                                 index += 4;
2928                                                 val = RREG32(reg);
2929                                                 val = (val & and_mask) | or_mask;
2930                                                 WREG32(reg, val);
2931                                                 break;
2932                                         case 3:
2933                                                 val = RBIOS16(index);
2934                                                 index += 2;
2935                                                 udelay(val);
2936                                                 break;
2937                                         case 4:
2938                                                 val = RBIOS16(index);
2939                                                 index += 2;
2940                                                 mdelay(val);
2941                                                 break;
2942                                         case 6:
2943                                                 slave_addr = id & 0xff;
2944                                                 slave_addr >>= 1; /* 7 bit addressing */
2945                                                 index++;
2946                                                 reg = RBIOS8(index);
2947                                                 index++;
2948                                                 val = RBIOS8(index);
2949                                                 index++;
2950                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2951                                                                     slave_addr,
2952                                                                     reg, val);
2953                                                 break;
2954                                         default:
2955                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2956                                                 break;
2957                                         }
2958                                         blocks--;
2959                                 }
2960                                 return true;
2961                         }
2962                 }
2963         } else {
2964                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2965                 if (offset) {
2966                         index = offset + 10;
2967                         id = RBIOS16(index);
2968                         while (id != 0xffff) {
2969                                 index += 2;
2970                                 switch (id >> 13) {
2971                                 case 0:
2972                                         reg = (id & 0x1fff) * 4;
2973                                         val = RBIOS32(index);
2974                                         WREG32(reg, val);
2975                                         break;
2976                                 case 2:
2977                                         reg = (id & 0x1fff) * 4;
2978                                         and_mask = RBIOS32(index);
2979                                         index += 4;
2980                                         or_mask = RBIOS32(index);
2981                                         index += 4;
2982                                         val = RREG32(reg);
2983                                         val = (val & and_mask) | or_mask;
2984                                         WREG32(reg, val);
2985                                         break;
2986                                 case 4:
2987                                         val = RBIOS16(index);
2988                                         index += 2;
2989                                         udelay(val);
2990                                         break;
2991                                 case 5:
2992                                         reg = id & 0x1fff;
2993                                         and_mask = RBIOS32(index);
2994                                         index += 4;
2995                                         or_mask = RBIOS32(index);
2996                                         index += 4;
2997                                         val = RREG32_PLL(reg);
2998                                         val = (val & and_mask) | or_mask;
2999                                         WREG32_PLL(reg, val);
3000                                         break;
3001                                 case 6:
3002                                         reg = id & 0x1fff;
3003                                         val = RBIOS8(index);
3004                                         index += 1;
3005                                         radeon_i2c_put_byte(tmds->i2c_bus,
3006                                                             tmds->slave_addr,
3007                                                             reg, val);
3008                                         break;
3009                                 default:
3010                                         DRM_ERROR("Unknown id %d\n", id >> 13);
3011                                         break;
3012                                 }
3013                                 id = RBIOS16(index);
3014                         }
3015                         return true;
3016                 }
3017         }
3018         return false;
3019 }
3020
3021 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3022 {
3023         struct radeon_device *rdev = dev->dev_private;
3024
3025         if (offset) {
3026                 while (RBIOS16(offset)) {
3027                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3028                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
3029                         uint32_t val, and_mask, or_mask;
3030                         uint32_t tmp;
3031
3032                         offset += 2;
3033                         switch (cmd) {
3034                         case 0:
3035                                 val = RBIOS32(offset);
3036                                 offset += 4;
3037                                 WREG32(addr, val);
3038                                 break;
3039                         case 1:
3040                                 val = RBIOS32(offset);
3041                                 offset += 4;
3042                                 WREG32(addr, val);
3043                                 break;
3044                         case 2:
3045                                 and_mask = RBIOS32(offset);
3046                                 offset += 4;
3047                                 or_mask = RBIOS32(offset);
3048                                 offset += 4;
3049                                 tmp = RREG32(addr);
3050                                 tmp &= and_mask;
3051                                 tmp |= or_mask;
3052                                 WREG32(addr, tmp);
3053                                 break;
3054                         case 3:
3055                                 and_mask = RBIOS32(offset);
3056                                 offset += 4;
3057                                 or_mask = RBIOS32(offset);
3058                                 offset += 4;
3059                                 tmp = RREG32(addr);
3060                                 tmp &= and_mask;
3061                                 tmp |= or_mask;
3062                                 WREG32(addr, tmp);
3063                                 break;
3064                         case 4:
3065                                 val = RBIOS16(offset);
3066                                 offset += 2;
3067                                 udelay(val);
3068                                 break;
3069                         case 5:
3070                                 val = RBIOS16(offset);
3071                                 offset += 2;
3072                                 switch (addr) {
3073                                 case 8:
3074                                         while (val--) {
3075                                                 if (!
3076                                                     (RREG32_PLL
3077                                                      (RADEON_CLK_PWRMGT_CNTL) &
3078                                                      RADEON_MC_BUSY))
3079                                                         break;
3080                                         }
3081                                         break;
3082                                 case 9:
3083                                         while (val--) {
3084                                                 if ((RREG32(RADEON_MC_STATUS) &
3085                                                      RADEON_MC_IDLE))
3086                                                         break;
3087                                         }
3088                                         break;
3089                                 default:
3090                                         break;
3091                                 }
3092                                 break;
3093                         default:
3094                                 break;
3095                         }
3096                 }
3097         }
3098 }
3099
3100 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3101 {
3102         struct radeon_device *rdev = dev->dev_private;
3103
3104         if (offset) {
3105                 while (RBIOS8(offset)) {
3106                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3107                         uint8_t addr = (RBIOS8(offset) & 0x3f);
3108                         uint32_t val, shift, tmp;
3109                         uint32_t and_mask, or_mask;
3110
3111                         offset++;
3112                         switch (cmd) {
3113                         case 0:
3114                                 val = RBIOS32(offset);
3115                                 offset += 4;
3116                                 WREG32_PLL(addr, val);
3117                                 break;
3118                         case 1:
3119                                 shift = RBIOS8(offset) * 8;
3120                                 offset++;
3121                                 and_mask = RBIOS8(offset) << shift;
3122                                 and_mask |= ~(0xff << shift);
3123                                 offset++;
3124                                 or_mask = RBIOS8(offset) << shift;
3125                                 offset++;
3126                                 tmp = RREG32_PLL(addr);
3127                                 tmp &= and_mask;
3128                                 tmp |= or_mask;
3129                                 WREG32_PLL(addr, tmp);
3130                                 break;
3131                         case 2:
3132                         case 3:
3133                                 tmp = 1000;
3134                                 switch (addr) {
3135                                 case 1:
3136                                         udelay(150);
3137                                         break;
3138                                 case 2:
3139                                         mdelay(1);
3140                                         break;
3141                                 case 3:
3142                                         while (tmp--) {
3143                                                 if (!
3144                                                     (RREG32_PLL
3145                                                      (RADEON_CLK_PWRMGT_CNTL) &
3146                                                      RADEON_MC_BUSY))
3147                                                         break;
3148                                         }
3149                                         break;
3150                                 case 4:
3151                                         while (tmp--) {
3152                                                 if (RREG32_PLL
3153                                                     (RADEON_CLK_PWRMGT_CNTL) &
3154                                                     RADEON_DLL_READY)
3155                                                         break;
3156                                         }
3157                                         break;
3158                                 case 5:
3159                                         tmp =
3160                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3161                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
3162 #if 0
3163                                                 uint32_t mclk_cntl =
3164                                                     RREG32_PLL
3165                                                     (RADEON_MCLK_CNTL);
3166                                                 mclk_cntl &= 0xffff0000;
3167                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
3168                                                 WREG32_PLL(RADEON_MCLK_CNTL,
3169                                                            mclk_cntl);
3170                                                 mdelay(10);
3171 #endif
3172                                                 WREG32_PLL
3173                                                     (RADEON_CLK_PWRMGT_CNTL,
3174                                                      tmp &
3175                                                      ~RADEON_CG_NO1_DEBUG_0);
3176                                                 mdelay(10);
3177                                         }
3178                                         break;
3179                                 default:
3180                                         break;
3181                                 }
3182                                 break;
3183                         default:
3184                                 break;
3185                         }
3186                 }
3187         }
3188 }
3189
3190 static void combios_parse_ram_reset_table(struct drm_device *dev,
3191                                           uint16_t offset)
3192 {
3193         struct radeon_device *rdev = dev->dev_private;
3194         uint32_t tmp;
3195
3196         if (offset) {
3197                 uint8_t val = RBIOS8(offset);
3198                 while (val != 0xff) {
3199                         offset++;
3200
3201                         if (val == 0x0f) {
3202                                 uint32_t channel_complete_mask;
3203
3204                                 if (ASIC_IS_R300(rdev))
3205                                         channel_complete_mask =
3206                                             R300_MEM_PWRUP_COMPLETE;
3207                                 else
3208                                         channel_complete_mask =
3209                                             RADEON_MEM_PWRUP_COMPLETE;
3210                                 tmp = 20000;
3211                                 while (tmp--) {
3212                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
3213                                              channel_complete_mask) ==
3214                                             channel_complete_mask)
3215                                                 break;
3216                                 }
3217                         } else {
3218                                 uint32_t or_mask = RBIOS16(offset);
3219                                 offset += 2;
3220
3221                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3222                                 tmp &= RADEON_SDRAM_MODE_MASK;
3223                                 tmp |= or_mask;
3224                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3225
3226                                 or_mask = val << 24;
3227                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3228                                 tmp &= RADEON_B3MEM_RESET_MASK;
3229                                 tmp |= or_mask;
3230                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3231                         }
3232                         val = RBIOS8(offset);
3233                 }
3234         }
3235 }
3236
3237 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3238                                    int mem_addr_mapping)
3239 {
3240         struct radeon_device *rdev = dev->dev_private;
3241         uint32_t mem_cntl;
3242         uint32_t mem_size;
3243         uint32_t addr = 0;
3244
3245         mem_cntl = RREG32(RADEON_MEM_CNTL);
3246         if (mem_cntl & RV100_HALF_MODE)
3247                 ram /= 2;
3248         mem_size = ram;
3249         mem_cntl &= ~(0xff << 8);
3250         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3251         WREG32(RADEON_MEM_CNTL, mem_cntl);
3252         RREG32(RADEON_MEM_CNTL);
3253
3254         /* sdram reset ? */
3255
3256         /* something like this????  */
3257         while (ram--) {
3258                 addr = ram * 1024 * 1024;
3259                 /* write to each page */
3260                 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3261                 /* read back and verify */
3262                 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3263                         return 0;
3264         }
3265
3266         return mem_size;
3267 }
3268
3269 static void combios_write_ram_size(struct drm_device *dev)
3270 {
3271         struct radeon_device *rdev = dev->dev_private;
3272         uint8_t rev;
3273         uint16_t offset;
3274         uint32_t mem_size = 0;
3275         uint32_t mem_cntl = 0;
3276
3277         /* should do something smarter here I guess... */
3278         if (rdev->flags & RADEON_IS_IGP)
3279                 return;
3280
3281         /* first check detected mem table */
3282         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3283         if (offset) {
3284                 rev = RBIOS8(offset);
3285                 if (rev < 3) {
3286                         mem_cntl = RBIOS32(offset + 1);
3287                         mem_size = RBIOS16(offset + 5);
3288                         if ((rdev->family < CHIP_R200) &&
3289                             !ASIC_IS_RN50(rdev))
3290                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3291                 }
3292         }
3293
3294         if (!mem_size) {
3295                 offset =
3296                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3297                 if (offset) {
3298                         rev = RBIOS8(offset - 1);
3299                         if (rev < 1) {
3300                                 if ((rdev->family < CHIP_R200)
3301                                     && !ASIC_IS_RN50(rdev)) {
3302                                         int ram = 0;
3303                                         int mem_addr_mapping = 0;
3304
3305                                         while (RBIOS8(offset)) {
3306                                                 ram = RBIOS8(offset);
3307                                                 mem_addr_mapping =
3308                                                     RBIOS8(offset + 1);
3309                                                 if (mem_addr_mapping != 0x25)
3310                                                         ram *= 2;
3311                                                 mem_size =
3312                                                     combios_detect_ram(dev, ram,
3313                                                                        mem_addr_mapping);
3314                                                 if (mem_size)
3315                                                         break;
3316                                                 offset += 2;
3317                                         }
3318                                 } else
3319                                         mem_size = RBIOS8(offset);
3320                         } else {
3321                                 mem_size = RBIOS8(offset);
3322                                 mem_size *= 2;  /* convert to MB */
3323                         }
3324                 }
3325         }
3326
3327         mem_size *= (1024 * 1024);      /* convert to bytes */
3328         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3329 }
3330
3331 void radeon_combios_asic_init(struct drm_device *dev)
3332 {
3333         struct radeon_device *rdev = dev->dev_private;
3334         uint16_t table;
3335
3336         /* port hardcoded mac stuff from radeonfb */
3337         if (rdev->bios == NULL)
3338                 return;
3339
3340         /* ASIC INIT 1 */
3341         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3342         if (table)
3343                 combios_parse_mmio_table(dev, table);
3344
3345         /* PLL INIT */
3346         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3347         if (table)
3348                 combios_parse_pll_table(dev, table);
3349
3350         /* ASIC INIT 2 */
3351         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3352         if (table)
3353                 combios_parse_mmio_table(dev, table);
3354
3355         if (!(rdev->flags & RADEON_IS_IGP)) {
3356                 /* ASIC INIT 4 */
3357                 table =
3358                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3359                 if (table)
3360                         combios_parse_mmio_table(dev, table);
3361
3362                 /* RAM RESET */
3363                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3364                 if (table)
3365                         combios_parse_ram_reset_table(dev, table);
3366
3367                 /* ASIC INIT 3 */
3368                 table =
3369                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3370                 if (table)
3371                         combios_parse_mmio_table(dev, table);
3372
3373                 /* write CONFIG_MEMSIZE */
3374                 combios_write_ram_size(dev);
3375         }
3376
3377         /* quirk for rs4xx HP nx6125 laptop to make it resume
3378          * - it hangs on resume inside the dynclk 1 table.
3379          */
3380         if (rdev->family == CHIP_RS480 &&
3381             rdev->pdev->subsystem_vendor == 0x103c &&
3382             rdev->pdev->subsystem_device == 0x308b)
3383                 return;
3384
3385         /* quirk for rs4xx HP dv5000 laptop to make it resume
3386          * - it hangs on resume inside the dynclk 1 table.
3387          */
3388         if (rdev->family == CHIP_RS480 &&
3389             rdev->pdev->subsystem_vendor == 0x103c &&
3390             rdev->pdev->subsystem_device == 0x30a4)
3391                 return;
3392
3393         /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3394          * - it hangs on resume inside the dynclk 1 table.
3395          */
3396         if (rdev->family == CHIP_RS480 &&
3397             rdev->pdev->subsystem_vendor == 0x103c &&
3398             rdev->pdev->subsystem_device == 0x30ae)
3399                 return;
3400
3401         /* DYN CLK 1 */
3402         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3403         if (table)
3404                 combios_parse_pll_table(dev, table);
3405
3406 }
3407
3408 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3409 {
3410         struct radeon_device *rdev = dev->dev_private;
3411         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3412
3413         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3414         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3415         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3416
3417         /* let the bios control the backlight */
3418         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3419
3420         /* tell the bios not to handle mode switching */
3421         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3422                            RADEON_ACC_MODE_CHANGE);
3423
3424         /* tell the bios a driver is loaded */
3425         bios_7_scratch |= RADEON_DRV_LOADED;
3426
3427         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3428         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3429         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3430 }
3431
3432 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3433 {
3434         struct drm_device *dev = encoder->dev;
3435         struct radeon_device *rdev = dev->dev_private;
3436         uint32_t bios_6_scratch;
3437
3438         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3439
3440         if (lock)
3441                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3442         else
3443                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3444
3445         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3446 }
3447
3448 void
3449 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3450                                       struct drm_encoder *encoder,
3451                                       bool connected)
3452 {
3453         struct drm_device *dev = connector->dev;
3454         struct radeon_device *rdev = dev->dev_private;
3455         struct radeon_connector *radeon_connector =
3456             to_radeon_connector(connector);
3457         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3458         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3459         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3460
3461         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3462             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3463                 if (connected) {
3464                         DRM_DEBUG_KMS("TV1 connected\n");
3465                         /* fix me */
3466                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3467                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3468                         bios_5_scratch |= RADEON_TV1_ON;
3469                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3470                 } else {
3471                         DRM_DEBUG_KMS("TV1 disconnected\n");
3472                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3473                         bios_5_scratch &= ~RADEON_TV1_ON;
3474                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3475                 }
3476         }
3477         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3478             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3479                 if (connected) {
3480                         DRM_DEBUG_KMS("LCD1 connected\n");
3481                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3482                         bios_5_scratch |= RADEON_LCD1_ON;
3483                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3484                 } else {
3485                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3486                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3487                         bios_5_scratch &= ~RADEON_LCD1_ON;
3488                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3489                 }
3490         }
3491         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3492             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3493                 if (connected) {
3494                         DRM_DEBUG_KMS("CRT1 connected\n");
3495                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3496                         bios_5_scratch |= RADEON_CRT1_ON;
3497                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3498                 } else {
3499                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3500                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3501                         bios_5_scratch &= ~RADEON_CRT1_ON;
3502                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3503                 }
3504         }
3505         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3506             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3507                 if (connected) {
3508                         DRM_DEBUG_KMS("CRT2 connected\n");
3509                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3510                         bios_5_scratch |= RADEON_CRT2_ON;
3511                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3512                 } else {
3513                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3514                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3515                         bios_5_scratch &= ~RADEON_CRT2_ON;
3516                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3517                 }
3518         }
3519         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3520             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3521                 if (connected) {
3522                         DRM_DEBUG_KMS("DFP1 connected\n");
3523                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3524                         bios_5_scratch |= RADEON_DFP1_ON;
3525                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3526                 } else {
3527                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3528                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3529                         bios_5_scratch &= ~RADEON_DFP1_ON;
3530                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3531                 }
3532         }
3533         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3534             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3535                 if (connected) {
3536                         DRM_DEBUG_KMS("DFP2 connected\n");
3537                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3538                         bios_5_scratch |= RADEON_DFP2_ON;
3539                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3540                 } else {
3541                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3542                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3543                         bios_5_scratch &= ~RADEON_DFP2_ON;
3544                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3545                 }
3546         }
3547         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3548         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3549 }
3550
3551 void
3552 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3553 {
3554         struct drm_device *dev = encoder->dev;
3555         struct radeon_device *rdev = dev->dev_private;
3556         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3557         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3558
3559         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3560                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3561                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3562         }
3563         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3564                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3565                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3566         }
3567         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3568                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3569                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3570         }
3571         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3572                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3573                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3574         }
3575         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3576                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3577                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3578         }
3579         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3580                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3581                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3582         }
3583         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3584 }
3585
3586 void
3587 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3588 {
3589         struct drm_device *dev = encoder->dev;
3590         struct radeon_device *rdev = dev->dev_private;
3591         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3592         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3593
3594         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3595                 if (on)
3596                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3597                 else
3598                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3599         }
3600         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3601                 if (on)
3602                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3603                 else
3604                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3605         }
3606         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3607                 if (on)
3608                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3609                 else
3610                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3611         }
3612         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3613                 if (on)
3614                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3615                 else
3616                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3617         }
3618         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3619 }