2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
114 enum radeon_combios_ddc {
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
149 struct radeon_device *rdev = dev->dev_private;
151 uint16_t offset = 0, check_offset;
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
161 case COMBIOS_BIOS_SUPPORT_TABLE:
164 case COMBIOS_DAC_PROGRAMMING_TABLE:
167 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
170 case COMBIOS_CRTC_INFO_TABLE:
173 case COMBIOS_PLL_INFO_TABLE:
176 case COMBIOS_TV_INFO_TABLE:
179 case COMBIOS_DFP_INFO_TABLE:
182 case COMBIOS_HW_CONFIG_INFO_TABLE:
185 case COMBIOS_MULTIMEDIA_INFO_TABLE:
188 case COMBIOS_TV_STD_PATCH_TABLE:
191 case COMBIOS_LCD_INFO_TABLE:
194 case COMBIOS_MOBILE_INFO_TABLE:
197 case COMBIOS_PLL_INIT_TABLE:
200 case COMBIOS_MEM_CONFIG_TABLE:
203 case COMBIOS_SAVE_MASK_TABLE:
206 case COMBIOS_HARDCODED_EDID_TABLE:
209 case COMBIOS_ASIC_INIT_2_TABLE:
212 case COMBIOS_CONNECTOR_INFO_TABLE:
215 case COMBIOS_DYN_CLK_1_TABLE:
218 case COMBIOS_RESERVED_MEM_TABLE:
221 case COMBIOS_EXT_TMDS_INFO_TABLE:
224 case COMBIOS_MEM_CLK_INFO_TABLE:
227 case COMBIOS_EXT_DAC_INFO_TABLE:
230 case COMBIOS_MISC_INFO_TABLE:
233 case COMBIOS_CRT_INFO_TABLE:
236 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
239 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
242 case COMBIOS_FAN_SPEED_INFO_TABLE:
245 case COMBIOS_OVERDRIVE_INFO_TABLE:
248 case COMBIOS_OEM_INFO_TABLE:
251 case COMBIOS_DYN_CLK_2_TABLE:
254 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
257 case COMBIOS_I2C_INFO_TABLE:
260 /* relative offset tables */
261 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
263 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
265 rev = RBIOS8(check_offset);
267 check_offset = RBIOS16(check_offset + 0x3);
269 offset = check_offset;
273 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
275 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
277 rev = RBIOS8(check_offset);
279 check_offset = RBIOS16(check_offset + 0x5);
281 offset = check_offset;
285 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
287 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
289 rev = RBIOS8(check_offset);
291 check_offset = RBIOS16(check_offset + 0x7);
293 offset = check_offset;
297 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
299 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
301 rev = RBIOS8(check_offset);
303 check_offset = RBIOS16(check_offset + 0x9);
305 offset = check_offset;
309 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
311 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
313 while (RBIOS8(check_offset++));
316 offset = check_offset;
319 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
321 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
323 check_offset = RBIOS16(check_offset + 0x11);
325 offset = check_offset;
328 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
330 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
332 check_offset = RBIOS16(check_offset + 0x13);
334 offset = check_offset;
337 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
339 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
341 check_offset = RBIOS16(check_offset + 0x15);
343 offset = check_offset;
346 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
348 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
350 check_offset = RBIOS16(check_offset + 0x17);
352 offset = check_offset;
355 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
357 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
359 check_offset = RBIOS16(check_offset + 0x2);
361 offset = check_offset;
364 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
366 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
368 check_offset = RBIOS16(check_offset + 0x4);
370 offset = check_offset;
378 size = RBIOS8(rdev->bios_header_start + 0x6);
379 /* check absolute offset tables */
380 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
381 offset = RBIOS16(rdev->bios_header_start + check_offset);
386 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
391 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
395 raw = rdev->bios + edid_info;
396 size = EDID_LENGTH * (raw[0x7e] + 1);
397 edid = kmalloc(size, GFP_KERNEL);
401 memcpy((unsigned char *)edid, raw, size);
403 if (!drm_edid_is_valid(edid)) {
408 rdev->mode_info.bios_hardcoded_edid = edid;
409 rdev->mode_info.bios_hardcoded_edid_size = size;
413 /* this is used for atom LCDs as well */
415 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
419 if (rdev->mode_info.bios_hardcoded_edid) {
420 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
422 memcpy((unsigned char *)edid,
423 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
424 rdev->mode_info.bios_hardcoded_edid_size);
431 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
432 enum radeon_combios_ddc ddc,
436 struct radeon_i2c_bus_rec i2c;
440 * DDC_NONE_DETECTED = none
441 * DDC_DVI = RADEON_GPIO_DVI_DDC
442 * DDC_VGA = RADEON_GPIO_VGA_DDC
443 * DDC_LCD = RADEON_GPIOPAD_MASK
444 * DDC_GPIO = RADEON_MDGPIO_MASK
446 * DDC_MONID = RADEON_GPIO_MONID
447 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
449 * DDC_MONID = RADEON_GPIO_MONID
450 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
452 * DDC_MONID = RADEON_GPIO_DVI_DDC
453 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
455 * DDC_MONID = RADEON_GPIO_MONID
456 * DDC_CRT2 = RADEON_GPIO_MONID
458 * DDC_MONID = RADEON_GPIOPAD_MASK
459 * DDC_CRT2 = RADEON_GPIO_MONID
462 case DDC_NONE_DETECTED:
467 ddc_line = RADEON_GPIO_DVI_DDC;
470 ddc_line = RADEON_GPIO_VGA_DDC;
473 ddc_line = RADEON_GPIOPAD_MASK;
476 ddc_line = RADEON_MDGPIO_MASK;
479 if (rdev->family == CHIP_RS300 ||
480 rdev->family == CHIP_RS400 ||
481 rdev->family == CHIP_RS480)
482 ddc_line = RADEON_GPIOPAD_MASK;
483 else if (rdev->family == CHIP_R300 ||
484 rdev->family == CHIP_R350) {
485 ddc_line = RADEON_GPIO_DVI_DDC;
488 ddc_line = RADEON_GPIO_MONID;
491 if (rdev->family == CHIP_R200 ||
492 rdev->family == CHIP_R300 ||
493 rdev->family == CHIP_R350) {
494 ddc_line = RADEON_GPIO_DVI_DDC;
496 } else if (rdev->family == CHIP_RS300 ||
497 rdev->family == CHIP_RS400 ||
498 rdev->family == CHIP_RS480)
499 ddc_line = RADEON_GPIO_MONID;
500 else if (rdev->family >= CHIP_RV350) {
501 ddc_line = RADEON_GPIO_MONID;
504 ddc_line = RADEON_GPIO_CRT2_DDC;
508 if (ddc_line == RADEON_GPIOPAD_MASK) {
509 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
510 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
511 i2c.a_clk_reg = RADEON_GPIOPAD_A;
512 i2c.a_data_reg = RADEON_GPIOPAD_A;
513 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
514 i2c.en_data_reg = RADEON_GPIOPAD_EN;
515 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
516 i2c.y_data_reg = RADEON_GPIOPAD_Y;
517 } else if (ddc_line == RADEON_MDGPIO_MASK) {
518 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
519 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
520 i2c.a_clk_reg = RADEON_MDGPIO_A;
521 i2c.a_data_reg = RADEON_MDGPIO_A;
522 i2c.en_clk_reg = RADEON_MDGPIO_EN;
523 i2c.en_data_reg = RADEON_MDGPIO_EN;
524 i2c.y_clk_reg = RADEON_MDGPIO_Y;
525 i2c.y_data_reg = RADEON_MDGPIO_Y;
527 i2c.mask_clk_reg = ddc_line;
528 i2c.mask_data_reg = ddc_line;
529 i2c.a_clk_reg = ddc_line;
530 i2c.a_data_reg = ddc_line;
531 i2c.en_clk_reg = ddc_line;
532 i2c.en_data_reg = ddc_line;
533 i2c.y_clk_reg = ddc_line;
534 i2c.y_data_reg = ddc_line;
537 if (clk_mask && data_mask) {
538 /* system specific masks */
539 i2c.mask_clk_mask = clk_mask;
540 i2c.mask_data_mask = data_mask;
541 i2c.a_clk_mask = clk_mask;
542 i2c.a_data_mask = data_mask;
543 i2c.en_clk_mask = clk_mask;
544 i2c.en_data_mask = data_mask;
545 i2c.y_clk_mask = clk_mask;
546 i2c.y_data_mask = data_mask;
547 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
548 (ddc_line == RADEON_MDGPIO_MASK)) {
549 /* default gpiopad masks */
550 i2c.mask_clk_mask = (0x20 << 8);
551 i2c.mask_data_mask = 0x80;
552 i2c.a_clk_mask = (0x20 << 8);
553 i2c.a_data_mask = 0x80;
554 i2c.en_clk_mask = (0x20 << 8);
555 i2c.en_data_mask = 0x80;
556 i2c.y_clk_mask = (0x20 << 8);
557 i2c.y_data_mask = 0x80;
559 /* default masks for ddc pads */
560 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
561 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
562 i2c.a_clk_mask = RADEON_GPIO_A_1;
563 i2c.a_data_mask = RADEON_GPIO_A_0;
564 i2c.en_clk_mask = RADEON_GPIO_EN_1;
565 i2c.en_data_mask = RADEON_GPIO_EN_0;
566 i2c.y_clk_mask = RADEON_GPIO_Y_1;
567 i2c.y_data_mask = RADEON_GPIO_Y_0;
570 switch (rdev->family) {
578 case RADEON_GPIO_DVI_DDC:
579 i2c.hw_capable = true;
582 i2c.hw_capable = false;
588 case RADEON_GPIO_DVI_DDC:
589 case RADEON_GPIO_MONID:
590 i2c.hw_capable = true;
593 i2c.hw_capable = false;
600 case RADEON_GPIO_VGA_DDC:
601 case RADEON_GPIO_DVI_DDC:
602 case RADEON_GPIO_CRT2_DDC:
603 i2c.hw_capable = true;
606 i2c.hw_capable = false;
613 case RADEON_GPIO_VGA_DDC:
614 case RADEON_GPIO_DVI_DDC:
615 i2c.hw_capable = true;
618 i2c.hw_capable = false;
627 case RADEON_GPIO_VGA_DDC:
628 case RADEON_GPIO_DVI_DDC:
629 i2c.hw_capable = true;
631 case RADEON_GPIO_MONID:
632 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
633 * reliably on some pre-r4xx hardware; not sure why.
635 i2c.hw_capable = false;
638 i2c.hw_capable = false;
643 i2c.hw_capable = false;
649 i2c.hpd = RADEON_HPD_NONE;
659 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
661 struct drm_device *dev = rdev->ddev;
662 struct radeon_i2c_bus_rec i2c;
664 u8 id, blocks, clk, data;
669 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
671 blocks = RBIOS8(offset + 2);
672 for (i = 0; i < blocks; i++) {
673 id = RBIOS8(offset + 3 + (i * 5) + 0);
675 clk = RBIOS8(offset + 3 + (i * 5) + 3);
676 data = RBIOS8(offset + 3 + (i * 5) + 4);
678 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
679 (1 << clk), (1 << data));
687 void radeon_combios_i2c_init(struct radeon_device *rdev)
689 struct drm_device *dev = rdev->ddev;
690 struct radeon_i2c_bus_rec i2c;
694 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
696 * 0x60, 0x64, 0x68, mm
700 * 0x60, 0x64, 0x68, gpiopads, mm
704 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
705 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
707 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
708 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
712 i2c.hw_capable = true;
715 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
717 if (rdev->family == CHIP_R300 ||
718 rdev->family == CHIP_R350) {
719 /* only 2 sw i2c pads */
720 } else if (rdev->family == CHIP_RS300 ||
721 rdev->family == CHIP_RS400 ||
722 rdev->family == CHIP_RS480) {
724 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
725 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
728 i2c = radeon_combios_get_i2c_info_from_table(rdev);
730 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
731 } else if ((rdev->family == CHIP_R200) ||
732 (rdev->family >= CHIP_R300)) {
734 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
735 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
738 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
739 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
741 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
742 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
746 bool radeon_combios_get_clock_info(struct drm_device *dev)
748 struct radeon_device *rdev = dev->dev_private;
750 struct radeon_pll *p1pll = &rdev->clock.p1pll;
751 struct radeon_pll *p2pll = &rdev->clock.p2pll;
752 struct radeon_pll *spll = &rdev->clock.spll;
753 struct radeon_pll *mpll = &rdev->clock.mpll;
757 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
759 rev = RBIOS8(pll_info);
762 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
763 p1pll->reference_div = RBIOS16(pll_info + 0x10);
764 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
765 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
766 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
767 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
770 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
771 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
773 p1pll->pll_in_min = 40;
774 p1pll->pll_in_max = 500;
779 spll->reference_freq = RBIOS16(pll_info + 0x1a);
780 spll->reference_div = RBIOS16(pll_info + 0x1c);
781 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
782 spll->pll_out_max = RBIOS32(pll_info + 0x22);
785 spll->pll_in_min = RBIOS32(pll_info + 0x48);
786 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
789 spll->pll_in_min = 40;
790 spll->pll_in_max = 500;
794 mpll->reference_freq = RBIOS16(pll_info + 0x26);
795 mpll->reference_div = RBIOS16(pll_info + 0x28);
796 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
797 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
800 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
801 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
804 mpll->pll_in_min = 40;
805 mpll->pll_in_max = 500;
808 /* default sclk/mclk */
809 sclk = RBIOS16(pll_info + 0xa);
810 mclk = RBIOS16(pll_info + 0x8);
816 rdev->clock.default_sclk = sclk;
817 rdev->clock.default_mclk = mclk;
819 if (RBIOS32(pll_info + 0x16))
820 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
822 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
829 bool radeon_combios_sideport_present(struct radeon_device *rdev)
831 struct drm_device *dev = rdev->ddev;
834 /* sideport is AMD only */
835 if (rdev->family == CHIP_RS400)
838 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
841 if (RBIOS16(igp_info + 0x4))
847 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
848 0x00000808, /* r100 */
849 0x00000808, /* rv100 */
850 0x00000808, /* rs100 */
851 0x00000808, /* rv200 */
852 0x00000808, /* rs200 */
853 0x00000808, /* r200 */
854 0x00000808, /* rv250 */
855 0x00000000, /* rs300 */
856 0x00000808, /* rv280 */
857 0x00000808, /* r300 */
858 0x00000808, /* r350 */
859 0x00000808, /* rv350 */
860 0x00000808, /* rv380 */
861 0x00000808, /* r420 */
862 0x00000808, /* r423 */
863 0x00000808, /* rv410 */
864 0x00000000, /* rs400 */
865 0x00000000, /* rs480 */
868 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
869 struct radeon_encoder_primary_dac *p_dac)
871 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
875 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
879 struct drm_device *dev = encoder->base.dev;
880 struct radeon_device *rdev = dev->dev_private;
882 uint8_t rev, bg, dac;
883 struct radeon_encoder_primary_dac *p_dac = NULL;
886 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
892 /* check CRT table */
893 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
895 rev = RBIOS8(dac_info) & 0x3;
897 bg = RBIOS8(dac_info + 0x2) & 0xf;
898 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
899 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
901 bg = RBIOS8(dac_info + 0x2) & 0xf;
902 dac = RBIOS8(dac_info + 0x3) & 0xf;
903 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
905 /* if the values are zeros, use the table */
906 if ((dac == 0) || (bg == 0))
913 /* Radeon 7000 (RV100) */
914 if (((dev->pdev->device == 0x5159) &&
915 (dev->pdev->subsystem_vendor == 0x174B) &&
916 (dev->pdev->subsystem_device == 0x7c28)) ||
917 /* Radeon 9100 (R200) */
918 ((dev->pdev->device == 0x514D) &&
919 (dev->pdev->subsystem_vendor == 0x174B) &&
920 (dev->pdev->subsystem_device == 0x7149))) {
921 /* vbios value is bad, use the default */
925 if (!found) /* fallback to defaults */
926 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
932 radeon_combios_get_tv_info(struct radeon_device *rdev)
934 struct drm_device *dev = rdev->ddev;
936 enum radeon_tv_std tv_std = TV_STD_NTSC;
938 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
940 if (RBIOS8(tv_info + 6) == 'T') {
941 switch (RBIOS8(tv_info + 7) & 0xf) {
943 tv_std = TV_STD_NTSC;
944 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
948 DRM_DEBUG_KMS("Default TV standard: PAL\n");
951 tv_std = TV_STD_PAL_M;
952 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
955 tv_std = TV_STD_PAL_60;
956 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
959 tv_std = TV_STD_NTSC_J;
960 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
963 tv_std = TV_STD_SCART_PAL;
964 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
967 tv_std = TV_STD_NTSC;
969 ("Unknown TV standard; defaulting to NTSC\n");
973 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
975 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
978 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
981 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
984 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
994 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
995 0x00000000, /* r100 */
996 0x00280000, /* rv100 */
997 0x00000000, /* rs100 */
998 0x00880000, /* rv200 */
999 0x00000000, /* rs200 */
1000 0x00000000, /* r200 */
1001 0x00770000, /* rv250 */
1002 0x00290000, /* rs300 */
1003 0x00560000, /* rv280 */
1004 0x00780000, /* r300 */
1005 0x00770000, /* r350 */
1006 0x00780000, /* rv350 */
1007 0x00780000, /* rv380 */
1008 0x01080000, /* r420 */
1009 0x01080000, /* r423 */
1010 0x01080000, /* rv410 */
1011 0x00780000, /* rs400 */
1012 0x00780000, /* rs480 */
1015 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1016 struct radeon_encoder_tv_dac *tv_dac)
1018 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1019 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1020 tv_dac->ps2_tvdac_adj = 0x00880000;
1021 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1022 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1026 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1030 struct drm_device *dev = encoder->base.dev;
1031 struct radeon_device *rdev = dev->dev_private;
1033 uint8_t rev, bg, dac;
1034 struct radeon_encoder_tv_dac *tv_dac = NULL;
1037 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1041 /* first check TV table */
1042 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1044 rev = RBIOS8(dac_info + 0x3);
1046 bg = RBIOS8(dac_info + 0xc) & 0xf;
1047 dac = RBIOS8(dac_info + 0xd) & 0xf;
1048 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1050 bg = RBIOS8(dac_info + 0xe) & 0xf;
1051 dac = RBIOS8(dac_info + 0xf) & 0xf;
1052 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1054 bg = RBIOS8(dac_info + 0x10) & 0xf;
1055 dac = RBIOS8(dac_info + 0x11) & 0xf;
1056 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1057 /* if the values are all zeros, use the table */
1058 if (tv_dac->ps2_tvdac_adj)
1060 } else if (rev > 1) {
1061 bg = RBIOS8(dac_info + 0xc) & 0xf;
1062 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1063 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1065 bg = RBIOS8(dac_info + 0xd) & 0xf;
1066 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1067 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1069 bg = RBIOS8(dac_info + 0xe) & 0xf;
1070 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1071 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1072 /* if the values are all zeros, use the table */
1073 if (tv_dac->ps2_tvdac_adj)
1076 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1079 /* then check CRT table */
1081 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1083 rev = RBIOS8(dac_info) & 0x3;
1085 bg = RBIOS8(dac_info + 0x3) & 0xf;
1086 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1087 tv_dac->ps2_tvdac_adj =
1088 (bg << 16) | (dac << 20);
1089 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1090 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1091 /* if the values are all zeros, use the table */
1092 if (tv_dac->ps2_tvdac_adj)
1095 bg = RBIOS8(dac_info + 0x4) & 0xf;
1096 dac = RBIOS8(dac_info + 0x5) & 0xf;
1097 tv_dac->ps2_tvdac_adj =
1098 (bg << 16) | (dac << 20);
1099 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1100 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1101 /* if the values are all zeros, use the table */
1102 if (tv_dac->ps2_tvdac_adj)
1106 DRM_INFO("No TV DAC info found in BIOS\n");
1110 if (!found) /* fallback to defaults */
1111 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1116 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1120 struct radeon_encoder_lvds *lvds = NULL;
1121 uint32_t fp_vert_stretch, fp_horz_stretch;
1122 uint32_t ppll_div_sel, ppll_val;
1123 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1125 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1130 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1131 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1133 /* These should be fail-safe defaults, fingers crossed */
1134 lvds->panel_pwr_delay = 200;
1135 lvds->panel_vcc_delay = 2000;
1137 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1138 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1139 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1141 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1142 lvds->native_mode.vdisplay =
1143 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1144 RADEON_VERT_PANEL_SHIFT) + 1;
1146 lvds->native_mode.vdisplay =
1147 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1149 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1150 lvds->native_mode.hdisplay =
1151 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1152 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1154 lvds->native_mode.hdisplay =
1155 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1157 if ((lvds->native_mode.hdisplay < 640) ||
1158 (lvds->native_mode.vdisplay < 480)) {
1159 lvds->native_mode.hdisplay = 640;
1160 lvds->native_mode.vdisplay = 480;
1163 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1164 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1165 if ((ppll_val & 0x000707ff) == 0x1bb)
1166 lvds->use_bios_dividers = false;
1168 lvds->panel_ref_divider =
1169 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1170 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1171 lvds->panel_fb_divider = ppll_val & 0x7ff;
1173 if ((lvds->panel_ref_divider != 0) &&
1174 (lvds->panel_fb_divider > 3))
1175 lvds->use_bios_dividers = true;
1177 lvds->panel_vcc_delay = 200;
1179 DRM_INFO("Panel info derived from registers\n");
1180 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1181 lvds->native_mode.vdisplay);
1186 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1189 struct drm_device *dev = encoder->base.dev;
1190 struct radeon_device *rdev = dev->dev_private;
1192 uint32_t panel_setup;
1195 struct radeon_encoder_lvds *lvds = NULL;
1197 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1200 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1205 for (i = 0; i < 24; i++)
1206 stmp[i] = RBIOS8(lcd_info + i + 1);
1209 DRM_INFO("Panel ID String: %s\n", stmp);
1211 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1212 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1214 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1215 lvds->native_mode.vdisplay);
1217 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1218 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1220 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1221 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1222 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1224 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1225 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1226 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1227 if ((lvds->panel_ref_divider != 0) &&
1228 (lvds->panel_fb_divider > 3))
1229 lvds->use_bios_dividers = true;
1231 panel_setup = RBIOS32(lcd_info + 0x39);
1232 lvds->lvds_gen_cntl = 0xff00;
1233 if (panel_setup & 0x1)
1234 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1236 if ((panel_setup >> 4) & 0x1)
1237 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1239 switch ((panel_setup >> 8) & 0x7) {
1241 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1244 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1247 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1253 if ((panel_setup >> 16) & 0x1)
1254 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1256 if ((panel_setup >> 17) & 0x1)
1257 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1259 if ((panel_setup >> 18) & 0x1)
1260 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1262 if ((panel_setup >> 23) & 0x1)
1263 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1265 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1267 for (i = 0; i < 32; i++) {
1268 tmp = RBIOS16(lcd_info + 64 + i * 2);
1272 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1273 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1274 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1276 if (hss > lvds->native_mode.hdisplay)
1279 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1280 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1281 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1283 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1284 (RBIOS8(tmp + 23) * 8);
1286 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1287 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1288 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1289 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1290 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1291 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1293 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1294 lvds->native_mode.flags = 0;
1295 /* set crtc values */
1296 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1301 DRM_INFO("No panel info found in BIOS\n");
1302 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1306 encoder->native_mode = lvds->native_mode;
1310 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1311 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1312 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1313 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1314 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1315 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1316 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1317 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1318 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1319 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1320 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1321 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1322 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1323 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1324 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1325 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1326 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1327 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1328 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1331 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1332 struct radeon_encoder_int_tmds *tmds)
1334 struct drm_device *dev = encoder->base.dev;
1335 struct radeon_device *rdev = dev->dev_private;
1338 for (i = 0; i < 4; i++) {
1339 tmds->tmds_pll[i].value =
1340 default_tmds_pll[rdev->family][i].value;
1341 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1347 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1348 struct radeon_encoder_int_tmds *tmds)
1350 struct drm_device *dev = encoder->base.dev;
1351 struct radeon_device *rdev = dev->dev_private;
1356 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1359 ver = RBIOS8(tmds_info);
1360 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1362 n = RBIOS8(tmds_info + 5) + 1;
1365 for (i = 0; i < n; i++) {
1366 tmds->tmds_pll[i].value =
1367 RBIOS32(tmds_info + i * 10 + 0x08);
1368 tmds->tmds_pll[i].freq =
1369 RBIOS16(tmds_info + i * 10 + 0x10);
1370 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1371 tmds->tmds_pll[i].freq,
1372 tmds->tmds_pll[i].value);
1374 } else if (ver == 4) {
1376 n = RBIOS8(tmds_info + 5) + 1;
1379 for (i = 0; i < n; i++) {
1380 tmds->tmds_pll[i].value =
1381 RBIOS32(tmds_info + stride + 0x08);
1382 tmds->tmds_pll[i].freq =
1383 RBIOS16(tmds_info + stride + 0x10);
1388 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1389 tmds->tmds_pll[i].freq,
1390 tmds->tmds_pll[i].value);
1394 DRM_INFO("No TMDS info found in BIOS\n");
1400 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1401 struct radeon_encoder_ext_tmds *tmds)
1403 struct drm_device *dev = encoder->base.dev;
1404 struct radeon_device *rdev = dev->dev_private;
1405 struct radeon_i2c_bus_rec i2c_bus;
1407 /* default for macs */
1408 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1409 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1411 /* XXX some macs have duallink chips */
1412 switch (rdev->mode_info.connector_table) {
1413 case CT_POWERBOOK_EXTERNAL:
1414 case CT_MINI_EXTERNAL:
1416 tmds->dvo_chip = DVO_SIL164;
1417 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1424 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1425 struct radeon_encoder_ext_tmds *tmds)
1427 struct drm_device *dev = encoder->base.dev;
1428 struct radeon_device *rdev = dev->dev_private;
1431 enum radeon_combios_ddc gpio;
1432 struct radeon_i2c_bus_rec i2c_bus;
1434 tmds->i2c_bus = NULL;
1435 if (rdev->flags & RADEON_IS_IGP) {
1436 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1437 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1438 tmds->dvo_chip = DVO_SIL164;
1439 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1441 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1443 ver = RBIOS8(offset);
1444 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1445 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1446 tmds->slave_addr >>= 1; /* 7 bit addressing */
1447 gpio = RBIOS8(offset + 4 + 3);
1448 if (gpio == DDC_LCD) {
1450 i2c_bus.valid = true;
1451 i2c_bus.hw_capable = true;
1452 i2c_bus.mm_i2c = true;
1453 i2c_bus.i2c_id = 0xa0;
1455 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1456 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1460 if (!tmds->i2c_bus) {
1461 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1468 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1470 struct radeon_device *rdev = dev->dev_private;
1471 struct radeon_i2c_bus_rec ddc_i2c;
1472 struct radeon_hpd hpd;
1474 rdev->mode_info.connector_table = radeon_connector_table;
1475 if (rdev->mode_info.connector_table == CT_NONE) {
1476 #ifdef CONFIG_PPC_PMAC
1477 if (of_machine_is_compatible("PowerBook3,3")) {
1478 /* powerbook with VGA */
1479 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1480 } else if (of_machine_is_compatible("PowerBook3,4") ||
1481 of_machine_is_compatible("PowerBook3,5")) {
1482 /* powerbook with internal tmds */
1483 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1484 } else if (of_machine_is_compatible("PowerBook5,1") ||
1485 of_machine_is_compatible("PowerBook5,2") ||
1486 of_machine_is_compatible("PowerBook5,3") ||
1487 of_machine_is_compatible("PowerBook5,4") ||
1488 of_machine_is_compatible("PowerBook5,5")) {
1489 /* powerbook with external single link tmds (sil164) */
1490 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1491 } else if (of_machine_is_compatible("PowerBook5,6")) {
1492 /* powerbook with external dual or single link tmds */
1493 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1494 } else if (of_machine_is_compatible("PowerBook5,7") ||
1495 of_machine_is_compatible("PowerBook5,8") ||
1496 of_machine_is_compatible("PowerBook5,9")) {
1497 /* PowerBook6,2 ? */
1498 /* powerbook with external dual link tmds (sil1178?) */
1499 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1500 } else if (of_machine_is_compatible("PowerBook4,1") ||
1501 of_machine_is_compatible("PowerBook4,2") ||
1502 of_machine_is_compatible("PowerBook4,3") ||
1503 of_machine_is_compatible("PowerBook6,3") ||
1504 of_machine_is_compatible("PowerBook6,5") ||
1505 of_machine_is_compatible("PowerBook6,7")) {
1507 rdev->mode_info.connector_table = CT_IBOOK;
1508 } else if (of_machine_is_compatible("PowerMac3,5")) {
1509 /* PowerMac G4 Silver radeon 7500 */
1510 rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1511 } else if (of_machine_is_compatible("PowerMac4,4")) {
1513 rdev->mode_info.connector_table = CT_EMAC;
1514 } else if (of_machine_is_compatible("PowerMac10,1")) {
1515 /* mini with internal tmds */
1516 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1517 } else if (of_machine_is_compatible("PowerMac10,2")) {
1518 /* mini with external tmds */
1519 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1520 } else if (of_machine_is_compatible("PowerMac12,1")) {
1522 /* imac g5 isight */
1523 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1524 } else if ((rdev->pdev->device == 0x4a48) &&
1525 (rdev->pdev->subsystem_vendor == 0x1002) &&
1526 (rdev->pdev->subsystem_device == 0x4a48)) {
1528 rdev->mode_info.connector_table = CT_MAC_X800;
1529 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1530 of_machine_is_compatible("PowerMac7,3")) &&
1531 (rdev->pdev->device == 0x4150) &&
1532 (rdev->pdev->subsystem_vendor == 0x1002) &&
1533 (rdev->pdev->subsystem_device == 0x4150)) {
1534 /* Mac G5 tower 9600 */
1535 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1536 } else if ((rdev->pdev->device == 0x4c66) &&
1537 (rdev->pdev->subsystem_vendor == 0x1002) &&
1538 (rdev->pdev->subsystem_device == 0x4c66)) {
1539 /* SAM440ep RV250 embedded board */
1540 rdev->mode_info.connector_table = CT_SAM440EP;
1542 #endif /* CONFIG_PPC_PMAC */
1544 if (ASIC_IS_RN50(rdev))
1545 rdev->mode_info.connector_table = CT_RN50_POWER;
1548 rdev->mode_info.connector_table = CT_GENERIC;
1551 switch (rdev->mode_info.connector_table) {
1553 DRM_INFO("Connector Table: %d (generic)\n",
1554 rdev->mode_info.connector_table);
1555 /* these are the most common settings */
1556 if (rdev->flags & RADEON_SINGLE_CRTC) {
1557 /* VGA - primary dac */
1558 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1559 hpd.hpd = RADEON_HPD_NONE;
1560 radeon_add_legacy_encoder(dev,
1561 radeon_get_encoder_enum(dev,
1562 ATOM_DEVICE_CRT1_SUPPORT,
1564 ATOM_DEVICE_CRT1_SUPPORT);
1565 radeon_add_legacy_connector(dev, 0,
1566 ATOM_DEVICE_CRT1_SUPPORT,
1567 DRM_MODE_CONNECTOR_VGA,
1569 CONNECTOR_OBJECT_ID_VGA,
1571 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1573 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1574 hpd.hpd = RADEON_HPD_NONE;
1575 radeon_add_legacy_encoder(dev,
1576 radeon_get_encoder_enum(dev,
1577 ATOM_DEVICE_LCD1_SUPPORT,
1579 ATOM_DEVICE_LCD1_SUPPORT);
1580 radeon_add_legacy_connector(dev, 0,
1581 ATOM_DEVICE_LCD1_SUPPORT,
1582 DRM_MODE_CONNECTOR_LVDS,
1584 CONNECTOR_OBJECT_ID_LVDS,
1587 /* VGA - primary dac */
1588 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1589 hpd.hpd = RADEON_HPD_NONE;
1590 radeon_add_legacy_encoder(dev,
1591 radeon_get_encoder_enum(dev,
1592 ATOM_DEVICE_CRT1_SUPPORT,
1594 ATOM_DEVICE_CRT1_SUPPORT);
1595 radeon_add_legacy_connector(dev, 1,
1596 ATOM_DEVICE_CRT1_SUPPORT,
1597 DRM_MODE_CONNECTOR_VGA,
1599 CONNECTOR_OBJECT_ID_VGA,
1602 /* DVI-I - tv dac, int tmds */
1603 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1604 hpd.hpd = RADEON_HPD_1;
1605 radeon_add_legacy_encoder(dev,
1606 radeon_get_encoder_enum(dev,
1607 ATOM_DEVICE_DFP1_SUPPORT,
1609 ATOM_DEVICE_DFP1_SUPPORT);
1610 radeon_add_legacy_encoder(dev,
1611 radeon_get_encoder_enum(dev,
1612 ATOM_DEVICE_CRT2_SUPPORT,
1614 ATOM_DEVICE_CRT2_SUPPORT);
1615 radeon_add_legacy_connector(dev, 0,
1616 ATOM_DEVICE_DFP1_SUPPORT |
1617 ATOM_DEVICE_CRT2_SUPPORT,
1618 DRM_MODE_CONNECTOR_DVII,
1620 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1623 /* VGA - primary dac */
1624 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1625 hpd.hpd = RADEON_HPD_NONE;
1626 radeon_add_legacy_encoder(dev,
1627 radeon_get_encoder_enum(dev,
1628 ATOM_DEVICE_CRT1_SUPPORT,
1630 ATOM_DEVICE_CRT1_SUPPORT);
1631 radeon_add_legacy_connector(dev, 1,
1632 ATOM_DEVICE_CRT1_SUPPORT,
1633 DRM_MODE_CONNECTOR_VGA,
1635 CONNECTOR_OBJECT_ID_VGA,
1639 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1641 ddc_i2c.valid = false;
1642 hpd.hpd = RADEON_HPD_NONE;
1643 radeon_add_legacy_encoder(dev,
1644 radeon_get_encoder_enum(dev,
1645 ATOM_DEVICE_TV1_SUPPORT,
1647 ATOM_DEVICE_TV1_SUPPORT);
1648 radeon_add_legacy_connector(dev, 2,
1649 ATOM_DEVICE_TV1_SUPPORT,
1650 DRM_MODE_CONNECTOR_SVIDEO,
1652 CONNECTOR_OBJECT_ID_SVIDEO,
1657 DRM_INFO("Connector Table: %d (ibook)\n",
1658 rdev->mode_info.connector_table);
1660 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1661 hpd.hpd = RADEON_HPD_NONE;
1662 radeon_add_legacy_encoder(dev,
1663 radeon_get_encoder_enum(dev,
1664 ATOM_DEVICE_LCD1_SUPPORT,
1666 ATOM_DEVICE_LCD1_SUPPORT);
1667 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1668 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1669 CONNECTOR_OBJECT_ID_LVDS,
1672 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1673 hpd.hpd = RADEON_HPD_NONE;
1674 radeon_add_legacy_encoder(dev,
1675 radeon_get_encoder_enum(dev,
1676 ATOM_DEVICE_CRT2_SUPPORT,
1678 ATOM_DEVICE_CRT2_SUPPORT);
1679 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1680 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1681 CONNECTOR_OBJECT_ID_VGA,
1684 ddc_i2c.valid = false;
1685 hpd.hpd = RADEON_HPD_NONE;
1686 radeon_add_legacy_encoder(dev,
1687 radeon_get_encoder_enum(dev,
1688 ATOM_DEVICE_TV1_SUPPORT,
1690 ATOM_DEVICE_TV1_SUPPORT);
1691 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1692 DRM_MODE_CONNECTOR_SVIDEO,
1694 CONNECTOR_OBJECT_ID_SVIDEO,
1697 case CT_POWERBOOK_EXTERNAL:
1698 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1699 rdev->mode_info.connector_table);
1701 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1702 hpd.hpd = RADEON_HPD_NONE;
1703 radeon_add_legacy_encoder(dev,
1704 radeon_get_encoder_enum(dev,
1705 ATOM_DEVICE_LCD1_SUPPORT,
1707 ATOM_DEVICE_LCD1_SUPPORT);
1708 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1709 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1710 CONNECTOR_OBJECT_ID_LVDS,
1712 /* DVI-I - primary dac, ext tmds */
1713 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1714 hpd.hpd = RADEON_HPD_2; /* ??? */
1715 radeon_add_legacy_encoder(dev,
1716 radeon_get_encoder_enum(dev,
1717 ATOM_DEVICE_DFP2_SUPPORT,
1719 ATOM_DEVICE_DFP2_SUPPORT);
1720 radeon_add_legacy_encoder(dev,
1721 radeon_get_encoder_enum(dev,
1722 ATOM_DEVICE_CRT1_SUPPORT,
1724 ATOM_DEVICE_CRT1_SUPPORT);
1725 /* XXX some are SL */
1726 radeon_add_legacy_connector(dev, 1,
1727 ATOM_DEVICE_DFP2_SUPPORT |
1728 ATOM_DEVICE_CRT1_SUPPORT,
1729 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1730 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1733 ddc_i2c.valid = false;
1734 hpd.hpd = RADEON_HPD_NONE;
1735 radeon_add_legacy_encoder(dev,
1736 radeon_get_encoder_enum(dev,
1737 ATOM_DEVICE_TV1_SUPPORT,
1739 ATOM_DEVICE_TV1_SUPPORT);
1740 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1741 DRM_MODE_CONNECTOR_SVIDEO,
1743 CONNECTOR_OBJECT_ID_SVIDEO,
1746 case CT_POWERBOOK_INTERNAL:
1747 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1748 rdev->mode_info.connector_table);
1750 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1751 hpd.hpd = RADEON_HPD_NONE;
1752 radeon_add_legacy_encoder(dev,
1753 radeon_get_encoder_enum(dev,
1754 ATOM_DEVICE_LCD1_SUPPORT,
1756 ATOM_DEVICE_LCD1_SUPPORT);
1757 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1758 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1759 CONNECTOR_OBJECT_ID_LVDS,
1761 /* DVI-I - primary dac, int tmds */
1762 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1763 hpd.hpd = RADEON_HPD_1; /* ??? */
1764 radeon_add_legacy_encoder(dev,
1765 radeon_get_encoder_enum(dev,
1766 ATOM_DEVICE_DFP1_SUPPORT,
1768 ATOM_DEVICE_DFP1_SUPPORT);
1769 radeon_add_legacy_encoder(dev,
1770 radeon_get_encoder_enum(dev,
1771 ATOM_DEVICE_CRT1_SUPPORT,
1773 ATOM_DEVICE_CRT1_SUPPORT);
1774 radeon_add_legacy_connector(dev, 1,
1775 ATOM_DEVICE_DFP1_SUPPORT |
1776 ATOM_DEVICE_CRT1_SUPPORT,
1777 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1778 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1781 ddc_i2c.valid = false;
1782 hpd.hpd = RADEON_HPD_NONE;
1783 radeon_add_legacy_encoder(dev,
1784 radeon_get_encoder_enum(dev,
1785 ATOM_DEVICE_TV1_SUPPORT,
1787 ATOM_DEVICE_TV1_SUPPORT);
1788 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1789 DRM_MODE_CONNECTOR_SVIDEO,
1791 CONNECTOR_OBJECT_ID_SVIDEO,
1794 case CT_POWERBOOK_VGA:
1795 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1796 rdev->mode_info.connector_table);
1798 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1799 hpd.hpd = RADEON_HPD_NONE;
1800 radeon_add_legacy_encoder(dev,
1801 radeon_get_encoder_enum(dev,
1802 ATOM_DEVICE_LCD1_SUPPORT,
1804 ATOM_DEVICE_LCD1_SUPPORT);
1805 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1806 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1807 CONNECTOR_OBJECT_ID_LVDS,
1809 /* VGA - primary dac */
1810 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1811 hpd.hpd = RADEON_HPD_NONE;
1812 radeon_add_legacy_encoder(dev,
1813 radeon_get_encoder_enum(dev,
1814 ATOM_DEVICE_CRT1_SUPPORT,
1816 ATOM_DEVICE_CRT1_SUPPORT);
1817 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1818 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1819 CONNECTOR_OBJECT_ID_VGA,
1822 ddc_i2c.valid = false;
1823 hpd.hpd = RADEON_HPD_NONE;
1824 radeon_add_legacy_encoder(dev,
1825 radeon_get_encoder_enum(dev,
1826 ATOM_DEVICE_TV1_SUPPORT,
1828 ATOM_DEVICE_TV1_SUPPORT);
1829 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1830 DRM_MODE_CONNECTOR_SVIDEO,
1832 CONNECTOR_OBJECT_ID_SVIDEO,
1835 case CT_MINI_EXTERNAL:
1836 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1837 rdev->mode_info.connector_table);
1838 /* DVI-I - tv dac, ext tmds */
1839 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1840 hpd.hpd = RADEON_HPD_2; /* ??? */
1841 radeon_add_legacy_encoder(dev,
1842 radeon_get_encoder_enum(dev,
1843 ATOM_DEVICE_DFP2_SUPPORT,
1845 ATOM_DEVICE_DFP2_SUPPORT);
1846 radeon_add_legacy_encoder(dev,
1847 radeon_get_encoder_enum(dev,
1848 ATOM_DEVICE_CRT2_SUPPORT,
1850 ATOM_DEVICE_CRT2_SUPPORT);
1851 /* XXX are any DL? */
1852 radeon_add_legacy_connector(dev, 0,
1853 ATOM_DEVICE_DFP2_SUPPORT |
1854 ATOM_DEVICE_CRT2_SUPPORT,
1855 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1856 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1859 ddc_i2c.valid = false;
1860 hpd.hpd = RADEON_HPD_NONE;
1861 radeon_add_legacy_encoder(dev,
1862 radeon_get_encoder_enum(dev,
1863 ATOM_DEVICE_TV1_SUPPORT,
1865 ATOM_DEVICE_TV1_SUPPORT);
1866 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1867 DRM_MODE_CONNECTOR_SVIDEO,
1869 CONNECTOR_OBJECT_ID_SVIDEO,
1872 case CT_MINI_INTERNAL:
1873 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1874 rdev->mode_info.connector_table);
1875 /* DVI-I - tv dac, int tmds */
1876 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1877 hpd.hpd = RADEON_HPD_1; /* ??? */
1878 radeon_add_legacy_encoder(dev,
1879 radeon_get_encoder_enum(dev,
1880 ATOM_DEVICE_DFP1_SUPPORT,
1882 ATOM_DEVICE_DFP1_SUPPORT);
1883 radeon_add_legacy_encoder(dev,
1884 radeon_get_encoder_enum(dev,
1885 ATOM_DEVICE_CRT2_SUPPORT,
1887 ATOM_DEVICE_CRT2_SUPPORT);
1888 radeon_add_legacy_connector(dev, 0,
1889 ATOM_DEVICE_DFP1_SUPPORT |
1890 ATOM_DEVICE_CRT2_SUPPORT,
1891 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1892 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1895 ddc_i2c.valid = false;
1896 hpd.hpd = RADEON_HPD_NONE;
1897 radeon_add_legacy_encoder(dev,
1898 radeon_get_encoder_enum(dev,
1899 ATOM_DEVICE_TV1_SUPPORT,
1901 ATOM_DEVICE_TV1_SUPPORT);
1902 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1903 DRM_MODE_CONNECTOR_SVIDEO,
1905 CONNECTOR_OBJECT_ID_SVIDEO,
1908 case CT_IMAC_G5_ISIGHT:
1909 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1910 rdev->mode_info.connector_table);
1911 /* DVI-D - int tmds */
1912 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1913 hpd.hpd = RADEON_HPD_1; /* ??? */
1914 radeon_add_legacy_encoder(dev,
1915 radeon_get_encoder_enum(dev,
1916 ATOM_DEVICE_DFP1_SUPPORT,
1918 ATOM_DEVICE_DFP1_SUPPORT);
1919 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1920 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1921 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1924 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1925 hpd.hpd = RADEON_HPD_NONE;
1926 radeon_add_legacy_encoder(dev,
1927 radeon_get_encoder_enum(dev,
1928 ATOM_DEVICE_CRT2_SUPPORT,
1930 ATOM_DEVICE_CRT2_SUPPORT);
1931 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1932 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1933 CONNECTOR_OBJECT_ID_VGA,
1936 ddc_i2c.valid = false;
1937 hpd.hpd = RADEON_HPD_NONE;
1938 radeon_add_legacy_encoder(dev,
1939 radeon_get_encoder_enum(dev,
1940 ATOM_DEVICE_TV1_SUPPORT,
1942 ATOM_DEVICE_TV1_SUPPORT);
1943 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1944 DRM_MODE_CONNECTOR_SVIDEO,
1946 CONNECTOR_OBJECT_ID_SVIDEO,
1950 DRM_INFO("Connector Table: %d (emac)\n",
1951 rdev->mode_info.connector_table);
1952 /* VGA - primary dac */
1953 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1954 hpd.hpd = RADEON_HPD_NONE;
1955 radeon_add_legacy_encoder(dev,
1956 radeon_get_encoder_enum(dev,
1957 ATOM_DEVICE_CRT1_SUPPORT,
1959 ATOM_DEVICE_CRT1_SUPPORT);
1960 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1961 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1962 CONNECTOR_OBJECT_ID_VGA,
1965 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1966 hpd.hpd = RADEON_HPD_NONE;
1967 radeon_add_legacy_encoder(dev,
1968 radeon_get_encoder_enum(dev,
1969 ATOM_DEVICE_CRT2_SUPPORT,
1971 ATOM_DEVICE_CRT2_SUPPORT);
1972 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1973 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1974 CONNECTOR_OBJECT_ID_VGA,
1977 ddc_i2c.valid = false;
1978 hpd.hpd = RADEON_HPD_NONE;
1979 radeon_add_legacy_encoder(dev,
1980 radeon_get_encoder_enum(dev,
1981 ATOM_DEVICE_TV1_SUPPORT,
1983 ATOM_DEVICE_TV1_SUPPORT);
1984 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1985 DRM_MODE_CONNECTOR_SVIDEO,
1987 CONNECTOR_OBJECT_ID_SVIDEO,
1991 DRM_INFO("Connector Table: %d (rn50-power)\n",
1992 rdev->mode_info.connector_table);
1993 /* VGA - primary dac */
1994 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1995 hpd.hpd = RADEON_HPD_NONE;
1996 radeon_add_legacy_encoder(dev,
1997 radeon_get_encoder_enum(dev,
1998 ATOM_DEVICE_CRT1_SUPPORT,
2000 ATOM_DEVICE_CRT1_SUPPORT);
2001 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2002 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2003 CONNECTOR_OBJECT_ID_VGA,
2005 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2006 hpd.hpd = RADEON_HPD_NONE;
2007 radeon_add_legacy_encoder(dev,
2008 radeon_get_encoder_enum(dev,
2009 ATOM_DEVICE_CRT2_SUPPORT,
2011 ATOM_DEVICE_CRT2_SUPPORT);
2012 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2013 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2014 CONNECTOR_OBJECT_ID_VGA,
2018 DRM_INFO("Connector Table: %d (mac x800)\n",
2019 rdev->mode_info.connector_table);
2020 /* DVI - primary dac, internal tmds */
2021 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2022 hpd.hpd = RADEON_HPD_1; /* ??? */
2023 radeon_add_legacy_encoder(dev,
2024 radeon_get_encoder_enum(dev,
2025 ATOM_DEVICE_DFP1_SUPPORT,
2027 ATOM_DEVICE_DFP1_SUPPORT);
2028 radeon_add_legacy_encoder(dev,
2029 radeon_get_encoder_enum(dev,
2030 ATOM_DEVICE_CRT1_SUPPORT,
2032 ATOM_DEVICE_CRT1_SUPPORT);
2033 radeon_add_legacy_connector(dev, 0,
2034 ATOM_DEVICE_DFP1_SUPPORT |
2035 ATOM_DEVICE_CRT1_SUPPORT,
2036 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2037 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2039 /* DVI - tv dac, dvo */
2040 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2041 hpd.hpd = RADEON_HPD_2; /* ??? */
2042 radeon_add_legacy_encoder(dev,
2043 radeon_get_encoder_enum(dev,
2044 ATOM_DEVICE_DFP2_SUPPORT,
2046 ATOM_DEVICE_DFP2_SUPPORT);
2047 radeon_add_legacy_encoder(dev,
2048 radeon_get_encoder_enum(dev,
2049 ATOM_DEVICE_CRT2_SUPPORT,
2051 ATOM_DEVICE_CRT2_SUPPORT);
2052 radeon_add_legacy_connector(dev, 1,
2053 ATOM_DEVICE_DFP2_SUPPORT |
2054 ATOM_DEVICE_CRT2_SUPPORT,
2055 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2056 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2059 case CT_MAC_G5_9600:
2060 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2061 rdev->mode_info.connector_table);
2062 /* DVI - tv dac, dvo */
2063 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2064 hpd.hpd = RADEON_HPD_1; /* ??? */
2065 radeon_add_legacy_encoder(dev,
2066 radeon_get_encoder_enum(dev,
2067 ATOM_DEVICE_DFP2_SUPPORT,
2069 ATOM_DEVICE_DFP2_SUPPORT);
2070 radeon_add_legacy_encoder(dev,
2071 radeon_get_encoder_enum(dev,
2072 ATOM_DEVICE_CRT2_SUPPORT,
2074 ATOM_DEVICE_CRT2_SUPPORT);
2075 radeon_add_legacy_connector(dev, 0,
2076 ATOM_DEVICE_DFP2_SUPPORT |
2077 ATOM_DEVICE_CRT2_SUPPORT,
2078 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2079 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2081 /* ADC - primary dac, internal tmds */
2082 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2083 hpd.hpd = RADEON_HPD_2; /* ??? */
2084 radeon_add_legacy_encoder(dev,
2085 radeon_get_encoder_enum(dev,
2086 ATOM_DEVICE_DFP1_SUPPORT,
2088 ATOM_DEVICE_DFP1_SUPPORT);
2089 radeon_add_legacy_encoder(dev,
2090 radeon_get_encoder_enum(dev,
2091 ATOM_DEVICE_CRT1_SUPPORT,
2093 ATOM_DEVICE_CRT1_SUPPORT);
2094 radeon_add_legacy_connector(dev, 1,
2095 ATOM_DEVICE_DFP1_SUPPORT |
2096 ATOM_DEVICE_CRT1_SUPPORT,
2097 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2098 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2101 ddc_i2c.valid = false;
2102 hpd.hpd = RADEON_HPD_NONE;
2103 radeon_add_legacy_encoder(dev,
2104 radeon_get_encoder_enum(dev,
2105 ATOM_DEVICE_TV1_SUPPORT,
2107 ATOM_DEVICE_TV1_SUPPORT);
2108 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2109 DRM_MODE_CONNECTOR_SVIDEO,
2111 CONNECTOR_OBJECT_ID_SVIDEO,
2115 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2116 rdev->mode_info.connector_table);
2118 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2119 hpd.hpd = RADEON_HPD_NONE;
2120 radeon_add_legacy_encoder(dev,
2121 radeon_get_encoder_enum(dev,
2122 ATOM_DEVICE_LCD1_SUPPORT,
2124 ATOM_DEVICE_LCD1_SUPPORT);
2125 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2126 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2127 CONNECTOR_OBJECT_ID_LVDS,
2129 /* DVI-I - secondary dac, int tmds */
2130 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2131 hpd.hpd = RADEON_HPD_1; /* ??? */
2132 radeon_add_legacy_encoder(dev,
2133 radeon_get_encoder_enum(dev,
2134 ATOM_DEVICE_DFP1_SUPPORT,
2136 ATOM_DEVICE_DFP1_SUPPORT);
2137 radeon_add_legacy_encoder(dev,
2138 radeon_get_encoder_enum(dev,
2139 ATOM_DEVICE_CRT2_SUPPORT,
2141 ATOM_DEVICE_CRT2_SUPPORT);
2142 radeon_add_legacy_connector(dev, 1,
2143 ATOM_DEVICE_DFP1_SUPPORT |
2144 ATOM_DEVICE_CRT2_SUPPORT,
2145 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2146 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2148 /* VGA - primary dac */
2149 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2150 hpd.hpd = RADEON_HPD_NONE;
2151 radeon_add_legacy_encoder(dev,
2152 radeon_get_encoder_enum(dev,
2153 ATOM_DEVICE_CRT1_SUPPORT,
2155 ATOM_DEVICE_CRT1_SUPPORT);
2156 radeon_add_legacy_connector(dev, 2,
2157 ATOM_DEVICE_CRT1_SUPPORT,
2158 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2159 CONNECTOR_OBJECT_ID_VGA,
2162 ddc_i2c.valid = false;
2163 hpd.hpd = RADEON_HPD_NONE;
2164 radeon_add_legacy_encoder(dev,
2165 radeon_get_encoder_enum(dev,
2166 ATOM_DEVICE_TV1_SUPPORT,
2168 ATOM_DEVICE_TV1_SUPPORT);
2169 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2170 DRM_MODE_CONNECTOR_SVIDEO,
2172 CONNECTOR_OBJECT_ID_SVIDEO,
2175 case CT_MAC_G4_SILVER:
2176 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2177 rdev->mode_info.connector_table);
2178 /* DVI-I - tv dac, int tmds */
2179 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2180 hpd.hpd = RADEON_HPD_1; /* ??? */
2181 radeon_add_legacy_encoder(dev,
2182 radeon_get_encoder_enum(dev,
2183 ATOM_DEVICE_DFP1_SUPPORT,
2185 ATOM_DEVICE_DFP1_SUPPORT);
2186 radeon_add_legacy_encoder(dev,
2187 radeon_get_encoder_enum(dev,
2188 ATOM_DEVICE_CRT2_SUPPORT,
2190 ATOM_DEVICE_CRT2_SUPPORT);
2191 radeon_add_legacy_connector(dev, 0,
2192 ATOM_DEVICE_DFP1_SUPPORT |
2193 ATOM_DEVICE_CRT2_SUPPORT,
2194 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2195 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2197 /* VGA - primary dac */
2198 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2199 hpd.hpd = RADEON_HPD_NONE;
2200 radeon_add_legacy_encoder(dev,
2201 radeon_get_encoder_enum(dev,
2202 ATOM_DEVICE_CRT1_SUPPORT,
2204 ATOM_DEVICE_CRT1_SUPPORT);
2205 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2206 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2207 CONNECTOR_OBJECT_ID_VGA,
2210 ddc_i2c.valid = false;
2211 hpd.hpd = RADEON_HPD_NONE;
2212 radeon_add_legacy_encoder(dev,
2213 radeon_get_encoder_enum(dev,
2214 ATOM_DEVICE_TV1_SUPPORT,
2216 ATOM_DEVICE_TV1_SUPPORT);
2217 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2218 DRM_MODE_CONNECTOR_SVIDEO,
2220 CONNECTOR_OBJECT_ID_SVIDEO,
2224 DRM_INFO("Connector table: %d (invalid)\n",
2225 rdev->mode_info.connector_table);
2229 radeon_link_encoder_connector(dev);
2234 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2236 enum radeon_combios_connector
2238 struct radeon_i2c_bus_rec *ddc_i2c,
2239 struct radeon_hpd *hpd)
2242 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2243 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2244 if (dev->pdev->device == 0x515e &&
2245 dev->pdev->subsystem_vendor == 0x1014) {
2246 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2247 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2251 /* X300 card with extra non-existent DVI port */
2252 if (dev->pdev->device == 0x5B60 &&
2253 dev->pdev->subsystem_vendor == 0x17af &&
2254 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2255 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2262 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2264 /* Acer 5102 has non-existent TV port */
2265 if (dev->pdev->device == 0x5975 &&
2266 dev->pdev->subsystem_vendor == 0x1025 &&
2267 dev->pdev->subsystem_device == 0x009f)
2270 /* HP dc5750 has non-existent TV port */
2271 if (dev->pdev->device == 0x5974 &&
2272 dev->pdev->subsystem_vendor == 0x103c &&
2273 dev->pdev->subsystem_device == 0x280a)
2276 /* MSI S270 has non-existent TV port */
2277 if (dev->pdev->device == 0x5955 &&
2278 dev->pdev->subsystem_vendor == 0x1462 &&
2279 dev->pdev->subsystem_device == 0x0131)
2285 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2287 struct radeon_device *rdev = dev->dev_private;
2288 uint32_t ext_tmds_info;
2290 if (rdev->flags & RADEON_IS_IGP) {
2292 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2294 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2296 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2297 if (ext_tmds_info) {
2298 uint8_t rev = RBIOS8(ext_tmds_info);
2299 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2302 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2304 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2308 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2310 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2315 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2317 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2320 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2322 struct radeon_device *rdev = dev->dev_private;
2323 uint32_t conn_info, entry, devices;
2324 uint16_t tmp, connector_object_id;
2325 enum radeon_combios_ddc ddc_type;
2326 enum radeon_combios_connector connector;
2328 struct radeon_i2c_bus_rec ddc_i2c;
2329 struct radeon_hpd hpd;
2331 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2333 for (i = 0; i < 4; i++) {
2334 entry = conn_info + 2 + i * 2;
2336 if (!RBIOS16(entry))
2339 tmp = RBIOS16(entry);
2341 connector = (tmp >> 12) & 0xf;
2343 ddc_type = (tmp >> 8) & 0xf;
2345 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2347 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2349 switch (connector) {
2350 case CONNECTOR_PROPRIETARY_LEGACY:
2351 case CONNECTOR_DVI_I_LEGACY:
2352 case CONNECTOR_DVI_D_LEGACY:
2353 if ((tmp >> 4) & 0x1)
2354 hpd.hpd = RADEON_HPD_2;
2356 hpd.hpd = RADEON_HPD_1;
2359 hpd.hpd = RADEON_HPD_NONE;
2363 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2367 switch (connector) {
2368 case CONNECTOR_PROPRIETARY_LEGACY:
2369 if ((tmp >> 4) & 0x1)
2370 devices = ATOM_DEVICE_DFP2_SUPPORT;
2372 devices = ATOM_DEVICE_DFP1_SUPPORT;
2373 radeon_add_legacy_encoder(dev,
2374 radeon_get_encoder_enum
2377 radeon_add_legacy_connector(dev, i, devices,
2378 legacy_connector_convert
2381 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2384 case CONNECTOR_CRT_LEGACY:
2386 devices = ATOM_DEVICE_CRT2_SUPPORT;
2387 radeon_add_legacy_encoder(dev,
2388 radeon_get_encoder_enum
2390 ATOM_DEVICE_CRT2_SUPPORT,
2392 ATOM_DEVICE_CRT2_SUPPORT);
2394 devices = ATOM_DEVICE_CRT1_SUPPORT;
2395 radeon_add_legacy_encoder(dev,
2396 radeon_get_encoder_enum
2398 ATOM_DEVICE_CRT1_SUPPORT,
2400 ATOM_DEVICE_CRT1_SUPPORT);
2402 radeon_add_legacy_connector(dev,
2405 legacy_connector_convert
2408 CONNECTOR_OBJECT_ID_VGA,
2411 case CONNECTOR_DVI_I_LEGACY:
2414 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2415 radeon_add_legacy_encoder(dev,
2416 radeon_get_encoder_enum
2418 ATOM_DEVICE_CRT2_SUPPORT,
2420 ATOM_DEVICE_CRT2_SUPPORT);
2422 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2423 radeon_add_legacy_encoder(dev,
2424 radeon_get_encoder_enum
2426 ATOM_DEVICE_CRT1_SUPPORT,
2428 ATOM_DEVICE_CRT1_SUPPORT);
2430 /* RV100 board with external TDMS bit mis-set.
2431 * Actually uses internal TMDS, clear the bit.
2433 if (dev->pdev->device == 0x5159 &&
2434 dev->pdev->subsystem_vendor == 0x1014 &&
2435 dev->pdev->subsystem_device == 0x029A) {
2438 if ((tmp >> 4) & 0x1) {
2439 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2440 radeon_add_legacy_encoder(dev,
2441 radeon_get_encoder_enum
2443 ATOM_DEVICE_DFP2_SUPPORT,
2445 ATOM_DEVICE_DFP2_SUPPORT);
2446 connector_object_id = combios_check_dl_dvi(dev, 0);
2448 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2449 radeon_add_legacy_encoder(dev,
2450 radeon_get_encoder_enum
2452 ATOM_DEVICE_DFP1_SUPPORT,
2454 ATOM_DEVICE_DFP1_SUPPORT);
2455 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2457 radeon_add_legacy_connector(dev,
2460 legacy_connector_convert
2463 connector_object_id,
2466 case CONNECTOR_DVI_D_LEGACY:
2467 if ((tmp >> 4) & 0x1) {
2468 devices = ATOM_DEVICE_DFP2_SUPPORT;
2469 connector_object_id = combios_check_dl_dvi(dev, 1);
2471 devices = ATOM_DEVICE_DFP1_SUPPORT;
2472 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2474 radeon_add_legacy_encoder(dev,
2475 radeon_get_encoder_enum
2478 radeon_add_legacy_connector(dev, i, devices,
2479 legacy_connector_convert
2482 connector_object_id,
2485 case CONNECTOR_CTV_LEGACY:
2486 case CONNECTOR_STV_LEGACY:
2487 radeon_add_legacy_encoder(dev,
2488 radeon_get_encoder_enum
2490 ATOM_DEVICE_TV1_SUPPORT,
2492 ATOM_DEVICE_TV1_SUPPORT);
2493 radeon_add_legacy_connector(dev, i,
2494 ATOM_DEVICE_TV1_SUPPORT,
2495 legacy_connector_convert
2498 CONNECTOR_OBJECT_ID_SVIDEO,
2502 DRM_ERROR("Unknown connector type: %d\n",
2509 uint16_t tmds_info =
2510 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2512 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2514 radeon_add_legacy_encoder(dev,
2515 radeon_get_encoder_enum(dev,
2516 ATOM_DEVICE_CRT1_SUPPORT,
2518 ATOM_DEVICE_CRT1_SUPPORT);
2519 radeon_add_legacy_encoder(dev,
2520 radeon_get_encoder_enum(dev,
2521 ATOM_DEVICE_DFP1_SUPPORT,
2523 ATOM_DEVICE_DFP1_SUPPORT);
2525 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2526 hpd.hpd = RADEON_HPD_1;
2527 radeon_add_legacy_connector(dev,
2529 ATOM_DEVICE_CRT1_SUPPORT |
2530 ATOM_DEVICE_DFP1_SUPPORT,
2531 DRM_MODE_CONNECTOR_DVII,
2533 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2537 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2538 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2540 radeon_add_legacy_encoder(dev,
2541 radeon_get_encoder_enum(dev,
2542 ATOM_DEVICE_CRT1_SUPPORT,
2544 ATOM_DEVICE_CRT1_SUPPORT);
2545 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2546 hpd.hpd = RADEON_HPD_NONE;
2547 radeon_add_legacy_connector(dev,
2549 ATOM_DEVICE_CRT1_SUPPORT,
2550 DRM_MODE_CONNECTOR_VGA,
2552 CONNECTOR_OBJECT_ID_VGA,
2555 DRM_DEBUG_KMS("No connector info found\n");
2561 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2563 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2565 uint16_t lcd_ddc_info =
2566 combios_get_table_offset(dev,
2567 COMBIOS_LCD_DDC_INFO_TABLE);
2569 radeon_add_legacy_encoder(dev,
2570 radeon_get_encoder_enum(dev,
2571 ATOM_DEVICE_LCD1_SUPPORT,
2573 ATOM_DEVICE_LCD1_SUPPORT);
2576 ddc_type = RBIOS8(lcd_ddc_info + 2);
2580 combios_setup_i2c_bus(rdev,
2582 RBIOS32(lcd_ddc_info + 3),
2583 RBIOS32(lcd_ddc_info + 7));
2584 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2588 combios_setup_i2c_bus(rdev,
2590 RBIOS32(lcd_ddc_info + 3),
2591 RBIOS32(lcd_ddc_info + 7));
2592 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2596 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2599 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2601 ddc_i2c.valid = false;
2603 hpd.hpd = RADEON_HPD_NONE;
2604 radeon_add_legacy_connector(dev,
2606 ATOM_DEVICE_LCD1_SUPPORT,
2607 DRM_MODE_CONNECTOR_LVDS,
2609 CONNECTOR_OBJECT_ID_LVDS,
2614 /* check TV table */
2615 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2617 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2619 if (RBIOS8(tv_info + 6) == 'T') {
2620 if (radeon_apply_legacy_tv_quirks(dev)) {
2621 hpd.hpd = RADEON_HPD_NONE;
2622 ddc_i2c.valid = false;
2623 radeon_add_legacy_encoder(dev,
2624 radeon_get_encoder_enum
2626 ATOM_DEVICE_TV1_SUPPORT,
2628 ATOM_DEVICE_TV1_SUPPORT);
2629 radeon_add_legacy_connector(dev, 6,
2630 ATOM_DEVICE_TV1_SUPPORT,
2631 DRM_MODE_CONNECTOR_SVIDEO,
2633 CONNECTOR_OBJECT_ID_SVIDEO,
2640 radeon_link_encoder_connector(dev);
2645 static const char *thermal_controller_names[] = {
2651 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2653 struct drm_device *dev = rdev->ddev;
2654 u16 offset, misc, misc2 = 0;
2655 u8 rev, blocks, tmp;
2656 int state_index = 0;
2657 struct radeon_i2c_bus_rec i2c_bus;
2659 rdev->pm.default_power_state_index = -1;
2661 /* allocate 2 power states */
2662 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2663 if (rdev->pm.power_state) {
2664 /* allocate 1 clock mode per state */
2665 rdev->pm.power_state[0].clock_info =
2666 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2667 rdev->pm.power_state[1].clock_info =
2668 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2669 if (!rdev->pm.power_state[0].clock_info ||
2670 !rdev->pm.power_state[1].clock_info)
2675 /* check for a thermal chip */
2676 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2678 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2680 rev = RBIOS8(offset);
2683 thermal_controller = RBIOS8(offset + 3);
2684 gpio = RBIOS8(offset + 4) & 0x3f;
2685 i2c_addr = RBIOS8(offset + 5);
2686 } else if (rev == 1) {
2687 thermal_controller = RBIOS8(offset + 4);
2688 gpio = RBIOS8(offset + 5) & 0x3f;
2689 i2c_addr = RBIOS8(offset + 6);
2690 } else if (rev == 2) {
2691 thermal_controller = RBIOS8(offset + 4);
2692 gpio = RBIOS8(offset + 5) & 0x3f;
2693 i2c_addr = RBIOS8(offset + 6);
2694 clk_bit = RBIOS8(offset + 0xa);
2695 data_bit = RBIOS8(offset + 0xb);
2697 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2698 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2699 thermal_controller_names[thermal_controller],
2701 if (gpio == DDC_LCD) {
2703 i2c_bus.valid = true;
2704 i2c_bus.hw_capable = true;
2705 i2c_bus.mm_i2c = true;
2706 i2c_bus.i2c_id = 0xa0;
2707 } else if (gpio == DDC_GPIO)
2708 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2710 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2711 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2712 if (rdev->pm.i2c_bus) {
2713 struct i2c_board_info info = { };
2714 const char *name = thermal_controller_names[thermal_controller];
2715 info.addr = i2c_addr >> 1;
2716 strlcpy(info.type, name, sizeof(info.type));
2717 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2721 /* boards with a thermal chip, but no overdrive table */
2723 /* Asus 9600xt has an f75375 on the monid bus */
2724 if ((dev->pdev->device == 0x4152) &&
2725 (dev->pdev->subsystem_vendor == 0x1043) &&
2726 (dev->pdev->subsystem_device == 0xc002)) {
2727 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2728 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2729 if (rdev->pm.i2c_bus) {
2730 struct i2c_board_info info = { };
2731 const char *name = "f75375";
2733 strlcpy(info.type, name, sizeof(info.type));
2734 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2735 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2741 if (rdev->flags & RADEON_IS_MOBILITY) {
2742 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2744 rev = RBIOS8(offset);
2745 blocks = RBIOS8(offset + 0x2);
2746 /* power mode 0 tends to be the only valid one */
2747 rdev->pm.power_state[state_index].num_clock_modes = 1;
2748 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2749 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2750 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2751 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2753 rdev->pm.power_state[state_index].type =
2754 POWER_STATE_TYPE_BATTERY;
2755 misc = RBIOS16(offset + 0x5 + 0x0);
2757 misc2 = RBIOS16(offset + 0x5 + 0xe);
2758 rdev->pm.power_state[state_index].misc = misc;
2759 rdev->pm.power_state[state_index].misc2 = misc2;
2761 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2763 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2766 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2768 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2770 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2771 RBIOS16(offset + 0x5 + 0xb) * 4;
2772 tmp = RBIOS8(offset + 0x5 + 0xd);
2773 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2775 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2776 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2777 if (entries && voltage_table_offset) {
2778 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2779 RBIOS16(voltage_table_offset) * 4;
2780 tmp = RBIOS8(voltage_table_offset + 0x2);
2781 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2783 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2785 switch ((misc2 & 0x700) >> 8) {
2788 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2791 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2794 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2797 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2800 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2804 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2806 rdev->pm.power_state[state_index].pcie_lanes =
2807 RBIOS8(offset + 0x5 + 0x10);
2808 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2811 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2814 /* XXX figure out some good default low power mode for desktop cards */
2818 /* add the default mode */
2819 rdev->pm.power_state[state_index].type =
2820 POWER_STATE_TYPE_DEFAULT;
2821 rdev->pm.power_state[state_index].num_clock_modes = 1;
2822 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2823 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2824 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2825 if ((state_index > 0) &&
2826 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2827 rdev->pm.power_state[state_index].clock_info[0].voltage =
2828 rdev->pm.power_state[0].clock_info[0].voltage;
2830 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2831 rdev->pm.power_state[state_index].pcie_lanes = 16;
2832 rdev->pm.power_state[state_index].flags = 0;
2833 rdev->pm.default_power_state_index = state_index;
2834 rdev->pm.num_power_states = state_index + 1;
2836 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2837 rdev->pm.current_clock_mode_index = 0;
2841 rdev->pm.default_power_state_index = state_index;
2842 rdev->pm.num_power_states = 0;
2844 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2845 rdev->pm.current_clock_mode_index = 0;
2848 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2850 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2851 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2856 switch (tmds->dvo_chip) {
2859 radeon_i2c_put_byte(tmds->i2c_bus,
2862 radeon_i2c_put_byte(tmds->i2c_bus,
2865 radeon_i2c_put_byte(tmds->i2c_bus,
2868 radeon_i2c_put_byte(tmds->i2c_bus,
2871 radeon_i2c_put_byte(tmds->i2c_bus,
2876 /* sil 1178 - untested */
2895 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2897 struct drm_device *dev = encoder->dev;
2898 struct radeon_device *rdev = dev->dev_private;
2899 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2901 uint8_t blocks, slave_addr, rev;
2903 uint32_t reg, val, and_mask, or_mask;
2904 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2909 if (rdev->flags & RADEON_IS_IGP) {
2910 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2911 rev = RBIOS8(offset);
2913 rev = RBIOS8(offset);
2915 blocks = RBIOS8(offset + 3);
2917 while (blocks > 0) {
2918 id = RBIOS16(index);
2922 reg = (id & 0x1fff) * 4;
2923 val = RBIOS32(index);
2928 reg = (id & 0x1fff) * 4;
2929 and_mask = RBIOS32(index);
2931 or_mask = RBIOS32(index);
2934 val = (val & and_mask) | or_mask;
2938 val = RBIOS16(index);
2943 val = RBIOS16(index);
2948 slave_addr = id & 0xff;
2949 slave_addr >>= 1; /* 7 bit addressing */
2951 reg = RBIOS8(index);
2953 val = RBIOS8(index);
2955 radeon_i2c_put_byte(tmds->i2c_bus,
2960 DRM_ERROR("Unknown id %d\n", id >> 13);
2969 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2971 index = offset + 10;
2972 id = RBIOS16(index);
2973 while (id != 0xffff) {
2977 reg = (id & 0x1fff) * 4;
2978 val = RBIOS32(index);
2982 reg = (id & 0x1fff) * 4;
2983 and_mask = RBIOS32(index);
2985 or_mask = RBIOS32(index);
2988 val = (val & and_mask) | or_mask;
2992 val = RBIOS16(index);
2998 and_mask = RBIOS32(index);
3000 or_mask = RBIOS32(index);
3002 val = RREG32_PLL(reg);
3003 val = (val & and_mask) | or_mask;
3004 WREG32_PLL(reg, val);
3008 val = RBIOS8(index);
3010 radeon_i2c_put_byte(tmds->i2c_bus,
3015 DRM_ERROR("Unknown id %d\n", id >> 13);
3018 id = RBIOS16(index);
3026 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3028 struct radeon_device *rdev = dev->dev_private;
3031 while (RBIOS16(offset)) {
3032 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3033 uint32_t addr = (RBIOS16(offset) & 0x1fff);
3034 uint32_t val, and_mask, or_mask;
3040 val = RBIOS32(offset);
3045 val = RBIOS32(offset);
3050 and_mask = RBIOS32(offset);
3052 or_mask = RBIOS32(offset);
3060 and_mask = RBIOS32(offset);
3062 or_mask = RBIOS32(offset);
3070 val = RBIOS16(offset);
3075 val = RBIOS16(offset);
3082 (RADEON_CLK_PWRMGT_CNTL) &
3089 if ((RREG32(RADEON_MC_STATUS) &
3105 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3107 struct radeon_device *rdev = dev->dev_private;
3110 while (RBIOS8(offset)) {
3111 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3112 uint8_t addr = (RBIOS8(offset) & 0x3f);
3113 uint32_t val, shift, tmp;
3114 uint32_t and_mask, or_mask;
3119 val = RBIOS32(offset);
3121 WREG32_PLL(addr, val);
3124 shift = RBIOS8(offset) * 8;
3126 and_mask = RBIOS8(offset) << shift;
3127 and_mask |= ~(0xff << shift);
3129 or_mask = RBIOS8(offset) << shift;
3131 tmp = RREG32_PLL(addr);
3134 WREG32_PLL(addr, tmp);
3150 (RADEON_CLK_PWRMGT_CNTL) &
3158 (RADEON_CLK_PWRMGT_CNTL) &
3165 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3166 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3168 uint32_t mclk_cntl =
3171 mclk_cntl &= 0xffff0000;
3172 /*mclk_cntl |= 0x00001111;*//* ??? */
3173 WREG32_PLL(RADEON_MCLK_CNTL,
3178 (RADEON_CLK_PWRMGT_CNTL,
3180 ~RADEON_CG_NO1_DEBUG_0);
3195 static void combios_parse_ram_reset_table(struct drm_device *dev,
3198 struct radeon_device *rdev = dev->dev_private;
3202 uint8_t val = RBIOS8(offset);
3203 while (val != 0xff) {
3207 uint32_t channel_complete_mask;
3209 if (ASIC_IS_R300(rdev))
3210 channel_complete_mask =
3211 R300_MEM_PWRUP_COMPLETE;
3213 channel_complete_mask =
3214 RADEON_MEM_PWRUP_COMPLETE;
3217 if ((RREG32(RADEON_MEM_STR_CNTL) &
3218 channel_complete_mask) ==
3219 channel_complete_mask)
3223 uint32_t or_mask = RBIOS16(offset);
3226 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3227 tmp &= RADEON_SDRAM_MODE_MASK;
3229 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3231 or_mask = val << 24;
3232 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3233 tmp &= RADEON_B3MEM_RESET_MASK;
3235 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3237 val = RBIOS8(offset);
3242 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3243 int mem_addr_mapping)
3245 struct radeon_device *rdev = dev->dev_private;
3250 mem_cntl = RREG32(RADEON_MEM_CNTL);
3251 if (mem_cntl & RV100_HALF_MODE)
3254 mem_cntl &= ~(0xff << 8);
3255 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3256 WREG32(RADEON_MEM_CNTL, mem_cntl);
3257 RREG32(RADEON_MEM_CNTL);
3261 /* something like this???? */
3263 addr = ram * 1024 * 1024;
3264 /* write to each page */
3265 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3266 /* read back and verify */
3267 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3274 static void combios_write_ram_size(struct drm_device *dev)
3276 struct radeon_device *rdev = dev->dev_private;
3279 uint32_t mem_size = 0;
3280 uint32_t mem_cntl = 0;
3282 /* should do something smarter here I guess... */
3283 if (rdev->flags & RADEON_IS_IGP)
3286 /* first check detected mem table */
3287 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3289 rev = RBIOS8(offset);
3291 mem_cntl = RBIOS32(offset + 1);
3292 mem_size = RBIOS16(offset + 5);
3293 if ((rdev->family < CHIP_R200) &&
3294 !ASIC_IS_RN50(rdev))
3295 WREG32(RADEON_MEM_CNTL, mem_cntl);
3301 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3303 rev = RBIOS8(offset - 1);
3305 if ((rdev->family < CHIP_R200)
3306 && !ASIC_IS_RN50(rdev)) {
3308 int mem_addr_mapping = 0;
3310 while (RBIOS8(offset)) {
3311 ram = RBIOS8(offset);
3314 if (mem_addr_mapping != 0x25)
3317 combios_detect_ram(dev, ram,
3324 mem_size = RBIOS8(offset);
3326 mem_size = RBIOS8(offset);
3327 mem_size *= 2; /* convert to MB */
3332 mem_size *= (1024 * 1024); /* convert to bytes */
3333 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3336 void radeon_combios_asic_init(struct drm_device *dev)
3338 struct radeon_device *rdev = dev->dev_private;
3341 /* port hardcoded mac stuff from radeonfb */
3342 if (rdev->bios == NULL)
3346 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3348 combios_parse_mmio_table(dev, table);
3351 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3353 combios_parse_pll_table(dev, table);
3356 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3358 combios_parse_mmio_table(dev, table);
3360 if (!(rdev->flags & RADEON_IS_IGP)) {
3363 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3365 combios_parse_mmio_table(dev, table);
3368 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3370 combios_parse_ram_reset_table(dev, table);
3374 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3376 combios_parse_mmio_table(dev, table);
3378 /* write CONFIG_MEMSIZE */
3379 combios_write_ram_size(dev);
3382 /* quirk for rs4xx HP nx6125 laptop to make it resume
3383 * - it hangs on resume inside the dynclk 1 table.
3385 if (rdev->family == CHIP_RS480 &&
3386 rdev->pdev->subsystem_vendor == 0x103c &&
3387 rdev->pdev->subsystem_device == 0x308b)
3390 /* quirk for rs4xx HP dv5000 laptop to make it resume
3391 * - it hangs on resume inside the dynclk 1 table.
3393 if (rdev->family == CHIP_RS480 &&
3394 rdev->pdev->subsystem_vendor == 0x103c &&
3395 rdev->pdev->subsystem_device == 0x30a4)
3398 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3399 * - it hangs on resume inside the dynclk 1 table.
3401 if (rdev->family == CHIP_RS480 &&
3402 rdev->pdev->subsystem_vendor == 0x103c &&
3403 rdev->pdev->subsystem_device == 0x30ae)
3407 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3409 combios_parse_pll_table(dev, table);
3413 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3415 struct radeon_device *rdev = dev->dev_private;
3416 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3418 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3419 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3420 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3422 /* let the bios control the backlight */
3423 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3425 /* tell the bios not to handle mode switching */
3426 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3427 RADEON_ACC_MODE_CHANGE);
3429 /* tell the bios a driver is loaded */
3430 bios_7_scratch |= RADEON_DRV_LOADED;
3432 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3433 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3434 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3437 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3439 struct drm_device *dev = encoder->dev;
3440 struct radeon_device *rdev = dev->dev_private;
3441 uint32_t bios_6_scratch;
3443 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3446 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3448 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3450 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3454 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3455 struct drm_encoder *encoder,
3458 struct drm_device *dev = connector->dev;
3459 struct radeon_device *rdev = dev->dev_private;
3460 struct radeon_connector *radeon_connector =
3461 to_radeon_connector(connector);
3462 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3463 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3464 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3466 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3467 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3469 DRM_DEBUG_KMS("TV1 connected\n");
3471 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3472 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3473 bios_5_scratch |= RADEON_TV1_ON;
3474 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3476 DRM_DEBUG_KMS("TV1 disconnected\n");
3477 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3478 bios_5_scratch &= ~RADEON_TV1_ON;
3479 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3482 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3483 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3485 DRM_DEBUG_KMS("LCD1 connected\n");
3486 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3487 bios_5_scratch |= RADEON_LCD1_ON;
3488 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3490 DRM_DEBUG_KMS("LCD1 disconnected\n");
3491 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3492 bios_5_scratch &= ~RADEON_LCD1_ON;
3493 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3496 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3497 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3499 DRM_DEBUG_KMS("CRT1 connected\n");
3500 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3501 bios_5_scratch |= RADEON_CRT1_ON;
3502 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3504 DRM_DEBUG_KMS("CRT1 disconnected\n");
3505 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3506 bios_5_scratch &= ~RADEON_CRT1_ON;
3507 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3510 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3511 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3513 DRM_DEBUG_KMS("CRT2 connected\n");
3514 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3515 bios_5_scratch |= RADEON_CRT2_ON;
3516 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3518 DRM_DEBUG_KMS("CRT2 disconnected\n");
3519 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3520 bios_5_scratch &= ~RADEON_CRT2_ON;
3521 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3524 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3525 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3527 DRM_DEBUG_KMS("DFP1 connected\n");
3528 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3529 bios_5_scratch |= RADEON_DFP1_ON;
3530 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3532 DRM_DEBUG_KMS("DFP1 disconnected\n");
3533 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3534 bios_5_scratch &= ~RADEON_DFP1_ON;
3535 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3538 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3539 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3541 DRM_DEBUG_KMS("DFP2 connected\n");
3542 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3543 bios_5_scratch |= RADEON_DFP2_ON;
3544 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3546 DRM_DEBUG_KMS("DFP2 disconnected\n");
3547 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3548 bios_5_scratch &= ~RADEON_DFP2_ON;
3549 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3552 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3553 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3557 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3559 struct drm_device *dev = encoder->dev;
3560 struct radeon_device *rdev = dev->dev_private;
3561 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3562 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3564 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3565 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3566 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3568 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3569 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3570 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3572 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3573 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3574 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3576 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3577 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3578 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3580 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3581 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3582 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3584 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3585 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3586 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3588 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3592 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3594 struct drm_device *dev = encoder->dev;
3595 struct radeon_device *rdev = dev->dev_private;
3596 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3597 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3599 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3601 bios_6_scratch |= RADEON_TV_DPMS_ON;
3603 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3605 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3607 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3609 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3611 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3613 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3615 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3617 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3619 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3621 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3623 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);