drivers/gpu/drm/radeon/radeon_bios.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35 #include <linux/acpi.h>
  36 /*
  37  * BIOS.
  38  */
  39
  40 /* If you boot an IGP board with a discrete card as the primary,
  41  * the IGP rom is not accessible via the rom bar as the IGP rom is
  42  * part of the system bios.  On boot, the system bios puts a
  43  * copy of the igp rom at the start of vram if a discrete card is
  44  * present.
  45  */
  46 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  47 {
  48         uint8_t __iomem *bios;
  49         resource_size_t vram_base;
  50         resource_size_t size = 256 * 1024; /* ??? */
  51
  52         if (!(rdev->flags & RADEON_IS_IGP))
  53                 if (!radeon_card_posted(rdev))
  54                         return false;
  55
  56         rdev->bios = NULL;
  57         vram_base = pci_resource_start(rdev->pdev, 0);
  58         bios = ioremap(vram_base, size);
  59         if (!bios) {
  60                 return false;
  61         }
  62
  63         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  64                 iounmap(bios);
  65                 return false;
  66         }
  67         rdev->bios = kmalloc(size, GFP_KERNEL);
  68         if (rdev->bios == NULL) {
  69                 iounmap(bios);
  70                 return false;
  71         }
  72         memcpy_fromio(rdev->bios, bios, size);
  73         iounmap(bios);
  74         return true;
  75 }
  76
  77 static bool radeon_read_bios(struct radeon_device *rdev)
  78 {
  79         uint8_t __iomem *bios;
  80         size_t size;
  81
  82         rdev->bios = NULL;
  83         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  84         bios = pci_map_rom(rdev->pdev, &size);
  85         if (!bios) {
  86                 return false;
  87         }
  88
  89         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  90                 pci_unmap_rom(rdev->pdev, bios);
  91                 return false;
  92         }
  93         rdev->bios = kmemdup(bios, size, GFP_KERNEL);
  94         if (rdev->bios == NULL) {
  95                 pci_unmap_rom(rdev->pdev, bios);
  96                 return false;
  97         }
  98         pci_unmap_rom(rdev->pdev, bios);
  99         return true;
 100 }
 101
 102 #ifdef CONFIG_ACPI
 103 /* ATRM is used to get the BIOS on the discrete cards in
 104  * dual-gpu systems.
 105  */
 106 /* retrieve the ROM in 4k blocks */
 107 #define ATRM_BIOS_PAGE 4096
 108 /**
 109  * radeon_atrm_call - fetch a chunk of the vbios
 110  *
 111  * @atrm_handle: acpi ATRM handle
 112  * @bios: vbios image pointer
 113  * @offset: offset of vbios image data to fetch
 114  * @len: length of vbios image data to fetch
 115  *
 116  * Executes ATRM to fetch a chunk of the discrete
 117  * vbios image on PX systems (all asics).
 118  * Returns the length of the buffer fetched.
 119  */
 120 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
 121                             int offset, int len)
 122 {
 123         acpi_status status;
 124         union acpi_object atrm_arg_elements[2], *obj;
 125         struct acpi_object_list atrm_arg;
 126         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
 127
 128         atrm_arg.count = 2;
 129         atrm_arg.pointer = &atrm_arg_elements[0];
 130
 131         atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
 132         atrm_arg_elements[0].integer.value = offset;
 133
 134         atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
 135         atrm_arg_elements[1].integer.value = len;
 136
 137         status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
 138         if (ACPI_FAILURE(status)) {
 139                 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
 140                 return -ENODEV;
 141         }
 142
 143         obj = (union acpi_object *)buffer.pointer;
 144         memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
 145         len = obj->buffer.length;
 146         kfree(buffer.pointer);
 147         return len;
 148 }
 149
 150 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
 151 {
 152         int ret;
 153         int size = 256 * 1024;
 154         int i;
 155         struct pci_dev *pdev = NULL;
 156         acpi_handle dhandle, atrm_handle;
 157         acpi_status status;
 158         bool found = false;
 159
 160         /* ATRM is for the discrete card only */
 161         if (rdev->flags & RADEON_IS_IGP)
 162                 return false;
 163
 164         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
 165                 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
 166                 if (!dhandle)
 167                         continue;
 168
 169                 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
 170                 if (!ACPI_FAILURE(status)) {
 171                         found = true;
 172                         break;
 173                 }
 174         }
 175
 176         if (!found)
 177                 return false;
 178
 179         rdev->bios = kmalloc(size, GFP_KERNEL);
 180         if (!rdev->bios) {
 181                 DRM_ERROR("Unable to allocate bios\n");
 182                 return false;
 183         }
 184
 185         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
 186                 ret = radeon_atrm_call(atrm_handle,
 187                                        rdev->bios,
 188                                        (i * ATRM_BIOS_PAGE),
 189                                        ATRM_BIOS_PAGE);
 190                 if (ret < ATRM_BIOS_PAGE)
 191                         break;
 192         }
 193
 194         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 195                 kfree(rdev->bios);
 196                 return false;
 197         }
 198         return true;
 199 }
 200 #else
 201 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
 202 {
 203         return false;
 204 }
 205 #endif
 206
 207 static bool ni_read_disabled_bios(struct radeon_device *rdev)
 208 {
 209         u32 bus_cntl;
 210         u32 d1vga_control;
 211         u32 d2vga_control;
 212         u32 vga_render_control;
 213         u32 rom_cntl;
 214         bool r;
 215
 216         bus_cntl = RREG32(R600_BUS_CNTL);
 217         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 218         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 219         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 220         rom_cntl = RREG32(R600_ROM_CNTL);
 221
 222         /* enable the rom */
 223         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 224         if (!ASIC_IS_NODCE(rdev)) {
 225                 /* Disable VGA mode */
 226                 WREG32(AVIVO_D1VGA_CONTROL,
 227                        (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 228                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 229                 WREG32(AVIVO_D2VGA_CONTROL,
 230                        (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 231                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 232                 WREG32(AVIVO_VGA_RENDER_CONTROL,
 233                        (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 234         }
 235         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 236
 237         r = radeon_read_bios(rdev);
 238
 239         /* restore regs */
 240         WREG32(R600_BUS_CNTL, bus_cntl);
 241         if (!ASIC_IS_NODCE(rdev)) {
 242                 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 243                 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 244                 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 245         }
 246         WREG32(R600_ROM_CNTL, rom_cntl);
 247         return r;
 248 }
 249
 250 static bool r700_read_disabled_bios(struct radeon_device *rdev)
 251 {
 252         uint32_t viph_control;
 253         uint32_t bus_cntl;
 254         uint32_t d1vga_control;
 255         uint32_t d2vga_control;
 256         uint32_t vga_render_control;
 257         uint32_t rom_cntl;
 258         uint32_t cg_spll_func_cntl = 0;
 259         uint32_t cg_spll_status;
 260         bool r;
 261
 262         viph_control = RREG32(RADEON_VIPH_CONTROL);
 263         bus_cntl = RREG32(R600_BUS_CNTL);
 264         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 265         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 266         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 267         rom_cntl = RREG32(R600_ROM_CNTL);
 268
 269         /* disable VIP */
 270         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 271         /* enable the rom */
 272         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 273         /* Disable VGA mode */
 274         WREG32(AVIVO_D1VGA_CONTROL,
 275                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 276                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 277         WREG32(AVIVO_D2VGA_CONTROL,
 278                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 279                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 280         WREG32(AVIVO_VGA_RENDER_CONTROL,
 281                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 282
 283         if (rdev->family == CHIP_RV730) {
 284                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 285
 286                 /* enable bypass mode */
 287                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
 288                                                 R600_SPLL_BYPASS_EN));
 289
 290                 /* wait for SPLL_CHG_STATUS to change to 1 */
 291                 cg_spll_status = 0;
 292                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 293                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 294
 295                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
 296         } else
 297                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 298
 299         r = radeon_read_bios(rdev);
 300
 301         /* restore regs */
 302         if (rdev->family == CHIP_RV730) {
 303                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 304
 305                 /* wait for SPLL_CHG_STATUS to change to 1 */
 306                 cg_spll_status = 0;
 307                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 308                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 309         }
 310         WREG32(RADEON_VIPH_CONTROL, viph_control);
 311         WREG32(R600_BUS_CNTL, bus_cntl);
 312         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 313         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 314         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 315         WREG32(R600_ROM_CNTL, rom_cntl);
 316         return r;
 317 }
 318
 319 static bool r600_read_disabled_bios(struct radeon_device *rdev)
 320 {
 321         uint32_t viph_control;
 322         uint32_t bus_cntl;
 323         uint32_t d1vga_control;
 324         uint32_t d2vga_control;
 325         uint32_t vga_render_control;
 326         uint32_t rom_cntl;
 327         uint32_t general_pwrmgt;
 328         uint32_t low_vid_lower_gpio_cntl;
 329         uint32_t medium_vid_lower_gpio_cntl;
 330         uint32_t high_vid_lower_gpio_cntl;
 331         uint32_t ctxsw_vid_lower_gpio_cntl;
 332         uint32_t lower_gpio_enable;
 333         bool r;
 334
 335         viph_control = RREG32(RADEON_VIPH_CONTROL);
 336         bus_cntl = RREG32(R600_BUS_CNTL);
 337         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 338         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 339         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 340         rom_cntl = RREG32(R600_ROM_CNTL);
 341         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
 342         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
 343         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
 344         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
 345         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
 346         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 347
 348         /* disable VIP */
 349         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 350         /* enable the rom */
 351         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 352         /* Disable VGA mode */
 353         WREG32(AVIVO_D1VGA_CONTROL,
 354                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 355                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 356         WREG32(AVIVO_D2VGA_CONTROL,
 357                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 358                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 359         WREG32(AVIVO_VGA_RENDER_CONTROL,
 360                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 361
 362         WREG32(R600_ROM_CNTL,
 363                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
 364                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
 365                 R600_SCK_OVERWRITE));
 366
 367         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
 368         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
 369                (low_vid_lower_gpio_cntl & ~0x400));
 370         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
 371                (medium_vid_lower_gpio_cntl & ~0x400));
 372         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
 373                (high_vid_lower_gpio_cntl & ~0x400));
 374         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
 375                (ctxsw_vid_lower_gpio_cntl & ~0x400));
 376         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 377
 378         r = radeon_read_bios(rdev);
 379
 380         /* restore regs */
 381         WREG32(RADEON_VIPH_CONTROL, viph_control);
 382         WREG32(R600_BUS_CNTL, bus_cntl);
 383         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 384         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 385         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 386         WREG32(R600_ROM_CNTL, rom_cntl);
 387         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
 388         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
 389         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
 390         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
 391         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
 392         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
 393         return r;
 394 }
 395
 396 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 397 {
 398         uint32_t seprom_cntl1;
 399         uint32_t viph_control;
 400         uint32_t bus_cntl;
 401         uint32_t d1vga_control;
 402         uint32_t d2vga_control;
 403         uint32_t vga_render_control;
 404         uint32_t gpiopad_a;
 405         uint32_t gpiopad_en;
 406         uint32_t gpiopad_mask;
 407         bool r;
 408
 409         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 410         viph_control = RREG32(RADEON_VIPH_CONTROL);
 411         bus_cntl = RREG32(RV370_BUS_CNTL);
 412         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 413         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 414         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 415         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 416         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
 417         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 418
 419         WREG32(RADEON_SEPROM_CNTL1,
 420                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 421                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 422         WREG32(RADEON_GPIOPAD_A, 0);
 423         WREG32(RADEON_GPIOPAD_EN, 0);
 424         WREG32(RADEON_GPIOPAD_MASK, 0);
 425
 426         /* disable VIP */
 427         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 428
 429         /* enable the rom */
 430         WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 431
 432         /* Disable VGA mode */
 433         WREG32(AVIVO_D1VGA_CONTROL,
 434                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 435                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 436         WREG32(AVIVO_D2VGA_CONTROL,
 437                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 438                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 439         WREG32(AVIVO_VGA_RENDER_CONTROL,
 440                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 441
 442         r = radeon_read_bios(rdev);
 443
 444         /* restore regs */
 445         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 446         WREG32(RADEON_VIPH_CONTROL, viph_control);
 447         WREG32(RV370_BUS_CNTL, bus_cntl);
 448         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 449         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 450         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 451         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 452         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
 453         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
 454         return r;
 455 }
 456
 457 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 458 {
 459         uint32_t seprom_cntl1;
 460         uint32_t viph_control;
 461         uint32_t bus_cntl;
 462         uint32_t crtc_gen_cntl;
 463         uint32_t crtc2_gen_cntl;
 464         uint32_t crtc_ext_cntl;
 465         uint32_t fp2_gen_cntl;
 466         bool r;
 467
 468         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 469         viph_control = RREG32(RADEON_VIPH_CONTROL);
 470         if (rdev->flags & RADEON_IS_PCIE)
 471                 bus_cntl = RREG32(RV370_BUS_CNTL);
 472         else
 473                 bus_cntl = RREG32(RADEON_BUS_CNTL);
 474         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 475         crtc2_gen_cntl = 0;
 476         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 477         fp2_gen_cntl = 0;
 478
 479         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 480                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 481         }
 482
 483         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 484                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 485         }
 486
 487         WREG32(RADEON_SEPROM_CNTL1,
 488                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 489                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 490
 491         /* disable VIP */
 492         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 493
 494         /* enable the rom */
 495         if (rdev->flags & RADEON_IS_PCIE)
 496                 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 497         else
 498                 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 499
 500         /* Turn off mem requests and CRTC for both controllers */
 501         WREG32(RADEON_CRTC_GEN_CNTL,
 502                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
 503                 (RADEON_CRTC_DISP_REQ_EN_B |
 504                  RADEON_CRTC_EXT_DISP_EN)));
 505         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 506                 WREG32(RADEON_CRTC2_GEN_CNTL,
 507                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
 508                         RADEON_CRTC2_DISP_REQ_EN_B));
 509         }
 510         /* Turn off CRTC */
 511         WREG32(RADEON_CRTC_EXT_CNTL,
 512                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
 513                 (RADEON_CRTC_SYNC_TRISTAT |
 514                  RADEON_CRTC_DISPLAY_DIS)));
 515
 516         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 517                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
 518         }
 519
 520         r = radeon_read_bios(rdev);
 521
 522         /* restore regs */
 523         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 524         WREG32(RADEON_VIPH_CONTROL, viph_control);
 525         if (rdev->flags & RADEON_IS_PCIE)
 526                 WREG32(RV370_BUS_CNTL, bus_cntl);
 527         else
 528                 WREG32(RADEON_BUS_CNTL, bus_cntl);
 529         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 530         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 531                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 532         }
 533         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 534         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 535                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 536         }
 537         return r;
 538 }
 539
 540 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 541 {
 542         if (rdev->flags & RADEON_IS_IGP)
 543                 return igp_read_bios_from_vram(rdev);
 544         else if (rdev->family >= CHIP_BARTS)
 545                 return ni_read_disabled_bios(rdev);
 546         else if (rdev->family >= CHIP_RV770)
 547                 return r700_read_disabled_bios(rdev);
 548         else if (rdev->family >= CHIP_R600)
 549                 return r600_read_disabled_bios(rdev);
 550         else if (rdev->family >= CHIP_RS600)
 551                 return avivo_read_disabled_bios(rdev);
 552         else
 553                 return legacy_read_disabled_bios(rdev);
 554 }
 555
 556 #ifdef CONFIG_ACPI
 557 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 558 {
 559         bool ret = false;
 560         struct acpi_table_header *hdr;
 561         acpi_size tbl_size;
 562         UEFI_ACPI_VFCT *vfct;
 563         GOP_VBIOS_CONTENT *vbios;
 564         VFCT_IMAGE_HEADER *vhdr;
 565
 566         if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
 567                 return false;
 568         if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
 569                 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
 570                 goto out_unmap;
 571         }
 572
 573         vfct = (UEFI_ACPI_VFCT *)hdr;
 574         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
 575                 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
 576                 goto out_unmap;
 577         }
 578
 579         vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
 580         vhdr = &vbios->VbiosHeader;
 581         DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
 582                         vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
 583                         vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
 584
 585         if (vhdr->PCIBus != rdev->pdev->bus->number ||
 586             vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
 587             vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
 588             vhdr->VendorID != rdev->pdev->vendor ||
 589             vhdr->DeviceID != rdev->pdev->device) {
 590                 DRM_INFO("ACPI VFCT table is not for this card\n");
 591                 goto out_unmap;
 592         };
 593
 594         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
 595                 DRM_ERROR("ACPI VFCT image truncated\n");
 596                 goto out_unmap;
 597         }
 598
 599         rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
 600         ret = !!rdev->bios;
 601
 602 out_unmap:
 603         return ret;
 604 }
 605 #else
 606 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 607 {
 608         return false;
 609 }
 610 #endif
 611
 612 bool radeon_get_bios(struct radeon_device *rdev)
 613 {
 614         bool r;
 615         uint16_t tmp;
 616
 617         r = radeon_atrm_get_bios(rdev);
 618         if (r == false)
 619                 r = radeon_acpi_vfct_bios(rdev);
 620         if (r == false)
 621                 r = igp_read_bios_from_vram(rdev);
 622         if (r == false)
 623                 r = radeon_read_bios(rdev);
 624         if (r == false) {
 625                 r = radeon_read_disabled_bios(rdev);
 626         }
 627         if (r == false || rdev->bios == NULL) {
 628                 DRM_ERROR("Unable to locate a BIOS ROM\n");
 629                 rdev->bios = NULL;
 630                 return false;
 631         }
 632         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 633                 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
 634                 goto free_bios;
 635         }
 636
 637         tmp = RBIOS16(0x18);
 638         if (RBIOS8(tmp + 0x14) != 0x0) {
 639                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
 640                 goto free_bios;
 641         }
 642
 643         rdev->bios_header_start = RBIOS16(0x48);
 644         if (!rdev->bios_header_start) {
 645                 goto free_bios;
 646         }
 647         tmp = rdev->bios_header_start + 4;
 648         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
 649             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
 650                 rdev->is_atom_bios = true;
 651         } else {
 652                 rdev->is_atom_bios = false;
 653         }
 654
 655         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
 656         return true;
 657 free_bios:
 658         kfree(rdev->bios);
 659         rdev->bios = NULL;
 660         return false;
 661 }