drivers/gpu/drm/radeon/radeon_bios.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35 #include <linux/acpi.h>
  36 /*
  37  * BIOS.
  38  */
  39
  40 /* If you boot an IGP board with a discrete card as the primary,
  41  * the IGP rom is not accessible via the rom bar as the IGP rom is
  42  * part of the system bios.  On boot, the system bios puts a
  43  * copy of the igp rom at the start of vram if a discrete card is
  44  * present.
  45  */
  46 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  47 {
  48         uint8_t __iomem *bios;
  49         resource_size_t vram_base;
  50         resource_size_t size = 256 * 1024; /* ??? */
  51
  52         if (!(rdev->flags & RADEON_IS_IGP))
  53                 if (!radeon_card_posted(rdev))
  54                         return false;
  55
  56         rdev->bios = NULL;
  57         vram_base = pci_resource_start(rdev->pdev, 0);
  58         bios = ioremap(vram_base, size);
  59         if (!bios) {
  60                 return false;
  61         }
  62
  63         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  64                 iounmap(bios);
  65                 return false;
  66         }
  67         rdev->bios = kmalloc(size, GFP_KERNEL);
  68         if (rdev->bios == NULL) {
  69                 iounmap(bios);
  70                 return false;
  71         }
  72         memcpy_fromio(rdev->bios, bios, size);
  73         iounmap(bios);
  74         return true;
  75 }
  76
  77 static bool radeon_read_bios(struct radeon_device *rdev)
  78 {
  79         uint8_t __iomem *bios;
  80         size_t size;
  81
  82         rdev->bios = NULL;
  83         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  84         bios = pci_map_rom(rdev->pdev, &size);
  85         if (!bios) {
  86                 return false;
  87         }
  88
  89         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  90                 pci_unmap_rom(rdev->pdev, bios);
  91                 return false;
  92         }
  93         rdev->bios = kmemdup(bios, size, GFP_KERNEL);
  94         if (rdev->bios == NULL) {
  95                 pci_unmap_rom(rdev->pdev, bios);
  96                 return false;
  97         }
  98         pci_unmap_rom(rdev->pdev, bios);
  99         return true;
 100 }
 101
 102 static bool radeon_read_platform_bios(struct radeon_device *rdev)
 103 {
 104         uint8_t __iomem *bios;
 105         size_t size;
 106
 107         rdev->bios = NULL;
 108
 109         bios = pci_platform_rom(rdev->pdev, &size);
 110         if (!bios) {
 111                 return false;
 112         }
 113
 114         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
 115                 return false;
 116         }
 117         rdev->bios = kmemdup(bios, size, GFP_KERNEL);
 118         if (rdev->bios == NULL) {
 119                 return false;
 120         }
 121
 122         return true;
 123 }
 124
 125 #ifdef CONFIG_ACPI
 126 /* ATRM is used to get the BIOS on the discrete cards in
 127  * dual-gpu systems.
 128  */
 129 /* retrieve the ROM in 4k blocks */
 130 #define ATRM_BIOS_PAGE 4096
 131 /**
 132  * radeon_atrm_call - fetch a chunk of the vbios
 133  *
 134  * @atrm_handle: acpi ATRM handle
 135  * @bios: vbios image pointer
 136  * @offset: offset of vbios image data to fetch
 137  * @len: length of vbios image data to fetch
 138  *
 139  * Executes ATRM to fetch a chunk of the discrete
 140  * vbios image on PX systems (all asics).
 141  * Returns the length of the buffer fetched.
 142  */
 143 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
 144                             int offset, int len)
 145 {
 146         acpi_status status;
 147         union acpi_object atrm_arg_elements[2], *obj;
 148         struct acpi_object_list atrm_arg;
 149         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
 150
 151         atrm_arg.count = 2;
 152         atrm_arg.pointer = &atrm_arg_elements[0];
 153
 154         atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
 155         atrm_arg_elements[0].integer.value = offset;
 156
 157         atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
 158         atrm_arg_elements[1].integer.value = len;
 159
 160         status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
 161         if (ACPI_FAILURE(status)) {
 162                 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
 163                 return -ENODEV;
 164         }
 165
 166         obj = (union acpi_object *)buffer.pointer;
 167         memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
 168         len = obj->buffer.length;
 169         kfree(buffer.pointer);
 170         return len;
 171 }
 172
 173 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
 174 {
 175         int ret;
 176         int size = 256 * 1024;
 177         int i;
 178         struct pci_dev *pdev = NULL;
 179         acpi_handle dhandle, atrm_handle;
 180         acpi_status status;
 181         bool found = false;
 182
 183         /* ATRM is for the discrete card only */
 184         if (rdev->flags & RADEON_IS_IGP)
 185                 return false;
 186
 187         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
 188                 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
 189                 if (!dhandle)
 190                         continue;
 191
 192                 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
 193                 if (!ACPI_FAILURE(status)) {
 194                         found = true;
 195                         break;
 196                 }
 197         }
 198
 199         if (!found)
 200                 return false;
 201
 202         rdev->bios = kmalloc(size, GFP_KERNEL);
 203         if (!rdev->bios) {
 204                 DRM_ERROR("Unable to allocate bios\n");
 205                 return false;
 206         }
 207
 208         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
 209                 ret = radeon_atrm_call(atrm_handle,
 210                                        rdev->bios,
 211                                        (i * ATRM_BIOS_PAGE),
 212                                        ATRM_BIOS_PAGE);
 213                 if (ret < ATRM_BIOS_PAGE)
 214                         break;
 215         }
 216
 217         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 218                 kfree(rdev->bios);
 219                 return false;
 220         }
 221         return true;
 222 }
 223 #else
 224 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
 225 {
 226         return false;
 227 }
 228 #endif
 229
 230 static bool ni_read_disabled_bios(struct radeon_device *rdev)
 231 {
 232         u32 bus_cntl;
 233         u32 d1vga_control;
 234         u32 d2vga_control;
 235         u32 vga_render_control;
 236         u32 rom_cntl;
 237         bool r;
 238
 239         bus_cntl = RREG32(R600_BUS_CNTL);
 240         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 241         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 242         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 243         rom_cntl = RREG32(R600_ROM_CNTL);
 244
 245         /* enable the rom */
 246         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 247         /* Disable VGA mode */
 248         WREG32(AVIVO_D1VGA_CONTROL,
 249                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 250                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 251         WREG32(AVIVO_D2VGA_CONTROL,
 252                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 253                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 254         WREG32(AVIVO_VGA_RENDER_CONTROL,
 255                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 256         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 257
 258         r = radeon_read_bios(rdev);
 259
 260         /* restore regs */
 261         WREG32(R600_BUS_CNTL, bus_cntl);
 262         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 263         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 264         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 265         WREG32(R600_ROM_CNTL, rom_cntl);
 266         return r;
 267 }
 268
 269 static bool r700_read_disabled_bios(struct radeon_device *rdev)
 270 {
 271         uint32_t viph_control;
 272         uint32_t bus_cntl;
 273         uint32_t d1vga_control;
 274         uint32_t d2vga_control;
 275         uint32_t vga_render_control;
 276         uint32_t rom_cntl;
 277         uint32_t cg_spll_func_cntl = 0;
 278         uint32_t cg_spll_status;
 279         bool r;
 280
 281         viph_control = RREG32(RADEON_VIPH_CONTROL);
 282         bus_cntl = RREG32(R600_BUS_CNTL);
 283         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 284         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 285         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 286         rom_cntl = RREG32(R600_ROM_CNTL);
 287
 288         /* disable VIP */
 289         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 290         /* enable the rom */
 291         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 292         /* Disable VGA mode */
 293         WREG32(AVIVO_D1VGA_CONTROL,
 294                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 295                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 296         WREG32(AVIVO_D2VGA_CONTROL,
 297                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 298                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 299         WREG32(AVIVO_VGA_RENDER_CONTROL,
 300                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 301
 302         if (rdev->family == CHIP_RV730) {
 303                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 304
 305                 /* enable bypass mode */
 306                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
 307                                                 R600_SPLL_BYPASS_EN));
 308
 309                 /* wait for SPLL_CHG_STATUS to change to 1 */
 310                 cg_spll_status = 0;
 311                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 312                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 313
 314                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
 315         } else
 316                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 317
 318         r = radeon_read_bios(rdev);
 319
 320         /* restore regs */
 321         if (rdev->family == CHIP_RV730) {
 322                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 323
 324                 /* wait for SPLL_CHG_STATUS to change to 1 */
 325                 cg_spll_status = 0;
 326                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 327                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 328         }
 329         WREG32(RADEON_VIPH_CONTROL, viph_control);
 330         WREG32(R600_BUS_CNTL, bus_cntl);
 331         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 332         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 333         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 334         WREG32(R600_ROM_CNTL, rom_cntl);
 335         return r;
 336 }
 337
 338 static bool r600_read_disabled_bios(struct radeon_device *rdev)
 339 {
 340         uint32_t viph_control;
 341         uint32_t bus_cntl;
 342         uint32_t d1vga_control;
 343         uint32_t d2vga_control;
 344         uint32_t vga_render_control;
 345         uint32_t rom_cntl;
 346         uint32_t general_pwrmgt;
 347         uint32_t low_vid_lower_gpio_cntl;
 348         uint32_t medium_vid_lower_gpio_cntl;
 349         uint32_t high_vid_lower_gpio_cntl;
 350         uint32_t ctxsw_vid_lower_gpio_cntl;
 351         uint32_t lower_gpio_enable;
 352         bool r;
 353
 354         viph_control = RREG32(RADEON_VIPH_CONTROL);
 355         bus_cntl = RREG32(R600_BUS_CNTL);
 356         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 357         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 358         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 359         rom_cntl = RREG32(R600_ROM_CNTL);
 360         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
 361         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
 362         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
 363         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
 364         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
 365         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 366
 367         /* disable VIP */
 368         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 369         /* enable the rom */
 370         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 371         /* Disable VGA mode */
 372         WREG32(AVIVO_D1VGA_CONTROL,
 373                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 374                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 375         WREG32(AVIVO_D2VGA_CONTROL,
 376                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 377                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 378         WREG32(AVIVO_VGA_RENDER_CONTROL,
 379                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 380
 381         WREG32(R600_ROM_CNTL,
 382                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
 383                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
 384                 R600_SCK_OVERWRITE));
 385
 386         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
 387         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
 388                (low_vid_lower_gpio_cntl & ~0x400));
 389         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
 390                (medium_vid_lower_gpio_cntl & ~0x400));
 391         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
 392                (high_vid_lower_gpio_cntl & ~0x400));
 393         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
 394                (ctxsw_vid_lower_gpio_cntl & ~0x400));
 395         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 396
 397         r = radeon_read_bios(rdev);
 398
 399         /* restore regs */
 400         WREG32(RADEON_VIPH_CONTROL, viph_control);
 401         WREG32(R600_BUS_CNTL, bus_cntl);
 402         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 403         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 404         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 405         WREG32(R600_ROM_CNTL, rom_cntl);
 406         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
 407         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
 408         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
 409         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
 410         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
 411         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
 412         return r;
 413 }
 414
 415 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 416 {
 417         uint32_t seprom_cntl1;
 418         uint32_t viph_control;
 419         uint32_t bus_cntl;
 420         uint32_t d1vga_control;
 421         uint32_t d2vga_control;
 422         uint32_t vga_render_control;
 423         uint32_t gpiopad_a;
 424         uint32_t gpiopad_en;
 425         uint32_t gpiopad_mask;
 426         bool r;
 427
 428         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 429         viph_control = RREG32(RADEON_VIPH_CONTROL);
 430         bus_cntl = RREG32(RV370_BUS_CNTL);
 431         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 432         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 433         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 434         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 435         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
 436         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 437
 438         WREG32(RADEON_SEPROM_CNTL1,
 439                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 440                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 441         WREG32(RADEON_GPIOPAD_A, 0);
 442         WREG32(RADEON_GPIOPAD_EN, 0);
 443         WREG32(RADEON_GPIOPAD_MASK, 0);
 444
 445         /* disable VIP */
 446         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 447
 448         /* enable the rom */
 449         WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 450
 451         /* Disable VGA mode */
 452         WREG32(AVIVO_D1VGA_CONTROL,
 453                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 454                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 455         WREG32(AVIVO_D2VGA_CONTROL,
 456                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 457                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 458         WREG32(AVIVO_VGA_RENDER_CONTROL,
 459                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 460
 461         r = radeon_read_bios(rdev);
 462
 463         /* restore regs */
 464         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 465         WREG32(RADEON_VIPH_CONTROL, viph_control);
 466         WREG32(RV370_BUS_CNTL, bus_cntl);
 467         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 468         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 469         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 470         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 471         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
 472         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
 473         return r;
 474 }
 475
 476 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 477 {
 478         uint32_t seprom_cntl1;
 479         uint32_t viph_control;
 480         uint32_t bus_cntl;
 481         uint32_t crtc_gen_cntl;
 482         uint32_t crtc2_gen_cntl;
 483         uint32_t crtc_ext_cntl;
 484         uint32_t fp2_gen_cntl;
 485         bool r;
 486
 487         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 488         viph_control = RREG32(RADEON_VIPH_CONTROL);
 489         if (rdev->flags & RADEON_IS_PCIE)
 490                 bus_cntl = RREG32(RV370_BUS_CNTL);
 491         else
 492                 bus_cntl = RREG32(RADEON_BUS_CNTL);
 493         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 494         crtc2_gen_cntl = 0;
 495         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 496         fp2_gen_cntl = 0;
 497
 498         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 499                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 500         }
 501
 502         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 503                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 504         }
 505
 506         WREG32(RADEON_SEPROM_CNTL1,
 507                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 508                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 509
 510         /* disable VIP */
 511         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 512
 513         /* enable the rom */
 514         if (rdev->flags & RADEON_IS_PCIE)
 515                 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 516         else
 517                 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 518
 519         /* Turn off mem requests and CRTC for both controllers */
 520         WREG32(RADEON_CRTC_GEN_CNTL,
 521                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
 522                 (RADEON_CRTC_DISP_REQ_EN_B |
 523                  RADEON_CRTC_EXT_DISP_EN)));
 524         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 525                 WREG32(RADEON_CRTC2_GEN_CNTL,
 526                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
 527                         RADEON_CRTC2_DISP_REQ_EN_B));
 528         }
 529         /* Turn off CRTC */
 530         WREG32(RADEON_CRTC_EXT_CNTL,
 531                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
 532                 (RADEON_CRTC_SYNC_TRISTAT |
 533                  RADEON_CRTC_DISPLAY_DIS)));
 534
 535         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 536                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
 537         }
 538
 539         r = radeon_read_bios(rdev);
 540
 541         /* restore regs */
 542         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 543         WREG32(RADEON_VIPH_CONTROL, viph_control);
 544         if (rdev->flags & RADEON_IS_PCIE)
 545                 WREG32(RV370_BUS_CNTL, bus_cntl);
 546         else
 547                 WREG32(RADEON_BUS_CNTL, bus_cntl);
 548         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 549         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 550                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 551         }
 552         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 553         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 554                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 555         }
 556         return r;
 557 }
 558
 559 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 560 {
 561         if (rdev->flags & RADEON_IS_IGP)
 562                 return igp_read_bios_from_vram(rdev);
 563         else if (rdev->family >= CHIP_BARTS)
 564                 return ni_read_disabled_bios(rdev);
 565         else if (rdev->family >= CHIP_RV770)
 566                 return r700_read_disabled_bios(rdev);
 567         else if (rdev->family >= CHIP_R600)
 568                 return r600_read_disabled_bios(rdev);
 569         else if (rdev->family >= CHIP_RS600)
 570                 return avivo_read_disabled_bios(rdev);
 571         else
 572                 return legacy_read_disabled_bios(rdev);
 573 }
 574
 575 #ifdef CONFIG_ACPI
 576 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 577 {
 578         bool ret = false;
 579         struct acpi_table_header *hdr;
 580         acpi_size tbl_size;
 581         UEFI_ACPI_VFCT *vfct;
 582         GOP_VBIOS_CONTENT *vbios;
 583         VFCT_IMAGE_HEADER *vhdr;
 584
 585         if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
 586                 return false;
 587         if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
 588                 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
 589                 goto out_unmap;
 590         }
 591
 592         vfct = (UEFI_ACPI_VFCT *)hdr;
 593         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
 594                 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
 595                 goto out_unmap;
 596         }
 597
 598         vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
 599         vhdr = &vbios->VbiosHeader;
 600         DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
 601                         vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
 602                         vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
 603
 604         if (vhdr->PCIBus != rdev->pdev->bus->number ||
 605             vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
 606             vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
 607             vhdr->VendorID != rdev->pdev->vendor ||
 608             vhdr->DeviceID != rdev->pdev->device) {
 609                 DRM_INFO("ACPI VFCT table is not for this card\n");
 610                 goto out_unmap;
 611         };
 612
 613         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
 614                 DRM_ERROR("ACPI VFCT image truncated\n");
 615                 goto out_unmap;
 616         }
 617
 618         rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
 619         ret = !!rdev->bios;
 620
 621 out_unmap:
 622         return ret;
 623 }
 624 #else
 625 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 626 {
 627         return false;
 628 }
 629 #endif
 630
 631 bool radeon_get_bios(struct radeon_device *rdev)
 632 {
 633         bool r;
 634         uint16_t tmp;
 635
 636         r = radeon_atrm_get_bios(rdev);
 637         if (r == false)
 638                 r = radeon_acpi_vfct_bios(rdev);
 639         if (r == false)
 640                 r = igp_read_bios_from_vram(rdev);
 641         if (r == false)
 642                 r = radeon_read_bios(rdev);
 643         if (r == false) {
 644                 r = radeon_read_disabled_bios(rdev);
 645         }
 646         if (r == false) {
 647                 r = radeon_read_platform_bios(rdev);
 648         }
 649         if (r == false || rdev->bios == NULL) {
 650                 DRM_ERROR("Unable to locate a BIOS ROM\n");
 651                 rdev->bios = NULL;
 652                 return false;
 653         }
 654         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 655                 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
 656                 goto free_bios;
 657         }
 658
 659         tmp = RBIOS16(0x18);
 660         if (RBIOS8(tmp + 0x14) != 0x0) {
 661                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
 662                 goto free_bios;
 663         }
 664
 665         rdev->bios_header_start = RBIOS16(0x48);
 666         if (!rdev->bios_header_start) {
 667                 goto free_bios;
 668         }
 669         tmp = rdev->bios_header_start + 4;
 670         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
 671             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
 672                 rdev->is_atom_bios = true;
 673         } else {
 674                 rdev->is_atom_bios = false;
 675         }
 676
 677         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
 678         return true;
 679 free_bios:
 680         kfree(rdev->bios);
 681         rdev->bios = NULL;
 682         return false;
 683 }