drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 extern void
  34 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  35                         uint32_t supported_device, u16 caps);
  36
  37 /* from radeon_legacy_encoder.c */
  38 extern void
  39 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                           uint32_t supported_device);
  41
  42 union atom_supported_devices {
  43         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  44         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  45         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  46 };
  47
  48 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
  49                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  50                                           u8 index)
  51 {
  52         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  53         if ((rdev->family == CHIP_R420) ||
  54             (rdev->family == CHIP_R423) ||
  55             (rdev->family == CHIP_RV410)) {
  56                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  57                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  58                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  59                         gpio->ucClkMaskShift = 0x19;
  60                         gpio->ucDataMaskShift = 0x18;
  61                 }
  62         }
  63
  64         /* some evergreen boards have bad data for this entry */
  65         if (ASIC_IS_DCE4(rdev)) {
  66                 if ((index == 7) &&
  67                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
  68                     (gpio->sucI2cId.ucAccess == 0)) {
  69                         gpio->sucI2cId.ucAccess = 0x97;
  70                         gpio->ucDataMaskShift = 8;
  71                         gpio->ucDataEnShift = 8;
  72                         gpio->ucDataY_Shift = 8;
  73                         gpio->ucDataA_Shift = 8;
  74                 }
  75         }
  76
  77         /* some DCE3 boards have bad data for this entry */
  78         if (ASIC_IS_DCE3(rdev)) {
  79                 if ((index == 4) &&
  80                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
  81                     (gpio->sucI2cId.ucAccess == 0x94))
  82                         gpio->sucI2cId.ucAccess = 0x14;
  83         }
  84 }
  85
  86 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  87 {
  88         struct radeon_i2c_bus_rec i2c;
  89
  90         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  91
  92         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  93         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  94         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  95         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  96         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  97         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  98         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  99         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 100         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 101         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 102         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 103         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 104         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 105         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 106         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 107         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 108
 109         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 110                 i2c.hw_capable = true;
 111         else
 112                 i2c.hw_capable = false;
 113
 114         if (gpio->sucI2cId.ucAccess == 0xa0)
 115                 i2c.mm_i2c = true;
 116         else
 117                 i2c.mm_i2c = false;
 118
 119         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 120
 121         if (i2c.mask_clk_reg)
 122                 i2c.valid = true;
 123         else
 124                 i2c.valid = false;
 125
 126         return i2c;
 127 }
 128
 129 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
 130                                                                uint8_t id)
 131 {
 132         struct atom_context *ctx = rdev->mode_info.atom_context;
 133         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 134         struct radeon_i2c_bus_rec i2c;
 135         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 136         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 137         uint16_t data_offset, size;
 138         int i, num_indices;
 139
 140         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 141         i2c.valid = false;
 142
 143         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 144                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 145
 146                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 147                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 148
 149                 gpio = &i2c_info->asGPIO_Info[0];
 150                 for (i = 0; i < num_indices; i++) {
 151
 152                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 153
 154                         if (gpio->sucI2cId.ucAccess == id) {
 155                                 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 156                                 break;
 157                         }
 158                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 159                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 160                 }
 161         }
 162
 163         return i2c;
 164 }
 165
 166 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 167 {
 168         struct atom_context *ctx = rdev->mode_info.atom_context;
 169         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 170         struct radeon_i2c_bus_rec i2c;
 171         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 172         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 173         uint16_t data_offset, size;
 174         int i, num_indices;
 175         char stmp[32];
 176
 177         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 178                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 179
 180                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 181                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 182
 183                 gpio = &i2c_info->asGPIO_Info[0];
 184                 for (i = 0; i < num_indices; i++) {
 185                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 186
 187                         i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 188
 189                         if (i2c.valid) {
 190                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 191                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 192                         }
 193                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 194                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 195                 }
 196         }
 197 }
 198
 199 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
 200                                                    u8 id)
 201 {
 202         struct atom_context *ctx = rdev->mode_info.atom_context;
 203         struct radeon_gpio_rec gpio;
 204         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 205         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 206         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 207         u16 data_offset, size;
 208         int i, num_indices;
 209
 210         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 211         gpio.valid = false;
 212
 213         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 214                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 215
 216                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 217                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 218
 219                 pin = gpio_info->asGPIO_Pin;
 220                 for (i = 0; i < num_indices; i++) {
 221                         if (id == pin->ucGPIO_ID) {
 222                                 gpio.id = pin->ucGPIO_ID;
 223                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 224                                 gpio.shift = pin->ucGpioPinBitShift;
 225                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 226                                 gpio.valid = true;
 227                                 break;
 228                         }
 229                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 230                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 231                 }
 232         }
 233
 234         return gpio;
 235 }
 236
 237 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 238                                                             struct radeon_gpio_rec *gpio)
 239 {
 240         struct radeon_hpd hpd;
 241         u32 reg;
 242
 243         memset(&hpd, 0, sizeof(struct radeon_hpd));
 244
 245         if (ASIC_IS_DCE6(rdev))
 246                 reg = SI_DC_GPIO_HPD_A;
 247         else if (ASIC_IS_DCE4(rdev))
 248                 reg = EVERGREEN_DC_GPIO_HPD_A;
 249         else
 250                 reg = AVIVO_DC_GPIO_HPD_A;
 251
 252         hpd.gpio = *gpio;
 253         if (gpio->reg == reg) {
 254                 switch(gpio->mask) {
 255                 case (1 << 0):
 256                         hpd.hpd = RADEON_HPD_1;
 257                         break;
 258                 case (1 << 8):
 259                         hpd.hpd = RADEON_HPD_2;
 260                         break;
 261                 case (1 << 16):
 262                         hpd.hpd = RADEON_HPD_3;
 263                         break;
 264                 case (1 << 24):
 265                         hpd.hpd = RADEON_HPD_4;
 266                         break;
 267                 case (1 << 26):
 268                         hpd.hpd = RADEON_HPD_5;
 269                         break;
 270                 case (1 << 28):
 271                         hpd.hpd = RADEON_HPD_6;
 272                         break;
 273                 default:
 274                         hpd.hpd = RADEON_HPD_NONE;
 275                         break;
 276                 }
 277         } else
 278                 hpd.hpd = RADEON_HPD_NONE;
 279         return hpd;
 280 }
 281
 282 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 283                                      uint32_t supported_device,
 284                                      int *connector_type,
 285                                      struct radeon_i2c_bus_rec *i2c_bus,
 286                                      uint16_t *line_mux,
 287                                      struct radeon_hpd *hpd)
 288 {
 289
 290         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 291         if ((dev->pdev->device == 0x791e) &&
 292             (dev->pdev->subsystem_vendor == 0x1043) &&
 293             (dev->pdev->subsystem_device == 0x826d)) {
 294                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 295                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 296                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 297         }
 298
 299         /* Asrock RS600 board lists the DVI port as HDMI */
 300         if ((dev->pdev->device == 0x7941) &&
 301             (dev->pdev->subsystem_vendor == 0x1849) &&
 302             (dev->pdev->subsystem_device == 0x7941)) {
 303                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 304                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 305                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 306         }
 307
 308         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 309         if ((dev->pdev->device == 0x796e) &&
 310             (dev->pdev->subsystem_vendor == 0x1462) &&
 311             (dev->pdev->subsystem_device == 0x7302)) {
 312                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 313                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 314                         return false;
 315         }
 316
 317         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 318         if ((dev->pdev->device == 0x7941) &&
 319             (dev->pdev->subsystem_vendor == 0x147b) &&
 320             (dev->pdev->subsystem_device == 0x2412)) {
 321                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 322                         return false;
 323         }
 324
 325         /* Falcon NW laptop lists vga ddc line for LVDS */
 326         if ((dev->pdev->device == 0x5653) &&
 327             (dev->pdev->subsystem_vendor == 0x1462) &&
 328             (dev->pdev->subsystem_device == 0x0291)) {
 329                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 330                         i2c_bus->valid = false;
 331                         *line_mux = 53;
 332                 }
 333         }
 334
 335         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 336         if ((dev->pdev->device == 0x7146) &&
 337             (dev->pdev->subsystem_vendor == 0x17af) &&
 338             (dev->pdev->subsystem_device == 0x2058)) {
 339                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 340                         return false;
 341         }
 342
 343         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 344         if ((dev->pdev->device == 0x7142) &&
 345             (dev->pdev->subsystem_vendor == 0x1458) &&
 346             (dev->pdev->subsystem_device == 0x2134)) {
 347                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 348                         return false;
 349         }
 350
 351
 352         /* Funky macbooks */
 353         if ((dev->pdev->device == 0x71C5) &&
 354             (dev->pdev->subsystem_vendor == 0x106b) &&
 355             (dev->pdev->subsystem_device == 0x0080)) {
 356                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 357                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 358                         return false;
 359                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 360                         *line_mux = 0x90;
 361         }
 362
 363         /* mac rv630, rv730, others */
 364         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 365             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 366                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 367                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 368         }
 369
 370         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 371         if ((dev->pdev->device == 0x9598) &&
 372             (dev->pdev->subsystem_vendor == 0x1043) &&
 373             (dev->pdev->subsystem_device == 0x01da)) {
 374                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 375                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 376                 }
 377         }
 378
 379         /* ASUS HD 3600 board lists the DVI port as HDMI */
 380         if ((dev->pdev->device == 0x9598) &&
 381             (dev->pdev->subsystem_vendor == 0x1043) &&
 382             (dev->pdev->subsystem_device == 0x01e4)) {
 383                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 384                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 385                 }
 386         }
 387
 388         /* ASUS HD 3450 board lists the DVI port as HDMI */
 389         if ((dev->pdev->device == 0x95C5) &&
 390             (dev->pdev->subsystem_vendor == 0x1043) &&
 391             (dev->pdev->subsystem_device == 0x01e2)) {
 392                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 393                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 394                 }
 395         }
 396
 397         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 398          * HDMI + VGA reporting as HDMI
 399          */
 400         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 401                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 402                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 403                         *line_mux = 0;
 404                 }
 405         }
 406
 407         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 408          * on the laptop and a DVI port on the docking station and
 409          * both share the same encoder, hpd pin, and ddc line.
 410          * So while the bios table is technically correct,
 411          * we drop the DVI port here since xrandr has no concept of
 412          * encoders and will try and drive both connectors
 413          * with different crtcs which isn't possible on the hardware
 414          * side and leaves no crtcs for LVDS or VGA.
 415          */
 416         if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
 417             (dev->pdev->subsystem_vendor == 0x1025) &&
 418             (dev->pdev->subsystem_device == 0x013c)) {
 419                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 420                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 421                         /* actually it's a DVI-D port not DVI-I */
 422                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 423                         return false;
 424                 }
 425         }
 426
 427         /* XFX Pine Group device rv730 reports no VGA DDC lines
 428          * even though they are wired up to record 0x93
 429          */
 430         if ((dev->pdev->device == 0x9498) &&
 431             (dev->pdev->subsystem_vendor == 0x1682) &&
 432             (dev->pdev->subsystem_device == 0x2452) &&
 433             (i2c_bus->valid == false) &&
 434             !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 435                 struct radeon_device *rdev = dev->dev_private;
 436                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 437         }
 438
 439         /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
 440         if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
 441             (dev->pdev->subsystem_vendor == 0x1734) &&
 442             (dev->pdev->subsystem_device == 0x11bd)) {
 443                 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 444                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 445                         *line_mux = 0x3103;
 446                 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
 447                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 448                 }
 449         }
 450
 451         /* Fujitsu D3003-S2 board lists DVI-I as DVI-I and VGA */
 452         if ((dev->pdev->device == 0x9805) &&
 453             (dev->pdev->subsystem_vendor == 0x1734) &&
 454             (dev->pdev->subsystem_device == 0x11bd)) {
 455                 if (*connector_type == DRM_MODE_CONNECTOR_VGA)
 456                         return false;
 457         }
 458
 459         return true;
 460 }
 461
 462 static const int supported_devices_connector_convert[] = {
 463         DRM_MODE_CONNECTOR_Unknown,
 464         DRM_MODE_CONNECTOR_VGA,
 465         DRM_MODE_CONNECTOR_DVII,
 466         DRM_MODE_CONNECTOR_DVID,
 467         DRM_MODE_CONNECTOR_DVIA,
 468         DRM_MODE_CONNECTOR_SVIDEO,
 469         DRM_MODE_CONNECTOR_Composite,
 470         DRM_MODE_CONNECTOR_LVDS,
 471         DRM_MODE_CONNECTOR_Unknown,
 472         DRM_MODE_CONNECTOR_Unknown,
 473         DRM_MODE_CONNECTOR_HDMIA,
 474         DRM_MODE_CONNECTOR_HDMIB,
 475         DRM_MODE_CONNECTOR_Unknown,
 476         DRM_MODE_CONNECTOR_Unknown,
 477         DRM_MODE_CONNECTOR_9PinDIN,
 478         DRM_MODE_CONNECTOR_DisplayPort
 479 };
 480
 481 static const uint16_t supported_devices_connector_object_id_convert[] = {
 482         CONNECTOR_OBJECT_ID_NONE,
 483         CONNECTOR_OBJECT_ID_VGA,
 484         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 485         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 486         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 487         CONNECTOR_OBJECT_ID_COMPOSITE,
 488         CONNECTOR_OBJECT_ID_SVIDEO,
 489         CONNECTOR_OBJECT_ID_LVDS,
 490         CONNECTOR_OBJECT_ID_9PIN_DIN,
 491         CONNECTOR_OBJECT_ID_9PIN_DIN,
 492         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 493         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 494         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 495         CONNECTOR_OBJECT_ID_SVIDEO
 496 };
 497
 498 static const int object_connector_convert[] = {
 499         DRM_MODE_CONNECTOR_Unknown,
 500         DRM_MODE_CONNECTOR_DVII,
 501         DRM_MODE_CONNECTOR_DVII,
 502         DRM_MODE_CONNECTOR_DVID,
 503         DRM_MODE_CONNECTOR_DVID,
 504         DRM_MODE_CONNECTOR_VGA,
 505         DRM_MODE_CONNECTOR_Composite,
 506         DRM_MODE_CONNECTOR_SVIDEO,
 507         DRM_MODE_CONNECTOR_Unknown,
 508         DRM_MODE_CONNECTOR_Unknown,
 509         DRM_MODE_CONNECTOR_9PinDIN,
 510         DRM_MODE_CONNECTOR_Unknown,
 511         DRM_MODE_CONNECTOR_HDMIA,
 512         DRM_MODE_CONNECTOR_HDMIB,
 513         DRM_MODE_CONNECTOR_LVDS,
 514         DRM_MODE_CONNECTOR_9PinDIN,
 515         DRM_MODE_CONNECTOR_Unknown,
 516         DRM_MODE_CONNECTOR_Unknown,
 517         DRM_MODE_CONNECTOR_Unknown,
 518         DRM_MODE_CONNECTOR_DisplayPort,
 519         DRM_MODE_CONNECTOR_eDP,
 520         DRM_MODE_CONNECTOR_Unknown
 521 };
 522
 523 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 524 {
 525         struct radeon_device *rdev = dev->dev_private;
 526         struct radeon_mode_info *mode_info = &rdev->mode_info;
 527         struct atom_context *ctx = mode_info->atom_context;
 528         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 529         u16 size, data_offset;
 530         u8 frev, crev;
 531         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 532         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 533         ATOM_OBJECT_TABLE *router_obj;
 534         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 535         ATOM_OBJECT_HEADER *obj_header;
 536         int i, j, k, path_size, device_support;
 537         int connector_type;
 538         u16 igp_lane_info, conn_id, connector_object_id;
 539         struct radeon_i2c_bus_rec ddc_bus;
 540         struct radeon_router router;
 541         struct radeon_gpio_rec gpio;
 542         struct radeon_hpd hpd;
 543
 544         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 545                 return false;
 546
 547         if (crev < 2)
 548                 return false;
 549
 550         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 551         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 552             (ctx->bios + data_offset +
 553              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 554         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 555             (ctx->bios + data_offset +
 556              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 557         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 558             (ctx->bios + data_offset +
 559              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 560         router_obj = (ATOM_OBJECT_TABLE *)
 561                 (ctx->bios + data_offset +
 562                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 563         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 564
 565         path_size = 0;
 566         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 567                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 568                 ATOM_DISPLAY_OBJECT_PATH *path;
 569                 addr += path_size;
 570                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 571                 path_size += le16_to_cpu(path->usSize);
 572
 573                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 574                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 575
 576                         con_obj_id =
 577                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 578                             >> OBJECT_ID_SHIFT;
 579                         con_obj_num =
 580                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 581                             >> ENUM_ID_SHIFT;
 582                         con_obj_type =
 583                             (le16_to_cpu(path->usConnObjectId) &
 584                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 585
 586                         /* TODO CV support */
 587                         if (le16_to_cpu(path->usDeviceTag) ==
 588                                 ATOM_DEVICE_CV_SUPPORT)
 589                                 continue;
 590
 591                         /* IGP chips */
 592                         if ((rdev->flags & RADEON_IS_IGP) &&
 593                             (con_obj_id ==
 594                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 595                                 uint16_t igp_offset = 0;
 596                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 597
 598                                 index =
 599                                     GetIndexIntoMasterTable(DATA,
 600                                                             IntegratedSystemInfo);
 601
 602                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 603                                                            &crev, &igp_offset)) {
 604
 605                                         if (crev >= 2) {
 606                                                 igp_obj =
 607                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 608                                                          *) (ctx->bios + igp_offset);
 609
 610                                                 if (igp_obj) {
 611                                                         uint32_t slot_config, ct;
 612
 613                                                         if (con_obj_num == 1)
 614                                                                 slot_config =
 615                                                                         igp_obj->
 616                                                                         ulDDISlot1Config;
 617                                                         else
 618                                                                 slot_config =
 619                                                                         igp_obj->
 620                                                                         ulDDISlot2Config;
 621
 622                                                         ct = (slot_config >> 16) & 0xff;
 623                                                         connector_type =
 624                                                                 object_connector_convert
 625                                                                 [ct];
 626                                                         connector_object_id = ct;
 627                                                         igp_lane_info =
 628                                                                 slot_config & 0xffff;
 629                                                 } else
 630                                                         continue;
 631                                         } else
 632                                                 continue;
 633                                 } else {
 634                                         igp_lane_info = 0;
 635                                         connector_type =
 636                                                 object_connector_convert[con_obj_id];
 637                                         connector_object_id = con_obj_id;
 638                                 }
 639                         } else {
 640                                 igp_lane_info = 0;
 641                                 connector_type =
 642                                     object_connector_convert[con_obj_id];
 643                                 connector_object_id = con_obj_id;
 644                         }
 645
 646                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 647                                 continue;
 648
 649                         router.ddc_valid = false;
 650                         router.cd_valid = false;
 651                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 652                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 653
 654                                 grph_obj_id =
 655                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 656                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 657                                 grph_obj_num =
 658                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 659                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 660                                 grph_obj_type =
 661                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 662                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 663
 664                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 665                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 666                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 667                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 668                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 669                                                                 (ctx->bios + data_offset +
 670                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 671                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 672                                                         u16 caps = 0;
 673
 674                                                         while (record->ucRecordSize > 0 &&
 675                                                                record->ucRecordType > 0 &&
 676                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 677                                                                 switch (record->ucRecordType) {
 678                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 679                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 680                                                                                 record;
 681                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 682                                                                         break;
 683                                                                 }
 684                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 685                                                                         ((char *)record + record->ucRecordSize);
 686                                                         }
 687                                                         radeon_add_atom_encoder(dev,
 688                                                                                 encoder_obj,
 689                                                                                 le16_to_cpu
 690                                                                                 (path->
 691                                                                                  usDeviceTag),
 692                                                                                 caps);
 693                                                 }
 694                                         }
 695                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 696                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 697                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 698                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 699                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 700                                                                 (ctx->bios + data_offset +
 701                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 702                                                         ATOM_I2C_RECORD *i2c_record;
 703                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 704                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 705                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 706                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 707                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 708                                                                 (ctx->bios + data_offset +
 709                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 710                                                         u8 *num_dst_objs = (u8 *)
 711                                                                 ((u8 *)router_src_dst_table + 1 +
 712                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 713                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 714                                                         int enum_id;
 715
 716                                                         router.router_id = router_obj_id;
 717                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 718                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 719                                                                     le16_to_cpu(dst_objs[enum_id]))
 720                                                                         break;
 721                                                         }
 722
 723                                                         while (record->ucRecordSize > 0 &&
 724                                                                record->ucRecordType > 0 &&
 725                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 726                                                                 switch (record->ucRecordType) {
 727                                                                 case ATOM_I2C_RECORD_TYPE:
 728                                                                         i2c_record =
 729                                                                                 (ATOM_I2C_RECORD *)
 730                                                                                 record;
 731                                                                         i2c_config =
 732                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 733                                                                                 &i2c_record->sucI2cId;
 734                                                                         router.i2c_info =
 735                                                                                 radeon_lookup_i2c_gpio(rdev,
 736                                                                                                        i2c_config->
 737                                                                                                        ucAccess);
 738                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 739                                                                         break;
 740                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 741                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 742                                                                                 record;
 743                                                                         router.ddc_valid = true;
 744                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 745                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 746                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 747                                                                         break;
 748                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 749                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 750                                                                                 record;
 751                                                                         router.cd_valid = true;
 752                                                                         router.cd_mux_type = cd_path->ucMuxType;
 753                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 754                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 755                                                                         break;
 756                                                                 }
 757                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 758                                                                         ((char *)record + record->ucRecordSize);
 759                                                         }
 760                                                 }
 761                                         }
 762                                 }
 763                         }
 764
 765                         /* look up gpio for ddc, hpd */
 766                         ddc_bus.valid = false;
 767                         hpd.hpd = RADEON_HPD_NONE;
 768                         if ((le16_to_cpu(path->usDeviceTag) &
 769                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 770                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 771                                         if (le16_to_cpu(path->usConnObjectId) ==
 772                                             le16_to_cpu(con_obj->asObjects[j].
 773                                                         usObjectID)) {
 774                                                 ATOM_COMMON_RECORD_HEADER
 775                                                     *record =
 776                                                     (ATOM_COMMON_RECORD_HEADER
 777                                                      *)
 778                                                     (ctx->bios + data_offset +
 779                                                      le16_to_cpu(con_obj->
 780                                                                  asObjects[j].
 781                                                                  usRecordOffset));
 782                                                 ATOM_I2C_RECORD *i2c_record;
 783                                                 ATOM_HPD_INT_RECORD *hpd_record;
 784                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 785
 786                                                 while (record->ucRecordSize > 0 &&
 787                                                        record->ucRecordType > 0 &&
 788                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 789                                                         switch (record->ucRecordType) {
 790                                                         case ATOM_I2C_RECORD_TYPE:
 791                                                                 i2c_record =
 792                                                                     (ATOM_I2C_RECORD *)
 793                                                                         record;
 794                                                                 i2c_config =
 795                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 796                                                                         &i2c_record->sucI2cId;
 797                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 798                                                                                                  i2c_config->
 799                                                                                                  ucAccess);
 800                                                                 break;
 801                                                         case ATOM_HPD_INT_RECORD_TYPE:
 802                                                                 hpd_record =
 803                                                                         (ATOM_HPD_INT_RECORD *)
 804                                                                         record;
 805                                                                 gpio = radeon_atombios_lookup_gpio(rdev,
 806                                                                                           hpd_record->ucHPDIntGPIOID);
 807                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 808                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 809                                                                 break;
 810                                                         }
 811                                                         record =
 812                                                             (ATOM_COMMON_RECORD_HEADER
 813                                                              *) ((char *)record
 814                                                                  +
 815                                                                  record->
 816                                                                  ucRecordSize);
 817                                                 }
 818                                                 break;
 819                                         }
 820                                 }
 821                         }
 822
 823                         /* needed for aux chan transactions */
 824                         ddc_bus.hpd = hpd.hpd;
 825
 826                         conn_id = le16_to_cpu(path->usConnObjectId);
 827
 828                         if (!radeon_atom_apply_quirks
 829                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 830                              &ddc_bus, &conn_id, &hpd))
 831                                 continue;
 832
 833                         radeon_add_atom_connector(dev,
 834                                                   conn_id,
 835                                                   le16_to_cpu(path->
 836                                                               usDeviceTag),
 837                                                   connector_type, &ddc_bus,
 838                                                   igp_lane_info,
 839                                                   connector_object_id,
 840                                                   &hpd,
 841                                                   &router);
 842
 843                 }
 844         }
 845
 846         radeon_link_encoder_connector(dev);
 847
 848         radeon_setup_mst_connector(dev);
 849         return true;
 850 }
 851
 852 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 853                                                  int connector_type,
 854                                                  uint16_t devices)
 855 {
 856         struct radeon_device *rdev = dev->dev_private;
 857
 858         if (rdev->flags & RADEON_IS_IGP) {
 859                 return supported_devices_connector_object_id_convert
 860                         [connector_type];
 861         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 862                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 863                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 864                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 865                 struct atom_context *ctx = mode_info->atom_context;
 866                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 867                 uint16_t size, data_offset;
 868                 uint8_t frev, crev;
 869                 ATOM_XTMDS_INFO *xtmds;
 870
 871                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 872                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 873
 874                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 875                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 876                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 877                                 else
 878                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 879                         } else {
 880                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 881                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 882                                 else
 883                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 884                         }
 885                 } else
 886                         return supported_devices_connector_object_id_convert
 887                                 [connector_type];
 888         } else {
 889                 return supported_devices_connector_object_id_convert
 890                         [connector_type];
 891         }
 892 }
 893
 894 struct bios_connector {
 895         bool valid;
 896         uint16_t line_mux;
 897         uint16_t devices;
 898         int connector_type;
 899         struct radeon_i2c_bus_rec ddc_bus;
 900         struct radeon_hpd hpd;
 901 };
 902
 903 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 904                                                                  drm_device
 905                                                                  *dev)
 906 {
 907         struct radeon_device *rdev = dev->dev_private;
 908         struct radeon_mode_info *mode_info = &rdev->mode_info;
 909         struct atom_context *ctx = mode_info->atom_context;
 910         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 911         uint16_t size, data_offset;
 912         uint8_t frev, crev;
 913         uint16_t device_support;
 914         uint8_t dac;
 915         union atom_supported_devices *supported_devices;
 916         int i, j, max_device;
 917         struct bios_connector *bios_connectors;
 918         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 919         struct radeon_router router;
 920
 921         router.ddc_valid = false;
 922         router.cd_valid = false;
 923
 924         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 925         if (!bios_connectors)
 926                 return false;
 927
 928         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 929                                     &data_offset)) {
 930                 kfree(bios_connectors);
 931                 return false;
 932         }
 933
 934         supported_devices =
 935             (union atom_supported_devices *)(ctx->bios + data_offset);
 936
 937         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 938
 939         if (frev > 1)
 940                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 941         else
 942                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 943
 944         for (i = 0; i < max_device; i++) {
 945                 ATOM_CONNECTOR_INFO_I2C ci =
 946                     supported_devices->info.asConnInfo[i];
 947
 948                 bios_connectors[i].valid = false;
 949
 950                 if (!(device_support & (1 << i))) {
 951                         continue;
 952                 }
 953
 954                 if (i == ATOM_DEVICE_CV_INDEX) {
 955                         DRM_DEBUG_KMS("Skipping Component Video\n");
 956                         continue;
 957                 }
 958
 959                 bios_connectors[i].connector_type =
 960                     supported_devices_connector_convert[ci.sucConnectorInfo.
 961                                                         sbfAccess.
 962                                                         bfConnectorType];
 963
 964                 if (bios_connectors[i].connector_type ==
 965                     DRM_MODE_CONNECTOR_Unknown)
 966                         continue;
 967
 968                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 969
 970                 bios_connectors[i].line_mux =
 971                         ci.sucI2cId.ucAccess;
 972
 973                 /* give tv unique connector ids */
 974                 if (i == ATOM_DEVICE_TV1_INDEX) {
 975                         bios_connectors[i].ddc_bus.valid = false;
 976                         bios_connectors[i].line_mux = 50;
 977                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 978                         bios_connectors[i].ddc_bus.valid = false;
 979                         bios_connectors[i].line_mux = 51;
 980                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 981                         bios_connectors[i].ddc_bus.valid = false;
 982                         bios_connectors[i].line_mux = 52;
 983                 } else
 984                         bios_connectors[i].ddc_bus =
 985                             radeon_lookup_i2c_gpio(rdev,
 986                                                    bios_connectors[i].line_mux);
 987
 988                 if ((crev > 1) && (frev > 1)) {
 989                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 990                         switch (isb) {
 991                         case 0x4:
 992                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 993                                 break;
 994                         case 0xa:
 995                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 996                                 break;
 997                         default:
 998                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 999                                 break;
1000                         }
1001                 } else {
1002                         if (i == ATOM_DEVICE_DFP1_INDEX)
1003                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1004                         else if (i == ATOM_DEVICE_DFP2_INDEX)
1005                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1006                         else
1007                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1008                 }
1009
1010                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1011                  * shared with a DVI port, we'll pick up the DVI connector when we
1012                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
1013                  */
1014                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1015                         bios_connectors[i].connector_type =
1016                             DRM_MODE_CONNECTOR_VGA;
1017
1018                 if (!radeon_atom_apply_quirks
1019                     (dev, (1 << i), &bios_connectors[i].connector_type,
1020                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1021                      &bios_connectors[i].hpd))
1022                         continue;
1023
1024                 bios_connectors[i].valid = true;
1025                 bios_connectors[i].devices = (1 << i);
1026
1027                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1028                         radeon_add_atom_encoder(dev,
1029                                                 radeon_get_encoder_enum(dev,
1030                                                                       (1 << i),
1031                                                                       dac),
1032                                                 (1 << i),
1033                                                 0);
1034                 else
1035                         radeon_add_legacy_encoder(dev,
1036                                                   radeon_get_encoder_enum(dev,
1037                                                                         (1 << i),
1038                                                                         dac),
1039                                                   (1 << i));
1040         }
1041
1042         /* combine shared connectors */
1043         for (i = 0; i < max_device; i++) {
1044                 if (bios_connectors[i].valid) {
1045                         for (j = 0; j < max_device; j++) {
1046                                 if (bios_connectors[j].valid && (i != j)) {
1047                                         if (bios_connectors[i].line_mux ==
1048                                             bios_connectors[j].line_mux) {
1049                                                 /* make sure not to combine LVDS */
1050                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051                                                         bios_connectors[i].line_mux = 53;
1052                                                         bios_connectors[i].ddc_bus.valid = false;
1053                                                         continue;
1054                                                 }
1055                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1056                                                         bios_connectors[j].line_mux = 53;
1057                                                         bios_connectors[j].ddc_bus.valid = false;
1058                                                         continue;
1059                                                 }
1060                                                 /* combine analog and digital for DVI-I */
1061                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1062                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1063                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1064                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1065                                                         bios_connectors[i].devices |=
1066                                                                 bios_connectors[j].devices;
1067                                                         bios_connectors[i].connector_type =
1068                                                                 DRM_MODE_CONNECTOR_DVII;
1069                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1070                                                                 bios_connectors[i].hpd =
1071                                                                         bios_connectors[j].hpd;
1072                                                         bios_connectors[j].valid = false;
1073                                                 }
1074                                         }
1075                                 }
1076                         }
1077                 }
1078         }
1079
1080         /* add the connectors */
1081         for (i = 0; i < max_device; i++) {
1082                 if (bios_connectors[i].valid) {
1083                         uint16_t connector_object_id =
1084                                 atombios_get_connector_object_id(dev,
1085                                                       bios_connectors[i].connector_type,
1086                                                       bios_connectors[i].devices);
1087                         radeon_add_atom_connector(dev,
1088                                                   bios_connectors[i].line_mux,
1089                                                   bios_connectors[i].devices,
1090                                                   bios_connectors[i].
1091                                                   connector_type,
1092                                                   &bios_connectors[i].ddc_bus,
1093                                                   0,
1094                                                   connector_object_id,
1095                                                   &bios_connectors[i].hpd,
1096                                                   &router);
1097                 }
1098         }
1099
1100         radeon_link_encoder_connector(dev);
1101
1102         kfree(bios_connectors);
1103         return true;
1104 }
1105
1106 union firmware_info {
1107         ATOM_FIRMWARE_INFO info;
1108         ATOM_FIRMWARE_INFO_V1_2 info_12;
1109         ATOM_FIRMWARE_INFO_V1_3 info_13;
1110         ATOM_FIRMWARE_INFO_V1_4 info_14;
1111         ATOM_FIRMWARE_INFO_V2_1 info_21;
1112         ATOM_FIRMWARE_INFO_V2_2 info_22;
1113 };
1114
1115 bool radeon_atom_get_clock_info(struct drm_device *dev)
1116 {
1117         struct radeon_device *rdev = dev->dev_private;
1118         struct radeon_mode_info *mode_info = &rdev->mode_info;
1119         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1120         union firmware_info *firmware_info;
1121         uint8_t frev, crev;
1122         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1123         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1124         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1125         struct radeon_pll *spll = &rdev->clock.spll;
1126         struct radeon_pll *mpll = &rdev->clock.mpll;
1127         uint16_t data_offset;
1128
1129         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1130                                    &frev, &crev, &data_offset)) {
1131                 firmware_info =
1132                         (union firmware_info *)(mode_info->atom_context->bios +
1133                                                 data_offset);
1134                 /* pixel clocks */
1135                 p1pll->reference_freq =
1136                     le16_to_cpu(firmware_info->info.usReferenceClock);
1137                 p1pll->reference_div = 0;
1138
1139                 if (crev < 2)
1140                         p1pll->pll_out_min =
1141                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1142                 else
1143                         p1pll->pll_out_min =
1144                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1145                 p1pll->pll_out_max =
1146                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1147
1148                 if (crev >= 4) {
1149                         p1pll->lcd_pll_out_min =
1150                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1151                         if (p1pll->lcd_pll_out_min == 0)
1152                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1153                         p1pll->lcd_pll_out_max =
1154                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1155                         if (p1pll->lcd_pll_out_max == 0)
1156                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1157                 } else {
1158                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1159                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1160                 }
1161
1162                 if (p1pll->pll_out_min == 0) {
1163                         if (ASIC_IS_AVIVO(rdev))
1164                                 p1pll->pll_out_min = 64800;
1165                         else
1166                                 p1pll->pll_out_min = 20000;
1167                 }
1168
1169                 p1pll->pll_in_min =
1170                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1171                 p1pll->pll_in_max =
1172                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1173
1174                 *p2pll = *p1pll;
1175
1176                 /* system clock */
1177                 if (ASIC_IS_DCE4(rdev))
1178                         spll->reference_freq =
1179                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1180                 else
1181                         spll->reference_freq =
1182                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1183                 spll->reference_div = 0;
1184
1185                 spll->pll_out_min =
1186                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1187                 spll->pll_out_max =
1188                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1189
1190                 /* ??? */
1191                 if (spll->pll_out_min == 0) {
1192                         if (ASIC_IS_AVIVO(rdev))
1193                                 spll->pll_out_min = 64800;
1194                         else
1195                                 spll->pll_out_min = 20000;
1196                 }
1197
1198                 spll->pll_in_min =
1199                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1200                 spll->pll_in_max =
1201                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1202
1203                 /* memory clock */
1204                 if (ASIC_IS_DCE4(rdev))
1205                         mpll->reference_freq =
1206                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1207                 else
1208                         mpll->reference_freq =
1209                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1210                 mpll->reference_div = 0;
1211
1212                 mpll->pll_out_min =
1213                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1214                 mpll->pll_out_max =
1215                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1216
1217                 /* ??? */
1218                 if (mpll->pll_out_min == 0) {
1219                         if (ASIC_IS_AVIVO(rdev))
1220                                 mpll->pll_out_min = 64800;
1221                         else
1222                                 mpll->pll_out_min = 20000;
1223                 }
1224
1225                 mpll->pll_in_min =
1226                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1227                 mpll->pll_in_max =
1228                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1229
1230                 rdev->clock.default_sclk =
1231                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1232                 rdev->clock.default_mclk =
1233                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1234
1235                 if (ASIC_IS_DCE4(rdev)) {
1236                         rdev->clock.default_dispclk =
1237                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1238                         if (rdev->clock.default_dispclk == 0) {
1239                                 if (ASIC_IS_DCE6(rdev))
1240                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1241                                 else if (ASIC_IS_DCE5(rdev))
1242                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1243                                 else
1244                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1245                         }
1246                         /* set a reasonable default for DP */
1247                         if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1248                                 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1249                                          rdev->clock.default_dispclk / 100);
1250                                 rdev->clock.default_dispclk = 60000;
1251                         }
1252                         rdev->clock.dp_extclk =
1253                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1254                         rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1255                 }
1256                 *dcpll = *p1pll;
1257
1258                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1259                 if (rdev->clock.max_pixel_clock == 0)
1260                         rdev->clock.max_pixel_clock = 40000;
1261
1262                 /* not technically a clock, but... */
1263                 rdev->mode_info.firmware_flags =
1264                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1265
1266                 if (ASIC_IS_DCE8(rdev)) {
1267                         rdev->clock.gpupll_outputfreq =
1268                                 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1269                         if (rdev->clock.gpupll_outputfreq == 0)
1270                                 rdev->clock.gpupll_outputfreq = 360000; /* 3.6 GHz */
1271                 }
1272
1273                 return true;
1274         }
1275
1276         return false;
1277 }
1278
1279 union igp_info {
1280         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1281         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1282         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1283         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1284         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1285 };
1286
1287 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1288 {
1289         struct radeon_mode_info *mode_info = &rdev->mode_info;
1290         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1291         union igp_info *igp_info;
1292         u8 frev, crev;
1293         u16 data_offset;
1294
1295         /* sideport is AMD only */
1296         if (rdev->family == CHIP_RS600)
1297                 return false;
1298
1299         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1300                                    &frev, &crev, &data_offset)) {
1301                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1302                                       data_offset);
1303                 switch (crev) {
1304                 case 1:
1305                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1306                                 return true;
1307                         break;
1308                 case 2:
1309                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1310                                 return true;
1311                         break;
1312                 default:
1313                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1314                         break;
1315                 }
1316         }
1317         return false;
1318 }
1319
1320 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1321                                    struct radeon_encoder_int_tmds *tmds)
1322 {
1323         struct drm_device *dev = encoder->base.dev;
1324         struct radeon_device *rdev = dev->dev_private;
1325         struct radeon_mode_info *mode_info = &rdev->mode_info;
1326         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1327         uint16_t data_offset;
1328         struct _ATOM_TMDS_INFO *tmds_info;
1329         uint8_t frev, crev;
1330         uint16_t maxfreq;
1331         int i;
1332
1333         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1334                                    &frev, &crev, &data_offset)) {
1335                 tmds_info =
1336                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1337                                                    data_offset);
1338
1339                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1340                 for (i = 0; i < 4; i++) {
1341                         tmds->tmds_pll[i].freq =
1342                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1343                         tmds->tmds_pll[i].value =
1344                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1345                         tmds->tmds_pll[i].value |=
1346                             (tmds_info->asMiscInfo[i].
1347                              ucPLL_VCO_Gain & 0x3f) << 6;
1348                         tmds->tmds_pll[i].value |=
1349                             (tmds_info->asMiscInfo[i].
1350                              ucPLL_DutyCycle & 0xf) << 12;
1351                         tmds->tmds_pll[i].value |=
1352                             (tmds_info->asMiscInfo[i].
1353                              ucPLL_VoltageSwing & 0xf) << 16;
1354
1355                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1356                                   tmds->tmds_pll[i].freq,
1357                                   tmds->tmds_pll[i].value);
1358
1359                         if (maxfreq == tmds->tmds_pll[i].freq) {
1360                                 tmds->tmds_pll[i].freq = 0xffffffff;
1361                                 break;
1362                         }
1363                 }
1364                 return true;
1365         }
1366         return false;
1367 }
1368
1369 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1370                                       struct radeon_atom_ss *ss,
1371                                       int id)
1372 {
1373         struct radeon_mode_info *mode_info = &rdev->mode_info;
1374         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1375         uint16_t data_offset, size;
1376         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1377         struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1378         uint8_t frev, crev;
1379         int i, num_indices;
1380
1381         memset(ss, 0, sizeof(struct radeon_atom_ss));
1382         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1383                                    &frev, &crev, &data_offset)) {
1384                 ss_info =
1385                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1386
1387                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1388                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1389                 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1390                         ((u8 *)&ss_info->asSS_Info[0]);
1391                 for (i = 0; i < num_indices; i++) {
1392                         if (ss_assign->ucSS_Id == id) {
1393                                 ss->percentage =
1394                                         le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1395                                 ss->type = ss_assign->ucSpreadSpectrumType;
1396                                 ss->step = ss_assign->ucSS_Step;
1397                                 ss->delay = ss_assign->ucSS_Delay;
1398                                 ss->range = ss_assign->ucSS_Range;
1399                                 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1400                                 return true;
1401                         }
1402                         ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1403                                 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1404                 }
1405         }
1406         return false;
1407 }
1408
1409 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1410                                                  struct radeon_atom_ss *ss,
1411                                                  int id)
1412 {
1413         struct radeon_mode_info *mode_info = &rdev->mode_info;
1414         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1415         u16 data_offset, size;
1416         union igp_info *igp_info;
1417         u8 frev, crev;
1418         u16 percentage = 0, rate = 0;
1419
1420         /* get any igp specific overrides */
1421         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1422                                    &frev, &crev, &data_offset)) {
1423                 igp_info = (union igp_info *)
1424                         (mode_info->atom_context->bios + data_offset);
1425                 switch (crev) {
1426                 case 6:
1427                         switch (id) {
1428                         case ASIC_INTERNAL_SS_ON_TMDS:
1429                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1430                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1431                                 break;
1432                         case ASIC_INTERNAL_SS_ON_HDMI:
1433                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1434                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1435                                 break;
1436                         case ASIC_INTERNAL_SS_ON_LVDS:
1437                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1438                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1439                                 break;
1440                         }
1441                         break;
1442                 case 7:
1443                         switch (id) {
1444                         case ASIC_INTERNAL_SS_ON_TMDS:
1445                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1446                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1447                                 break;
1448                         case ASIC_INTERNAL_SS_ON_HDMI:
1449                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1450                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1451                                 break;
1452                         case ASIC_INTERNAL_SS_ON_LVDS:
1453                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1454                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1455                                 break;
1456                         }
1457                         break;
1458                 case 8:
1459                         switch (id) {
1460                         case ASIC_INTERNAL_SS_ON_TMDS:
1461                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1462                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1463                                 break;
1464                         case ASIC_INTERNAL_SS_ON_HDMI:
1465                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1466                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1467                                 break;
1468                         case ASIC_INTERNAL_SS_ON_LVDS:
1469                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1470                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1471                                 break;
1472                         }
1473                         break;
1474                 default:
1475                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1476                         break;
1477                 }
1478                 if (percentage)
1479                         ss->percentage = percentage;
1480                 if (rate)
1481                         ss->rate = rate;
1482         }
1483 }
1484
1485 union asic_ss_info {
1486         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1487         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1488         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1489 };
1490
1491 union asic_ss_assignment {
1492         struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1493         struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1494         struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1495 };
1496
1497 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1498                                       struct radeon_atom_ss *ss,
1499                                       int id, u32 clock)
1500 {
1501         struct radeon_mode_info *mode_info = &rdev->mode_info;
1502         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1503         uint16_t data_offset, size;
1504         union asic_ss_info *ss_info;
1505         union asic_ss_assignment *ss_assign;
1506         uint8_t frev, crev;
1507         int i, num_indices;
1508
1509         if (id == ASIC_INTERNAL_MEMORY_SS) {
1510                 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1511                         return false;
1512         }
1513         if (id == ASIC_INTERNAL_ENGINE_SS) {
1514                 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1515                         return false;
1516         }
1517
1518         memset(ss, 0, sizeof(struct radeon_atom_ss));
1519         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1520                                    &frev, &crev, &data_offset)) {
1521
1522                 ss_info =
1523                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1524
1525                 switch (frev) {
1526                 case 1:
1527                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1528                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1529
1530                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1531                         for (i = 0; i < num_indices; i++) {
1532                                 if ((ss_assign->v1.ucClockIndication == id) &&
1533                                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1534                                         ss->percentage =
1535                                                 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1536                                         ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1537                                         ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1538                                         ss->percentage_divider = 100;
1539                                         return true;
1540                                 }
1541                                 ss_assign = (union asic_ss_assignment *)
1542                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1543                         }
1544                         break;
1545                 case 2:
1546                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1547                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1548                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1549                         for (i = 0; i < num_indices; i++) {
1550                                 if ((ss_assign->v2.ucClockIndication == id) &&
1551                                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1552                                         ss->percentage =
1553                                                 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1554                                         ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1555                                         ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1556                                         ss->percentage_divider = 100;
1557                                         if ((crev == 2) &&
1558                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
1559                                              (id == ASIC_INTERNAL_MEMORY_SS)))
1560                                                 ss->rate /= 100;
1561                                         return true;
1562                                 }
1563                                 ss_assign = (union asic_ss_assignment *)
1564                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1565                         }
1566                         break;
1567                 case 3:
1568                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1569                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1570                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1571                         for (i = 0; i < num_indices; i++) {
1572                                 if ((ss_assign->v3.ucClockIndication == id) &&
1573                                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1574                                         ss->percentage =
1575                                                 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1576                                         ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1577                                         ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1578                                         if (ss_assign->v3.ucSpreadSpectrumMode &
1579                                             SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1580                                                 ss->percentage_divider = 1000;
1581                                         else
1582                                                 ss->percentage_divider = 100;
1583                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1584                                             (id == ASIC_INTERNAL_MEMORY_SS))
1585                                                 ss->rate /= 100;
1586                                         if (rdev->flags & RADEON_IS_IGP)
1587                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1588                                         return true;
1589                                 }
1590                                 ss_assign = (union asic_ss_assignment *)
1591                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1592                         }
1593                         break;
1594                 default:
1595                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1596                         break;
1597                 }
1598
1599         }
1600         return false;
1601 }
1602
1603 union lvds_info {
1604         struct _ATOM_LVDS_INFO info;
1605         struct _ATOM_LVDS_INFO_V12 info_12;
1606 };
1607
1608 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1609                                                               radeon_encoder
1610                                                               *encoder)
1611 {
1612         struct drm_device *dev = encoder->base.dev;
1613         struct radeon_device *rdev = dev->dev_private;
1614         struct radeon_mode_info *mode_info = &rdev->mode_info;
1615         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1616         uint16_t data_offset, misc;
1617         union lvds_info *lvds_info;
1618         uint8_t frev, crev;
1619         struct radeon_encoder_atom_dig *lvds = NULL;
1620         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1621
1622         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1623                                    &frev, &crev, &data_offset)) {
1624                 lvds_info =
1625                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1626                 lvds =
1627                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1628
1629                 if (!lvds)
1630                         return NULL;
1631
1632                 lvds->native_mode.clock =
1633                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1634                 lvds->native_mode.hdisplay =
1635                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1636                 lvds->native_mode.vdisplay =
1637                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1638                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1639                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1640                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1641                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1642                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1643                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1644                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1645                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1646                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1647                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1648                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1649                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1650                 lvds->panel_pwr_delay =
1651                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1652                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1653
1654                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1655                 if (misc & ATOM_VSYNC_POLARITY)
1656                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1657                 if (misc & ATOM_HSYNC_POLARITY)
1658                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1659                 if (misc & ATOM_COMPOSITESYNC)
1660                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1661                 if (misc & ATOM_INTERLACE)
1662                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1663                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1664                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1665
1666                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1667                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1668
1669                 /* set crtc values */
1670                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1671
1672                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1673
1674                 encoder->native_mode = lvds->native_mode;
1675
1676                 if (encoder_enum == 2)
1677                         lvds->linkb = true;
1678                 else
1679                         lvds->linkb = false;
1680
1681                 /* parse the lcd record table */
1682                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1683                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1684                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1685                         bool bad_record = false;
1686                         u8 *record;
1687
1688                         if ((frev == 1) && (crev < 2))
1689                                 /* absolute */
1690                                 record = (u8 *)(mode_info->atom_context->bios +
1691                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1692                         else
1693                                 /* relative */
1694                                 record = (u8 *)(mode_info->atom_context->bios +
1695                                                 data_offset +
1696                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1697                         while (*record != ATOM_RECORD_END_TYPE) {
1698                                 switch (*record) {
1699                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1700                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1701                                         break;
1702                                 case LCD_RTS_RECORD_TYPE:
1703                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1704                                         break;
1705                                 case LCD_CAP_RECORD_TYPE:
1706                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1707                                         break;
1708                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1709                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1710                                         if (fake_edid_record->ucFakeEDIDLength) {
1711                                                 struct edid *edid;
1712                                                 int edid_size =
1713                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1714                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1715                                                 if (edid) {
1716                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1717                                                                fake_edid_record->ucFakeEDIDLength);
1718
1719                                                         if (drm_edid_is_valid(edid)) {
1720                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1721                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1722                                                         } else
1723                                                                 kfree(edid);
1724                                                 }
1725                                         }
1726                                         record += fake_edid_record->ucFakeEDIDLength ?
1727                                                 fake_edid_record->ucFakeEDIDLength + 2 :
1728                                                 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1729                                         break;
1730                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1731                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1732                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1733                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1734                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1735                                         break;
1736                                 default:
1737                                         DRM_ERROR("Bad LCD record %d\n", *record);
1738                                         bad_record = true;
1739                                         break;
1740                                 }
1741                                 if (bad_record)
1742                                         break;
1743                         }
1744                 }
1745         }
1746         return lvds;
1747 }
1748
1749 struct radeon_encoder_primary_dac *
1750 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1751 {
1752         struct drm_device *dev = encoder->base.dev;
1753         struct radeon_device *rdev = dev->dev_private;
1754         struct radeon_mode_info *mode_info = &rdev->mode_info;
1755         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1756         uint16_t data_offset;
1757         struct _COMPASSIONATE_DATA *dac_info;
1758         uint8_t frev, crev;
1759         uint8_t bg, dac;
1760         struct radeon_encoder_primary_dac *p_dac = NULL;
1761
1762         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1763                                    &frev, &crev, &data_offset)) {
1764                 dac_info = (struct _COMPASSIONATE_DATA *)
1765                         (mode_info->atom_context->bios + data_offset);
1766
1767                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1768
1769                 if (!p_dac)
1770                         return NULL;
1771
1772                 bg = dac_info->ucDAC1_BG_Adjustment;
1773                 dac = dac_info->ucDAC1_DAC_Adjustment;
1774                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1775
1776         }
1777         return p_dac;
1778 }
1779
1780 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1781                                 struct drm_display_mode *mode)
1782 {
1783         struct radeon_mode_info *mode_info = &rdev->mode_info;
1784         ATOM_ANALOG_TV_INFO *tv_info;
1785         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1786         ATOM_DTD_FORMAT *dtd_timings;
1787         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1788         u8 frev, crev;
1789         u16 data_offset, misc;
1790
1791         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1792                                     &frev, &crev, &data_offset))
1793                 return false;
1794
1795         switch (crev) {
1796         case 1:
1797                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1798                 if (index >= MAX_SUPPORTED_TV_TIMING)
1799                         return false;
1800
1801                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1802                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1803                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1804                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1805                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1806
1807                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1808                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1809                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1810                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1811                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1812
1813                 mode->flags = 0;
1814                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1815                 if (misc & ATOM_VSYNC_POLARITY)
1816                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1817                 if (misc & ATOM_HSYNC_POLARITY)
1818                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1819                 if (misc & ATOM_COMPOSITESYNC)
1820                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1821                 if (misc & ATOM_INTERLACE)
1822                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1823                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1824                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1825
1826                 mode->crtc_clock = mode->clock =
1827                         le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1828
1829                 if (index == 1) {
1830                         /* PAL timings appear to have wrong values for totals */
1831                         mode->crtc_htotal -= 1;
1832                         mode->crtc_vtotal -= 1;
1833                 }
1834                 break;
1835         case 2:
1836                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1837                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1838                         return false;
1839
1840                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1841                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1842                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1843                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1844                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1845                         le16_to_cpu(dtd_timings->usHSyncOffset);
1846                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1847                         le16_to_cpu(dtd_timings->usHSyncWidth);
1848
1849                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1850                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1851                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1852                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1853                         le16_to_cpu(dtd_timings->usVSyncOffset);
1854                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1855                         le16_to_cpu(dtd_timings->usVSyncWidth);
1856
1857                 mode->flags = 0;
1858                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1859                 if (misc & ATOM_VSYNC_POLARITY)
1860                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1861                 if (misc & ATOM_HSYNC_POLARITY)
1862                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1863                 if (misc & ATOM_COMPOSITESYNC)
1864                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1865                 if (misc & ATOM_INTERLACE)
1866                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1867                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1868                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1869
1870                 mode->crtc_clock = mode->clock =
1871                         le16_to_cpu(dtd_timings->usPixClk) * 10;
1872                 break;
1873         }
1874         return true;
1875 }
1876
1877 enum radeon_tv_std
1878 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1879 {
1880         struct radeon_mode_info *mode_info = &rdev->mode_info;
1881         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1882         uint16_t data_offset;
1883         uint8_t frev, crev;
1884         struct _ATOM_ANALOG_TV_INFO *tv_info;
1885         enum radeon_tv_std tv_std = TV_STD_NTSC;
1886
1887         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1888                                    &frev, &crev, &data_offset)) {
1889
1890                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1891                         (mode_info->atom_context->bios + data_offset);
1892
1893                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1894                 case ATOM_TV_NTSC:
1895                         tv_std = TV_STD_NTSC;
1896                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1897                         break;
1898                 case ATOM_TV_NTSCJ:
1899                         tv_std = TV_STD_NTSC_J;
1900                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1901                         break;
1902                 case ATOM_TV_PAL:
1903                         tv_std = TV_STD_PAL;
1904                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1905                         break;
1906                 case ATOM_TV_PALM:
1907                         tv_std = TV_STD_PAL_M;
1908                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1909                         break;
1910                 case ATOM_TV_PALN:
1911                         tv_std = TV_STD_PAL_N;
1912                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1913                         break;
1914                 case ATOM_TV_PALCN:
1915                         tv_std = TV_STD_PAL_CN;
1916                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1917                         break;
1918                 case ATOM_TV_PAL60:
1919                         tv_std = TV_STD_PAL_60;
1920                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1921                         break;
1922                 case ATOM_TV_SECAM:
1923                         tv_std = TV_STD_SECAM;
1924                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1925                         break;
1926                 default:
1927                         tv_std = TV_STD_NTSC;
1928                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1929                         break;
1930                 }
1931         }
1932         return tv_std;
1933 }
1934
1935 struct radeon_encoder_tv_dac *
1936 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1937 {
1938         struct drm_device *dev = encoder->base.dev;
1939         struct radeon_device *rdev = dev->dev_private;
1940         struct radeon_mode_info *mode_info = &rdev->mode_info;
1941         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1942         uint16_t data_offset;
1943         struct _COMPASSIONATE_DATA *dac_info;
1944         uint8_t frev, crev;
1945         uint8_t bg, dac;
1946         struct radeon_encoder_tv_dac *tv_dac = NULL;
1947
1948         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1949                                    &frev, &crev, &data_offset)) {
1950
1951                 dac_info = (struct _COMPASSIONATE_DATA *)
1952                         (mode_info->atom_context->bios + data_offset);
1953
1954                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1955
1956                 if (!tv_dac)
1957                         return NULL;
1958
1959                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1960                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1961                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1962
1963                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1964                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1965                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1966
1967                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1968                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1969                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1970
1971                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1972         }
1973         return tv_dac;
1974 }
1975
1976 static const char *thermal_controller_names[] = {
1977         "NONE",
1978         "lm63",
1979         "adm1032",
1980         "adm1030",
1981         "max6649",
1982         "lm63", /* lm64 */
1983         "f75375",
1984         "asc7xxx",
1985 };
1986
1987 static const char *pp_lib_thermal_controller_names[] = {
1988         "NONE",
1989         "lm63",
1990         "adm1032",
1991         "adm1030",
1992         "max6649",
1993         "lm63", /* lm64 */
1994         "f75375",
1995         "RV6xx",
1996         "RV770",
1997         "adt7473",
1998         "NONE",
1999         "External GPIO",
2000         "Evergreen",
2001         "emc2103",
2002         "Sumo",
2003         "Northern Islands",
2004         "Southern Islands",
2005         "lm96163",
2006         "Sea Islands",
2007 };
2008
2009 union power_info {
2010         struct _ATOM_POWERPLAY_INFO info;
2011         struct _ATOM_POWERPLAY_INFO_V2 info_2;
2012         struct _ATOM_POWERPLAY_INFO_V3 info_3;
2013         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2014         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2015         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2016 };
2017
2018 union pplib_clock_info {
2019         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2020         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2021         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2022         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2023         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2024         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2025 };
2026
2027 union pplib_power_state {
2028         struct _ATOM_PPLIB_STATE v1;
2029         struct _ATOM_PPLIB_STATE_V2 v2;
2030 };
2031
2032 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2033                                                  int state_index,
2034                                                  u32 misc, u32 misc2)
2035 {
2036         rdev->pm.power_state[state_index].misc = misc;
2037         rdev->pm.power_state[state_index].misc2 = misc2;
2038         /* order matters! */
2039         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2040                 rdev->pm.power_state[state_index].type =
2041                         POWER_STATE_TYPE_POWERSAVE;
2042         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2043                 rdev->pm.power_state[state_index].type =
2044                         POWER_STATE_TYPE_BATTERY;
2045         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2046                 rdev->pm.power_state[state_index].type =
2047                         POWER_STATE_TYPE_BATTERY;
2048         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2049                 rdev->pm.power_state[state_index].type =
2050                         POWER_STATE_TYPE_BALANCED;
2051         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2052                 rdev->pm.power_state[state_index].type =
2053                         POWER_STATE_TYPE_PERFORMANCE;
2054                 rdev->pm.power_state[state_index].flags &=
2055                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2056         }
2057         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2058                 rdev->pm.power_state[state_index].type =
2059                         POWER_STATE_TYPE_BALANCED;
2060         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2061                 rdev->pm.power_state[state_index].type =
2062                         POWER_STATE_TYPE_DEFAULT;
2063                 rdev->pm.default_power_state_index = state_index;
2064                 rdev->pm.power_state[state_index].default_clock_mode =
2065                         &rdev->pm.power_state[state_index].clock_info[0];
2066         } else if (state_index == 0) {
2067                 rdev->pm.power_state[state_index].clock_info[0].flags |=
2068                         RADEON_PM_MODE_NO_DISPLAY;
2069         }
2070 }
2071
2072 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2073 {
2074         struct radeon_mode_info *mode_info = &rdev->mode_info;
2075         u32 misc, misc2 = 0;
2076         int num_modes = 0, i;
2077         int state_index = 0;
2078         struct radeon_i2c_bus_rec i2c_bus;
2079         union power_info *power_info;
2080         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2081         u16 data_offset;
2082         u8 frev, crev;
2083
2084         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2085                                    &frev, &crev, &data_offset))
2086                 return state_index;
2087         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2088
2089         /* add the i2c bus for thermal/fan chip */
2090         if ((power_info->info.ucOverdriveThermalController > 0) &&
2091             (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2092                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2093                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
2094                          power_info->info.ucOverdriveControllerAddress >> 1);
2095                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2096                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2097                 if (rdev->pm.i2c_bus) {
2098                         struct i2c_board_info info = { };
2099                         const char *name = thermal_controller_names[power_info->info.
2100                                                                     ucOverdriveThermalController];
2101                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2102                         strlcpy(info.type, name, sizeof(info.type));
2103                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2104                 }
2105         }
2106         num_modes = power_info->info.ucNumOfPowerModeEntries;
2107         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2108                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2109         if (num_modes == 0)
2110                 return state_index;
2111         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2112         if (!rdev->pm.power_state)
2113                 return state_index;
2114         /* last mode is usually default, array is low to high */
2115         for (i = 0; i < num_modes; i++) {
2116                 rdev->pm.power_state[state_index].clock_info =
2117                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2118                 if (!rdev->pm.power_state[state_index].clock_info)
2119                         return state_index;
2120                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2121                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2122                 switch (frev) {
2123                 case 1:
2124                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2125                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2126                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2127                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2128                         /* skip invalid modes */
2129                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2130                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2131                                 continue;
2132                         rdev->pm.power_state[state_index].pcie_lanes =
2133                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2134                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2135                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2136                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2137                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2138                                         VOLTAGE_GPIO;
2139                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2140                                         radeon_atombios_lookup_gpio(rdev,
2141                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2142                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2143                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2144                                                 true;
2145                                 else
2146                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2147                                                 false;
2148                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2149                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2150                                         VOLTAGE_VDDC;
2151                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2152                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2153                         }
2154                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2155                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2156                         state_index++;
2157                         break;
2158                 case 2:
2159                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2160                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2161                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2162                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2163                         /* skip invalid modes */
2164                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2165                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2166                                 continue;
2167                         rdev->pm.power_state[state_index].pcie_lanes =
2168                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2169                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2170                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2171                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2172                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2173                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2174                                         VOLTAGE_GPIO;
2175                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2176                                         radeon_atombios_lookup_gpio(rdev,
2177                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2178                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2179                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2180                                                 true;
2181                                 else
2182                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2183                                                 false;
2184                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2185                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2186                                         VOLTAGE_VDDC;
2187                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2188                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2189                         }
2190                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2191                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2192                         state_index++;
2193                         break;
2194                 case 3:
2195                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2196                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2197                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2198                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2199                         /* skip invalid modes */
2200                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2201                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2202                                 continue;
2203                         rdev->pm.power_state[state_index].pcie_lanes =
2204                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2205                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2206                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2207                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2208                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2209                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2210                                         VOLTAGE_GPIO;
2211                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2212                                         radeon_atombios_lookup_gpio(rdev,
2213                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2214                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2215                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2216                                                 true;
2217                                 else
2218                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2219                                                 false;
2220                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2221                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2222                                         VOLTAGE_VDDC;
2223                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2224                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2225                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2226                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2227                                                 true;
2228                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2229                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2230                                 }
2231                         }
2232                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2233                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2234                         state_index++;
2235                         break;
2236                 }
2237         }
2238         /* last mode is usually default */
2239         if (rdev->pm.default_power_state_index == -1) {
2240                 rdev->pm.power_state[state_index - 1].type =
2241                         POWER_STATE_TYPE_DEFAULT;
2242                 rdev->pm.default_power_state_index = state_index - 1;
2243                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2244                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2245                 rdev->pm.power_state[state_index].flags &=
2246                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2247                 rdev->pm.power_state[state_index].misc = 0;
2248                 rdev->pm.power_state[state_index].misc2 = 0;
2249         }
2250         return state_index;
2251 }
2252
2253 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2254                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2255 {
2256         struct radeon_i2c_bus_rec i2c_bus;
2257
2258         /* add the i2c bus for thermal/fan chip */
2259         if (controller->ucType > 0) {
2260                 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2261                         rdev->pm.no_fan = true;
2262                 rdev->pm.fan_pulses_per_revolution =
2263                         controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2264                 if (rdev->pm.fan_pulses_per_revolution) {
2265                         rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2266                         rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2267                 }
2268                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2269                         DRM_INFO("Internal thermal controller %s fan control\n",
2270                                  (controller->ucFanParameters &
2271                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2272                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2273                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2274                         DRM_INFO("Internal thermal controller %s fan control\n",
2275                                  (controller->ucFanParameters &
2276                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2277                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2278                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2279                         DRM_INFO("Internal thermal controller %s fan control\n",
2280                                  (controller->ucFanParameters &
2281                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2282                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2283                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2284                         DRM_INFO("Internal thermal controller %s fan control\n",
2285                                  (controller->ucFanParameters &
2286                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2287                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2288                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2289                         DRM_INFO("Internal thermal controller %s fan control\n",
2290                                  (controller->ucFanParameters &
2291                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2292                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2293                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2294                         DRM_INFO("Internal thermal controller %s fan control\n",
2295                                  (controller->ucFanParameters &
2296                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2297                         rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2298                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2299                         DRM_INFO("Internal thermal controller %s fan control\n",
2300                                  (controller->ucFanParameters &
2301                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2302                         rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2303                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2304                         DRM_INFO("Internal thermal controller %s fan control\n",
2305                                  (controller->ucFanParameters &
2306                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2307                         rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2308                 } else if (controller->ucType ==
2309                            ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2310                         DRM_INFO("External GPIO thermal controller %s fan control\n",
2311                                  (controller->ucFanParameters &
2312                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2313                         rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2314                 } else if (controller->ucType ==
2315                            ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2316                         DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2317                                  (controller->ucFanParameters &
2318                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2319                         rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2320                 } else if (controller->ucType ==
2321                            ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2322                         DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2323                                  (controller->ucFanParameters &
2324                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2325                         rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2326                 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2327                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2328                                  pp_lib_thermal_controller_names[controller->ucType],
2329                                  controller->ucI2cAddress >> 1,
2330                                  (controller->ucFanParameters &
2331                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2332                         rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2333                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2334                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2335                         if (rdev->pm.i2c_bus) {
2336                                 struct i2c_board_info info = { };
2337                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2338                                 info.addr = controller->ucI2cAddress >> 1;
2339                                 strlcpy(info.type, name, sizeof(info.type));
2340                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2341                         }
2342                 } else {
2343                         DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2344                                  controller->ucType,
2345                                  controller->ucI2cAddress >> 1,
2346                                  (controller->ucFanParameters &
2347                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2348                 }
2349         }
2350 }
2351
2352 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2353                                           u16 *vddc, u16 *vddci, u16 *mvdd)
2354 {
2355         struct radeon_mode_info *mode_info = &rdev->mode_info;
2356         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2357         u8 frev, crev;
2358         u16 data_offset;
2359         union firmware_info *firmware_info;
2360
2361         *vddc = 0;
2362         *vddci = 0;
2363         *mvdd = 0;
2364
2365         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2366                                    &frev, &crev, &data_offset)) {
2367                 firmware_info =
2368                         (union firmware_info *)(mode_info->atom_context->bios +
2369                                                 data_offset);
2370                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2371                 if ((frev == 2) && (crev >= 2)) {
2372                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2373                         *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2374                 }
2375         }
2376 }
2377
2378 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2379                                                        int state_index, int mode_index,
2380                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2381 {
2382         int j;
2383         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2384         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2385         u16 vddc, vddci, mvdd;
2386
2387         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2388
2389         rdev->pm.power_state[state_index].misc = misc;
2390         rdev->pm.power_state[state_index].misc2 = misc2;
2391         rdev->pm.power_state[state_index].pcie_lanes =
2392                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2393                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2394         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2395         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2396                 rdev->pm.power_state[state_index].type =
2397                         POWER_STATE_TYPE_BATTERY;
2398                 break;
2399         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2400                 rdev->pm.power_state[state_index].type =
2401                         POWER_STATE_TYPE_BALANCED;
2402                 break;
2403         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2404                 rdev->pm.power_state[state_index].type =
2405                         POWER_STATE_TYPE_PERFORMANCE;
2406                 break;
2407         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2408                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2409                         rdev->pm.power_state[state_index].type =
2410                                 POWER_STATE_TYPE_PERFORMANCE;
2411                 break;
2412         }
2413         rdev->pm.power_state[state_index].flags = 0;
2414         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2415                 rdev->pm.power_state[state_index].flags |=
2416                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2417         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2418                 rdev->pm.power_state[state_index].type =
2419                         POWER_STATE_TYPE_DEFAULT;
2420                 rdev->pm.default_power_state_index = state_index;
2421                 rdev->pm.power_state[state_index].default_clock_mode =
2422                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2423                 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2424                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2425                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2426                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2427                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2428                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2429                 } else {
2430                         u16 max_vddci = 0;
2431
2432                         if (ASIC_IS_DCE4(rdev))
2433                                 radeon_atom_get_max_voltage(rdev,
2434                                                             SET_VOLTAGE_TYPE_ASIC_VDDCI,
2435                                                             &max_vddci);
2436                         /* patch the table values with the default sclk/mclk from firmware info */
2437                         for (j = 0; j < mode_index; j++) {
2438                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2439                                         rdev->clock.default_mclk;
2440                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2441                                         rdev->clock.default_sclk;
2442                                 if (vddc)
2443                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2444                                                 vddc;
2445                                 if (max_vddci)
2446                                         rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2447                                                 max_vddci;
2448                         }
2449                 }
2450         }
2451 }
2452
2453 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2454                                                    int state_index, int mode_index,
2455                                                    union pplib_clock_info *clock_info)
2456 {
2457         u32 sclk, mclk;
2458         u16 vddc;
2459
2460         if (rdev->flags & RADEON_IS_IGP) {
2461                 if (rdev->family >= CHIP_PALM) {
2462                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2463                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2464                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2465                 } else {
2466                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2467                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2468                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2469                 }
2470         } else if (rdev->family >= CHIP_BONAIRE) {
2471                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2472                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2473                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2474                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2475                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2476                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2477                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2478                         VOLTAGE_NONE;
2479         } else if (rdev->family >= CHIP_TAHITI) {
2480                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2481                 sclk |= clock_info->si.ucEngineClockHigh << 16;
2482                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2483                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2484                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2485                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2486                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2487                         VOLTAGE_SW;
2488                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2489                         le16_to_cpu(clock_info->si.usVDDC);
2490                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2491                         le16_to_cpu(clock_info->si.usVDDCI);
2492         } else if (rdev->family >= CHIP_CEDAR) {
2493                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2494                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2495                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2496                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2497                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2498                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2499                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2500                         VOLTAGE_SW;
2501                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2502                         le16_to_cpu(clock_info->evergreen.usVDDC);
2503                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2504                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2505         } else {
2506                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2507                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2508                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2509                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2510                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2511                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2512                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2513                         VOLTAGE_SW;
2514                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2515                         le16_to_cpu(clock_info->r600.usVDDC);
2516         }
2517
2518         /* patch up vddc if necessary */
2519         switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2520         case ATOM_VIRTUAL_VOLTAGE_ID0:
2521         case ATOM_VIRTUAL_VOLTAGE_ID1:
2522         case ATOM_VIRTUAL_VOLTAGE_ID2:
2523         case ATOM_VIRTUAL_VOLTAGE_ID3:
2524         case ATOM_VIRTUAL_VOLTAGE_ID4:
2525         case ATOM_VIRTUAL_VOLTAGE_ID5:
2526         case ATOM_VIRTUAL_VOLTAGE_ID6:
2527         case ATOM_VIRTUAL_VOLTAGE_ID7:
2528                 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2529                                              rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2530                                              &vddc) == 0)
2531                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2532                 break;
2533         default:
2534                 break;
2535         }
2536
2537         if (rdev->flags & RADEON_IS_IGP) {
2538                 /* skip invalid modes */
2539                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2540                         return false;
2541         } else {
2542                 /* skip invalid modes */
2543                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2544                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2545                         return false;
2546         }
2547         return true;
2548 }
2549
2550 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2551 {
2552         struct radeon_mode_info *mode_info = &rdev->mode_info;
2553         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2554         union pplib_power_state *power_state;
2555         int i, j;
2556         int state_index = 0, mode_index = 0;
2557         union pplib_clock_info *clock_info;
2558         bool valid;
2559         union power_info *power_info;
2560         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2561         u16 data_offset;
2562         u8 frev, crev;
2563
2564         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2565                                    &frev, &crev, &data_offset))
2566                 return state_index;
2567         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2568
2569         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2570         if (power_info->pplib.ucNumStates == 0)
2571                 return state_index;
2572         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2573                                        power_info->pplib.ucNumStates, GFP_KERNEL);
2574         if (!rdev->pm.power_state)
2575                 return state_index;
2576         /* first mode is usually default, followed by low to high */
2577         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2578                 mode_index = 0;
2579                 power_state = (union pplib_power_state *)
2580                         (mode_info->atom_context->bios + data_offset +
2581                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2582                          i * power_info->pplib.ucStateEntrySize);
2583                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2584                         (mode_info->atom_context->bios + data_offset +
2585                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2586                          (power_state->v1.ucNonClockStateIndex *
2587                           power_info->pplib.ucNonClockSize));
2588                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2589                                                              ((power_info->pplib.ucStateEntrySize - 1) ?
2590                                                               (power_info->pplib.ucStateEntrySize - 1) : 1),
2591                                                              GFP_KERNEL);
2592                 if (!rdev->pm.power_state[i].clock_info)
2593                         return state_index;
2594                 if (power_info->pplib.ucStateEntrySize - 1) {
2595                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2596                                 clock_info = (union pplib_clock_info *)
2597                                         (mode_info->atom_context->bios + data_offset +
2598                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2599                                          (power_state->v1.ucClockStateIndices[j] *
2600                                           power_info->pplib.ucClockInfoSize));
2601                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2602                                                                                state_index, mode_index,
2603                                                                                clock_info);
2604                                 if (valid)
2605                                         mode_index++;
2606                         }
2607                 } else {
2608                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2609                                 rdev->clock.default_mclk;
2610                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2611                                 rdev->clock.default_sclk;
2612                         mode_index++;
2613                 }
2614                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2615                 if (mode_index) {
2616                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2617                                                                    non_clock_info);
2618                         state_index++;
2619                 }
2620         }
2621         /* if multiple clock modes, mark the lowest as no display */
2622         for (i = 0; i < state_index; i++) {
2623                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2624                         rdev->pm.power_state[i].clock_info[0].flags |=
2625                                 RADEON_PM_MODE_NO_DISPLAY;
2626         }
2627         /* first mode is usually default */
2628         if (rdev->pm.default_power_state_index == -1) {
2629                 rdev->pm.power_state[0].type =
2630                         POWER_STATE_TYPE_DEFAULT;
2631                 rdev->pm.default_power_state_index = 0;
2632                 rdev->pm.power_state[0].default_clock_mode =
2633                         &rdev->pm.power_state[0].clock_info[0];
2634         }
2635         return state_index;
2636 }
2637
2638 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2639 {
2640         struct radeon_mode_info *mode_info = &rdev->mode_info;
2641         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2642         union pplib_power_state *power_state;
2643         int i, j, non_clock_array_index, clock_array_index;
2644         int state_index = 0, mode_index = 0;
2645         union pplib_clock_info *clock_info;
2646         struct _StateArray *state_array;
2647         struct _ClockInfoArray *clock_info_array;
2648         struct _NonClockInfoArray *non_clock_info_array;
2649         bool valid;
2650         union power_info *power_info;
2651         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2652         u16 data_offset;
2653         u8 frev, crev;
2654         u8 *power_state_offset;
2655
2656         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2657                                    &frev, &crev, &data_offset))
2658                 return state_index;
2659         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2660
2661         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2662         state_array = (struct _StateArray *)
2663                 (mode_info->atom_context->bios + data_offset +
2664                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2665         clock_info_array = (struct _ClockInfoArray *)
2666                 (mode_info->atom_context->bios + data_offset +
2667                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2668         non_clock_info_array = (struct _NonClockInfoArray *)
2669                 (mode_info->atom_context->bios + data_offset +
2670                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2671         if (state_array->ucNumEntries == 0)
2672                 return state_index;
2673         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2674                                        state_array->ucNumEntries, GFP_KERNEL);
2675         if (!rdev->pm.power_state)
2676                 return state_index;
2677         power_state_offset = (u8 *)state_array->states;
2678         for (i = 0; i < state_array->ucNumEntries; i++) {
2679                 mode_index = 0;
2680                 power_state = (union pplib_power_state *)power_state_offset;
2681                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2682                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2683                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2684                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2685                                                              (power_state->v2.ucNumDPMLevels ?
2686                                                               power_state->v2.ucNumDPMLevels : 1),
2687                                                              GFP_KERNEL);
2688                 if (!rdev->pm.power_state[i].clock_info)
2689                         return state_index;
2690                 if (power_state->v2.ucNumDPMLevels) {
2691                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2692                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2693                                 clock_info = (union pplib_clock_info *)
2694                                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2695                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2696                                                                                state_index, mode_index,
2697                                                                                clock_info);
2698                                 if (valid)
2699                                         mode_index++;
2700                         }
2701                 } else {
2702                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2703                                 rdev->clock.default_mclk;
2704                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2705                                 rdev->clock.default_sclk;
2706                         mode_index++;
2707                 }
2708                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2709                 if (mode_index) {
2710                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2711                                                                    non_clock_info);
2712                         state_index++;
2713                 }
2714                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2715         }
2716         /* if multiple clock modes, mark the lowest as no display */
2717         for (i = 0; i < state_index; i++) {
2718                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2719                         rdev->pm.power_state[i].clock_info[0].flags |=
2720                                 RADEON_PM_MODE_NO_DISPLAY;
2721         }
2722         /* first mode is usually default */
2723         if (rdev->pm.default_power_state_index == -1) {
2724                 rdev->pm.power_state[0].type =
2725                         POWER_STATE_TYPE_DEFAULT;
2726                 rdev->pm.default_power_state_index = 0;
2727                 rdev->pm.power_state[0].default_clock_mode =
2728                         &rdev->pm.power_state[0].clock_info[0];
2729         }
2730         return state_index;
2731 }
2732
2733 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2734 {
2735         struct radeon_mode_info *mode_info = &rdev->mode_info;
2736         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2737         u16 data_offset;
2738         u8 frev, crev;
2739         int state_index = 0;
2740
2741         rdev->pm.default_power_state_index = -1;
2742
2743         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2744                                    &frev, &crev, &data_offset)) {
2745                 switch (frev) {
2746                 case 1:
2747                 case 2:
2748                 case 3:
2749                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2750                         break;
2751                 case 4:
2752                 case 5:
2753                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2754                         break;
2755                 case 6:
2756                         state_index = radeon_atombios_parse_power_table_6(rdev);
2757                         break;
2758                 default:
2759                         break;
2760                 }
2761         }
2762
2763         if (state_index == 0) {
2764                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2765                 if (rdev->pm.power_state) {
2766                         rdev->pm.power_state[0].clock_info =
2767                                 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2768                         if (rdev->pm.power_state[0].clock_info) {
2769                                 /* add the default mode */
2770                                 rdev->pm.power_state[state_index].type =
2771                                         POWER_STATE_TYPE_DEFAULT;
2772                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2773                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2774                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2775                                 rdev->pm.power_state[state_index].default_clock_mode =
2776                                         &rdev->pm.power_state[state_index].clock_info[0];
2777                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2778                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2779                                 rdev->pm.default_power_state_index = state_index;
2780                                 rdev->pm.power_state[state_index].flags = 0;
2781                                 state_index++;
2782                         }
2783                 }
2784         }
2785
2786         rdev->pm.num_power_states = state_index;
2787
2788         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2789         rdev->pm.current_clock_mode_index = 0;
2790         if (rdev->pm.default_power_state_index >= 0)
2791                 rdev->pm.current_vddc =
2792                         rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2793         else
2794                 rdev->pm.current_vddc = 0;
2795 }
2796
2797 union get_clock_dividers {
2798         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2799         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2800         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2801         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2802         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2803         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2804         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2805 };
2806
2807 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2808                                    u8 clock_type,
2809                                    u32 clock,
2810                                    bool strobe_mode,
2811                                    struct atom_clock_dividers *dividers)
2812 {
2813         union get_clock_dividers args;
2814         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2815         u8 frev, crev;
2816
2817         memset(&args, 0, sizeof(args));
2818         memset(dividers, 0, sizeof(struct atom_clock_dividers));
2819
2820         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2821                 return -EINVAL;
2822
2823         switch (crev) {
2824         case 1:
2825                 /* r4xx, r5xx */
2826                 args.v1.ucAction = clock_type;
2827                 args.v1.ulClock = cpu_to_le32(clock);   /* 10 khz */
2828
2829                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2830
2831                 dividers->post_div = args.v1.ucPostDiv;
2832                 dividers->fb_div = args.v1.ucFbDiv;
2833                 dividers->enable_post_div = true;
2834                 break;
2835         case 2:
2836         case 3:
2837         case 5:
2838                 /* r6xx, r7xx, evergreen, ni, si */
2839                 if (rdev->family <= CHIP_RV770) {
2840                         args.v2.ucAction = clock_type;
2841                         args.v2.ulClock = cpu_to_le32(clock);   /* 10 khz */
2842
2843                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2844
2845                         dividers->post_div = args.v2.ucPostDiv;
2846                         dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2847                         dividers->ref_div = args.v2.ucAction;
2848                         if (rdev->family == CHIP_RV770) {
2849                                 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2850                                         true : false;
2851                                 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2852                         } else
2853                                 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2854                 } else {
2855                         if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2856                                 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2857
2858                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2859
2860                                 dividers->post_div = args.v3.ucPostDiv;
2861                                 dividers->enable_post_div = (args.v3.ucCntlFlag &
2862                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2863                                 dividers->enable_dithen = (args.v3.ucCntlFlag &
2864                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2865                                 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2866                                 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2867                                 dividers->ref_div = args.v3.ucRefDiv;
2868                                 dividers->vco_mode = (args.v3.ucCntlFlag &
2869                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2870                         } else {
2871                                 /* for SI we use ComputeMemoryClockParam for memory plls */
2872                                 if (rdev->family >= CHIP_TAHITI)
2873                                         return -EINVAL;
2874                                 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2875                                 if (strobe_mode)
2876                                         args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2877
2878                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2879
2880                                 dividers->post_div = args.v5.ucPostDiv;
2881                                 dividers->enable_post_div = (args.v5.ucCntlFlag &
2882                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2883                                 dividers->enable_dithen = (args.v5.ucCntlFlag &
2884                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2885                                 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2886                                 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2887                                 dividers->ref_div = args.v5.ucRefDiv;
2888                                 dividers->vco_mode = (args.v5.ucCntlFlag &
2889                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2890                         }
2891                 }
2892                 break;
2893         case 4:
2894                 /* fusion */
2895                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
2896
2897                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2898
2899                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2900                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2901                 break;
2902         case 6:
2903                 /* CI */
2904                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2905                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2906                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
2907
2908                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2909
2910                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2911                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2912                 dividers->ref_div = args.v6_out.ucPllRefDiv;
2913                 dividers->post_div = args.v6_out.ucPllPostDiv;
2914                 dividers->flags = args.v6_out.ucPllCntlFlag;
2915                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2916                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2917                 break;
2918         default:
2919                 return -EINVAL;
2920         }
2921         return 0;
2922 }
2923
2924 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2925                                         u32 clock,
2926                                         bool strobe_mode,
2927                                         struct atom_mpll_param *mpll_param)
2928 {
2929         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2930         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2931         u8 frev, crev;
2932
2933         memset(&args, 0, sizeof(args));
2934         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2935
2936         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2937                 return -EINVAL;
2938
2939         switch (frev) {
2940         case 2:
2941                 switch (crev) {
2942                 case 1:
2943                         /* SI */
2944                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
2945                         args.ucInputFlag = 0;
2946                         if (strobe_mode)
2947                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2948
2949                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2950
2951                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2952                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2953                         mpll_param->post_div = args.ucPostDiv;
2954                         mpll_param->dll_speed = args.ucDllSpeed;
2955                         mpll_param->bwcntl = args.ucBWCntl;
2956                         mpll_param->vco_mode =
2957                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2958                         mpll_param->yclk_sel =
2959                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2960                         mpll_param->qdr =
2961                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2962                         mpll_param->half_rate =
2963                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2964                         break;
2965                 default:
2966                         return -EINVAL;
2967                 }
2968                 break;
2969         default:
2970                 return -EINVAL;
2971         }
2972         return 0;
2973 }
2974
2975 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2976 {
2977         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2978         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2979
2980         args.ucEnable = enable;
2981
2982         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2983 }
2984
2985 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2986 {
2987         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2988         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2989
2990         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2991         return le32_to_cpu(args.ulReturnEngineClock);
2992 }
2993
2994 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2995 {
2996         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2997         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2998
2999         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3000         return le32_to_cpu(args.ulReturnMemoryClock);
3001 }
3002
3003 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3004                                   uint32_t eng_clock)
3005 {
3006         SET_ENGINE_CLOCK_PS_ALLOCATION args;
3007         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3008
3009         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
3010
3011         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3012 }
3013
3014 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3015                                   uint32_t mem_clock)
3016 {
3017         SET_MEMORY_CLOCK_PS_ALLOCATION args;
3018         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3019
3020         if (rdev->flags & RADEON_IS_IGP)
3021                 return;
3022
3023         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
3024
3025         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3026 }
3027
3028 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3029                                          u32 eng_clock, u32 mem_clock)
3030 {
3031         SET_ENGINE_CLOCK_PS_ALLOCATION args;
3032         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3033         u32 tmp;
3034
3035         memset(&args, 0, sizeof(args));
3036
3037         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3038         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3039
3040         args.ulTargetEngineClock = cpu_to_le32(tmp);
3041         if (mem_clock)
3042                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3043
3044         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3045 }
3046
3047 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3048                                    u32 mem_clock)
3049 {
3050         u32 args;
3051         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3052
3053         args = cpu_to_le32(mem_clock);  /* 10 khz */
3054
3055         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3056 }
3057
3058 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3059                                u32 mem_clock)
3060 {
3061         SET_MEMORY_CLOCK_PS_ALLOCATION args;
3062         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3063         u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3064
3065         args.ulTargetMemoryClock = cpu_to_le32(tmp);    /* 10 khz */
3066
3067         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3068 }
3069
3070 union set_voltage {
3071         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3072         struct _SET_VOLTAGE_PARAMETERS v1;
3073         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3074         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3075 };
3076
3077 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3078 {
3079         union set_voltage args;
3080         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3081         u8 frev, crev, volt_index = voltage_level;
3082
3083         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3084                 return;
3085
3086         /* 0xff01 is a flag rather then an actual voltage */
3087         if (voltage_level == 0xff01)
3088                 return;
3089
3090         switch (crev) {
3091         case 1:
3092                 args.v1.ucVoltageType = voltage_type;
3093                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3094                 args.v1.ucVoltageIndex = volt_index;
3095                 break;
3096         case 2:
3097                 args.v2.ucVoltageType = voltage_type;
3098                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3099                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3100                 break;
3101         case 3:
3102                 args.v3.ucVoltageType = voltage_type;
3103                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3104                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3105                 break;
3106         default:
3107                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3108                 return;
3109         }
3110
3111         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3112 }
3113
3114 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3115                              u16 voltage_id, u16 *voltage)
3116 {
3117         union set_voltage args;
3118         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3119         u8 frev, crev;
3120
3121         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3122                 return -EINVAL;
3123
3124         switch (crev) {
3125         case 1:
3126                 return -EINVAL;
3127         case 2:
3128                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3129                 args.v2.ucVoltageMode = 0;
3130                 args.v2.usVoltageLevel = 0;
3131
3132                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3133
3134                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3135                 break;
3136         case 3:
3137                 args.v3.ucVoltageType = voltage_type;
3138                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3139                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3140
3141                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3142
3143                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3144                 break;
3145         default:
3146                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3147                 return -EINVAL;
3148         }
3149
3150         return 0;
3151 }
3152
3153 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3154                                                       u16 *voltage,
3155                                                       u16 leakage_idx)
3156 {
3157         return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3158 }
3159
3160 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3161                                           u16 *leakage_id)
3162 {
3163         union set_voltage args;
3164         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3165         u8 frev, crev;
3166
3167         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3168                 return -EINVAL;
3169
3170         switch (crev) {
3171         case 3:
3172         case 4:
3173                 args.v3.ucVoltageType = 0;
3174                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3175                 args.v3.usVoltageLevel = 0;
3176
3177                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3178
3179                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3180                 break;
3181         default:
3182                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3183                 return -EINVAL;
3184         }
3185
3186         return 0;
3187 }
3188
3189 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3190                                                          u16 *vddc, u16 *vddci,
3191                                                          u16 virtual_voltage_id,
3192                                                          u16 vbios_voltage_id)
3193 {
3194         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3195         u8 frev, crev;
3196         u16 data_offset, size;
3197         int i, j;
3198         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3199         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3200
3201         *vddc = 0;
3202         *vddci = 0;
3203
3204         if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3205                                     &frev, &crev, &data_offset))
3206                 return -EINVAL;
3207
3208         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3209                 (rdev->mode_info.atom_context->bios + data_offset);
3210
3211         switch (frev) {
3212         case 1:
3213                 return -EINVAL;
3214         case 2:
3215                 switch (crev) {
3216                 case 1:
3217                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3218                                 return -EINVAL;
3219                         leakage_bin = (u16 *)
3220                                 (rdev->mode_info.atom_context->bios + data_offset +
3221                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
3222                         vddc_id_buf = (u16 *)
3223                                 (rdev->mode_info.atom_context->bios + data_offset +
3224                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3225                         vddc_buf = (u16 *)
3226                                 (rdev->mode_info.atom_context->bios + data_offset +
3227                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3228                         vddci_id_buf = (u16 *)
3229                                 (rdev->mode_info.atom_context->bios + data_offset +
3230                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3231                         vddci_buf = (u16 *)
3232                                 (rdev->mode_info.atom_context->bios + data_offset +
3233                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3234
3235                         if (profile->ucElbVDDC_Num > 0) {
3236                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3237                                         if (vddc_id_buf[i] == virtual_voltage_id) {
3238                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3239                                                         if (vbios_voltage_id <= leakage_bin[j]) {
3240                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3241                                                                 break;
3242                                                         }
3243                                                 }
3244                                                 break;
3245                                         }
3246                                 }
3247                         }
3248                         if (profile->ucElbVDDCI_Num > 0) {
3249                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3250                                         if (vddci_id_buf[i] == virtual_voltage_id) {
3251                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3252                                                         if (vbios_voltage_id <= leakage_bin[j]) {
3253                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3254                                                                 break;
3255                                                         }
3256                                                 }
3257                                                 break;
3258                                         }
3259                                 }
3260                         }
3261                         break;
3262                 default:
3263                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3264                         return -EINVAL;
3265                 }
3266                 break;
3267         default:
3268                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3269                 return -EINVAL;
3270         }
3271
3272         return 0;
3273 }
3274
3275 union get_voltage_info {
3276         struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3277         struct  _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3278 };
3279
3280 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3281                                 u16 virtual_voltage_id,
3282                                 u16 *voltage)
3283 {
3284         int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3285         u32 entry_id;
3286         u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3287         union get_voltage_info args;
3288
3289         for (entry_id = 0; entry_id < count; entry_id++) {
3290                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3291                     virtual_voltage_id)
3292                         break;
3293         }
3294
3295         if (entry_id >= count)
3296                 return -EINVAL;
3297
3298         args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3299         args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3300         args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3301         args.in.ulSCLKFreq =
3302                 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3303
3304         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3305
3306         *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3307
3308         return 0;
3309 }
3310
3311 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3312                                           u16 voltage_level, u8 voltage_type,
3313                                           u32 *gpio_value, u32 *gpio_mask)
3314 {
3315         union set_voltage args;
3316         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3317         u8 frev, crev;
3318
3319         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3320                 return -EINVAL;
3321
3322         switch (crev) {
3323         case 1:
3324                 return -EINVAL;
3325         case 2:
3326                 args.v2.ucVoltageType = voltage_type;
3327                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3328                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3329
3330                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3331
3332                 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3333
3334                 args.v2.ucVoltageType = voltage_type;
3335                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3336                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3337
3338                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3339
3340                 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3341                 break;
3342         default:
3343                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3344                 return -EINVAL;
3345         }
3346
3347         return 0;
3348 }
3349
3350 union voltage_object_info {
3351         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3352         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3353         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3354 };
3355
3356 union voltage_object {
3357         struct _ATOM_VOLTAGE_OBJECT v1;
3358         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3359         union _ATOM_VOLTAGE_OBJECT_V3 v3;
3360 };
3361
3362 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3363                                                           u8 voltage_type)
3364 {
3365         u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3366         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3367         u8 *start = (u8 *)v1;
3368
3369         while (offset < size) {
3370                 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3371                 if (vo->ucVoltageType == voltage_type)
3372                         return vo;
3373                 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3374                         vo->asFormula.ucNumOfVoltageEntries;
3375         }
3376         return NULL;
3377 }
3378
3379 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3380                                                              u8 voltage_type)
3381 {
3382         u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3383         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3384         u8 *start = (u8*)v2;
3385
3386         while (offset < size) {
3387                 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3388                 if (vo->ucVoltageType == voltage_type)
3389                         return vo;
3390                 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3391                         (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3392         }
3393         return NULL;
3394 }
3395
3396 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3397                                                              u8 voltage_type, u8 voltage_mode)
3398 {
3399         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3400         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3401         u8 *start = (u8*)v3;
3402
3403         while (offset < size) {
3404                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3405                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3406                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3407                         return vo;
3408                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3409         }
3410         return NULL;
3411 }
3412
3413 bool
3414 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3415                             u8 voltage_type, u8 voltage_mode)
3416 {
3417         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3418         u8 frev, crev;
3419         u16 data_offset, size;
3420         union voltage_object_info *voltage_info;
3421         union voltage_object *voltage_object = NULL;
3422
3423         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3424                                    &frev, &crev, &data_offset)) {
3425                 voltage_info = (union voltage_object_info *)
3426                         (rdev->mode_info.atom_context->bios + data_offset);
3427
3428                 switch (frev) {
3429                 case 1:
3430                 case 2:
3431                         switch (crev) {
3432                         case 1:
3433                                 voltage_object = (union voltage_object *)
3434                                         atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3435                                 if (voltage_object &&
3436                                     (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3437                                         return true;
3438                                 break;
3439                         case 2:
3440                                 voltage_object = (union voltage_object *)
3441                                         atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3442                                 if (voltage_object &&
3443                                     (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3444                                         return true;
3445                                 break;
3446                         default:
3447                                 DRM_ERROR("unknown voltage object table\n");
3448                                 return false;
3449                         }
3450                         break;
3451                 case 3:
3452                         switch (crev) {
3453                         case 1:
3454                                 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3455                                                                   voltage_type, voltage_mode))
3456                                         return true;
3457                                 break;
3458                         default:
3459                                 DRM_ERROR("unknown voltage object table\n");
3460                                 return false;
3461                         }
3462                         break;
3463                 default:
3464                         DRM_ERROR("unknown voltage object table\n");
3465                         return false;
3466                 }
3467
3468         }
3469         return false;
3470 }
3471
3472 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3473                               u8 voltage_type,
3474                               u8 *svd_gpio_id, u8 *svc_gpio_id)
3475 {
3476         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3477         u8 frev, crev;
3478         u16 data_offset, size;
3479         union voltage_object_info *voltage_info;
3480         union voltage_object *voltage_object = NULL;
3481
3482         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3483                                    &frev, &crev, &data_offset)) {
3484                 voltage_info = (union voltage_object_info *)
3485                         (rdev->mode_info.atom_context->bios + data_offset);
3486
3487                 switch (frev) {
3488                 case 3:
3489                         switch (crev) {
3490                         case 1:
3491                                 voltage_object = (union voltage_object *)
3492                                         atom_lookup_voltage_object_v3(&voltage_info->v3,
3493                                                                       voltage_type,
3494                                                                       VOLTAGE_OBJ_SVID2);
3495                                 if (voltage_object) {
3496                                         *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3497                                         *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3498                                 } else {
3499                                         return -EINVAL;
3500                                 }
3501                                 break;
3502                         default:
3503                                 DRM_ERROR("unknown voltage object table\n");
3504                                 return -EINVAL;
3505                         }
3506                         break;
3507                 default:
3508                         DRM_ERROR("unknown voltage object table\n");
3509                         return -EINVAL;
3510                 }
3511
3512         }
3513         return 0;
3514 }
3515
3516 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3517                                 u8 voltage_type, u16 *max_voltage)
3518 {
3519         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3520         u8 frev, crev;
3521         u16 data_offset, size;
3522         union voltage_object_info *voltage_info;
3523         union voltage_object *voltage_object = NULL;
3524
3525         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3526                                    &frev, &crev, &data_offset)) {
3527                 voltage_info = (union voltage_object_info *)
3528                         (rdev->mode_info.atom_context->bios + data_offset);
3529
3530                 switch (crev) {
3531                 case 1:
3532                         voltage_object = (union voltage_object *)
3533                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3534                         if (voltage_object) {
3535                                 ATOM_VOLTAGE_FORMULA *formula =
3536                                         &voltage_object->v1.asFormula;
3537                                 if (formula->ucFlag & 1)
3538                                         *max_voltage =
3539                                                 le16_to_cpu(formula->usVoltageBaseLevel) +
3540                                                 formula->ucNumOfVoltageEntries / 2 *
3541                                                 le16_to_cpu(formula->usVoltageStep);
3542                                 else
3543                                         *max_voltage =
3544                                                 le16_to_cpu(formula->usVoltageBaseLevel) +
3545                                                 (formula->ucNumOfVoltageEntries - 1) *
3546                                                 le16_to_cpu(formula->usVoltageStep);
3547                                 return 0;
3548                         }
3549                         break;
3550                 case 2:
3551                         voltage_object = (union voltage_object *)
3552                                 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3553                         if (voltage_object) {
3554                                 ATOM_VOLTAGE_FORMULA_V2 *formula =
3555                                         &voltage_object->v2.asFormula;
3556                                 if (formula->ucNumOfVoltageEntries) {
3557                                         VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3558                                                 ((u8 *)&formula->asVIDAdjustEntries[0] +
3559                                                  (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3560                                         *max_voltage =
3561                                                 le16_to_cpu(lut->usVoltageValue);
3562                                         return 0;
3563                                 }
3564                         }
3565                         break;
3566                 default:
3567                         DRM_ERROR("unknown voltage object table\n");
3568                         return -EINVAL;
3569                 }
3570
3571         }
3572         return -EINVAL;
3573 }
3574
3575 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3576                                 u8 voltage_type, u16 *min_voltage)
3577 {
3578         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3579         u8 frev, crev;
3580         u16 data_offset, size;
3581         union voltage_object_info *voltage_info;
3582         union voltage_object *voltage_object = NULL;
3583
3584         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3585                                    &frev, &crev, &data_offset)) {
3586                 voltage_info = (union voltage_object_info *)
3587                         (rdev->mode_info.atom_context->bios + data_offset);
3588
3589                 switch (crev) {
3590                 case 1:
3591                         voltage_object = (union voltage_object *)
3592                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3593                         if (voltage_object) {
3594                                 ATOM_VOLTAGE_FORMULA *formula =
3595                                         &voltage_object->v1.asFormula;
3596                                 *min_voltage =
3597                                         le16_to_cpu(formula->usVoltageBaseLevel);
3598                                 return 0;
3599                         }
3600                         break;
3601                 case 2:
3602                         voltage_object = (union voltage_object *)
3603                                 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3604                         if (voltage_object) {
3605                                 ATOM_VOLTAGE_FORMULA_V2 *formula =
3606                                         &voltage_object->v2.asFormula;
3607                                 if (formula->ucNumOfVoltageEntries) {
3608                                         *min_voltage =
3609                                                 le16_to_cpu(formula->asVIDAdjustEntries[
3610                                                                     0
3611                                                                     ].usVoltageValue);
3612                                         return 0;
3613                                 }
3614                         }
3615                         break;
3616                 default:
3617                         DRM_ERROR("unknown voltage object table\n");
3618                         return -EINVAL;
3619                 }
3620
3621         }
3622         return -EINVAL;
3623 }
3624
3625 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3626                                  u8 voltage_type, u16 *voltage_step)
3627 {
3628         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3629         u8 frev, crev;
3630         u16 data_offset, size;
3631         union voltage_object_info *voltage_info;
3632         union voltage_object *voltage_object = NULL;
3633
3634         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3635                                    &frev, &crev, &data_offset)) {
3636                 voltage_info = (union voltage_object_info *)
3637                         (rdev->mode_info.atom_context->bios + data_offset);
3638
3639                 switch (crev) {
3640                 case 1:
3641                         voltage_object = (union voltage_object *)
3642                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3643                         if (voltage_object) {
3644                                 ATOM_VOLTAGE_FORMULA *formula =
3645                                         &voltage_object->v1.asFormula;
3646                                 if (formula->ucFlag & 1)
3647                                         *voltage_step =
3648                                                 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3649                                 else
3650                                         *voltage_step =
3651                                                 le16_to_cpu(formula->usVoltageStep);
3652                                 return 0;
3653                         }
3654                         break;
3655                 case 2:
3656                         return -EINVAL;
3657                 default:
3658                         DRM_ERROR("unknown voltage object table\n");
3659                         return -EINVAL;
3660                 }
3661
3662         }
3663         return -EINVAL;
3664 }
3665
3666 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3667                                       u8 voltage_type,
3668                                       u16 nominal_voltage,
3669                                       u16 *true_voltage)
3670 {
3671         u16 min_voltage, max_voltage, voltage_step;
3672
3673         if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3674                 return -EINVAL;
3675         if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3676                 return -EINVAL;
3677         if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3678                 return -EINVAL;
3679
3680         if (nominal_voltage <= min_voltage)
3681                 *true_voltage = min_voltage;
3682         else if (nominal_voltage >= max_voltage)
3683                 *true_voltage = max_voltage;
3684         else
3685                 *true_voltage = min_voltage +
3686                         ((nominal_voltage - min_voltage) / voltage_step) *
3687                         voltage_step;
3688
3689         return 0;
3690 }
3691
3692 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3693                                   u8 voltage_type, u8 voltage_mode,
3694                                   struct atom_voltage_table *voltage_table)
3695 {
3696         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3697         u8 frev, crev;
3698         u16 data_offset, size;
3699         int i, ret;
3700         union voltage_object_info *voltage_info;
3701         union voltage_object *voltage_object = NULL;
3702
3703         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3704                                    &frev, &crev, &data_offset)) {
3705                 voltage_info = (union voltage_object_info *)
3706                         (rdev->mode_info.atom_context->bios + data_offset);
3707
3708                 switch (frev) {
3709                 case 1:
3710                 case 2:
3711                         switch (crev) {
3712                         case 1:
3713                                 DRM_ERROR("old table version %d, %d\n", frev, crev);
3714                                 return -EINVAL;
3715                         case 2:
3716                                 voltage_object = (union voltage_object *)
3717                                         atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3718                                 if (voltage_object) {
3719                                         ATOM_VOLTAGE_FORMULA_V2 *formula =
3720                                                 &voltage_object->v2.asFormula;
3721                                         VOLTAGE_LUT_ENTRY *lut;
3722                                         if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3723                                                 return -EINVAL;
3724                                         lut = &formula->asVIDAdjustEntries[0];
3725                                         for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3726                                                 voltage_table->entries[i].value =
3727                                                         le16_to_cpu(lut->usVoltageValue);
3728                                                 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3729                                                                                             voltage_table->entries[i].value,
3730                                                                                             voltage_type,
3731                                                                                             &voltage_table->entries[i].smio_low,
3732                                                                                             &voltage_table->mask_low);
3733                                                 if (ret)
3734                                                         return ret;
3735                                                 lut = (VOLTAGE_LUT_ENTRY *)
3736                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3737                                         }
3738                                         voltage_table->count = formula->ucNumOfVoltageEntries;
3739                                         return 0;
3740                                 }
3741                                 break;
3742                         default:
3743                                 DRM_ERROR("unknown voltage object table\n");
3744                                 return -EINVAL;
3745                         }
3746                         break;
3747                 case 3:
3748                         switch (crev) {
3749                         case 1:
3750                                 voltage_object = (union voltage_object *)
3751                                         atom_lookup_voltage_object_v3(&voltage_info->v3,
3752                                                                       voltage_type, voltage_mode);
3753                                 if (voltage_object) {
3754                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3755                                                 &voltage_object->v3.asGpioVoltageObj;
3756                                         VOLTAGE_LUT_ENTRY_V2 *lut;
3757                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3758                                                 return -EINVAL;
3759                                         lut = &gpio->asVolGpioLut[0];
3760                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3761                                                 voltage_table->entries[i].value =
3762                                                         le16_to_cpu(lut->usVoltageValue);
3763                                                 voltage_table->entries[i].smio_low =
3764                                                         le32_to_cpu(lut->ulVoltageId);
3765                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3766                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3767                                         }
3768                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3769                                         voltage_table->count = gpio->ucGpioEntryNum;
3770                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
3771                                         return 0;
3772                                 }
3773                                 break;
3774                         default:
3775                                 DRM_ERROR("unknown voltage object table\n");
3776                                 return -EINVAL;
3777                         }
3778                         break;
3779                 default:
3780                         DRM_ERROR("unknown voltage object table\n");
3781                         return -EINVAL;
3782                 }
3783         }
3784         return -EINVAL;
3785 }
3786
3787 union vram_info {
3788         struct _ATOM_VRAM_INFO_V3 v1_3;
3789         struct _ATOM_VRAM_INFO_V4 v1_4;
3790         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3791 };
3792
3793 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3794                                 u8 module_index, struct atom_memory_info *mem_info)
3795 {
3796         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3797         u8 frev, crev, i;
3798         u16 data_offset, size;
3799         union vram_info *vram_info;
3800
3801         memset(mem_info, 0, sizeof(struct atom_memory_info));
3802
3803         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3804                                    &frev, &crev, &data_offset)) {
3805                 vram_info = (union vram_info *)
3806                         (rdev->mode_info.atom_context->bios + data_offset);
3807                 switch (frev) {
3808                 case 1:
3809                         switch (crev) {
3810                         case 3:
3811                                 /* r6xx */
3812                                 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3813                                         ATOM_VRAM_MODULE_V3 *vram_module =
3814                                                 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3815
3816                                         for (i = 0; i < module_index; i++) {
3817                                                 if (le16_to_cpu(vram_module->usSize) == 0)
3818                                                         return -EINVAL;
3819                                                 vram_module = (ATOM_VRAM_MODULE_V3 *)
3820                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3821                                         }
3822                                         mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3823                                         mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3824                                 } else
3825                                         return -EINVAL;
3826                                 break;
3827                         case 4:
3828                                 /* r7xx, evergreen */
3829                                 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3830                                         ATOM_VRAM_MODULE_V4 *vram_module =
3831                                                 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3832
3833                                         for (i = 0; i < module_index; i++) {
3834                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3835                                                         return -EINVAL;
3836                                                 vram_module = (ATOM_VRAM_MODULE_V4 *)
3837                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3838                                         }
3839                                         mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3840                                         mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3841                                 } else
3842                                         return -EINVAL;
3843                                 break;
3844                         default:
3845                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3846                                 return -EINVAL;
3847                         }
3848                         break;
3849                 case 2:
3850                         switch (crev) {
3851                         case 1:
3852                                 /* ni */
3853                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3854                                         ATOM_VRAM_MODULE_V7 *vram_module =
3855                                                 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3856
3857                                         for (i = 0; i < module_index; i++) {
3858                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3859                                                         return -EINVAL;
3860                                                 vram_module = (ATOM_VRAM_MODULE_V7 *)
3861                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3862                                         }
3863                                         mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3864                                         mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3865                                 } else
3866                                         return -EINVAL;
3867                                 break;
3868                         default:
3869                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3870                                 return -EINVAL;
3871                         }
3872                         break;
3873                 default:
3874                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3875                         return -EINVAL;
3876                 }
3877                 return 0;
3878         }
3879         return -EINVAL;
3880 }
3881
3882 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3883                                      bool gddr5, u8 module_index,
3884                                      struct atom_memory_clock_range_table *mclk_range_table)
3885 {
3886         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3887         u8 frev, crev, i;
3888         u16 data_offset, size;
3889         union vram_info *vram_info;
3890         u32 mem_timing_size = gddr5 ?
3891                 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3892
3893         memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3894
3895         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3896                                    &frev, &crev, &data_offset)) {
3897                 vram_info = (union vram_info *)
3898                         (rdev->mode_info.atom_context->bios + data_offset);
3899                 switch (frev) {
3900                 case 1:
3901                         switch (crev) {
3902                         case 3:
3903                                 DRM_ERROR("old table version %d, %d\n", frev, crev);
3904                                 return -EINVAL;
3905                         case 4:
3906                                 /* r7xx, evergreen */
3907                                 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3908                                         ATOM_VRAM_MODULE_V4 *vram_module =
3909                                                 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3910                                         ATOM_MEMORY_TIMING_FORMAT *format;
3911
3912                                         for (i = 0; i < module_index; i++) {
3913                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3914                                                         return -EINVAL;
3915                                                 vram_module = (ATOM_VRAM_MODULE_V4 *)
3916                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3917                                         }
3918                                         mclk_range_table->num_entries = (u8)
3919                                                 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3920                                                  mem_timing_size);
3921                                         format = &vram_module->asMemTiming[0];
3922                                         for (i = 0; i < mclk_range_table->num_entries; i++) {
3923                                                 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3924                                                 format = (ATOM_MEMORY_TIMING_FORMAT *)
3925                                                         ((u8 *)format + mem_timing_size);
3926                                         }
3927                                 } else
3928                                         return -EINVAL;
3929                                 break;
3930                         default:
3931                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3932                                 return -EINVAL;
3933                         }
3934                         break;
3935                 case 2:
3936                         DRM_ERROR("new table version %d, %d\n", frev, crev);
3937                         return -EINVAL;
3938                 default:
3939                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3940                         return -EINVAL;
3941                 }
3942                 return 0;
3943         }
3944         return -EINVAL;
3945 }
3946
3947 #define MEM_ID_MASK           0xff000000
3948 #define MEM_ID_SHIFT          24
3949 #define CLOCK_RANGE_MASK      0x00ffffff
3950 #define CLOCK_RANGE_SHIFT     0
3951 #define LOW_NIBBLE_MASK       0xf
3952 #define DATA_EQU_PREV         0
3953 #define DATA_FROM_TABLE       4
3954
3955 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3956                                   u8 module_index,
3957                                   struct atom_mc_reg_table *reg_table)
3958 {
3959         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3960         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3961         u32 i = 0, j;
3962         u16 data_offset, size;
3963         union vram_info *vram_info;
3964
3965         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3966
3967         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3968                                    &frev, &crev, &data_offset)) {
3969                 vram_info = (union vram_info *)
3970                         (rdev->mode_info.atom_context->bios + data_offset);
3971                 switch (frev) {
3972                 case 1:
3973                         DRM_ERROR("old table version %d, %d\n", frev, crev);
3974                         return -EINVAL;
3975                 case 2:
3976                         switch (crev) {
3977                         case 1:
3978                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3979                                         ATOM_INIT_REG_BLOCK *reg_block =
3980                                                 (ATOM_INIT_REG_BLOCK *)
3981                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
3982                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
3983                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3984                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
3985                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
3986                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
3987                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
3988                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
3989                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
3990                                                 return -EINVAL;
3991                                         while (i < num_entries) {
3992                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
3993                                                         break;
3994                                                 reg_table->mc_reg_address[i].s1 =
3995                                                         (u16)(le16_to_cpu(format->usRegIndex));
3996                                                 reg_table->mc_reg_address[i].pre_reg_data =
3997                                                         (u8)(format->ucPreRegDataLength);
3998                                                 i++;
3999                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4000                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4001                                         }
4002                                         reg_table->last = i;
4003                                         while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4004                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4005                                                 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4006                                                                 >> MEM_ID_SHIFT);
4007                                                 if (module_index == t_mem_id) {
4008                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4009                                                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4010                                                                       >> CLOCK_RANGE_SHIFT);
4011                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
4012                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4013                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4014                                                                                 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4015                                                                         j++;
4016                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4017                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4018                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4019                                                                 }
4020                                                         }
4021                                                         num_ranges++;
4022                                                 }
4023                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4024                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4025                                         }
4026                                         if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4027                                                 return -EINVAL;
4028                                         reg_table->num_entries = num_ranges;
4029                                 } else
4030                                         return -EINVAL;
4031                                 break;
4032                         default:
4033                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4034                                 return -EINVAL;
4035                         }
4036                         break;
4037                 default:
4038                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4039                         return -EINVAL;
4040                 }
4041                 return 0;
4042         }
4043         return -EINVAL;
4044 }
4045
4046 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4047 {
4048         struct radeon_device *rdev = dev->dev_private;
4049         uint32_t bios_2_scratch, bios_6_scratch;
4050
4051         if (rdev->family >= CHIP_R600) {
4052                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4053                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4054         } else {
4055                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4056                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4057         }
4058
4059         /* let the bios control the backlight */
4060         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4061
4062         /* tell the bios not to handle mode switching */
4063         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4064
4065         /* clear the vbios dpms state */
4066         if (ASIC_IS_DCE4(rdev))
4067                 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4068
4069         if (rdev->family >= CHIP_R600) {
4070                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4071                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4072         } else {
4073                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4074                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4075         }
4076
4077 }
4078
4079 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4080 {
4081         uint32_t scratch_reg;
4082         int i;
4083
4084         if (rdev->family >= CHIP_R600)
4085                 scratch_reg = R600_BIOS_0_SCRATCH;
4086         else
4087                 scratch_reg = RADEON_BIOS_0_SCRATCH;
4088
4089         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4090                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4091 }
4092
4093 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4094 {
4095         uint32_t scratch_reg;
4096         int i;
4097
4098         if (rdev->family >= CHIP_R600)
4099                 scratch_reg = R600_BIOS_0_SCRATCH;
4100         else
4101                 scratch_reg = RADEON_BIOS_0_SCRATCH;
4102
4103         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4104                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4105 }
4106
4107 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4108 {
4109         struct drm_device *dev = encoder->dev;
4110         struct radeon_device *rdev = dev->dev_private;
4111         uint32_t bios_6_scratch;
4112
4113         if (rdev->family >= CHIP_R600)
4114                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4115         else
4116                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4117
4118         if (lock) {
4119                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4120                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4121         } else {
4122                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4123                 bios_6_scratch |= ATOM_S6_ACC_MODE;
4124         }
4125
4126         if (rdev->family >= CHIP_R600)
4127                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4128         else
4129                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4130 }
4131
4132 /* at some point we may want to break this out into individual functions */
4133 void
4134 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4135                                        struct drm_encoder *encoder,
4136                                        bool connected)
4137 {
4138         struct drm_device *dev = connector->dev;
4139         struct radeon_device *rdev = dev->dev_private;
4140         struct radeon_connector *radeon_connector =
4141             to_radeon_connector(connector);
4142         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4143         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4144
4145         if (rdev->family >= CHIP_R600) {
4146                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4147                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4148                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4149         } else {
4150                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4151                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4152                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4153         }
4154
4155         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4156             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4157                 if (connected) {
4158                         DRM_DEBUG_KMS("TV1 connected\n");
4159                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4160                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4161                 } else {
4162                         DRM_DEBUG_KMS("TV1 disconnected\n");
4163                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4164                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4165                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4166                 }
4167         }
4168         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4169             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4170                 if (connected) {
4171                         DRM_DEBUG_KMS("CV connected\n");
4172                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4173                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4174                 } else {
4175                         DRM_DEBUG_KMS("CV disconnected\n");
4176                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
4177                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4178                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4179                 }
4180         }
4181         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4182             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4183                 if (connected) {
4184                         DRM_DEBUG_KMS("LCD1 connected\n");
4185                         bios_0_scratch |= ATOM_S0_LCD1;
4186                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4187                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4188                 } else {
4189                         DRM_DEBUG_KMS("LCD1 disconnected\n");
4190                         bios_0_scratch &= ~ATOM_S0_LCD1;
4191                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4192                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4193                 }
4194         }
4195         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4196             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4197                 if (connected) {
4198                         DRM_DEBUG_KMS("CRT1 connected\n");
4199                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4200                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4201                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4202                 } else {
4203                         DRM_DEBUG_KMS("CRT1 disconnected\n");
4204                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4205                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4206                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4207                 }
4208         }
4209         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4210             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4211                 if (connected) {
4212                         DRM_DEBUG_KMS("CRT2 connected\n");
4213                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4214                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4215                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4216                 } else {
4217                         DRM_DEBUG_KMS("CRT2 disconnected\n");
4218                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4219                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4220                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4221                 }
4222         }
4223         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4224             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4225                 if (connected) {
4226                         DRM_DEBUG_KMS("DFP1 connected\n");
4227                         bios_0_scratch |= ATOM_S0_DFP1;
4228                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4229                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4230                 } else {
4231                         DRM_DEBUG_KMS("DFP1 disconnected\n");
4232                         bios_0_scratch &= ~ATOM_S0_DFP1;
4233                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4234                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4235                 }
4236         }
4237         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4238             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4239                 if (connected) {
4240                         DRM_DEBUG_KMS("DFP2 connected\n");
4241                         bios_0_scratch |= ATOM_S0_DFP2;
4242                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4243                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4244                 } else {
4245                         DRM_DEBUG_KMS("DFP2 disconnected\n");
4246                         bios_0_scratch &= ~ATOM_S0_DFP2;
4247                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4248                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4249                 }
4250         }
4251         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4252             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4253                 if (connected) {
4254                         DRM_DEBUG_KMS("DFP3 connected\n");
4255                         bios_0_scratch |= ATOM_S0_DFP3;
4256                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4257                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4258                 } else {
4259                         DRM_DEBUG_KMS("DFP3 disconnected\n");
4260                         bios_0_scratch &= ~ATOM_S0_DFP3;
4261                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4262                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4263                 }
4264         }
4265         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4266             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4267                 if (connected) {
4268                         DRM_DEBUG_KMS("DFP4 connected\n");
4269                         bios_0_scratch |= ATOM_S0_DFP4;
4270                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4271                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4272                 } else {
4273                         DRM_DEBUG_KMS("DFP4 disconnected\n");
4274                         bios_0_scratch &= ~ATOM_S0_DFP4;
4275                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4276                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4277                 }
4278         }
4279         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4280             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4281                 if (connected) {
4282                         DRM_DEBUG_KMS("DFP5 connected\n");
4283                         bios_0_scratch |= ATOM_S0_DFP5;
4284                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4285                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4286                 } else {
4287                         DRM_DEBUG_KMS("DFP5 disconnected\n");
4288                         bios_0_scratch &= ~ATOM_S0_DFP5;
4289                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4290                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4291                 }
4292         }
4293         if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4294             (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4295                 if (connected) {
4296                         DRM_DEBUG_KMS("DFP6 connected\n");
4297                         bios_0_scratch |= ATOM_S0_DFP6;
4298                         bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4299                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4300                 } else {
4301                         DRM_DEBUG_KMS("DFP6 disconnected\n");
4302                         bios_0_scratch &= ~ATOM_S0_DFP6;
4303                         bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4304                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4305                 }
4306         }
4307
4308         if (rdev->family >= CHIP_R600) {
4309                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4310                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4311                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4312         } else {
4313                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4314                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4315                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4316         }
4317 }
4318
4319 void
4320 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4321 {
4322         struct drm_device *dev = encoder->dev;
4323         struct radeon_device *rdev = dev->dev_private;
4324         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4325         uint32_t bios_3_scratch;
4326
4327         if (ASIC_IS_DCE4(rdev))
4328                 return;
4329
4330         if (rdev->family >= CHIP_R600)
4331                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4332         else
4333                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4334
4335         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4336                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4337                 bios_3_scratch |= (crtc << 18);
4338         }
4339         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4340                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4341                 bios_3_scratch |= (crtc << 24);
4342         }
4343         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4344                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4345                 bios_3_scratch |= (crtc << 16);
4346         }
4347         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4348                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4349                 bios_3_scratch |= (crtc << 20);
4350         }
4351         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4352                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4353                 bios_3_scratch |= (crtc << 17);
4354         }
4355         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4356                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4357                 bios_3_scratch |= (crtc << 19);
4358         }
4359         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4360                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4361                 bios_3_scratch |= (crtc << 23);
4362         }
4363         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4364                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4365                 bios_3_scratch |= (crtc << 25);
4366         }
4367
4368         if (rdev->family >= CHIP_R600)
4369                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4370         else
4371                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4372 }
4373
4374 void
4375 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4376 {
4377         struct drm_device *dev = encoder->dev;
4378         struct radeon_device *rdev = dev->dev_private;
4379         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4380         uint32_t bios_2_scratch;
4381
4382         if (ASIC_IS_DCE4(rdev))
4383                 return;
4384
4385         if (rdev->family >= CHIP_R600)
4386                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4387         else
4388                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4389
4390         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4391                 if (on)
4392                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4393                 else
4394                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4395         }
4396         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4397                 if (on)
4398                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4399                 else
4400                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4401         }
4402         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4403                 if (on)
4404                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4405                 else
4406                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4407         }
4408         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4409                 if (on)
4410                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4411                 else
4412                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4413         }
4414         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4415                 if (on)
4416                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4417                 else
4418                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4419         }
4420         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4421                 if (on)
4422                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4423                 else
4424                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4425         }
4426         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4427                 if (on)
4428                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4429                 else
4430                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4431         }
4432         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4433                 if (on)
4434                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4435                 else
4436                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4437         }
4438         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4439                 if (on)
4440                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4441                 else
4442                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4443         }
4444         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4445                 if (on)
4446                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4447                 else
4448                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4449         }
4450
4451         if (rdev->family >= CHIP_R600)
4452                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4453         else
4454                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4455 }