drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id);
  51
  52 /* from radeon_legacy_encoder.c */
  53 extern void
  54 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  55                           uint32_t supported_device);
  56
  57 union atom_supported_devices {
  58         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  59         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  61 };
  62
  63 static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
  64                                                            *dev, uint8_t id)
  65 {
  66         struct radeon_device *rdev = dev->dev_private;
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset;
  73
  74         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  75         i2c.valid = false;
  76
  77         atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  78
  79         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  80
  81         gpio = i2c_info->asGPIO_Info[id];
  82
  83         i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
  84         i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
  85         i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
  86         i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
  87         i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
  88         i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
  89         i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
  90         i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
  91         i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
  92         i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
  93         i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
  94         i2c.put_data_mask = (1 << gpio.ucDataEnShift);
  95         i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
  96         i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
  97         i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
  98         i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
  99         i2c.valid = true;
 100
 101         return i2c;
 102 }
 103
 104 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 105                                      uint32_t supported_device,
 106                                      int *connector_type,
 107                                      struct radeon_i2c_bus_rec *i2c_bus,
 108                                      uint16_t *line_mux)
 109 {
 110
 111         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 112         if ((dev->pdev->device == 0x791e) &&
 113             (dev->pdev->subsystem_vendor == 0x1043) &&
 114             (dev->pdev->subsystem_device == 0x826d)) {
 115                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 116                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 117                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 118         }
 119
 120         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 121         if ((dev->pdev->device == 0x7941) &&
 122             (dev->pdev->subsystem_vendor == 0x147b) &&
 123             (dev->pdev->subsystem_device == 0x2412)) {
 124                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 125                         return false;
 126         }
 127
 128         /* Falcon NW laptop lists vga ddc line for LVDS */
 129         if ((dev->pdev->device == 0x5653) &&
 130             (dev->pdev->subsystem_vendor == 0x1462) &&
 131             (dev->pdev->subsystem_device == 0x0291)) {
 132                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 133                         i2c_bus->valid = false;
 134                         *line_mux = 53;
 135                 }
 136         }
 137
 138         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 139         if ((dev->pdev->device == 0x7146) &&
 140             (dev->pdev->subsystem_vendor == 0x17af) &&
 141             (dev->pdev->subsystem_device == 0x2058)) {
 142                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 143                         return false;
 144         }
 145
 146         /* Funky macbooks */
 147         if ((dev->pdev->device == 0x71C5) &&
 148             (dev->pdev->subsystem_vendor == 0x106b) &&
 149             (dev->pdev->subsystem_device == 0x0080)) {
 150                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 151                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 152                         return false;
 153         }
 154
 155         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 156         if ((dev->pdev->device == 0x9598) &&
 157             (dev->pdev->subsystem_vendor == 0x1043) &&
 158             (dev->pdev->subsystem_device == 0x01da)) {
 159                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 160                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 161                 }
 162         }
 163
 164         /* ASUS HD 3600 board lists the DVI port as HDMI */
 165         if ((dev->pdev->device == 0x9598) &&
 166             (dev->pdev->subsystem_vendor == 0x1043) &&
 167             (dev->pdev->subsystem_device == 0x01e4)) {
 168                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 169                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 170                 }
 171         }
 172
 173         /* ASUS HD 3450 board lists the DVI port as HDMI */
 174         if ((dev->pdev->device == 0x95C5) &&
 175             (dev->pdev->subsystem_vendor == 0x1043) &&
 176             (dev->pdev->subsystem_device == 0x01e2)) {
 177                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 178                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 179                 }
 180         }
 181
 182         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 183          * HDMI + VGA reporting as HDMI
 184          */
 185         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 186                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 187                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 188                         *line_mux = 0;
 189                 }
 190         }
 191
 192         return true;
 193 }
 194
 195 const int supported_devices_connector_convert[] = {
 196         DRM_MODE_CONNECTOR_Unknown,
 197         DRM_MODE_CONNECTOR_VGA,
 198         DRM_MODE_CONNECTOR_DVII,
 199         DRM_MODE_CONNECTOR_DVID,
 200         DRM_MODE_CONNECTOR_DVIA,
 201         DRM_MODE_CONNECTOR_SVIDEO,
 202         DRM_MODE_CONNECTOR_Composite,
 203         DRM_MODE_CONNECTOR_LVDS,
 204         DRM_MODE_CONNECTOR_Unknown,
 205         DRM_MODE_CONNECTOR_Unknown,
 206         DRM_MODE_CONNECTOR_HDMIA,
 207         DRM_MODE_CONNECTOR_HDMIB,
 208         DRM_MODE_CONNECTOR_Unknown,
 209         DRM_MODE_CONNECTOR_Unknown,
 210         DRM_MODE_CONNECTOR_9PinDIN,
 211         DRM_MODE_CONNECTOR_DisplayPort
 212 };
 213
 214 const uint16_t supported_devices_connector_object_id_convert[] = {
 215         CONNECTOR_OBJECT_ID_NONE,
 216         CONNECTOR_OBJECT_ID_VGA,
 217         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 218         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 219         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 220         CONNECTOR_OBJECT_ID_COMPOSITE,
 221         CONNECTOR_OBJECT_ID_SVIDEO,
 222         CONNECTOR_OBJECT_ID_LVDS,
 223         CONNECTOR_OBJECT_ID_9PIN_DIN,
 224         CONNECTOR_OBJECT_ID_9PIN_DIN,
 225         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 226         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 227         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 228         CONNECTOR_OBJECT_ID_SVIDEO
 229 };
 230
 231 const int object_connector_convert[] = {
 232         DRM_MODE_CONNECTOR_Unknown,
 233         DRM_MODE_CONNECTOR_DVII,
 234         DRM_MODE_CONNECTOR_DVII,
 235         DRM_MODE_CONNECTOR_DVID,
 236         DRM_MODE_CONNECTOR_DVID,
 237         DRM_MODE_CONNECTOR_VGA,
 238         DRM_MODE_CONNECTOR_Composite,
 239         DRM_MODE_CONNECTOR_SVIDEO,
 240         DRM_MODE_CONNECTOR_Unknown,
 241         DRM_MODE_CONNECTOR_Unknown,
 242         DRM_MODE_CONNECTOR_9PinDIN,
 243         DRM_MODE_CONNECTOR_Unknown,
 244         DRM_MODE_CONNECTOR_HDMIA,
 245         DRM_MODE_CONNECTOR_HDMIB,
 246         DRM_MODE_CONNECTOR_LVDS,
 247         DRM_MODE_CONNECTOR_9PinDIN,
 248         DRM_MODE_CONNECTOR_Unknown,
 249         DRM_MODE_CONNECTOR_Unknown,
 250         DRM_MODE_CONNECTOR_Unknown,
 251         DRM_MODE_CONNECTOR_DisplayPort
 252 };
 253
 254 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 255 {
 256         struct radeon_device *rdev = dev->dev_private;
 257         struct radeon_mode_info *mode_info = &rdev->mode_info;
 258         struct atom_context *ctx = mode_info->atom_context;
 259         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 260         uint16_t size, data_offset;
 261         uint8_t frev, crev, line_mux = 0;
 262         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 263         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 264         ATOM_OBJECT_HEADER *obj_header;
 265         int i, j, path_size, device_support;
 266         int connector_type;
 267         uint16_t igp_lane_info, conn_id, connector_object_id;
 268         bool linkb;
 269         struct radeon_i2c_bus_rec ddc_bus;
 270
 271         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 272
 273         if (data_offset == 0)
 274                 return false;
 275
 276         if (crev < 2)
 277                 return false;
 278
 279         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 280         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 281             (ctx->bios + data_offset +
 282              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 283         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 284             (ctx->bios + data_offset +
 285              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 286         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 287
 288         path_size = 0;
 289         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 290                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 291                 ATOM_DISPLAY_OBJECT_PATH *path;
 292                 addr += path_size;
 293                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 294                 path_size += le16_to_cpu(path->usSize);
 295                 linkb = false;
 296
 297                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 298                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 299
 300                         con_obj_id =
 301                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 302                             >> OBJECT_ID_SHIFT;
 303                         con_obj_num =
 304                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 305                             >> ENUM_ID_SHIFT;
 306                         con_obj_type =
 307                             (le16_to_cpu(path->usConnObjectId) &
 308                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 309
 310                         /* TODO CV support */
 311                         if (le16_to_cpu(path->usDeviceTag) ==
 312                                 ATOM_DEVICE_CV_SUPPORT)
 313                                 continue;
 314
 315                         /* IGP chips */
 316                         if ((rdev->flags & RADEON_IS_IGP) &&
 317                             (con_obj_id ==
 318                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 319                                 uint16_t igp_offset = 0;
 320                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 321
 322                                 index =
 323                                     GetIndexIntoMasterTable(DATA,
 324                                                             IntegratedSystemInfo);
 325
 326                                 atom_parse_data_header(ctx, index, &size, &frev,
 327                                                        &crev, &igp_offset);
 328
 329                                 if (crev >= 2) {
 330                                         igp_obj =
 331                                             (ATOM_INTEGRATED_SYSTEM_INFO_V2
 332                                              *) (ctx->bios + igp_offset);
 333
 334                                         if (igp_obj) {
 335                                                 uint32_t slot_config, ct;
 336
 337                                                 if (con_obj_num == 1)
 338                                                         slot_config =
 339                                                             igp_obj->
 340                                                             ulDDISlot1Config;
 341                                                 else
 342                                                         slot_config =
 343                                                             igp_obj->
 344                                                             ulDDISlot2Config;
 345
 346                                                 ct = (slot_config >> 16) & 0xff;
 347                                                 connector_type =
 348                                                     object_connector_convert
 349                                                     [ct];
 350                                                 connector_object_id = ct;
 351                                                 igp_lane_info =
 352                                                     slot_config & 0xffff;
 353                                         } else
 354                                                 continue;
 355                                 } else
 356                                         continue;
 357                         } else {
 358                                 igp_lane_info = 0;
 359                                 connector_type =
 360                                     object_connector_convert[con_obj_id];
 361                                 connector_object_id = con_obj_id;
 362                         }
 363
 364                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 365                                 continue;
 366
 367                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 368                              j++) {
 369                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 370
 371                                 enc_obj_id =
 372                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 373                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 374                                 enc_obj_num =
 375                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 376                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 377                                 enc_obj_type =
 378                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 379                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 380
 381                                 /* FIXME: add support for router objects */
 382                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 383                                         if (enc_obj_num == 2)
 384                                                 linkb = true;
 385                                         else
 386                                                 linkb = false;
 387
 388                                         radeon_add_atom_encoder(dev,
 389                                                                 enc_obj_id,
 390                                                                 le16_to_cpu
 391                                                                 (path->
 392                                                                  usDeviceTag));
 393
 394                                 }
 395                         }
 396
 397                         /* look up gpio for ddc */
 398                         if ((le16_to_cpu(path->usDeviceTag) &
 399                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
 400                             == 0) {
 401                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 402                                         if (le16_to_cpu(path->usConnObjectId) ==
 403                                             le16_to_cpu(con_obj->asObjects[j].
 404                                                         usObjectID)) {
 405                                                 ATOM_COMMON_RECORD_HEADER
 406                                                     *record =
 407                                                     (ATOM_COMMON_RECORD_HEADER
 408                                                      *)
 409                                                     (ctx->bios + data_offset +
 410                                                      le16_to_cpu(con_obj->
 411                                                                  asObjects[j].
 412                                                                  usRecordOffset));
 413                                                 ATOM_I2C_RECORD *i2c_record;
 414
 415                                                 while (record->ucRecordType > 0
 416                                                        && record->
 417                                                        ucRecordType <=
 418                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 419                                                         switch (record->
 420                                                                 ucRecordType) {
 421                                                         case ATOM_I2C_RECORD_TYPE:
 422                                                                 i2c_record =
 423                                                                     (ATOM_I2C_RECORD
 424                                                                      *) record;
 425                                                                 line_mux =
 426                                                                     i2c_record->
 427                                                                     sucI2cId.
 428                                                                     bfI2C_LineMux;
 429                                                                 break;
 430                                                         }
 431                                                         record =
 432                                                             (ATOM_COMMON_RECORD_HEADER
 433                                                              *) ((char *)record
 434                                                                  +
 435                                                                  record->
 436                                                                  ucRecordSize);
 437                                                 }
 438                                                 break;
 439                                         }
 440                                 }
 441                         } else
 442                                 line_mux = 0;
 443
 444                         if ((le16_to_cpu(path->usDeviceTag) ==
 445                              ATOM_DEVICE_TV1_SUPPORT)
 446                             || (le16_to_cpu(path->usDeviceTag) ==
 447                                 ATOM_DEVICE_TV2_SUPPORT)
 448                             || (le16_to_cpu(path->usDeviceTag) ==
 449                                 ATOM_DEVICE_CV_SUPPORT))
 450                                 ddc_bus.valid = false;
 451                         else
 452                                 ddc_bus = radeon_lookup_gpio(dev, line_mux);
 453
 454                         conn_id = le16_to_cpu(path->usConnObjectId);
 455
 456                         if (!radeon_atom_apply_quirks
 457                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 458                              &ddc_bus, &conn_id))
 459                                 continue;
 460
 461                         radeon_add_atom_connector(dev,
 462                                                   conn_id,
 463                                                   le16_to_cpu(path->
 464                                                               usDeviceTag),
 465                                                   connector_type, &ddc_bus,
 466                                                   linkb, igp_lane_info,
 467                                                   connector_object_id);
 468
 469                 }
 470         }
 471
 472         radeon_link_encoder_connector(dev);
 473
 474         return true;
 475 }
 476
 477 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 478                                                  int connector_type,
 479                                                  uint16_t devices)
 480 {
 481         struct radeon_device *rdev = dev->dev_private;
 482
 483         if (rdev->flags & RADEON_IS_IGP) {
 484                 return supported_devices_connector_object_id_convert
 485                         [connector_type];
 486         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 487                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 488                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 489                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 490                 struct atom_context *ctx = mode_info->atom_context;
 491                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 492                 uint16_t size, data_offset;
 493                 uint8_t frev, crev;
 494                 ATOM_XTMDS_INFO *xtmds;
 495
 496                 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 497                 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 498
 499                 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 500                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 501                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 502                         else
 503                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 504                 } else {
 505                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 506                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 507                         else
 508                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 509                 }
 510         } else {
 511                 return supported_devices_connector_object_id_convert
 512                         [connector_type];
 513         }
 514 }
 515
 516 struct bios_connector {
 517         bool valid;
 518         uint16_t line_mux;
 519         uint16_t devices;
 520         int connector_type;
 521         struct radeon_i2c_bus_rec ddc_bus;
 522 };
 523
 524 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 525                                                                  drm_device
 526                                                                  *dev)
 527 {
 528         struct radeon_device *rdev = dev->dev_private;
 529         struct radeon_mode_info *mode_info = &rdev->mode_info;
 530         struct atom_context *ctx = mode_info->atom_context;
 531         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 532         uint16_t size, data_offset;
 533         uint8_t frev, crev;
 534         uint16_t device_support;
 535         uint8_t dac;
 536         union atom_supported_devices *supported_devices;
 537         int i, j;
 538         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 539
 540         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 541
 542         supported_devices =
 543             (union atom_supported_devices *)(ctx->bios + data_offset);
 544
 545         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 546
 547         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 548                 ATOM_CONNECTOR_INFO_I2C ci =
 549                     supported_devices->info.asConnInfo[i];
 550
 551                 bios_connectors[i].valid = false;
 552
 553                 if (!(device_support & (1 << i))) {
 554                         continue;
 555                 }
 556
 557                 if (i == ATOM_DEVICE_CV_INDEX) {
 558                         DRM_DEBUG("Skipping Component Video\n");
 559                         continue;
 560                 }
 561
 562                 bios_connectors[i].connector_type =
 563                     supported_devices_connector_convert[ci.sucConnectorInfo.
 564                                                         sbfAccess.
 565                                                         bfConnectorType];
 566
 567                 if (bios_connectors[i].connector_type ==
 568                     DRM_MODE_CONNECTOR_Unknown)
 569                         continue;
 570
 571                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 572
 573                 if ((rdev->family == CHIP_RS690) ||
 574                     (rdev->family == CHIP_RS740)) {
 575                         if ((i == ATOM_DEVICE_DFP2_INDEX)
 576                             && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
 577                                 bios_connectors[i].line_mux =
 578                                     ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
 579                         else if ((i == ATOM_DEVICE_DFP3_INDEX)
 580                                  && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
 581                                 bios_connectors[i].line_mux =
 582                                     ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
 583                         else
 584                                 bios_connectors[i].line_mux =
 585                                     ci.sucI2cId.sbfAccess.bfI2C_LineMux;
 586                 } else
 587                         bios_connectors[i].line_mux =
 588                             ci.sucI2cId.sbfAccess.bfI2C_LineMux;
 589
 590                 /* give tv unique connector ids */
 591                 if (i == ATOM_DEVICE_TV1_INDEX) {
 592                         bios_connectors[i].ddc_bus.valid = false;
 593                         bios_connectors[i].line_mux = 50;
 594                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 595                         bios_connectors[i].ddc_bus.valid = false;
 596                         bios_connectors[i].line_mux = 51;
 597                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 598                         bios_connectors[i].ddc_bus.valid = false;
 599                         bios_connectors[i].line_mux = 52;
 600                 } else
 601                         bios_connectors[i].ddc_bus =
 602                             radeon_lookup_gpio(dev,
 603                                                bios_connectors[i].line_mux);
 604
 605                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 606                  * shared with a DVI port, we'll pick up the DVI connector when we
 607                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 608                  */
 609                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 610                         bios_connectors[i].connector_type =
 611                             DRM_MODE_CONNECTOR_VGA;
 612
 613                 if (!radeon_atom_apply_quirks
 614                     (dev, (1 << i), &bios_connectors[i].connector_type,
 615                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
 616                         continue;
 617
 618                 bios_connectors[i].valid = true;
 619                 bios_connectors[i].devices = (1 << i);
 620
 621                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 622                         radeon_add_atom_encoder(dev,
 623                                                 radeon_get_encoder_id(dev,
 624                                                                       (1 << i),
 625                                                                       dac),
 626                                                 (1 << i));
 627                 else
 628                         radeon_add_legacy_encoder(dev,
 629                                                   radeon_get_encoder_id(dev,
 630                                                                         (1 <<
 631                                                                          i),
 632                                                                         dac),
 633                                                   (1 << i));
 634         }
 635
 636         /* combine shared connectors */
 637         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 638                 if (bios_connectors[i].valid) {
 639                         for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
 640                                 if (bios_connectors[j].valid && (i != j)) {
 641                                         if (bios_connectors[i].line_mux ==
 642                                             bios_connectors[j].line_mux) {
 643                                                 if (((bios_connectors[i].
 644                                                       devices &
 645                                                       (ATOM_DEVICE_DFP_SUPPORT))
 646                                                      && (bios_connectors[j].
 647                                                          devices &
 648                                                          (ATOM_DEVICE_CRT_SUPPORT)))
 649                                                     ||
 650                                                     ((bios_connectors[j].
 651                                                       devices &
 652                                                       (ATOM_DEVICE_DFP_SUPPORT))
 653                                                      && (bios_connectors[i].
 654                                                          devices &
 655                                                          (ATOM_DEVICE_CRT_SUPPORT)))) {
 656                                                         bios_connectors[i].
 657                                                             devices |=
 658                                                             bios_connectors[j].
 659                                                             devices;
 660                                                         bios_connectors[i].
 661                                                             connector_type =
 662                                                             DRM_MODE_CONNECTOR_DVII;
 663                                                         bios_connectors[j].
 664                                                             valid = false;
 665                                                 }
 666                                         }
 667                                 }
 668                         }
 669                 }
 670         }
 671
 672         /* add the connectors */
 673         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 674                 if (bios_connectors[i].valid) {
 675                         uint16_t connector_object_id =
 676                                 atombios_get_connector_object_id(dev,
 677                                                       bios_connectors[i].connector_type,
 678                                                       bios_connectors[i].devices);
 679                         radeon_add_atom_connector(dev,
 680                                                   bios_connectors[i].line_mux,
 681                                                   bios_connectors[i].devices,
 682                                                   bios_connectors[i].
 683                                                   connector_type,
 684                                                   &bios_connectors[i].ddc_bus,
 685                                                   false, 0,
 686                                                   connector_object_id);
 687                 }
 688         }
 689
 690         radeon_link_encoder_connector(dev);
 691
 692         return true;
 693 }
 694
 695 union firmware_info {
 696         ATOM_FIRMWARE_INFO info;
 697         ATOM_FIRMWARE_INFO_V1_2 info_12;
 698         ATOM_FIRMWARE_INFO_V1_3 info_13;
 699         ATOM_FIRMWARE_INFO_V1_4 info_14;
 700 };
 701
 702 bool radeon_atom_get_clock_info(struct drm_device *dev)
 703 {
 704         struct radeon_device *rdev = dev->dev_private;
 705         struct radeon_mode_info *mode_info = &rdev->mode_info;
 706         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 707         union firmware_info *firmware_info;
 708         uint8_t frev, crev;
 709         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 710         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 711         struct radeon_pll *spll = &rdev->clock.spll;
 712         struct radeon_pll *mpll = &rdev->clock.mpll;
 713         uint16_t data_offset;
 714
 715         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 716                                &crev, &data_offset);
 717
 718         firmware_info =
 719             (union firmware_info *)(mode_info->atom_context->bios +
 720                                     data_offset);
 721
 722         if (firmware_info) {
 723                 /* pixel clocks */
 724                 p1pll->reference_freq =
 725                     le16_to_cpu(firmware_info->info.usReferenceClock);
 726                 p1pll->reference_div = 0;
 727
 728                 if (crev < 2)
 729                         p1pll->pll_out_min =
 730                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 731                 else
 732                         p1pll->pll_out_min =
 733                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 734                 p1pll->pll_out_max =
 735                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 736
 737                 if (p1pll->pll_out_min == 0) {
 738                         if (ASIC_IS_AVIVO(rdev))
 739                                 p1pll->pll_out_min = 64800;
 740                         else
 741                                 p1pll->pll_out_min = 20000;
 742                 } else if (p1pll->pll_out_min > 64800) {
 743                         /* Limiting the pll output range is a good thing generally as
 744                          * it limits the number of possible pll combinations for a given
 745                          * frequency presumably to the ones that work best on each card.
 746                          * However, certain duallink DVI monitors seem to like
 747                          * pll combinations that would be limited by this at least on
 748                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 749                          * family.
 750                          */
 751                         p1pll->pll_out_min = 64800;
 752                 }
 753
 754                 p1pll->pll_in_min =
 755                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 756                 p1pll->pll_in_max =
 757                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 758
 759                 *p2pll = *p1pll;
 760
 761                 /* system clock */
 762                 spll->reference_freq =
 763                     le16_to_cpu(firmware_info->info.usReferenceClock);
 764                 spll->reference_div = 0;
 765
 766                 spll->pll_out_min =
 767                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 768                 spll->pll_out_max =
 769                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 770
 771                 /* ??? */
 772                 if (spll->pll_out_min == 0) {
 773                         if (ASIC_IS_AVIVO(rdev))
 774                                 spll->pll_out_min = 64800;
 775                         else
 776                                 spll->pll_out_min = 20000;
 777                 }
 778
 779                 spll->pll_in_min =
 780                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 781                 spll->pll_in_max =
 782                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 783
 784                 /* memory clock */
 785                 mpll->reference_freq =
 786                     le16_to_cpu(firmware_info->info.usReferenceClock);
 787                 mpll->reference_div = 0;
 788
 789                 mpll->pll_out_min =
 790                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 791                 mpll->pll_out_max =
 792                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 793
 794                 /* ??? */
 795                 if (mpll->pll_out_min == 0) {
 796                         if (ASIC_IS_AVIVO(rdev))
 797                                 mpll->pll_out_min = 64800;
 798                         else
 799                                 mpll->pll_out_min = 20000;
 800                 }
 801
 802                 mpll->pll_in_min =
 803                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 804                 mpll->pll_in_max =
 805                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 806
 807                 rdev->clock.default_sclk =
 808                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 809                 rdev->clock.default_mclk =
 810                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 811
 812                 return true;
 813         }
 814         return false;
 815 }
 816
 817 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
 818                                    struct radeon_encoder_int_tmds *tmds)
 819 {
 820         struct drm_device *dev = encoder->base.dev;
 821         struct radeon_device *rdev = dev->dev_private;
 822         struct radeon_mode_info *mode_info = &rdev->mode_info;
 823         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
 824         uint16_t data_offset;
 825         struct _ATOM_TMDS_INFO *tmds_info;
 826         uint8_t frev, crev;
 827         uint16_t maxfreq;
 828         int i;
 829
 830         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 831                                &crev, &data_offset);
 832
 833         tmds_info =
 834             (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
 835                                        data_offset);
 836
 837         if (tmds_info) {
 838                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
 839                 for (i = 0; i < 4; i++) {
 840                         tmds->tmds_pll[i].freq =
 841                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
 842                         tmds->tmds_pll[i].value =
 843                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
 844                         tmds->tmds_pll[i].value |=
 845                             (tmds_info->asMiscInfo[i].
 846                              ucPLL_VCO_Gain & 0x3f) << 6;
 847                         tmds->tmds_pll[i].value |=
 848                             (tmds_info->asMiscInfo[i].
 849                              ucPLL_DutyCycle & 0xf) << 12;
 850                         tmds->tmds_pll[i].value |=
 851                             (tmds_info->asMiscInfo[i].
 852                              ucPLL_VoltageSwing & 0xf) << 16;
 853
 854                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
 855                                   tmds->tmds_pll[i].freq,
 856                                   tmds->tmds_pll[i].value);
 857
 858                         if (maxfreq == tmds->tmds_pll[i].freq) {
 859                                 tmds->tmds_pll[i].freq = 0xffffffff;
 860                                 break;
 861                         }
 862                 }
 863                 return true;
 864         }
 865         return false;
 866 }
 867
 868 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
 869                                                           radeon_encoder
 870                                                           *encoder,
 871                                                           int id)
 872 {
 873         struct drm_device *dev = encoder->base.dev;
 874         struct radeon_device *rdev = dev->dev_private;
 875         struct radeon_mode_info *mode_info = &rdev->mode_info;
 876         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
 877         uint16_t data_offset;
 878         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
 879         uint8_t frev, crev;
 880         struct radeon_atom_ss *ss = NULL;
 881
 882         if (id > ATOM_MAX_SS_ENTRY)
 883                 return NULL;
 884
 885         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 886                                &crev, &data_offset);
 887
 888         ss_info =
 889             (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
 890
 891         if (ss_info) {
 892                 ss =
 893                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
 894
 895                 if (!ss)
 896                         return NULL;
 897
 898                 ss->percentage = le16_to_cpu(ss_info->asSS_Info[id].usSpreadSpectrumPercentage);
 899                 ss->type = ss_info->asSS_Info[id].ucSpreadSpectrumType;
 900                 ss->step = ss_info->asSS_Info[id].ucSS_Step;
 901                 ss->delay = ss_info->asSS_Info[id].ucSS_Delay;
 902                 ss->range = ss_info->asSS_Info[id].ucSS_Range;
 903                 ss->refdiv = ss_info->asSS_Info[id].ucRecommendedRef_Div;
 904         }
 905         return ss;
 906 }
 907
 908 union lvds_info {
 909         struct _ATOM_LVDS_INFO info;
 910         struct _ATOM_LVDS_INFO_V12 info_12;
 911 };
 912
 913 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
 914                                                               radeon_encoder
 915                                                               *encoder)
 916 {
 917         struct drm_device *dev = encoder->base.dev;
 918         struct radeon_device *rdev = dev->dev_private;
 919         struct radeon_mode_info *mode_info = &rdev->mode_info;
 920         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
 921         uint16_t data_offset;
 922         union lvds_info *lvds_info;
 923         uint8_t frev, crev;
 924         struct radeon_encoder_atom_dig *lvds = NULL;
 925
 926         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 927                                &crev, &data_offset);
 928
 929         lvds_info =
 930             (union lvds_info *)(mode_info->atom_context->bios + data_offset);
 931
 932         if (lvds_info) {
 933                 lvds =
 934                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
 935
 936                 if (!lvds)
 937                         return NULL;
 938
 939                 lvds->native_mode.clock =
 940                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
 941                 lvds->native_mode.hdisplay =
 942                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
 943                 lvds->native_mode.vdisplay =
 944                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
 945                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
 946                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
 947                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
 948                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
 949                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
 950                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
 951                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
 952                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
 953                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
 954                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
 955                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
 956                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
 957                 lvds->panel_pwr_delay =
 958                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
 959                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
 960                 /* set crtc values */
 961                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
 962
 963                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
 964
 965                 encoder->native_mode = lvds->native_mode;
 966         }
 967         return lvds;
 968 }
 969
 970 struct radeon_encoder_primary_dac *
 971 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
 972 {
 973         struct drm_device *dev = encoder->base.dev;
 974         struct radeon_device *rdev = dev->dev_private;
 975         struct radeon_mode_info *mode_info = &rdev->mode_info;
 976         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
 977         uint16_t data_offset;
 978         struct _COMPASSIONATE_DATA *dac_info;
 979         uint8_t frev, crev;
 980         uint8_t bg, dac;
 981         struct radeon_encoder_primary_dac *p_dac = NULL;
 982
 983         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
 984
 985         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
 986
 987         if (dac_info) {
 988                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
 989
 990                 if (!p_dac)
 991                         return NULL;
 992
 993                 bg = dac_info->ucDAC1_BG_Adjustment;
 994                 dac = dac_info->ucDAC1_DAC_Adjustment;
 995                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 996
 997         }
 998         return p_dac;
 999 }
1000
1001 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1002                                 struct drm_display_mode *mode)
1003 {
1004         struct radeon_mode_info *mode_info = &rdev->mode_info;
1005         ATOM_ANALOG_TV_INFO *tv_info;
1006         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1007         ATOM_DTD_FORMAT *dtd_timings;
1008         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1009         u8 frev, crev;
1010         u16 data_offset, misc;
1011
1012         atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1013
1014         switch (crev) {
1015         case 1:
1016                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1017                 if (index > MAX_SUPPORTED_TV_TIMING)
1018                         return false;
1019
1020                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1021                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1022                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1023                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1024                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1025
1026                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1027                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1028                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1029                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1030                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1031
1032                 mode->flags = 0;
1033                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1034                 if (misc & ATOM_VSYNC_POLARITY)
1035                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1036                 if (misc & ATOM_HSYNC_POLARITY)
1037                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1038                 if (misc & ATOM_COMPOSITESYNC)
1039                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1040                 if (misc & ATOM_INTERLACE)
1041                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1042                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1043                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1044
1045                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1046
1047                 if (index == 1) {
1048                         /* PAL timings appear to have wrong values for totals */
1049                         mode->crtc_htotal -= 1;
1050                         mode->crtc_vtotal -= 1;
1051                 }
1052                 break;
1053         case 2:
1054                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1055                 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1056                         return false;
1057
1058                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1059                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1060                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1061                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1062                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1063                         le16_to_cpu(dtd_timings->usHSyncOffset);
1064                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1065                         le16_to_cpu(dtd_timings->usHSyncWidth);
1066
1067                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1068                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1069                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1070                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1071                         le16_to_cpu(dtd_timings->usVSyncOffset);
1072                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1073                         le16_to_cpu(dtd_timings->usVSyncWidth);
1074
1075                 mode->flags = 0;
1076                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1077                 if (misc & ATOM_VSYNC_POLARITY)
1078                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1079                 if (misc & ATOM_HSYNC_POLARITY)
1080                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1081                 if (misc & ATOM_COMPOSITESYNC)
1082                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1083                 if (misc & ATOM_INTERLACE)
1084                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1085                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1086                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1087
1088                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1089                 break;
1090         }
1091         return true;
1092 }
1093
1094 struct radeon_encoder_tv_dac *
1095 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1096 {
1097         struct drm_device *dev = encoder->base.dev;
1098         struct radeon_device *rdev = dev->dev_private;
1099         struct radeon_mode_info *mode_info = &rdev->mode_info;
1100         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1101         uint16_t data_offset;
1102         struct _COMPASSIONATE_DATA *dac_info;
1103         uint8_t frev, crev;
1104         uint8_t bg, dac;
1105         struct radeon_encoder_tv_dac *tv_dac = NULL;
1106
1107         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1108
1109         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1110
1111         if (dac_info) {
1112                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1113
1114                 if (!tv_dac)
1115                         return NULL;
1116
1117                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1118                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1119                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1120
1121                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1122                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1123                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1124
1125                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1126                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1127                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1128
1129         }
1130         return tv_dac;
1131 }
1132
1133 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1134 {
1135         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1136         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1137
1138         args.ucEnable = enable;
1139
1140         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1141 }
1142
1143 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1144 {
1145         ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1146         int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1147
1148         args.ucEnable = enable;
1149
1150         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1151 }
1152
1153 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1154 {
1155         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1156         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1157
1158         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1159         return args.ulReturnEngineClock;
1160 }
1161
1162 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1163 {
1164         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1165         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1166
1167         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1168         return args.ulReturnMemoryClock;
1169 }
1170
1171 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1172                                   uint32_t eng_clock)
1173 {
1174         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1175         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1176
1177         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
1178
1179         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1180 }
1181
1182 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1183                                   uint32_t mem_clock)
1184 {
1185         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1186         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1187
1188         if (rdev->flags & RADEON_IS_IGP)
1189                 return;
1190
1191         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1192
1193         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1194 }
1195
1196 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1197 {
1198         struct radeon_device *rdev = dev->dev_private;
1199         uint32_t bios_2_scratch, bios_6_scratch;
1200
1201         if (rdev->family >= CHIP_R600) {
1202                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1203                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1204         } else {
1205                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1206                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1207         }
1208
1209         /* let the bios control the backlight */
1210         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1211
1212         /* tell the bios not to handle mode switching */
1213         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1214
1215         if (rdev->family >= CHIP_R600) {
1216                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1217                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1218         } else {
1219                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1220                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1221         }
1222
1223 }
1224
1225 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1226 {
1227         uint32_t scratch_reg;
1228         int i;
1229
1230         if (rdev->family >= CHIP_R600)
1231                 scratch_reg = R600_BIOS_0_SCRATCH;
1232         else
1233                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1234
1235         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1236                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1237 }
1238
1239 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1240 {
1241         uint32_t scratch_reg;
1242         int i;
1243
1244         if (rdev->family >= CHIP_R600)
1245                 scratch_reg = R600_BIOS_0_SCRATCH;
1246         else
1247                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1248
1249         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1250                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1251 }
1252
1253 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1254 {
1255         struct drm_device *dev = encoder->dev;
1256         struct radeon_device *rdev = dev->dev_private;
1257         uint32_t bios_6_scratch;
1258
1259         if (rdev->family >= CHIP_R600)
1260                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1261         else
1262                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1263
1264         if (lock)
1265                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1266         else
1267                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1268
1269         if (rdev->family >= CHIP_R600)
1270                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1271         else
1272                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1273 }
1274
1275 /* at some point we may want to break this out into individual functions */
1276 void
1277 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1278                                        struct drm_encoder *encoder,
1279                                        bool connected)
1280 {
1281         struct drm_device *dev = connector->dev;
1282         struct radeon_device *rdev = dev->dev_private;
1283         struct radeon_connector *radeon_connector =
1284             to_radeon_connector(connector);
1285         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1286         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1287
1288         if (rdev->family >= CHIP_R600) {
1289                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1290                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1291                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1292         } else {
1293                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1294                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1295                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1296         }
1297
1298         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1299             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1300                 if (connected) {
1301                         DRM_DEBUG("TV1 connected\n");
1302                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1303                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1304                 } else {
1305                         DRM_DEBUG("TV1 disconnected\n");
1306                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1307                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1308                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1309                 }
1310         }
1311         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1312             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1313                 if (connected) {
1314                         DRM_DEBUG("CV connected\n");
1315                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1316                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1317                 } else {
1318                         DRM_DEBUG("CV disconnected\n");
1319                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
1320                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1321                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1322                 }
1323         }
1324         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1325             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1326                 if (connected) {
1327                         DRM_DEBUG("LCD1 connected\n");
1328                         bios_0_scratch |= ATOM_S0_LCD1;
1329                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1330                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1331                 } else {
1332                         DRM_DEBUG("LCD1 disconnected\n");
1333                         bios_0_scratch &= ~ATOM_S0_LCD1;
1334                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1335                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1336                 }
1337         }
1338         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1339             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1340                 if (connected) {
1341                         DRM_DEBUG("CRT1 connected\n");
1342                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1343                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1344                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1345                 } else {
1346                         DRM_DEBUG("CRT1 disconnected\n");
1347                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1348                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1349                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1350                 }
1351         }
1352         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1353             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1354                 if (connected) {
1355                         DRM_DEBUG("CRT2 connected\n");
1356                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1357                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1358                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1359                 } else {
1360                         DRM_DEBUG("CRT2 disconnected\n");
1361                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1362                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1363                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1364                 }
1365         }
1366         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1367             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1368                 if (connected) {
1369                         DRM_DEBUG("DFP1 connected\n");
1370                         bios_0_scratch |= ATOM_S0_DFP1;
1371                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1372                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1373                 } else {
1374                         DRM_DEBUG("DFP1 disconnected\n");
1375                         bios_0_scratch &= ~ATOM_S0_DFP1;
1376                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1377                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1378                 }
1379         }
1380         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1381             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1382                 if (connected) {
1383                         DRM_DEBUG("DFP2 connected\n");
1384                         bios_0_scratch |= ATOM_S0_DFP2;
1385                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1386                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1387                 } else {
1388                         DRM_DEBUG("DFP2 disconnected\n");
1389                         bios_0_scratch &= ~ATOM_S0_DFP2;
1390                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1391                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1392                 }
1393         }
1394         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1395             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1396                 if (connected) {
1397                         DRM_DEBUG("DFP3 connected\n");
1398                         bios_0_scratch |= ATOM_S0_DFP3;
1399                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1400                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1401                 } else {
1402                         DRM_DEBUG("DFP3 disconnected\n");
1403                         bios_0_scratch &= ~ATOM_S0_DFP3;
1404                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1405                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1406                 }
1407         }
1408         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1409             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1410                 if (connected) {
1411                         DRM_DEBUG("DFP4 connected\n");
1412                         bios_0_scratch |= ATOM_S0_DFP4;
1413                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1414                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1415                 } else {
1416                         DRM_DEBUG("DFP4 disconnected\n");
1417                         bios_0_scratch &= ~ATOM_S0_DFP4;
1418                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1419                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1420                 }
1421         }
1422         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1423             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1424                 if (connected) {
1425                         DRM_DEBUG("DFP5 connected\n");
1426                         bios_0_scratch |= ATOM_S0_DFP5;
1427                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1428                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1429                 } else {
1430                         DRM_DEBUG("DFP5 disconnected\n");
1431                         bios_0_scratch &= ~ATOM_S0_DFP5;
1432                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1433                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1434                 }
1435         }
1436
1437         if (rdev->family >= CHIP_R600) {
1438                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1439                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1440                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1441         } else {
1442                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1443                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1444                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1445         }
1446 }
1447
1448 void
1449 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1450 {
1451         struct drm_device *dev = encoder->dev;
1452         struct radeon_device *rdev = dev->dev_private;
1453         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1454         uint32_t bios_3_scratch;
1455
1456         if (rdev->family >= CHIP_R600)
1457                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1458         else
1459                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1460
1461         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1462                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1463                 bios_3_scratch |= (crtc << 18);
1464         }
1465         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1466                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1467                 bios_3_scratch |= (crtc << 24);
1468         }
1469         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1470                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1471                 bios_3_scratch |= (crtc << 16);
1472         }
1473         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1474                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1475                 bios_3_scratch |= (crtc << 20);
1476         }
1477         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1478                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1479                 bios_3_scratch |= (crtc << 17);
1480         }
1481         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1482                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1483                 bios_3_scratch |= (crtc << 19);
1484         }
1485         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1486                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1487                 bios_3_scratch |= (crtc << 23);
1488         }
1489         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1490                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1491                 bios_3_scratch |= (crtc << 25);
1492         }
1493
1494         if (rdev->family >= CHIP_R600)
1495                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1496         else
1497                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1498 }
1499
1500 void
1501 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1502 {
1503         struct drm_device *dev = encoder->dev;
1504         struct radeon_device *rdev = dev->dev_private;
1505         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1506         uint32_t bios_2_scratch;
1507
1508         if (rdev->family >= CHIP_R600)
1509                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1510         else
1511                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1512
1513         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1514                 if (on)
1515                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1516                 else
1517                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1518         }
1519         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1520                 if (on)
1521                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1522                 else
1523                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1524         }
1525         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1526                 if (on)
1527                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1528                 else
1529                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1530         }
1531         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1532                 if (on)
1533                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1534                 else
1535                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1536         }
1537         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1538                 if (on)
1539                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1540                 else
1541                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1542         }
1543         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1544                 if (on)
1545                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1546                 else
1547                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1548         }
1549         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1550                 if (on)
1551                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1552                 else
1553                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1554         }
1555         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1556                 if (on)
1557                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1558                 else
1559                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1560         }
1561         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1562                 if (on)
1563                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1564                 else
1565                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1566         }
1567         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1568                 if (on)
1569                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1570                 else
1571                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1572         }
1573
1574         if (rdev->family >= CHIP_R600)
1575                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1576         else
1577                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1578 }