drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id);
  51
  52 /* from radeon_legacy_encoder.c */
  53 extern void
  54 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  55                           uint32_t supported_device);
  56
  57 union atom_supported_devices {
  58         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  59         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  61 };
  62
  63 static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
  64                                                            *dev, uint8_t id)
  65 {
  66         struct radeon_device *rdev = dev->dev_private;
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset;
  73
  74         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  75         i2c.valid = false;
  76
  77         atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  78
  79         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  80
  81         gpio = i2c_info->asGPIO_Info[id];
  82
  83         i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
  84         i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
  85         i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
  86         i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
  87         i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
  88         i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
  89         i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
  90         i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
  91         i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
  92         i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
  93         i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
  94         i2c.put_data_mask = (1 << gpio.ucDataEnShift);
  95         i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
  96         i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
  97         i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
  98         i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
  99         i2c.valid = true;
 100
 101         return i2c;
 102 }
 103
 104 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 105                                      uint32_t supported_device,
 106                                      int *connector_type,
 107                                      struct radeon_i2c_bus_rec *i2c_bus,
 108                                      uint16_t *line_mux)
 109 {
 110
 111         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 112         if ((dev->pdev->device == 0x791e) &&
 113             (dev->pdev->subsystem_vendor == 0x1043) &&
 114             (dev->pdev->subsystem_device == 0x826d)) {
 115                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 116                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 117                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 118         }
 119
 120         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 121         if ((dev->pdev->device == 0x7941) &&
 122             (dev->pdev->subsystem_vendor == 0x147b) &&
 123             (dev->pdev->subsystem_device == 0x2412)) {
 124                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 125                         return false;
 126         }
 127
 128         /* Falcon NW laptop lists vga ddc line for LVDS */
 129         if ((dev->pdev->device == 0x5653) &&
 130             (dev->pdev->subsystem_vendor == 0x1462) &&
 131             (dev->pdev->subsystem_device == 0x0291)) {
 132                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 133                         i2c_bus->valid = false;
 134                         *line_mux = 53;
 135                 }
 136         }
 137
 138         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 139         if ((dev->pdev->device == 0x7146) &&
 140             (dev->pdev->subsystem_vendor == 0x17af) &&
 141             (dev->pdev->subsystem_device == 0x2058)) {
 142                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 143                         return false;
 144         }
 145
 146         /* Funky macbooks */
 147         if ((dev->pdev->device == 0x71C5) &&
 148             (dev->pdev->subsystem_vendor == 0x106b) &&
 149             (dev->pdev->subsystem_device == 0x0080)) {
 150                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 151                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 152                         return false;
 153         }
 154
 155         /* mac rv630, rv730, others */
 156         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 157             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 158                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 159                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 160         }
 161
 162         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 163         if ((dev->pdev->device == 0x9598) &&
 164             (dev->pdev->subsystem_vendor == 0x1043) &&
 165             (dev->pdev->subsystem_device == 0x01da)) {
 166                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 167                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 168                 }
 169         }
 170
 171         /* ASUS HD 3600 board lists the DVI port as HDMI */
 172         if ((dev->pdev->device == 0x9598) &&
 173             (dev->pdev->subsystem_vendor == 0x1043) &&
 174             (dev->pdev->subsystem_device == 0x01e4)) {
 175                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 176                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 177                 }
 178         }
 179
 180         /* ASUS HD 3450 board lists the DVI port as HDMI */
 181         if ((dev->pdev->device == 0x95C5) &&
 182             (dev->pdev->subsystem_vendor == 0x1043) &&
 183             (dev->pdev->subsystem_device == 0x01e2)) {
 184                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 185                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 186                 }
 187         }
 188
 189         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 190          * HDMI + VGA reporting as HDMI
 191          */
 192         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 193                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 194                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 195                         *line_mux = 0;
 196                 }
 197         }
 198
 199         return true;
 200 }
 201
 202 const int supported_devices_connector_convert[] = {
 203         DRM_MODE_CONNECTOR_Unknown,
 204         DRM_MODE_CONNECTOR_VGA,
 205         DRM_MODE_CONNECTOR_DVII,
 206         DRM_MODE_CONNECTOR_DVID,
 207         DRM_MODE_CONNECTOR_DVIA,
 208         DRM_MODE_CONNECTOR_SVIDEO,
 209         DRM_MODE_CONNECTOR_Composite,
 210         DRM_MODE_CONNECTOR_LVDS,
 211         DRM_MODE_CONNECTOR_Unknown,
 212         DRM_MODE_CONNECTOR_Unknown,
 213         DRM_MODE_CONNECTOR_HDMIA,
 214         DRM_MODE_CONNECTOR_HDMIB,
 215         DRM_MODE_CONNECTOR_Unknown,
 216         DRM_MODE_CONNECTOR_Unknown,
 217         DRM_MODE_CONNECTOR_9PinDIN,
 218         DRM_MODE_CONNECTOR_DisplayPort
 219 };
 220
 221 const uint16_t supported_devices_connector_object_id_convert[] = {
 222         CONNECTOR_OBJECT_ID_NONE,
 223         CONNECTOR_OBJECT_ID_VGA,
 224         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 225         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 226         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 227         CONNECTOR_OBJECT_ID_COMPOSITE,
 228         CONNECTOR_OBJECT_ID_SVIDEO,
 229         CONNECTOR_OBJECT_ID_LVDS,
 230         CONNECTOR_OBJECT_ID_9PIN_DIN,
 231         CONNECTOR_OBJECT_ID_9PIN_DIN,
 232         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 233         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 234         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 235         CONNECTOR_OBJECT_ID_SVIDEO
 236 };
 237
 238 const int object_connector_convert[] = {
 239         DRM_MODE_CONNECTOR_Unknown,
 240         DRM_MODE_CONNECTOR_DVII,
 241         DRM_MODE_CONNECTOR_DVII,
 242         DRM_MODE_CONNECTOR_DVID,
 243         DRM_MODE_CONNECTOR_DVID,
 244         DRM_MODE_CONNECTOR_VGA,
 245         DRM_MODE_CONNECTOR_Composite,
 246         DRM_MODE_CONNECTOR_SVIDEO,
 247         DRM_MODE_CONNECTOR_Unknown,
 248         DRM_MODE_CONNECTOR_Unknown,
 249         DRM_MODE_CONNECTOR_9PinDIN,
 250         DRM_MODE_CONNECTOR_Unknown,
 251         DRM_MODE_CONNECTOR_HDMIA,
 252         DRM_MODE_CONNECTOR_HDMIB,
 253         DRM_MODE_CONNECTOR_LVDS,
 254         DRM_MODE_CONNECTOR_9PinDIN,
 255         DRM_MODE_CONNECTOR_Unknown,
 256         DRM_MODE_CONNECTOR_Unknown,
 257         DRM_MODE_CONNECTOR_Unknown,
 258         DRM_MODE_CONNECTOR_DisplayPort
 259 };
 260
 261 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 262 {
 263         struct radeon_device *rdev = dev->dev_private;
 264         struct radeon_mode_info *mode_info = &rdev->mode_info;
 265         struct atom_context *ctx = mode_info->atom_context;
 266         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 267         uint16_t size, data_offset;
 268         uint8_t frev, crev, line_mux = 0;
 269         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 270         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 271         ATOM_OBJECT_HEADER *obj_header;
 272         int i, j, path_size, device_support;
 273         int connector_type;
 274         uint16_t igp_lane_info, conn_id, connector_object_id;
 275         bool linkb;
 276         struct radeon_i2c_bus_rec ddc_bus;
 277
 278         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 279
 280         if (data_offset == 0)
 281                 return false;
 282
 283         if (crev < 2)
 284                 return false;
 285
 286         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 287         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 288             (ctx->bios + data_offset +
 289              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 290         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 291             (ctx->bios + data_offset +
 292              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 293         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 294
 295         path_size = 0;
 296         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 297                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 298                 ATOM_DISPLAY_OBJECT_PATH *path;
 299                 addr += path_size;
 300                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 301                 path_size += le16_to_cpu(path->usSize);
 302                 linkb = false;
 303
 304                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 305                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 306
 307                         con_obj_id =
 308                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 309                             >> OBJECT_ID_SHIFT;
 310                         con_obj_num =
 311                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 312                             >> ENUM_ID_SHIFT;
 313                         con_obj_type =
 314                             (le16_to_cpu(path->usConnObjectId) &
 315                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 316
 317                         /* TODO CV support */
 318                         if (le16_to_cpu(path->usDeviceTag) ==
 319                                 ATOM_DEVICE_CV_SUPPORT)
 320                                 continue;
 321
 322                         /* IGP chips */
 323                         if ((rdev->flags & RADEON_IS_IGP) &&
 324                             (con_obj_id ==
 325                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 326                                 uint16_t igp_offset = 0;
 327                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 328
 329                                 index =
 330                                     GetIndexIntoMasterTable(DATA,
 331                                                             IntegratedSystemInfo);
 332
 333                                 atom_parse_data_header(ctx, index, &size, &frev,
 334                                                        &crev, &igp_offset);
 335
 336                                 if (crev >= 2) {
 337                                         igp_obj =
 338                                             (ATOM_INTEGRATED_SYSTEM_INFO_V2
 339                                              *) (ctx->bios + igp_offset);
 340
 341                                         if (igp_obj) {
 342                                                 uint32_t slot_config, ct;
 343
 344                                                 if (con_obj_num == 1)
 345                                                         slot_config =
 346                                                             igp_obj->
 347                                                             ulDDISlot1Config;
 348                                                 else
 349                                                         slot_config =
 350                                                             igp_obj->
 351                                                             ulDDISlot2Config;
 352
 353                                                 ct = (slot_config >> 16) & 0xff;
 354                                                 connector_type =
 355                                                     object_connector_convert
 356                                                     [ct];
 357                                                 connector_object_id = ct;
 358                                                 igp_lane_info =
 359                                                     slot_config & 0xffff;
 360                                         } else
 361                                                 continue;
 362                                 } else
 363                                         continue;
 364                         } else {
 365                                 igp_lane_info = 0;
 366                                 connector_type =
 367                                     object_connector_convert[con_obj_id];
 368                                 connector_object_id = con_obj_id;
 369                         }
 370
 371                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 372                                 continue;
 373
 374                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 375                              j++) {
 376                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 377
 378                                 enc_obj_id =
 379                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 380                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 381                                 enc_obj_num =
 382                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 383                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 384                                 enc_obj_type =
 385                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 386                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 387
 388                                 /* FIXME: add support for router objects */
 389                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 390                                         if (enc_obj_num == 2)
 391                                                 linkb = true;
 392                                         else
 393                                                 linkb = false;
 394
 395                                         radeon_add_atom_encoder(dev,
 396                                                                 enc_obj_id,
 397                                                                 le16_to_cpu
 398                                                                 (path->
 399                                                                  usDeviceTag));
 400
 401                                 }
 402                         }
 403
 404                         /* look up gpio for ddc */
 405                         if ((le16_to_cpu(path->usDeviceTag) &
 406                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
 407                             == 0) {
 408                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 409                                         if (le16_to_cpu(path->usConnObjectId) ==
 410                                             le16_to_cpu(con_obj->asObjects[j].
 411                                                         usObjectID)) {
 412                                                 ATOM_COMMON_RECORD_HEADER
 413                                                     *record =
 414                                                     (ATOM_COMMON_RECORD_HEADER
 415                                                      *)
 416                                                     (ctx->bios + data_offset +
 417                                                      le16_to_cpu(con_obj->
 418                                                                  asObjects[j].
 419                                                                  usRecordOffset));
 420                                                 ATOM_I2C_RECORD *i2c_record;
 421
 422                                                 while (record->ucRecordType > 0
 423                                                        && record->
 424                                                        ucRecordType <=
 425                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 426                                                         switch (record->
 427                                                                 ucRecordType) {
 428                                                         case ATOM_I2C_RECORD_TYPE:
 429                                                                 i2c_record =
 430                                                                     (ATOM_I2C_RECORD
 431                                                                      *) record;
 432                                                                 line_mux =
 433                                                                     i2c_record->
 434                                                                     sucI2cId.
 435                                                                     bfI2C_LineMux;
 436                                                                 break;
 437                                                         }
 438                                                         record =
 439                                                             (ATOM_COMMON_RECORD_HEADER
 440                                                              *) ((char *)record
 441                                                                  +
 442                                                                  record->
 443                                                                  ucRecordSize);
 444                                                 }
 445                                                 break;
 446                                         }
 447                                 }
 448                         } else
 449                                 line_mux = 0;
 450
 451                         if ((le16_to_cpu(path->usDeviceTag) ==
 452                              ATOM_DEVICE_TV1_SUPPORT)
 453                             || (le16_to_cpu(path->usDeviceTag) ==
 454                                 ATOM_DEVICE_TV2_SUPPORT)
 455                             || (le16_to_cpu(path->usDeviceTag) ==
 456                                 ATOM_DEVICE_CV_SUPPORT))
 457                                 ddc_bus.valid = false;
 458                         else
 459                                 ddc_bus = radeon_lookup_gpio(dev, line_mux);
 460
 461                         conn_id = le16_to_cpu(path->usConnObjectId);
 462
 463                         if (!radeon_atom_apply_quirks
 464                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 465                              &ddc_bus, &conn_id))
 466                                 continue;
 467
 468                         radeon_add_atom_connector(dev,
 469                                                   conn_id,
 470                                                   le16_to_cpu(path->
 471                                                               usDeviceTag),
 472                                                   connector_type, &ddc_bus,
 473                                                   linkb, igp_lane_info,
 474                                                   connector_object_id);
 475
 476                 }
 477         }
 478
 479         radeon_link_encoder_connector(dev);
 480
 481         return true;
 482 }
 483
 484 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 485                                                  int connector_type,
 486                                                  uint16_t devices)
 487 {
 488         struct radeon_device *rdev = dev->dev_private;
 489
 490         if (rdev->flags & RADEON_IS_IGP) {
 491                 return supported_devices_connector_object_id_convert
 492                         [connector_type];
 493         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 494                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 495                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 496                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 497                 struct atom_context *ctx = mode_info->atom_context;
 498                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 499                 uint16_t size, data_offset;
 500                 uint8_t frev, crev;
 501                 ATOM_XTMDS_INFO *xtmds;
 502
 503                 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 504                 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 505
 506                 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 507                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 508                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 509                         else
 510                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 511                 } else {
 512                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 513                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 514                         else
 515                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 516                 }
 517         } else {
 518                 return supported_devices_connector_object_id_convert
 519                         [connector_type];
 520         }
 521 }
 522
 523 struct bios_connector {
 524         bool valid;
 525         uint16_t line_mux;
 526         uint16_t devices;
 527         int connector_type;
 528         struct radeon_i2c_bus_rec ddc_bus;
 529 };
 530
 531 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 532                                                                  drm_device
 533                                                                  *dev)
 534 {
 535         struct radeon_device *rdev = dev->dev_private;
 536         struct radeon_mode_info *mode_info = &rdev->mode_info;
 537         struct atom_context *ctx = mode_info->atom_context;
 538         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 539         uint16_t size, data_offset;
 540         uint8_t frev, crev;
 541         uint16_t device_support;
 542         uint8_t dac;
 543         union atom_supported_devices *supported_devices;
 544         int i, j;
 545         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 546
 547         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 548
 549         supported_devices =
 550             (union atom_supported_devices *)(ctx->bios + data_offset);
 551
 552         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 553
 554         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 555                 ATOM_CONNECTOR_INFO_I2C ci =
 556                     supported_devices->info.asConnInfo[i];
 557
 558                 bios_connectors[i].valid = false;
 559
 560                 if (!(device_support & (1 << i))) {
 561                         continue;
 562                 }
 563
 564                 if (i == ATOM_DEVICE_CV_INDEX) {
 565                         DRM_DEBUG("Skipping Component Video\n");
 566                         continue;
 567                 }
 568
 569                 bios_connectors[i].connector_type =
 570                     supported_devices_connector_convert[ci.sucConnectorInfo.
 571                                                         sbfAccess.
 572                                                         bfConnectorType];
 573
 574                 if (bios_connectors[i].connector_type ==
 575                     DRM_MODE_CONNECTOR_Unknown)
 576                         continue;
 577
 578                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 579
 580                 if ((rdev->family == CHIP_RS690) ||
 581                     (rdev->family == CHIP_RS740)) {
 582                         if ((i == ATOM_DEVICE_DFP2_INDEX)
 583                             && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
 584                                 bios_connectors[i].line_mux =
 585                                     ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
 586                         else if ((i == ATOM_DEVICE_DFP3_INDEX)
 587                                  && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
 588                                 bios_connectors[i].line_mux =
 589                                     ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
 590                         else
 591                                 bios_connectors[i].line_mux =
 592                                     ci.sucI2cId.sbfAccess.bfI2C_LineMux;
 593                 } else
 594                         bios_connectors[i].line_mux =
 595                             ci.sucI2cId.sbfAccess.bfI2C_LineMux;
 596
 597                 /* give tv unique connector ids */
 598                 if (i == ATOM_DEVICE_TV1_INDEX) {
 599                         bios_connectors[i].ddc_bus.valid = false;
 600                         bios_connectors[i].line_mux = 50;
 601                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 602                         bios_connectors[i].ddc_bus.valid = false;
 603                         bios_connectors[i].line_mux = 51;
 604                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 605                         bios_connectors[i].ddc_bus.valid = false;
 606                         bios_connectors[i].line_mux = 52;
 607                 } else
 608                         bios_connectors[i].ddc_bus =
 609                             radeon_lookup_gpio(dev,
 610                                                bios_connectors[i].line_mux);
 611
 612                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 613                  * shared with a DVI port, we'll pick up the DVI connector when we
 614                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 615                  */
 616                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 617                         bios_connectors[i].connector_type =
 618                             DRM_MODE_CONNECTOR_VGA;
 619
 620                 if (!radeon_atom_apply_quirks
 621                     (dev, (1 << i), &bios_connectors[i].connector_type,
 622                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
 623                         continue;
 624
 625                 bios_connectors[i].valid = true;
 626                 bios_connectors[i].devices = (1 << i);
 627
 628                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 629                         radeon_add_atom_encoder(dev,
 630                                                 radeon_get_encoder_id(dev,
 631                                                                       (1 << i),
 632                                                                       dac),
 633                                                 (1 << i));
 634                 else
 635                         radeon_add_legacy_encoder(dev,
 636                                                   radeon_get_encoder_id(dev,
 637                                                                         (1 <<
 638                                                                          i),
 639                                                                         dac),
 640                                                   (1 << i));
 641         }
 642
 643         /* combine shared connectors */
 644         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 645                 if (bios_connectors[i].valid) {
 646                         for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
 647                                 if (bios_connectors[j].valid && (i != j)) {
 648                                         if (bios_connectors[i].line_mux ==
 649                                             bios_connectors[j].line_mux) {
 650                                                 if (((bios_connectors[i].
 651                                                       devices &
 652                                                       (ATOM_DEVICE_DFP_SUPPORT))
 653                                                      && (bios_connectors[j].
 654                                                          devices &
 655                                                          (ATOM_DEVICE_CRT_SUPPORT)))
 656                                                     ||
 657                                                     ((bios_connectors[j].
 658                                                       devices &
 659                                                       (ATOM_DEVICE_DFP_SUPPORT))
 660                                                      && (bios_connectors[i].
 661                                                          devices &
 662                                                          (ATOM_DEVICE_CRT_SUPPORT)))) {
 663                                                         bios_connectors[i].
 664                                                             devices |=
 665                                                             bios_connectors[j].
 666                                                             devices;
 667                                                         bios_connectors[i].
 668                                                             connector_type =
 669                                                             DRM_MODE_CONNECTOR_DVII;
 670                                                         bios_connectors[j].
 671                                                             valid = false;
 672                                                 }
 673                                         }
 674                                 }
 675                         }
 676                 }
 677         }
 678
 679         /* add the connectors */
 680         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 681                 if (bios_connectors[i].valid) {
 682                         uint16_t connector_object_id =
 683                                 atombios_get_connector_object_id(dev,
 684                                                       bios_connectors[i].connector_type,
 685                                                       bios_connectors[i].devices);
 686                         radeon_add_atom_connector(dev,
 687                                                   bios_connectors[i].line_mux,
 688                                                   bios_connectors[i].devices,
 689                                                   bios_connectors[i].
 690                                                   connector_type,
 691                                                   &bios_connectors[i].ddc_bus,
 692                                                   false, 0,
 693                                                   connector_object_id);
 694                 }
 695         }
 696
 697         radeon_link_encoder_connector(dev);
 698
 699         return true;
 700 }
 701
 702 union firmware_info {
 703         ATOM_FIRMWARE_INFO info;
 704         ATOM_FIRMWARE_INFO_V1_2 info_12;
 705         ATOM_FIRMWARE_INFO_V1_3 info_13;
 706         ATOM_FIRMWARE_INFO_V1_4 info_14;
 707 };
 708
 709 bool radeon_atom_get_clock_info(struct drm_device *dev)
 710 {
 711         struct radeon_device *rdev = dev->dev_private;
 712         struct radeon_mode_info *mode_info = &rdev->mode_info;
 713         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 714         union firmware_info *firmware_info;
 715         uint8_t frev, crev;
 716         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 717         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 718         struct radeon_pll *spll = &rdev->clock.spll;
 719         struct radeon_pll *mpll = &rdev->clock.mpll;
 720         uint16_t data_offset;
 721
 722         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 723                                &crev, &data_offset);
 724
 725         firmware_info =
 726             (union firmware_info *)(mode_info->atom_context->bios +
 727                                     data_offset);
 728
 729         if (firmware_info) {
 730                 /* pixel clocks */
 731                 p1pll->reference_freq =
 732                     le16_to_cpu(firmware_info->info.usReferenceClock);
 733                 p1pll->reference_div = 0;
 734
 735                 if (crev < 2)
 736                         p1pll->pll_out_min =
 737                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 738                 else
 739                         p1pll->pll_out_min =
 740                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 741                 p1pll->pll_out_max =
 742                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 743
 744                 if (p1pll->pll_out_min == 0) {
 745                         if (ASIC_IS_AVIVO(rdev))
 746                                 p1pll->pll_out_min = 64800;
 747                         else
 748                                 p1pll->pll_out_min = 20000;
 749                 } else if (p1pll->pll_out_min > 64800) {
 750                         /* Limiting the pll output range is a good thing generally as
 751                          * it limits the number of possible pll combinations for a given
 752                          * frequency presumably to the ones that work best on each card.
 753                          * However, certain duallink DVI monitors seem to like
 754                          * pll combinations that would be limited by this at least on
 755                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 756                          * family.
 757                          */
 758                         p1pll->pll_out_min = 64800;
 759                 }
 760
 761                 p1pll->pll_in_min =
 762                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 763                 p1pll->pll_in_max =
 764                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 765
 766                 *p2pll = *p1pll;
 767
 768                 /* system clock */
 769                 spll->reference_freq =
 770                     le16_to_cpu(firmware_info->info.usReferenceClock);
 771                 spll->reference_div = 0;
 772
 773                 spll->pll_out_min =
 774                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 775                 spll->pll_out_max =
 776                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 777
 778                 /* ??? */
 779                 if (spll->pll_out_min == 0) {
 780                         if (ASIC_IS_AVIVO(rdev))
 781                                 spll->pll_out_min = 64800;
 782                         else
 783                                 spll->pll_out_min = 20000;
 784                 }
 785
 786                 spll->pll_in_min =
 787                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 788                 spll->pll_in_max =
 789                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 790
 791                 /* memory clock */
 792                 mpll->reference_freq =
 793                     le16_to_cpu(firmware_info->info.usReferenceClock);
 794                 mpll->reference_div = 0;
 795
 796                 mpll->pll_out_min =
 797                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 798                 mpll->pll_out_max =
 799                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 800
 801                 /* ??? */
 802                 if (mpll->pll_out_min == 0) {
 803                         if (ASIC_IS_AVIVO(rdev))
 804                                 mpll->pll_out_min = 64800;
 805                         else
 806                                 mpll->pll_out_min = 20000;
 807                 }
 808
 809                 mpll->pll_in_min =
 810                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 811                 mpll->pll_in_max =
 812                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 813
 814                 rdev->clock.default_sclk =
 815                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 816                 rdev->clock.default_mclk =
 817                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 818
 819                 return true;
 820         }
 821         return false;
 822 }
 823
 824 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
 825                                    struct radeon_encoder_int_tmds *tmds)
 826 {
 827         struct drm_device *dev = encoder->base.dev;
 828         struct radeon_device *rdev = dev->dev_private;
 829         struct radeon_mode_info *mode_info = &rdev->mode_info;
 830         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
 831         uint16_t data_offset;
 832         struct _ATOM_TMDS_INFO *tmds_info;
 833         uint8_t frev, crev;
 834         uint16_t maxfreq;
 835         int i;
 836
 837         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 838                                &crev, &data_offset);
 839
 840         tmds_info =
 841             (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
 842                                        data_offset);
 843
 844         if (tmds_info) {
 845                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
 846                 for (i = 0; i < 4; i++) {
 847                         tmds->tmds_pll[i].freq =
 848                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
 849                         tmds->tmds_pll[i].value =
 850                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
 851                         tmds->tmds_pll[i].value |=
 852                             (tmds_info->asMiscInfo[i].
 853                              ucPLL_VCO_Gain & 0x3f) << 6;
 854                         tmds->tmds_pll[i].value |=
 855                             (tmds_info->asMiscInfo[i].
 856                              ucPLL_DutyCycle & 0xf) << 12;
 857                         tmds->tmds_pll[i].value |=
 858                             (tmds_info->asMiscInfo[i].
 859                              ucPLL_VoltageSwing & 0xf) << 16;
 860
 861                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
 862                                   tmds->tmds_pll[i].freq,
 863                                   tmds->tmds_pll[i].value);
 864
 865                         if (maxfreq == tmds->tmds_pll[i].freq) {
 866                                 tmds->tmds_pll[i].freq = 0xffffffff;
 867                                 break;
 868                         }
 869                 }
 870                 return true;
 871         }
 872         return false;
 873 }
 874
 875 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
 876                                                           radeon_encoder
 877                                                           *encoder,
 878                                                           int id)
 879 {
 880         struct drm_device *dev = encoder->base.dev;
 881         struct radeon_device *rdev = dev->dev_private;
 882         struct radeon_mode_info *mode_info = &rdev->mode_info;
 883         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
 884         uint16_t data_offset;
 885         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
 886         uint8_t frev, crev;
 887         struct radeon_atom_ss *ss = NULL;
 888
 889         if (id > ATOM_MAX_SS_ENTRY)
 890                 return NULL;
 891
 892         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 893                                &crev, &data_offset);
 894
 895         ss_info =
 896             (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
 897
 898         if (ss_info) {
 899                 ss =
 900                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
 901
 902                 if (!ss)
 903                         return NULL;
 904
 905                 ss->percentage = le16_to_cpu(ss_info->asSS_Info[id].usSpreadSpectrumPercentage);
 906                 ss->type = ss_info->asSS_Info[id].ucSpreadSpectrumType;
 907                 ss->step = ss_info->asSS_Info[id].ucSS_Step;
 908                 ss->delay = ss_info->asSS_Info[id].ucSS_Delay;
 909                 ss->range = ss_info->asSS_Info[id].ucSS_Range;
 910                 ss->refdiv = ss_info->asSS_Info[id].ucRecommendedRef_Div;
 911         }
 912         return ss;
 913 }
 914
 915 union lvds_info {
 916         struct _ATOM_LVDS_INFO info;
 917         struct _ATOM_LVDS_INFO_V12 info_12;
 918 };
 919
 920 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
 921                                                               radeon_encoder
 922                                                               *encoder)
 923 {
 924         struct drm_device *dev = encoder->base.dev;
 925         struct radeon_device *rdev = dev->dev_private;
 926         struct radeon_mode_info *mode_info = &rdev->mode_info;
 927         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
 928         uint16_t data_offset;
 929         union lvds_info *lvds_info;
 930         uint8_t frev, crev;
 931         struct radeon_encoder_atom_dig *lvds = NULL;
 932
 933         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 934                                &crev, &data_offset);
 935
 936         lvds_info =
 937             (union lvds_info *)(mode_info->atom_context->bios + data_offset);
 938
 939         if (lvds_info) {
 940                 lvds =
 941                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
 942
 943                 if (!lvds)
 944                         return NULL;
 945
 946                 lvds->native_mode.clock =
 947                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
 948                 lvds->native_mode.hdisplay =
 949                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
 950                 lvds->native_mode.vdisplay =
 951                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
 952                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
 953                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
 954                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
 955                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
 956                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
 957                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
 958                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
 959                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
 960                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
 961                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
 962                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
 963                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
 964                 lvds->panel_pwr_delay =
 965                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
 966                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
 967                 /* set crtc values */
 968                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
 969
 970                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
 971
 972                 encoder->native_mode = lvds->native_mode;
 973         }
 974         return lvds;
 975 }
 976
 977 struct radeon_encoder_primary_dac *
 978 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
 979 {
 980         struct drm_device *dev = encoder->base.dev;
 981         struct radeon_device *rdev = dev->dev_private;
 982         struct radeon_mode_info *mode_info = &rdev->mode_info;
 983         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
 984         uint16_t data_offset;
 985         struct _COMPASSIONATE_DATA *dac_info;
 986         uint8_t frev, crev;
 987         uint8_t bg, dac;
 988         struct radeon_encoder_primary_dac *p_dac = NULL;
 989
 990         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
 991
 992         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
 993
 994         if (dac_info) {
 995                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
 996
 997                 if (!p_dac)
 998                         return NULL;
 999
1000                 bg = dac_info->ucDAC1_BG_Adjustment;
1001                 dac = dac_info->ucDAC1_DAC_Adjustment;
1002                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1003
1004         }
1005         return p_dac;
1006 }
1007
1008 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1009                                 struct drm_display_mode *mode)
1010 {
1011         struct radeon_mode_info *mode_info = &rdev->mode_info;
1012         ATOM_ANALOG_TV_INFO *tv_info;
1013         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1014         ATOM_DTD_FORMAT *dtd_timings;
1015         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1016         u8 frev, crev;
1017         u16 data_offset, misc;
1018
1019         atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1020
1021         switch (crev) {
1022         case 1:
1023                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1024                 if (index > MAX_SUPPORTED_TV_TIMING)
1025                         return false;
1026
1027                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1028                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1029                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1030                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1031                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1032
1033                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1034                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1035                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1036                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1037                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1038
1039                 mode->flags = 0;
1040                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1041                 if (misc & ATOM_VSYNC_POLARITY)
1042                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1043                 if (misc & ATOM_HSYNC_POLARITY)
1044                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1045                 if (misc & ATOM_COMPOSITESYNC)
1046                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1047                 if (misc & ATOM_INTERLACE)
1048                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1049                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1050                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1051
1052                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1053
1054                 if (index == 1) {
1055                         /* PAL timings appear to have wrong values for totals */
1056                         mode->crtc_htotal -= 1;
1057                         mode->crtc_vtotal -= 1;
1058                 }
1059                 break;
1060         case 2:
1061                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1062                 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1063                         return false;
1064
1065                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1066                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1067                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1068                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1069                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1070                         le16_to_cpu(dtd_timings->usHSyncOffset);
1071                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1072                         le16_to_cpu(dtd_timings->usHSyncWidth);
1073
1074                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1075                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1076                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1077                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1078                         le16_to_cpu(dtd_timings->usVSyncOffset);
1079                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1080                         le16_to_cpu(dtd_timings->usVSyncWidth);
1081
1082                 mode->flags = 0;
1083                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1084                 if (misc & ATOM_VSYNC_POLARITY)
1085                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1086                 if (misc & ATOM_HSYNC_POLARITY)
1087                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1088                 if (misc & ATOM_COMPOSITESYNC)
1089                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1090                 if (misc & ATOM_INTERLACE)
1091                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1092                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1093                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1094
1095                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1096                 break;
1097         }
1098         return true;
1099 }
1100
1101 struct radeon_encoder_tv_dac *
1102 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1103 {
1104         struct drm_device *dev = encoder->base.dev;
1105         struct radeon_device *rdev = dev->dev_private;
1106         struct radeon_mode_info *mode_info = &rdev->mode_info;
1107         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1108         uint16_t data_offset;
1109         struct _COMPASSIONATE_DATA *dac_info;
1110         uint8_t frev, crev;
1111         uint8_t bg, dac;
1112         struct radeon_encoder_tv_dac *tv_dac = NULL;
1113
1114         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1115
1116         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1117
1118         if (dac_info) {
1119                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1120
1121                 if (!tv_dac)
1122                         return NULL;
1123
1124                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1125                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1126                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1127
1128                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1129                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1130                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1131
1132                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1133                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1134                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1135
1136         }
1137         return tv_dac;
1138 }
1139
1140 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1141 {
1142         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1143         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1144
1145         args.ucEnable = enable;
1146
1147         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1148 }
1149
1150 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1151 {
1152         ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1153         int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1154
1155         args.ucEnable = enable;
1156
1157         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1158 }
1159
1160 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1161 {
1162         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1163         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1164
1165         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1166         return args.ulReturnEngineClock;
1167 }
1168
1169 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1170 {
1171         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1172         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1173
1174         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1175         return args.ulReturnMemoryClock;
1176 }
1177
1178 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1179                                   uint32_t eng_clock)
1180 {
1181         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1182         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1183
1184         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
1185
1186         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1187 }
1188
1189 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1190                                   uint32_t mem_clock)
1191 {
1192         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1193         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1194
1195         if (rdev->flags & RADEON_IS_IGP)
1196                 return;
1197
1198         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1199
1200         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1201 }
1202
1203 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1204 {
1205         struct radeon_device *rdev = dev->dev_private;
1206         uint32_t bios_2_scratch, bios_6_scratch;
1207
1208         if (rdev->family >= CHIP_R600) {
1209                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1210                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1211         } else {
1212                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1213                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1214         }
1215
1216         /* let the bios control the backlight */
1217         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1218
1219         /* tell the bios not to handle mode switching */
1220         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1221
1222         if (rdev->family >= CHIP_R600) {
1223                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1224                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1225         } else {
1226                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1227                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1228         }
1229
1230 }
1231
1232 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1233 {
1234         uint32_t scratch_reg;
1235         int i;
1236
1237         if (rdev->family >= CHIP_R600)
1238                 scratch_reg = R600_BIOS_0_SCRATCH;
1239         else
1240                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1241
1242         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1243                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1244 }
1245
1246 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1247 {
1248         uint32_t scratch_reg;
1249         int i;
1250
1251         if (rdev->family >= CHIP_R600)
1252                 scratch_reg = R600_BIOS_0_SCRATCH;
1253         else
1254                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1255
1256         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1257                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1258 }
1259
1260 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1261 {
1262         struct drm_device *dev = encoder->dev;
1263         struct radeon_device *rdev = dev->dev_private;
1264         uint32_t bios_6_scratch;
1265
1266         if (rdev->family >= CHIP_R600)
1267                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1268         else
1269                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1270
1271         if (lock)
1272                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1273         else
1274                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1275
1276         if (rdev->family >= CHIP_R600)
1277                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1278         else
1279                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1280 }
1281
1282 /* at some point we may want to break this out into individual functions */
1283 void
1284 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1285                                        struct drm_encoder *encoder,
1286                                        bool connected)
1287 {
1288         struct drm_device *dev = connector->dev;
1289         struct radeon_device *rdev = dev->dev_private;
1290         struct radeon_connector *radeon_connector =
1291             to_radeon_connector(connector);
1292         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1293         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1294
1295         if (rdev->family >= CHIP_R600) {
1296                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1297                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1298                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1299         } else {
1300                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1301                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1302                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1303         }
1304
1305         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1306             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1307                 if (connected) {
1308                         DRM_DEBUG("TV1 connected\n");
1309                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1310                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1311                 } else {
1312                         DRM_DEBUG("TV1 disconnected\n");
1313                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1314                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1315                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1316                 }
1317         }
1318         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1319             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1320                 if (connected) {
1321                         DRM_DEBUG("CV connected\n");
1322                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1323                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1324                 } else {
1325                         DRM_DEBUG("CV disconnected\n");
1326                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
1327                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1328                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1329                 }
1330         }
1331         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1332             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1333                 if (connected) {
1334                         DRM_DEBUG("LCD1 connected\n");
1335                         bios_0_scratch |= ATOM_S0_LCD1;
1336                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1337                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1338                 } else {
1339                         DRM_DEBUG("LCD1 disconnected\n");
1340                         bios_0_scratch &= ~ATOM_S0_LCD1;
1341                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1342                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1343                 }
1344         }
1345         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1346             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1347                 if (connected) {
1348                         DRM_DEBUG("CRT1 connected\n");
1349                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1350                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1351                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1352                 } else {
1353                         DRM_DEBUG("CRT1 disconnected\n");
1354                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1355                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1356                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1357                 }
1358         }
1359         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1360             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1361                 if (connected) {
1362                         DRM_DEBUG("CRT2 connected\n");
1363                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1364                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1365                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1366                 } else {
1367                         DRM_DEBUG("CRT2 disconnected\n");
1368                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1369                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1370                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1371                 }
1372         }
1373         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1374             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1375                 if (connected) {
1376                         DRM_DEBUG("DFP1 connected\n");
1377                         bios_0_scratch |= ATOM_S0_DFP1;
1378                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1379                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1380                 } else {
1381                         DRM_DEBUG("DFP1 disconnected\n");
1382                         bios_0_scratch &= ~ATOM_S0_DFP1;
1383                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1384                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1385                 }
1386         }
1387         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1388             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1389                 if (connected) {
1390                         DRM_DEBUG("DFP2 connected\n");
1391                         bios_0_scratch |= ATOM_S0_DFP2;
1392                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1393                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1394                 } else {
1395                         DRM_DEBUG("DFP2 disconnected\n");
1396                         bios_0_scratch &= ~ATOM_S0_DFP2;
1397                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1398                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1399                 }
1400         }
1401         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1402             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1403                 if (connected) {
1404                         DRM_DEBUG("DFP3 connected\n");
1405                         bios_0_scratch |= ATOM_S0_DFP3;
1406                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1407                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1408                 } else {
1409                         DRM_DEBUG("DFP3 disconnected\n");
1410                         bios_0_scratch &= ~ATOM_S0_DFP3;
1411                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1412                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1413                 }
1414         }
1415         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1416             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1417                 if (connected) {
1418                         DRM_DEBUG("DFP4 connected\n");
1419                         bios_0_scratch |= ATOM_S0_DFP4;
1420                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1421                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1422                 } else {
1423                         DRM_DEBUG("DFP4 disconnected\n");
1424                         bios_0_scratch &= ~ATOM_S0_DFP4;
1425                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1426                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1427                 }
1428         }
1429         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1430             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1431                 if (connected) {
1432                         DRM_DEBUG("DFP5 connected\n");
1433                         bios_0_scratch |= ATOM_S0_DFP5;
1434                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1435                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1436                 } else {
1437                         DRM_DEBUG("DFP5 disconnected\n");
1438                         bios_0_scratch &= ~ATOM_S0_DFP5;
1439                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1440                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1441                 }
1442         }
1443
1444         if (rdev->family >= CHIP_R600) {
1445                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1446                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1447                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1448         } else {
1449                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1450                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1451                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1452         }
1453 }
1454
1455 void
1456 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1457 {
1458         struct drm_device *dev = encoder->dev;
1459         struct radeon_device *rdev = dev->dev_private;
1460         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1461         uint32_t bios_3_scratch;
1462
1463         if (rdev->family >= CHIP_R600)
1464                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1465         else
1466                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1467
1468         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1469                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1470                 bios_3_scratch |= (crtc << 18);
1471         }
1472         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1473                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1474                 bios_3_scratch |= (crtc << 24);
1475         }
1476         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1477                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1478                 bios_3_scratch |= (crtc << 16);
1479         }
1480         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1481                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1482                 bios_3_scratch |= (crtc << 20);
1483         }
1484         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1485                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1486                 bios_3_scratch |= (crtc << 17);
1487         }
1488         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1489                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1490                 bios_3_scratch |= (crtc << 19);
1491         }
1492         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1493                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1494                 bios_3_scratch |= (crtc << 23);
1495         }
1496         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1497                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1498                 bios_3_scratch |= (crtc << 25);
1499         }
1500
1501         if (rdev->family >= CHIP_R600)
1502                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1503         else
1504                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1505 }
1506
1507 void
1508 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1509 {
1510         struct drm_device *dev = encoder->dev;
1511         struct radeon_device *rdev = dev->dev_private;
1512         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1513         uint32_t bios_2_scratch;
1514
1515         if (rdev->family >= CHIP_R600)
1516                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1517         else
1518                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1519
1520         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1521                 if (on)
1522                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1523                 else
1524                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1525         }
1526         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1527                 if (on)
1528                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1529                 else
1530                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1531         }
1532         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1533                 if (on)
1534                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1535                 else
1536                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1537         }
1538         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1539                 if (on)
1540                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1541                 else
1542                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1543         }
1544         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1545                 if (on)
1546                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1547                 else
1548                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1549         }
1550         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1551                 if (on)
1552                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1553                 else
1554                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1555         }
1556         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1557                 if (on)
1558                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1559                 else
1560                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1561         }
1562         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1563                 if (on)
1564                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1565                 else
1566                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1567         }
1568         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1569                 if (on)
1570                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1571                 else
1572                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1573         }
1574         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1575                 if (on)
1576                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1577                 else
1578                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1579         }
1580
1581         if (rdev->family >= CHIP_R600)
1582                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1583         else
1584                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1585 }