Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / radeon / radeon_asic.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28
29 #include <linux/console.h>
30 #include <drm/drmP.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include "radeon_reg.h"
35 #include "radeon.h"
36 #include "radeon_asic.h"
37 #include "atom.h"
38
39 /*
40  * Registers accessors functions.
41  */
42 /**
43  * radeon_invalid_rreg - dummy reg read function
44  *
45  * @rdev: radeon device pointer
46  * @reg: offset of register
47  *
48  * Dummy register read function.  Used for register blocks
49  * that certain asics don't have (all asics).
50  * Returns the value in the register.
51  */
52 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
53 {
54         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
55         BUG_ON(1);
56         return 0;
57 }
58
59 /**
60  * radeon_invalid_wreg - dummy reg write function
61  *
62  * @rdev: radeon device pointer
63  * @reg: offset of register
64  * @v: value to write to the register
65  *
66  * Dummy register read function.  Used for register blocks
67  * that certain asics don't have (all asics).
68  */
69 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
70 {
71         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
72                   reg, v);
73         BUG_ON(1);
74 }
75
76 /**
77  * radeon_register_accessor_init - sets up the register accessor callbacks
78  *
79  * @rdev: radeon device pointer
80  *
81  * Sets up the register accessor callbacks for various register
82  * apertures.  Not all asics have all apertures (all asics).
83  */
84 static void radeon_register_accessor_init(struct radeon_device *rdev)
85 {
86         rdev->mc_rreg = &radeon_invalid_rreg;
87         rdev->mc_wreg = &radeon_invalid_wreg;
88         rdev->pll_rreg = &radeon_invalid_rreg;
89         rdev->pll_wreg = &radeon_invalid_wreg;
90         rdev->pciep_rreg = &radeon_invalid_rreg;
91         rdev->pciep_wreg = &radeon_invalid_wreg;
92
93         /* Don't change order as we are overridding accessor. */
94         if (rdev->family < CHIP_RV515) {
95                 rdev->pcie_reg_mask = 0xff;
96         } else {
97                 rdev->pcie_reg_mask = 0x7ff;
98         }
99         /* FIXME: not sure here */
100         if (rdev->family <= CHIP_R580) {
101                 rdev->pll_rreg = &r100_pll_rreg;
102                 rdev->pll_wreg = &r100_pll_wreg;
103         }
104         if (rdev->family >= CHIP_R420) {
105                 rdev->mc_rreg = &r420_mc_rreg;
106                 rdev->mc_wreg = &r420_mc_wreg;
107         }
108         if (rdev->family >= CHIP_RV515) {
109                 rdev->mc_rreg = &rv515_mc_rreg;
110                 rdev->mc_wreg = &rv515_mc_wreg;
111         }
112         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
113                 rdev->mc_rreg = &rs400_mc_rreg;
114                 rdev->mc_wreg = &rs400_mc_wreg;
115         }
116         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
117                 rdev->mc_rreg = &rs690_mc_rreg;
118                 rdev->mc_wreg = &rs690_mc_wreg;
119         }
120         if (rdev->family == CHIP_RS600) {
121                 rdev->mc_rreg = &rs600_mc_rreg;
122                 rdev->mc_wreg = &rs600_mc_wreg;
123         }
124         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
125                 rdev->mc_rreg = &rs780_mc_rreg;
126                 rdev->mc_wreg = &rs780_mc_wreg;
127         }
128
129         if (rdev->family >= CHIP_BONAIRE) {
130                 rdev->pciep_rreg = &cik_pciep_rreg;
131                 rdev->pciep_wreg = &cik_pciep_wreg;
132         } else if (rdev->family >= CHIP_R600) {
133                 rdev->pciep_rreg = &r600_pciep_rreg;
134                 rdev->pciep_wreg = &r600_pciep_wreg;
135         }
136 }
137
138 static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
139                                                     u32 reg, u32 *val)
140 {
141         return -EINVAL;
142 }
143
144 /* helper to disable agp */
145 /**
146  * radeon_agp_disable - AGP disable helper function
147  *
148  * @rdev: radeon device pointer
149  *
150  * Removes AGP flags and changes the gart callbacks on AGP
151  * cards when using the internal gart rather than AGP (all asics).
152  */
153 void radeon_agp_disable(struct radeon_device *rdev)
154 {
155         rdev->flags &= ~RADEON_IS_AGP;
156         if (rdev->family >= CHIP_R600) {
157                 DRM_INFO("Forcing AGP to PCIE mode\n");
158                 rdev->flags |= RADEON_IS_PCIE;
159         } else if (rdev->family >= CHIP_RV515 ||
160                         rdev->family == CHIP_RV380 ||
161                         rdev->family == CHIP_RV410 ||
162                         rdev->family == CHIP_R423) {
163                 DRM_INFO("Forcing AGP to PCIE mode\n");
164                 rdev->flags |= RADEON_IS_PCIE;
165                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
166                 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
167                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
168         } else {
169                 DRM_INFO("Forcing AGP to PCI mode\n");
170                 rdev->flags |= RADEON_IS_PCI;
171                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
172                 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
173                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
174         }
175         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
176 }
177
178 /*
179  * ASIC
180  */
181
182 static struct radeon_asic_ring r100_gfx_ring = {
183         .ib_execute = &r100_ring_ib_execute,
184         .emit_fence = &r100_fence_ring_emit,
185         .emit_semaphore = &r100_semaphore_ring_emit,
186         .cs_parse = &r100_cs_parse,
187         .ring_start = &r100_ring_start,
188         .ring_test = &r100_ring_test,
189         .ib_test = &r100_ib_test,
190         .is_lockup = &r100_gpu_is_lockup,
191         .get_rptr = &r100_gfx_get_rptr,
192         .get_wptr = &r100_gfx_get_wptr,
193         .set_wptr = &r100_gfx_set_wptr,
194 };
195
196 static struct radeon_asic r100_asic = {
197         .init = &r100_init,
198         .fini = &r100_fini,
199         .suspend = &r100_suspend,
200         .resume = &r100_resume,
201         .vga_set_state = &r100_vga_set_state,
202         .asic_reset = &r100_asic_reset,
203         .mmio_hdp_flush = NULL,
204         .gui_idle = &r100_gui_idle,
205         .mc_wait_for_idle = &r100_mc_wait_for_idle,
206         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
207         .gart = {
208                 .tlb_flush = &r100_pci_gart_tlb_flush,
209                 .get_page_entry = &r100_pci_gart_get_page_entry,
210                 .set_page = &r100_pci_gart_set_page,
211         },
212         .ring = {
213                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
214         },
215         .irq = {
216                 .set = &r100_irq_set,
217                 .process = &r100_irq_process,
218         },
219         .display = {
220                 .bandwidth_update = &r100_bandwidth_update,
221                 .get_vblank_counter = &r100_get_vblank_counter,
222                 .wait_for_vblank = &r100_wait_for_vblank,
223                 .set_backlight_level = &radeon_legacy_set_backlight_level,
224                 .get_backlight_level = &radeon_legacy_get_backlight_level,
225         },
226         .copy = {
227                 .blit = &r100_copy_blit,
228                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
229                 .dma = NULL,
230                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
231                 .copy = &r100_copy_blit,
232                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233         },
234         .surface = {
235                 .set_reg = r100_set_surface_reg,
236                 .clear_reg = r100_clear_surface_reg,
237         },
238         .hpd = {
239                 .init = &r100_hpd_init,
240                 .fini = &r100_hpd_fini,
241                 .sense = &r100_hpd_sense,
242                 .set_polarity = &r100_hpd_set_polarity,
243         },
244         .pm = {
245                 .misc = &r100_pm_misc,
246                 .prepare = &r100_pm_prepare,
247                 .finish = &r100_pm_finish,
248                 .init_profile = &r100_pm_init_profile,
249                 .get_dynpm_state = &r100_pm_get_dynpm_state,
250                 .get_engine_clock = &radeon_legacy_get_engine_clock,
251                 .set_engine_clock = &radeon_legacy_set_engine_clock,
252                 .get_memory_clock = &radeon_legacy_get_memory_clock,
253                 .set_memory_clock = NULL,
254                 .get_pcie_lanes = NULL,
255                 .set_pcie_lanes = NULL,
256                 .set_clock_gating = &radeon_legacy_set_clock_gating,
257         },
258         .pflip = {
259                 .page_flip = &r100_page_flip,
260                 .page_flip_pending = &r100_page_flip_pending,
261         },
262 };
263
264 static struct radeon_asic r200_asic = {
265         .init = &r100_init,
266         .fini = &r100_fini,
267         .suspend = &r100_suspend,
268         .resume = &r100_resume,
269         .vga_set_state = &r100_vga_set_state,
270         .asic_reset = &r100_asic_reset,
271         .mmio_hdp_flush = NULL,
272         .gui_idle = &r100_gui_idle,
273         .mc_wait_for_idle = &r100_mc_wait_for_idle,
274         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
275         .gart = {
276                 .tlb_flush = &r100_pci_gart_tlb_flush,
277                 .get_page_entry = &r100_pci_gart_get_page_entry,
278                 .set_page = &r100_pci_gart_set_page,
279         },
280         .ring = {
281                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
282         },
283         .irq = {
284                 .set = &r100_irq_set,
285                 .process = &r100_irq_process,
286         },
287         .display = {
288                 .bandwidth_update = &r100_bandwidth_update,
289                 .get_vblank_counter = &r100_get_vblank_counter,
290                 .wait_for_vblank = &r100_wait_for_vblank,
291                 .set_backlight_level = &radeon_legacy_set_backlight_level,
292                 .get_backlight_level = &radeon_legacy_get_backlight_level,
293         },
294         .copy = {
295                 .blit = &r100_copy_blit,
296                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
297                 .dma = &r200_copy_dma,
298                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
299                 .copy = &r100_copy_blit,
300                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
301         },
302         .surface = {
303                 .set_reg = r100_set_surface_reg,
304                 .clear_reg = r100_clear_surface_reg,
305         },
306         .hpd = {
307                 .init = &r100_hpd_init,
308                 .fini = &r100_hpd_fini,
309                 .sense = &r100_hpd_sense,
310                 .set_polarity = &r100_hpd_set_polarity,
311         },
312         .pm = {
313                 .misc = &r100_pm_misc,
314                 .prepare = &r100_pm_prepare,
315                 .finish = &r100_pm_finish,
316                 .init_profile = &r100_pm_init_profile,
317                 .get_dynpm_state = &r100_pm_get_dynpm_state,
318                 .get_engine_clock = &radeon_legacy_get_engine_clock,
319                 .set_engine_clock = &radeon_legacy_set_engine_clock,
320                 .get_memory_clock = &radeon_legacy_get_memory_clock,
321                 .set_memory_clock = NULL,
322                 .get_pcie_lanes = NULL,
323                 .set_pcie_lanes = NULL,
324                 .set_clock_gating = &radeon_legacy_set_clock_gating,
325         },
326         .pflip = {
327                 .page_flip = &r100_page_flip,
328                 .page_flip_pending = &r100_page_flip_pending,
329         },
330 };
331
332 static struct radeon_asic_ring r300_gfx_ring = {
333         .ib_execute = &r100_ring_ib_execute,
334         .emit_fence = &r300_fence_ring_emit,
335         .emit_semaphore = &r100_semaphore_ring_emit,
336         .cs_parse = &r300_cs_parse,
337         .ring_start = &r300_ring_start,
338         .ring_test = &r100_ring_test,
339         .ib_test = &r100_ib_test,
340         .is_lockup = &r100_gpu_is_lockup,
341         .get_rptr = &r100_gfx_get_rptr,
342         .get_wptr = &r100_gfx_get_wptr,
343         .set_wptr = &r100_gfx_set_wptr,
344 };
345
346 static struct radeon_asic_ring rv515_gfx_ring = {
347         .ib_execute = &r100_ring_ib_execute,
348         .emit_fence = &r300_fence_ring_emit,
349         .emit_semaphore = &r100_semaphore_ring_emit,
350         .cs_parse = &r300_cs_parse,
351         .ring_start = &rv515_ring_start,
352         .ring_test = &r100_ring_test,
353         .ib_test = &r100_ib_test,
354         .is_lockup = &r100_gpu_is_lockup,
355         .get_rptr = &r100_gfx_get_rptr,
356         .get_wptr = &r100_gfx_get_wptr,
357         .set_wptr = &r100_gfx_set_wptr,
358 };
359
360 static struct radeon_asic r300_asic = {
361         .init = &r300_init,
362         .fini = &r300_fini,
363         .suspend = &r300_suspend,
364         .resume = &r300_resume,
365         .vga_set_state = &r100_vga_set_state,
366         .asic_reset = &r300_asic_reset,
367         .mmio_hdp_flush = NULL,
368         .gui_idle = &r100_gui_idle,
369         .mc_wait_for_idle = &r300_mc_wait_for_idle,
370         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
371         .gart = {
372                 .tlb_flush = &r100_pci_gart_tlb_flush,
373                 .get_page_entry = &r100_pci_gart_get_page_entry,
374                 .set_page = &r100_pci_gart_set_page,
375         },
376         .ring = {
377                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
378         },
379         .irq = {
380                 .set = &r100_irq_set,
381                 .process = &r100_irq_process,
382         },
383         .display = {
384                 .bandwidth_update = &r100_bandwidth_update,
385                 .get_vblank_counter = &r100_get_vblank_counter,
386                 .wait_for_vblank = &r100_wait_for_vblank,
387                 .set_backlight_level = &radeon_legacy_set_backlight_level,
388                 .get_backlight_level = &radeon_legacy_get_backlight_level,
389         },
390         .copy = {
391                 .blit = &r100_copy_blit,
392                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
393                 .dma = &r200_copy_dma,
394                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
395                 .copy = &r100_copy_blit,
396                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
397         },
398         .surface = {
399                 .set_reg = r100_set_surface_reg,
400                 .clear_reg = r100_clear_surface_reg,
401         },
402         .hpd = {
403                 .init = &r100_hpd_init,
404                 .fini = &r100_hpd_fini,
405                 .sense = &r100_hpd_sense,
406                 .set_polarity = &r100_hpd_set_polarity,
407         },
408         .pm = {
409                 .misc = &r100_pm_misc,
410                 .prepare = &r100_pm_prepare,
411                 .finish = &r100_pm_finish,
412                 .init_profile = &r100_pm_init_profile,
413                 .get_dynpm_state = &r100_pm_get_dynpm_state,
414                 .get_engine_clock = &radeon_legacy_get_engine_clock,
415                 .set_engine_clock = &radeon_legacy_set_engine_clock,
416                 .get_memory_clock = &radeon_legacy_get_memory_clock,
417                 .set_memory_clock = NULL,
418                 .get_pcie_lanes = &rv370_get_pcie_lanes,
419                 .set_pcie_lanes = &rv370_set_pcie_lanes,
420                 .set_clock_gating = &radeon_legacy_set_clock_gating,
421         },
422         .pflip = {
423                 .page_flip = &r100_page_flip,
424                 .page_flip_pending = &r100_page_flip_pending,
425         },
426 };
427
428 static struct radeon_asic r300_asic_pcie = {
429         .init = &r300_init,
430         .fini = &r300_fini,
431         .suspend = &r300_suspend,
432         .resume = &r300_resume,
433         .vga_set_state = &r100_vga_set_state,
434         .asic_reset = &r300_asic_reset,
435         .mmio_hdp_flush = NULL,
436         .gui_idle = &r100_gui_idle,
437         .mc_wait_for_idle = &r300_mc_wait_for_idle,
438         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
439         .gart = {
440                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
441                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
442                 .set_page = &rv370_pcie_gart_set_page,
443         },
444         .ring = {
445                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
446         },
447         .irq = {
448                 .set = &r100_irq_set,
449                 .process = &r100_irq_process,
450         },
451         .display = {
452                 .bandwidth_update = &r100_bandwidth_update,
453                 .get_vblank_counter = &r100_get_vblank_counter,
454                 .wait_for_vblank = &r100_wait_for_vblank,
455                 .set_backlight_level = &radeon_legacy_set_backlight_level,
456                 .get_backlight_level = &radeon_legacy_get_backlight_level,
457         },
458         .copy = {
459                 .blit = &r100_copy_blit,
460                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
461                 .dma = &r200_copy_dma,
462                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
463                 .copy = &r100_copy_blit,
464                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
465         },
466         .surface = {
467                 .set_reg = r100_set_surface_reg,
468                 .clear_reg = r100_clear_surface_reg,
469         },
470         .hpd = {
471                 .init = &r100_hpd_init,
472                 .fini = &r100_hpd_fini,
473                 .sense = &r100_hpd_sense,
474                 .set_polarity = &r100_hpd_set_polarity,
475         },
476         .pm = {
477                 .misc = &r100_pm_misc,
478                 .prepare = &r100_pm_prepare,
479                 .finish = &r100_pm_finish,
480                 .init_profile = &r100_pm_init_profile,
481                 .get_dynpm_state = &r100_pm_get_dynpm_state,
482                 .get_engine_clock = &radeon_legacy_get_engine_clock,
483                 .set_engine_clock = &radeon_legacy_set_engine_clock,
484                 .get_memory_clock = &radeon_legacy_get_memory_clock,
485                 .set_memory_clock = NULL,
486                 .get_pcie_lanes = &rv370_get_pcie_lanes,
487                 .set_pcie_lanes = &rv370_set_pcie_lanes,
488                 .set_clock_gating = &radeon_legacy_set_clock_gating,
489         },
490         .pflip = {
491                 .page_flip = &r100_page_flip,
492                 .page_flip_pending = &r100_page_flip_pending,
493         },
494 };
495
496 static struct radeon_asic r420_asic = {
497         .init = &r420_init,
498         .fini = &r420_fini,
499         .suspend = &r420_suspend,
500         .resume = &r420_resume,
501         .vga_set_state = &r100_vga_set_state,
502         .asic_reset = &r300_asic_reset,
503         .mmio_hdp_flush = NULL,
504         .gui_idle = &r100_gui_idle,
505         .mc_wait_for_idle = &r300_mc_wait_for_idle,
506         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
507         .gart = {
508                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
509                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
510                 .set_page = &rv370_pcie_gart_set_page,
511         },
512         .ring = {
513                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
514         },
515         .irq = {
516                 .set = &r100_irq_set,
517                 .process = &r100_irq_process,
518         },
519         .display = {
520                 .bandwidth_update = &r100_bandwidth_update,
521                 .get_vblank_counter = &r100_get_vblank_counter,
522                 .wait_for_vblank = &r100_wait_for_vblank,
523                 .set_backlight_level = &atombios_set_backlight_level,
524                 .get_backlight_level = &atombios_get_backlight_level,
525         },
526         .copy = {
527                 .blit = &r100_copy_blit,
528                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
529                 .dma = &r200_copy_dma,
530                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
531                 .copy = &r100_copy_blit,
532                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
533         },
534         .surface = {
535                 .set_reg = r100_set_surface_reg,
536                 .clear_reg = r100_clear_surface_reg,
537         },
538         .hpd = {
539                 .init = &r100_hpd_init,
540                 .fini = &r100_hpd_fini,
541                 .sense = &r100_hpd_sense,
542                 .set_polarity = &r100_hpd_set_polarity,
543         },
544         .pm = {
545                 .misc = &r100_pm_misc,
546                 .prepare = &r100_pm_prepare,
547                 .finish = &r100_pm_finish,
548                 .init_profile = &r420_pm_init_profile,
549                 .get_dynpm_state = &r100_pm_get_dynpm_state,
550                 .get_engine_clock = &radeon_atom_get_engine_clock,
551                 .set_engine_clock = &radeon_atom_set_engine_clock,
552                 .get_memory_clock = &radeon_atom_get_memory_clock,
553                 .set_memory_clock = &radeon_atom_set_memory_clock,
554                 .get_pcie_lanes = &rv370_get_pcie_lanes,
555                 .set_pcie_lanes = &rv370_set_pcie_lanes,
556                 .set_clock_gating = &radeon_atom_set_clock_gating,
557         },
558         .pflip = {
559                 .page_flip = &r100_page_flip,
560                 .page_flip_pending = &r100_page_flip_pending,
561         },
562 };
563
564 static struct radeon_asic rs400_asic = {
565         .init = &rs400_init,
566         .fini = &rs400_fini,
567         .suspend = &rs400_suspend,
568         .resume = &rs400_resume,
569         .vga_set_state = &r100_vga_set_state,
570         .asic_reset = &r300_asic_reset,
571         .mmio_hdp_flush = NULL,
572         .gui_idle = &r100_gui_idle,
573         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
574         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
575         .gart = {
576                 .tlb_flush = &rs400_gart_tlb_flush,
577                 .get_page_entry = &rs400_gart_get_page_entry,
578                 .set_page = &rs400_gart_set_page,
579         },
580         .ring = {
581                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
582         },
583         .irq = {
584                 .set = &r100_irq_set,
585                 .process = &r100_irq_process,
586         },
587         .display = {
588                 .bandwidth_update = &r100_bandwidth_update,
589                 .get_vblank_counter = &r100_get_vblank_counter,
590                 .wait_for_vblank = &r100_wait_for_vblank,
591                 .set_backlight_level = &radeon_legacy_set_backlight_level,
592                 .get_backlight_level = &radeon_legacy_get_backlight_level,
593         },
594         .copy = {
595                 .blit = &r100_copy_blit,
596                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
597                 .dma = &r200_copy_dma,
598                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
599                 .copy = &r100_copy_blit,
600                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
601         },
602         .surface = {
603                 .set_reg = r100_set_surface_reg,
604                 .clear_reg = r100_clear_surface_reg,
605         },
606         .hpd = {
607                 .init = &r100_hpd_init,
608                 .fini = &r100_hpd_fini,
609                 .sense = &r100_hpd_sense,
610                 .set_polarity = &r100_hpd_set_polarity,
611         },
612         .pm = {
613                 .misc = &r100_pm_misc,
614                 .prepare = &r100_pm_prepare,
615                 .finish = &r100_pm_finish,
616                 .init_profile = &r100_pm_init_profile,
617                 .get_dynpm_state = &r100_pm_get_dynpm_state,
618                 .get_engine_clock = &radeon_legacy_get_engine_clock,
619                 .set_engine_clock = &radeon_legacy_set_engine_clock,
620                 .get_memory_clock = &radeon_legacy_get_memory_clock,
621                 .set_memory_clock = NULL,
622                 .get_pcie_lanes = NULL,
623                 .set_pcie_lanes = NULL,
624                 .set_clock_gating = &radeon_legacy_set_clock_gating,
625         },
626         .pflip = {
627                 .page_flip = &r100_page_flip,
628                 .page_flip_pending = &r100_page_flip_pending,
629         },
630 };
631
632 static struct radeon_asic rs600_asic = {
633         .init = &rs600_init,
634         .fini = &rs600_fini,
635         .suspend = &rs600_suspend,
636         .resume = &rs600_resume,
637         .vga_set_state = &r100_vga_set_state,
638         .asic_reset = &rs600_asic_reset,
639         .mmio_hdp_flush = NULL,
640         .gui_idle = &r100_gui_idle,
641         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
642         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
643         .gart = {
644                 .tlb_flush = &rs600_gart_tlb_flush,
645                 .get_page_entry = &rs600_gart_get_page_entry,
646                 .set_page = &rs600_gart_set_page,
647         },
648         .ring = {
649                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
650         },
651         .irq = {
652                 .set = &rs600_irq_set,
653                 .process = &rs600_irq_process,
654         },
655         .display = {
656                 .bandwidth_update = &rs600_bandwidth_update,
657                 .get_vblank_counter = &rs600_get_vblank_counter,
658                 .wait_for_vblank = &avivo_wait_for_vblank,
659                 .set_backlight_level = &atombios_set_backlight_level,
660                 .get_backlight_level = &atombios_get_backlight_level,
661         },
662         .copy = {
663                 .blit = &r100_copy_blit,
664                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
665                 .dma = &r200_copy_dma,
666                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
667                 .copy = &r100_copy_blit,
668                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
669         },
670         .surface = {
671                 .set_reg = r100_set_surface_reg,
672                 .clear_reg = r100_clear_surface_reg,
673         },
674         .hpd = {
675                 .init = &rs600_hpd_init,
676                 .fini = &rs600_hpd_fini,
677                 .sense = &rs600_hpd_sense,
678                 .set_polarity = &rs600_hpd_set_polarity,
679         },
680         .pm = {
681                 .misc = &rs600_pm_misc,
682                 .prepare = &rs600_pm_prepare,
683                 .finish = &rs600_pm_finish,
684                 .init_profile = &r420_pm_init_profile,
685                 .get_dynpm_state = &r100_pm_get_dynpm_state,
686                 .get_engine_clock = &radeon_atom_get_engine_clock,
687                 .set_engine_clock = &radeon_atom_set_engine_clock,
688                 .get_memory_clock = &radeon_atom_get_memory_clock,
689                 .set_memory_clock = &radeon_atom_set_memory_clock,
690                 .get_pcie_lanes = NULL,
691                 .set_pcie_lanes = NULL,
692                 .set_clock_gating = &radeon_atom_set_clock_gating,
693         },
694         .pflip = {
695                 .page_flip = &rs600_page_flip,
696                 .page_flip_pending = &rs600_page_flip_pending,
697         },
698 };
699
700 static struct radeon_asic rs690_asic = {
701         .init = &rs690_init,
702         .fini = &rs690_fini,
703         .suspend = &rs690_suspend,
704         .resume = &rs690_resume,
705         .vga_set_state = &r100_vga_set_state,
706         .asic_reset = &rs600_asic_reset,
707         .mmio_hdp_flush = NULL,
708         .gui_idle = &r100_gui_idle,
709         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
710         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
711         .gart = {
712                 .tlb_flush = &rs400_gart_tlb_flush,
713                 .get_page_entry = &rs400_gart_get_page_entry,
714                 .set_page = &rs400_gart_set_page,
715         },
716         .ring = {
717                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
718         },
719         .irq = {
720                 .set = &rs600_irq_set,
721                 .process = &rs600_irq_process,
722         },
723         .display = {
724                 .get_vblank_counter = &rs600_get_vblank_counter,
725                 .bandwidth_update = &rs690_bandwidth_update,
726                 .wait_for_vblank = &avivo_wait_for_vblank,
727                 .set_backlight_level = &atombios_set_backlight_level,
728                 .get_backlight_level = &atombios_get_backlight_level,
729         },
730         .copy = {
731                 .blit = &r100_copy_blit,
732                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
733                 .dma = &r200_copy_dma,
734                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
735                 .copy = &r200_copy_dma,
736                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
737         },
738         .surface = {
739                 .set_reg = r100_set_surface_reg,
740                 .clear_reg = r100_clear_surface_reg,
741         },
742         .hpd = {
743                 .init = &rs600_hpd_init,
744                 .fini = &rs600_hpd_fini,
745                 .sense = &rs600_hpd_sense,
746                 .set_polarity = &rs600_hpd_set_polarity,
747         },
748         .pm = {
749                 .misc = &rs600_pm_misc,
750                 .prepare = &rs600_pm_prepare,
751                 .finish = &rs600_pm_finish,
752                 .init_profile = &r420_pm_init_profile,
753                 .get_dynpm_state = &r100_pm_get_dynpm_state,
754                 .get_engine_clock = &radeon_atom_get_engine_clock,
755                 .set_engine_clock = &radeon_atom_set_engine_clock,
756                 .get_memory_clock = &radeon_atom_get_memory_clock,
757                 .set_memory_clock = &radeon_atom_set_memory_clock,
758                 .get_pcie_lanes = NULL,
759                 .set_pcie_lanes = NULL,
760                 .set_clock_gating = &radeon_atom_set_clock_gating,
761         },
762         .pflip = {
763                 .page_flip = &rs600_page_flip,
764                 .page_flip_pending = &rs600_page_flip_pending,
765         },
766 };
767
768 static struct radeon_asic rv515_asic = {
769         .init = &rv515_init,
770         .fini = &rv515_fini,
771         .suspend = &rv515_suspend,
772         .resume = &rv515_resume,
773         .vga_set_state = &r100_vga_set_state,
774         .asic_reset = &rs600_asic_reset,
775         .mmio_hdp_flush = NULL,
776         .gui_idle = &r100_gui_idle,
777         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
778         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
779         .gart = {
780                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
781                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
782                 .set_page = &rv370_pcie_gart_set_page,
783         },
784         .ring = {
785                 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
786         },
787         .irq = {
788                 .set = &rs600_irq_set,
789                 .process = &rs600_irq_process,
790         },
791         .display = {
792                 .get_vblank_counter = &rs600_get_vblank_counter,
793                 .bandwidth_update = &rv515_bandwidth_update,
794                 .wait_for_vblank = &avivo_wait_for_vblank,
795                 .set_backlight_level = &atombios_set_backlight_level,
796                 .get_backlight_level = &atombios_get_backlight_level,
797         },
798         .copy = {
799                 .blit = &r100_copy_blit,
800                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
801                 .dma = &r200_copy_dma,
802                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
803                 .copy = &r100_copy_blit,
804                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
805         },
806         .surface = {
807                 .set_reg = r100_set_surface_reg,
808                 .clear_reg = r100_clear_surface_reg,
809         },
810         .hpd = {
811                 .init = &rs600_hpd_init,
812                 .fini = &rs600_hpd_fini,
813                 .sense = &rs600_hpd_sense,
814                 .set_polarity = &rs600_hpd_set_polarity,
815         },
816         .pm = {
817                 .misc = &rs600_pm_misc,
818                 .prepare = &rs600_pm_prepare,
819                 .finish = &rs600_pm_finish,
820                 .init_profile = &r420_pm_init_profile,
821                 .get_dynpm_state = &r100_pm_get_dynpm_state,
822                 .get_engine_clock = &radeon_atom_get_engine_clock,
823                 .set_engine_clock = &radeon_atom_set_engine_clock,
824                 .get_memory_clock = &radeon_atom_get_memory_clock,
825                 .set_memory_clock = &radeon_atom_set_memory_clock,
826                 .get_pcie_lanes = &rv370_get_pcie_lanes,
827                 .set_pcie_lanes = &rv370_set_pcie_lanes,
828                 .set_clock_gating = &radeon_atom_set_clock_gating,
829         },
830         .pflip = {
831                 .page_flip = &rs600_page_flip,
832                 .page_flip_pending = &rs600_page_flip_pending,
833         },
834 };
835
836 static struct radeon_asic r520_asic = {
837         .init = &r520_init,
838         .fini = &rv515_fini,
839         .suspend = &rv515_suspend,
840         .resume = &r520_resume,
841         .vga_set_state = &r100_vga_set_state,
842         .asic_reset = &rs600_asic_reset,
843         .mmio_hdp_flush = NULL,
844         .gui_idle = &r100_gui_idle,
845         .mc_wait_for_idle = &r520_mc_wait_for_idle,
846         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
847         .gart = {
848                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
849                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
850                 .set_page = &rv370_pcie_gart_set_page,
851         },
852         .ring = {
853                 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
854         },
855         .irq = {
856                 .set = &rs600_irq_set,
857                 .process = &rs600_irq_process,
858         },
859         .display = {
860                 .bandwidth_update = &rv515_bandwidth_update,
861                 .get_vblank_counter = &rs600_get_vblank_counter,
862                 .wait_for_vblank = &avivo_wait_for_vblank,
863                 .set_backlight_level = &atombios_set_backlight_level,
864                 .get_backlight_level = &atombios_get_backlight_level,
865         },
866         .copy = {
867                 .blit = &r100_copy_blit,
868                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
869                 .dma = &r200_copy_dma,
870                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
871                 .copy = &r100_copy_blit,
872                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
873         },
874         .surface = {
875                 .set_reg = r100_set_surface_reg,
876                 .clear_reg = r100_clear_surface_reg,
877         },
878         .hpd = {
879                 .init = &rs600_hpd_init,
880                 .fini = &rs600_hpd_fini,
881                 .sense = &rs600_hpd_sense,
882                 .set_polarity = &rs600_hpd_set_polarity,
883         },
884         .pm = {
885                 .misc = &rs600_pm_misc,
886                 .prepare = &rs600_pm_prepare,
887                 .finish = &rs600_pm_finish,
888                 .init_profile = &r420_pm_init_profile,
889                 .get_dynpm_state = &r100_pm_get_dynpm_state,
890                 .get_engine_clock = &radeon_atom_get_engine_clock,
891                 .set_engine_clock = &radeon_atom_set_engine_clock,
892                 .get_memory_clock = &radeon_atom_get_memory_clock,
893                 .set_memory_clock = &radeon_atom_set_memory_clock,
894                 .get_pcie_lanes = &rv370_get_pcie_lanes,
895                 .set_pcie_lanes = &rv370_set_pcie_lanes,
896                 .set_clock_gating = &radeon_atom_set_clock_gating,
897         },
898         .pflip = {
899                 .page_flip = &rs600_page_flip,
900                 .page_flip_pending = &rs600_page_flip_pending,
901         },
902 };
903
904 static struct radeon_asic_ring r600_gfx_ring = {
905         .ib_execute = &r600_ring_ib_execute,
906         .emit_fence = &r600_fence_ring_emit,
907         .emit_semaphore = &r600_semaphore_ring_emit,
908         .cs_parse = &r600_cs_parse,
909         .ring_test = &r600_ring_test,
910         .ib_test = &r600_ib_test,
911         .is_lockup = &r600_gfx_is_lockup,
912         .get_rptr = &r600_gfx_get_rptr,
913         .get_wptr = &r600_gfx_get_wptr,
914         .set_wptr = &r600_gfx_set_wptr,
915 };
916
917 static struct radeon_asic_ring r600_dma_ring = {
918         .ib_execute = &r600_dma_ring_ib_execute,
919         .emit_fence = &r600_dma_fence_ring_emit,
920         .emit_semaphore = &r600_dma_semaphore_ring_emit,
921         .cs_parse = &r600_dma_cs_parse,
922         .ring_test = &r600_dma_ring_test,
923         .ib_test = &r600_dma_ib_test,
924         .is_lockup = &r600_dma_is_lockup,
925         .get_rptr = &r600_dma_get_rptr,
926         .get_wptr = &r600_dma_get_wptr,
927         .set_wptr = &r600_dma_set_wptr,
928 };
929
930 static struct radeon_asic r600_asic = {
931         .init = &r600_init,
932         .fini = &r600_fini,
933         .suspend = &r600_suspend,
934         .resume = &r600_resume,
935         .vga_set_state = &r600_vga_set_state,
936         .asic_reset = &r600_asic_reset,
937         .mmio_hdp_flush = r600_mmio_hdp_flush,
938         .gui_idle = &r600_gui_idle,
939         .mc_wait_for_idle = &r600_mc_wait_for_idle,
940         .get_xclk = &r600_get_xclk,
941         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
942         .get_allowed_info_register = r600_get_allowed_info_register,
943         .gart = {
944                 .tlb_flush = &r600_pcie_gart_tlb_flush,
945                 .get_page_entry = &rs600_gart_get_page_entry,
946                 .set_page = &rs600_gart_set_page,
947         },
948         .ring = {
949                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
950                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
951         },
952         .irq = {
953                 .set = &r600_irq_set,
954                 .process = &r600_irq_process,
955         },
956         .display = {
957                 .bandwidth_update = &rv515_bandwidth_update,
958                 .get_vblank_counter = &rs600_get_vblank_counter,
959                 .wait_for_vblank = &avivo_wait_for_vblank,
960                 .set_backlight_level = &atombios_set_backlight_level,
961                 .get_backlight_level = &atombios_get_backlight_level,
962         },
963         .copy = {
964                 .blit = &r600_copy_cpdma,
965                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
966                 .dma = &r600_copy_dma,
967                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
968                 .copy = &r600_copy_cpdma,
969                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
970         },
971         .surface = {
972                 .set_reg = r600_set_surface_reg,
973                 .clear_reg = r600_clear_surface_reg,
974         },
975         .hpd = {
976                 .init = &r600_hpd_init,
977                 .fini = &r600_hpd_fini,
978                 .sense = &r600_hpd_sense,
979                 .set_polarity = &r600_hpd_set_polarity,
980         },
981         .pm = {
982                 .misc = &r600_pm_misc,
983                 .prepare = &rs600_pm_prepare,
984                 .finish = &rs600_pm_finish,
985                 .init_profile = &r600_pm_init_profile,
986                 .get_dynpm_state = &r600_pm_get_dynpm_state,
987                 .get_engine_clock = &radeon_atom_get_engine_clock,
988                 .set_engine_clock = &radeon_atom_set_engine_clock,
989                 .get_memory_clock = &radeon_atom_get_memory_clock,
990                 .set_memory_clock = &radeon_atom_set_memory_clock,
991                 .get_pcie_lanes = &r600_get_pcie_lanes,
992                 .set_pcie_lanes = &r600_set_pcie_lanes,
993                 .set_clock_gating = NULL,
994                 .get_temperature = &rv6xx_get_temp,
995         },
996         .pflip = {
997                 .page_flip = &rs600_page_flip,
998                 .page_flip_pending = &rs600_page_flip_pending,
999         },
1000 };
1001
1002 static struct radeon_asic_ring rv6xx_uvd_ring = {
1003         .ib_execute = &uvd_v1_0_ib_execute,
1004         .emit_fence = &uvd_v1_0_fence_emit,
1005         .emit_semaphore = &uvd_v1_0_semaphore_emit,
1006         .cs_parse = &radeon_uvd_cs_parse,
1007         .ring_test = &uvd_v1_0_ring_test,
1008         .ib_test = &uvd_v1_0_ib_test,
1009         .is_lockup = &radeon_ring_test_lockup,
1010         .get_rptr = &uvd_v1_0_get_rptr,
1011         .get_wptr = &uvd_v1_0_get_wptr,
1012         .set_wptr = &uvd_v1_0_set_wptr,
1013 };
1014
1015 static struct radeon_asic rv6xx_asic = {
1016         .init = &r600_init,
1017         .fini = &r600_fini,
1018         .suspend = &r600_suspend,
1019         .resume = &r600_resume,
1020         .vga_set_state = &r600_vga_set_state,
1021         .asic_reset = &r600_asic_reset,
1022         .mmio_hdp_flush = r600_mmio_hdp_flush,
1023         .gui_idle = &r600_gui_idle,
1024         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1025         .get_xclk = &r600_get_xclk,
1026         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1027         .get_allowed_info_register = r600_get_allowed_info_register,
1028         .gart = {
1029                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1030                 .get_page_entry = &rs600_gart_get_page_entry,
1031                 .set_page = &rs600_gart_set_page,
1032         },
1033         .ring = {
1034                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1035                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1036                 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1037         },
1038         .irq = {
1039                 .set = &r600_irq_set,
1040                 .process = &r600_irq_process,
1041         },
1042         .display = {
1043                 .bandwidth_update = &rv515_bandwidth_update,
1044                 .get_vblank_counter = &rs600_get_vblank_counter,
1045                 .wait_for_vblank = &avivo_wait_for_vblank,
1046                 .set_backlight_level = &atombios_set_backlight_level,
1047                 .get_backlight_level = &atombios_get_backlight_level,
1048         },
1049         .copy = {
1050                 .blit = &r600_copy_cpdma,
1051                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1052                 .dma = &r600_copy_dma,
1053                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1054                 .copy = &r600_copy_cpdma,
1055                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1056         },
1057         .surface = {
1058                 .set_reg = r600_set_surface_reg,
1059                 .clear_reg = r600_clear_surface_reg,
1060         },
1061         .hpd = {
1062                 .init = &r600_hpd_init,
1063                 .fini = &r600_hpd_fini,
1064                 .sense = &r600_hpd_sense,
1065                 .set_polarity = &r600_hpd_set_polarity,
1066         },
1067         .pm = {
1068                 .misc = &r600_pm_misc,
1069                 .prepare = &rs600_pm_prepare,
1070                 .finish = &rs600_pm_finish,
1071                 .init_profile = &r600_pm_init_profile,
1072                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1073                 .get_engine_clock = &radeon_atom_get_engine_clock,
1074                 .set_engine_clock = &radeon_atom_set_engine_clock,
1075                 .get_memory_clock = &radeon_atom_get_memory_clock,
1076                 .set_memory_clock = &radeon_atom_set_memory_clock,
1077                 .get_pcie_lanes = &r600_get_pcie_lanes,
1078                 .set_pcie_lanes = &r600_set_pcie_lanes,
1079                 .set_clock_gating = NULL,
1080                 .get_temperature = &rv6xx_get_temp,
1081                 .set_uvd_clocks = &r600_set_uvd_clocks,
1082         },
1083         .dpm = {
1084                 .init = &rv6xx_dpm_init,
1085                 .setup_asic = &rv6xx_setup_asic,
1086                 .enable = &rv6xx_dpm_enable,
1087                 .late_enable = &r600_dpm_late_enable,
1088                 .disable = &rv6xx_dpm_disable,
1089                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1090                 .set_power_state = &rv6xx_dpm_set_power_state,
1091                 .post_set_power_state = &r600_dpm_post_set_power_state,
1092                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1093                 .fini = &rv6xx_dpm_fini,
1094                 .get_sclk = &rv6xx_dpm_get_sclk,
1095                 .get_mclk = &rv6xx_dpm_get_mclk,
1096                 .print_power_state = &rv6xx_dpm_print_power_state,
1097                 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1098                 .force_performance_level = &rv6xx_dpm_force_performance_level,
1099                 .get_current_sclk = &rv6xx_dpm_get_current_sclk,
1100                 .get_current_mclk = &rv6xx_dpm_get_current_mclk,
1101         },
1102         .pflip = {
1103                 .page_flip = &rs600_page_flip,
1104                 .page_flip_pending = &rs600_page_flip_pending,
1105         },
1106 };
1107
1108 static struct radeon_asic rs780_asic = {
1109         .init = &r600_init,
1110         .fini = &r600_fini,
1111         .suspend = &r600_suspend,
1112         .resume = &r600_resume,
1113         .vga_set_state = &r600_vga_set_state,
1114         .asic_reset = &r600_asic_reset,
1115         .mmio_hdp_flush = r600_mmio_hdp_flush,
1116         .gui_idle = &r600_gui_idle,
1117         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1118         .get_xclk = &r600_get_xclk,
1119         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1120         .get_allowed_info_register = r600_get_allowed_info_register,
1121         .gart = {
1122                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1123                 .get_page_entry = &rs600_gart_get_page_entry,
1124                 .set_page = &rs600_gart_set_page,
1125         },
1126         .ring = {
1127                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1128                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1129                 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1130         },
1131         .irq = {
1132                 .set = &r600_irq_set,
1133                 .process = &r600_irq_process,
1134         },
1135         .display = {
1136                 .bandwidth_update = &rs690_bandwidth_update,
1137                 .get_vblank_counter = &rs600_get_vblank_counter,
1138                 .wait_for_vblank = &avivo_wait_for_vblank,
1139                 .set_backlight_level = &atombios_set_backlight_level,
1140                 .get_backlight_level = &atombios_get_backlight_level,
1141         },
1142         .copy = {
1143                 .blit = &r600_copy_cpdma,
1144                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1145                 .dma = &r600_copy_dma,
1146                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1147                 .copy = &r600_copy_cpdma,
1148                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1149         },
1150         .surface = {
1151                 .set_reg = r600_set_surface_reg,
1152                 .clear_reg = r600_clear_surface_reg,
1153         },
1154         .hpd = {
1155                 .init = &r600_hpd_init,
1156                 .fini = &r600_hpd_fini,
1157                 .sense = &r600_hpd_sense,
1158                 .set_polarity = &r600_hpd_set_polarity,
1159         },
1160         .pm = {
1161                 .misc = &r600_pm_misc,
1162                 .prepare = &rs600_pm_prepare,
1163                 .finish = &rs600_pm_finish,
1164                 .init_profile = &rs780_pm_init_profile,
1165                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1166                 .get_engine_clock = &radeon_atom_get_engine_clock,
1167                 .set_engine_clock = &radeon_atom_set_engine_clock,
1168                 .get_memory_clock = NULL,
1169                 .set_memory_clock = NULL,
1170                 .get_pcie_lanes = NULL,
1171                 .set_pcie_lanes = NULL,
1172                 .set_clock_gating = NULL,
1173                 .get_temperature = &rv6xx_get_temp,
1174                 .set_uvd_clocks = &r600_set_uvd_clocks,
1175         },
1176         .dpm = {
1177                 .init = &rs780_dpm_init,
1178                 .setup_asic = &rs780_dpm_setup_asic,
1179                 .enable = &rs780_dpm_enable,
1180                 .late_enable = &r600_dpm_late_enable,
1181                 .disable = &rs780_dpm_disable,
1182                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1183                 .set_power_state = &rs780_dpm_set_power_state,
1184                 .post_set_power_state = &r600_dpm_post_set_power_state,
1185                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1186                 .fini = &rs780_dpm_fini,
1187                 .get_sclk = &rs780_dpm_get_sclk,
1188                 .get_mclk = &rs780_dpm_get_mclk,
1189                 .print_power_state = &rs780_dpm_print_power_state,
1190                 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1191                 .force_performance_level = &rs780_dpm_force_performance_level,
1192                 .get_current_sclk = &rs780_dpm_get_current_sclk,
1193                 .get_current_mclk = &rs780_dpm_get_current_mclk,
1194         },
1195         .pflip = {
1196                 .page_flip = &rs600_page_flip,
1197                 .page_flip_pending = &rs600_page_flip_pending,
1198         },
1199 };
1200
1201 static struct radeon_asic_ring rv770_uvd_ring = {
1202         .ib_execute = &uvd_v1_0_ib_execute,
1203         .emit_fence = &uvd_v2_2_fence_emit,
1204         .emit_semaphore = &uvd_v2_2_semaphore_emit,
1205         .cs_parse = &radeon_uvd_cs_parse,
1206         .ring_test = &uvd_v1_0_ring_test,
1207         .ib_test = &uvd_v1_0_ib_test,
1208         .is_lockup = &radeon_ring_test_lockup,
1209         .get_rptr = &uvd_v1_0_get_rptr,
1210         .get_wptr = &uvd_v1_0_get_wptr,
1211         .set_wptr = &uvd_v1_0_set_wptr,
1212 };
1213
1214 static struct radeon_asic rv770_asic = {
1215         .init = &rv770_init,
1216         .fini = &rv770_fini,
1217         .suspend = &rv770_suspend,
1218         .resume = &rv770_resume,
1219         .asic_reset = &r600_asic_reset,
1220         .vga_set_state = &r600_vga_set_state,
1221         .mmio_hdp_flush = r600_mmio_hdp_flush,
1222         .gui_idle = &r600_gui_idle,
1223         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1224         .get_xclk = &rv770_get_xclk,
1225         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1226         .get_allowed_info_register = r600_get_allowed_info_register,
1227         .gart = {
1228                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1229                 .get_page_entry = &rs600_gart_get_page_entry,
1230                 .set_page = &rs600_gart_set_page,
1231         },
1232         .ring = {
1233                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1234                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1235                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1236         },
1237         .irq = {
1238                 .set = &r600_irq_set,
1239                 .process = &r600_irq_process,
1240         },
1241         .display = {
1242                 .bandwidth_update = &rv515_bandwidth_update,
1243                 .get_vblank_counter = &rs600_get_vblank_counter,
1244                 .wait_for_vblank = &avivo_wait_for_vblank,
1245                 .set_backlight_level = &atombios_set_backlight_level,
1246                 .get_backlight_level = &atombios_get_backlight_level,
1247         },
1248         .copy = {
1249                 .blit = &r600_copy_cpdma,
1250                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1251                 .dma = &rv770_copy_dma,
1252                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1253                 .copy = &rv770_copy_dma,
1254                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1255         },
1256         .surface = {
1257                 .set_reg = r600_set_surface_reg,
1258                 .clear_reg = r600_clear_surface_reg,
1259         },
1260         .hpd = {
1261                 .init = &r600_hpd_init,
1262                 .fini = &r600_hpd_fini,
1263                 .sense = &r600_hpd_sense,
1264                 .set_polarity = &r600_hpd_set_polarity,
1265         },
1266         .pm = {
1267                 .misc = &rv770_pm_misc,
1268                 .prepare = &rs600_pm_prepare,
1269                 .finish = &rs600_pm_finish,
1270                 .init_profile = &r600_pm_init_profile,
1271                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1272                 .get_engine_clock = &radeon_atom_get_engine_clock,
1273                 .set_engine_clock = &radeon_atom_set_engine_clock,
1274                 .get_memory_clock = &radeon_atom_get_memory_clock,
1275                 .set_memory_clock = &radeon_atom_set_memory_clock,
1276                 .get_pcie_lanes = &r600_get_pcie_lanes,
1277                 .set_pcie_lanes = &r600_set_pcie_lanes,
1278                 .set_clock_gating = &radeon_atom_set_clock_gating,
1279                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1280                 .get_temperature = &rv770_get_temp,
1281         },
1282         .dpm = {
1283                 .init = &rv770_dpm_init,
1284                 .setup_asic = &rv770_dpm_setup_asic,
1285                 .enable = &rv770_dpm_enable,
1286                 .late_enable = &rv770_dpm_late_enable,
1287                 .disable = &rv770_dpm_disable,
1288                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1289                 .set_power_state = &rv770_dpm_set_power_state,
1290                 .post_set_power_state = &r600_dpm_post_set_power_state,
1291                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1292                 .fini = &rv770_dpm_fini,
1293                 .get_sclk = &rv770_dpm_get_sclk,
1294                 .get_mclk = &rv770_dpm_get_mclk,
1295                 .print_power_state = &rv770_dpm_print_power_state,
1296                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1297                 .force_performance_level = &rv770_dpm_force_performance_level,
1298                 .vblank_too_short = &rv770_dpm_vblank_too_short,
1299                 .get_current_sclk = &rv770_dpm_get_current_sclk,
1300                 .get_current_mclk = &rv770_dpm_get_current_mclk,
1301         },
1302         .pflip = {
1303                 .page_flip = &rv770_page_flip,
1304                 .page_flip_pending = &rv770_page_flip_pending,
1305         },
1306 };
1307
1308 static struct radeon_asic_ring evergreen_gfx_ring = {
1309         .ib_execute = &evergreen_ring_ib_execute,
1310         .emit_fence = &r600_fence_ring_emit,
1311         .emit_semaphore = &r600_semaphore_ring_emit,
1312         .cs_parse = &evergreen_cs_parse,
1313         .ring_test = &r600_ring_test,
1314         .ib_test = &r600_ib_test,
1315         .is_lockup = &evergreen_gfx_is_lockup,
1316         .get_rptr = &r600_gfx_get_rptr,
1317         .get_wptr = &r600_gfx_get_wptr,
1318         .set_wptr = &r600_gfx_set_wptr,
1319 };
1320
1321 static struct radeon_asic_ring evergreen_dma_ring = {
1322         .ib_execute = &evergreen_dma_ring_ib_execute,
1323         .emit_fence = &evergreen_dma_fence_ring_emit,
1324         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1325         .cs_parse = &evergreen_dma_cs_parse,
1326         .ring_test = &r600_dma_ring_test,
1327         .ib_test = &r600_dma_ib_test,
1328         .is_lockup = &evergreen_dma_is_lockup,
1329         .get_rptr = &r600_dma_get_rptr,
1330         .get_wptr = &r600_dma_get_wptr,
1331         .set_wptr = &r600_dma_set_wptr,
1332 };
1333
1334 static struct radeon_asic evergreen_asic = {
1335         .init = &evergreen_init,
1336         .fini = &evergreen_fini,
1337         .suspend = &evergreen_suspend,
1338         .resume = &evergreen_resume,
1339         .asic_reset = &evergreen_asic_reset,
1340         .vga_set_state = &r600_vga_set_state,
1341         .mmio_hdp_flush = r600_mmio_hdp_flush,
1342         .gui_idle = &r600_gui_idle,
1343         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1344         .get_xclk = &rv770_get_xclk,
1345         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1346         .get_allowed_info_register = evergreen_get_allowed_info_register,
1347         .gart = {
1348                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1349                 .get_page_entry = &rs600_gart_get_page_entry,
1350                 .set_page = &rs600_gart_set_page,
1351         },
1352         .ring = {
1353                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1354                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1355                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1356         },
1357         .irq = {
1358                 .set = &evergreen_irq_set,
1359                 .process = &evergreen_irq_process,
1360         },
1361         .display = {
1362                 .bandwidth_update = &evergreen_bandwidth_update,
1363                 .get_vblank_counter = &evergreen_get_vblank_counter,
1364                 .wait_for_vblank = &dce4_wait_for_vblank,
1365                 .set_backlight_level = &atombios_set_backlight_level,
1366                 .get_backlight_level = &atombios_get_backlight_level,
1367         },
1368         .copy = {
1369                 .blit = &r600_copy_cpdma,
1370                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1371                 .dma = &evergreen_copy_dma,
1372                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1373                 .copy = &evergreen_copy_dma,
1374                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1375         },
1376         .surface = {
1377                 .set_reg = r600_set_surface_reg,
1378                 .clear_reg = r600_clear_surface_reg,
1379         },
1380         .hpd = {
1381                 .init = &evergreen_hpd_init,
1382                 .fini = &evergreen_hpd_fini,
1383                 .sense = &evergreen_hpd_sense,
1384                 .set_polarity = &evergreen_hpd_set_polarity,
1385         },
1386         .pm = {
1387                 .misc = &evergreen_pm_misc,
1388                 .prepare = &evergreen_pm_prepare,
1389                 .finish = &evergreen_pm_finish,
1390                 .init_profile = &r600_pm_init_profile,
1391                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1392                 .get_engine_clock = &radeon_atom_get_engine_clock,
1393                 .set_engine_clock = &radeon_atom_set_engine_clock,
1394                 .get_memory_clock = &radeon_atom_get_memory_clock,
1395                 .set_memory_clock = &radeon_atom_set_memory_clock,
1396                 .get_pcie_lanes = &r600_get_pcie_lanes,
1397                 .set_pcie_lanes = &r600_set_pcie_lanes,
1398                 .set_clock_gating = NULL,
1399                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1400                 .get_temperature = &evergreen_get_temp,
1401         },
1402         .dpm = {
1403                 .init = &cypress_dpm_init,
1404                 .setup_asic = &cypress_dpm_setup_asic,
1405                 .enable = &cypress_dpm_enable,
1406                 .late_enable = &rv770_dpm_late_enable,
1407                 .disable = &cypress_dpm_disable,
1408                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1409                 .set_power_state = &cypress_dpm_set_power_state,
1410                 .post_set_power_state = &r600_dpm_post_set_power_state,
1411                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1412                 .fini = &cypress_dpm_fini,
1413                 .get_sclk = &rv770_dpm_get_sclk,
1414                 .get_mclk = &rv770_dpm_get_mclk,
1415                 .print_power_state = &rv770_dpm_print_power_state,
1416                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1417                 .force_performance_level = &rv770_dpm_force_performance_level,
1418                 .vblank_too_short = &cypress_dpm_vblank_too_short,
1419                 .get_current_sclk = &rv770_dpm_get_current_sclk,
1420                 .get_current_mclk = &rv770_dpm_get_current_mclk,
1421         },
1422         .pflip = {
1423                 .page_flip = &evergreen_page_flip,
1424                 .page_flip_pending = &evergreen_page_flip_pending,
1425         },
1426 };
1427
1428 static struct radeon_asic sumo_asic = {
1429         .init = &evergreen_init,
1430         .fini = &evergreen_fini,
1431         .suspend = &evergreen_suspend,
1432         .resume = &evergreen_resume,
1433         .asic_reset = &evergreen_asic_reset,
1434         .vga_set_state = &r600_vga_set_state,
1435         .mmio_hdp_flush = r600_mmio_hdp_flush,
1436         .gui_idle = &r600_gui_idle,
1437         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1438         .get_xclk = &r600_get_xclk,
1439         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1440         .get_allowed_info_register = evergreen_get_allowed_info_register,
1441         .gart = {
1442                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1443                 .get_page_entry = &rs600_gart_get_page_entry,
1444                 .set_page = &rs600_gart_set_page,
1445         },
1446         .ring = {
1447                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1448                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1449                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1450         },
1451         .irq = {
1452                 .set = &evergreen_irq_set,
1453                 .process = &evergreen_irq_process,
1454         },
1455         .display = {
1456                 .bandwidth_update = &evergreen_bandwidth_update,
1457                 .get_vblank_counter = &evergreen_get_vblank_counter,
1458                 .wait_for_vblank = &dce4_wait_for_vblank,
1459                 .set_backlight_level = &atombios_set_backlight_level,
1460                 .get_backlight_level = &atombios_get_backlight_level,
1461         },
1462         .copy = {
1463                 .blit = &r600_copy_cpdma,
1464                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1465                 .dma = &evergreen_copy_dma,
1466                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1467                 .copy = &evergreen_copy_dma,
1468                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1469         },
1470         .surface = {
1471                 .set_reg = r600_set_surface_reg,
1472                 .clear_reg = r600_clear_surface_reg,
1473         },
1474         .hpd = {
1475                 .init = &evergreen_hpd_init,
1476                 .fini = &evergreen_hpd_fini,
1477                 .sense = &evergreen_hpd_sense,
1478                 .set_polarity = &evergreen_hpd_set_polarity,
1479         },
1480         .pm = {
1481                 .misc = &evergreen_pm_misc,
1482                 .prepare = &evergreen_pm_prepare,
1483                 .finish = &evergreen_pm_finish,
1484                 .init_profile = &sumo_pm_init_profile,
1485                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1486                 .get_engine_clock = &radeon_atom_get_engine_clock,
1487                 .set_engine_clock = &radeon_atom_set_engine_clock,
1488                 .get_memory_clock = NULL,
1489                 .set_memory_clock = NULL,
1490                 .get_pcie_lanes = NULL,
1491                 .set_pcie_lanes = NULL,
1492                 .set_clock_gating = NULL,
1493                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1494                 .get_temperature = &sumo_get_temp,
1495         },
1496         .dpm = {
1497                 .init = &sumo_dpm_init,
1498                 .setup_asic = &sumo_dpm_setup_asic,
1499                 .enable = &sumo_dpm_enable,
1500                 .late_enable = &sumo_dpm_late_enable,
1501                 .disable = &sumo_dpm_disable,
1502                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1503                 .set_power_state = &sumo_dpm_set_power_state,
1504                 .post_set_power_state = &sumo_dpm_post_set_power_state,
1505                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1506                 .fini = &sumo_dpm_fini,
1507                 .get_sclk = &sumo_dpm_get_sclk,
1508                 .get_mclk = &sumo_dpm_get_mclk,
1509                 .print_power_state = &sumo_dpm_print_power_state,
1510                 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1511                 .force_performance_level = &sumo_dpm_force_performance_level,
1512                 .get_current_sclk = &sumo_dpm_get_current_sclk,
1513                 .get_current_mclk = &sumo_dpm_get_current_mclk,
1514         },
1515         .pflip = {
1516                 .page_flip = &evergreen_page_flip,
1517                 .page_flip_pending = &evergreen_page_flip_pending,
1518         },
1519 };
1520
1521 static struct radeon_asic btc_asic = {
1522         .init = &evergreen_init,
1523         .fini = &evergreen_fini,
1524         .suspend = &evergreen_suspend,
1525         .resume = &evergreen_resume,
1526         .asic_reset = &evergreen_asic_reset,
1527         .vga_set_state = &r600_vga_set_state,
1528         .mmio_hdp_flush = r600_mmio_hdp_flush,
1529         .gui_idle = &r600_gui_idle,
1530         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1531         .get_xclk = &rv770_get_xclk,
1532         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1533         .get_allowed_info_register = evergreen_get_allowed_info_register,
1534         .gart = {
1535                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1536                 .get_page_entry = &rs600_gart_get_page_entry,
1537                 .set_page = &rs600_gart_set_page,
1538         },
1539         .ring = {
1540                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1541                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1542                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1543         },
1544         .irq = {
1545                 .set = &evergreen_irq_set,
1546                 .process = &evergreen_irq_process,
1547         },
1548         .display = {
1549                 .bandwidth_update = &evergreen_bandwidth_update,
1550                 .get_vblank_counter = &evergreen_get_vblank_counter,
1551                 .wait_for_vblank = &dce4_wait_for_vblank,
1552                 .set_backlight_level = &atombios_set_backlight_level,
1553                 .get_backlight_level = &atombios_get_backlight_level,
1554         },
1555         .copy = {
1556                 .blit = &r600_copy_cpdma,
1557                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1558                 .dma = &evergreen_copy_dma,
1559                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1560                 .copy = &evergreen_copy_dma,
1561                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1562         },
1563         .surface = {
1564                 .set_reg = r600_set_surface_reg,
1565                 .clear_reg = r600_clear_surface_reg,
1566         },
1567         .hpd = {
1568                 .init = &evergreen_hpd_init,
1569                 .fini = &evergreen_hpd_fini,
1570                 .sense = &evergreen_hpd_sense,
1571                 .set_polarity = &evergreen_hpd_set_polarity,
1572         },
1573         .pm = {
1574                 .misc = &evergreen_pm_misc,
1575                 .prepare = &evergreen_pm_prepare,
1576                 .finish = &evergreen_pm_finish,
1577                 .init_profile = &btc_pm_init_profile,
1578                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1579                 .get_engine_clock = &radeon_atom_get_engine_clock,
1580                 .set_engine_clock = &radeon_atom_set_engine_clock,
1581                 .get_memory_clock = &radeon_atom_get_memory_clock,
1582                 .set_memory_clock = &radeon_atom_set_memory_clock,
1583                 .get_pcie_lanes = &r600_get_pcie_lanes,
1584                 .set_pcie_lanes = &r600_set_pcie_lanes,
1585                 .set_clock_gating = NULL,
1586                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1587                 .get_temperature = &evergreen_get_temp,
1588         },
1589         .dpm = {
1590                 .init = &btc_dpm_init,
1591                 .setup_asic = &btc_dpm_setup_asic,
1592                 .enable = &btc_dpm_enable,
1593                 .late_enable = &rv770_dpm_late_enable,
1594                 .disable = &btc_dpm_disable,
1595                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1596                 .set_power_state = &btc_dpm_set_power_state,
1597                 .post_set_power_state = &btc_dpm_post_set_power_state,
1598                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1599                 .fini = &btc_dpm_fini,
1600                 .get_sclk = &btc_dpm_get_sclk,
1601                 .get_mclk = &btc_dpm_get_mclk,
1602                 .print_power_state = &rv770_dpm_print_power_state,
1603                 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1604                 .force_performance_level = &rv770_dpm_force_performance_level,
1605                 .vblank_too_short = &btc_dpm_vblank_too_short,
1606                 .get_current_sclk = &btc_dpm_get_current_sclk,
1607                 .get_current_mclk = &btc_dpm_get_current_mclk,
1608         },
1609         .pflip = {
1610                 .page_flip = &evergreen_page_flip,
1611                 .page_flip_pending = &evergreen_page_flip_pending,
1612         },
1613 };
1614
1615 static struct radeon_asic_ring cayman_gfx_ring = {
1616         .ib_execute = &cayman_ring_ib_execute,
1617         .ib_parse = &evergreen_ib_parse,
1618         .emit_fence = &cayman_fence_ring_emit,
1619         .emit_semaphore = &r600_semaphore_ring_emit,
1620         .cs_parse = &evergreen_cs_parse,
1621         .ring_test = &r600_ring_test,
1622         .ib_test = &r600_ib_test,
1623         .is_lockup = &cayman_gfx_is_lockup,
1624         .vm_flush = &cayman_vm_flush,
1625         .get_rptr = &cayman_gfx_get_rptr,
1626         .get_wptr = &cayman_gfx_get_wptr,
1627         .set_wptr = &cayman_gfx_set_wptr,
1628 };
1629
1630 static struct radeon_asic_ring cayman_dma_ring = {
1631         .ib_execute = &cayman_dma_ring_ib_execute,
1632         .ib_parse = &evergreen_dma_ib_parse,
1633         .emit_fence = &evergreen_dma_fence_ring_emit,
1634         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1635         .cs_parse = &evergreen_dma_cs_parse,
1636         .ring_test = &r600_dma_ring_test,
1637         .ib_test = &r600_dma_ib_test,
1638         .is_lockup = &cayman_dma_is_lockup,
1639         .vm_flush = &cayman_dma_vm_flush,
1640         .get_rptr = &cayman_dma_get_rptr,
1641         .get_wptr = &cayman_dma_get_wptr,
1642         .set_wptr = &cayman_dma_set_wptr
1643 };
1644
1645 static struct radeon_asic_ring cayman_uvd_ring = {
1646         .ib_execute = &uvd_v1_0_ib_execute,
1647         .emit_fence = &uvd_v2_2_fence_emit,
1648         .emit_semaphore = &uvd_v3_1_semaphore_emit,
1649         .cs_parse = &radeon_uvd_cs_parse,
1650         .ring_test = &uvd_v1_0_ring_test,
1651         .ib_test = &uvd_v1_0_ib_test,
1652         .is_lockup = &radeon_ring_test_lockup,
1653         .get_rptr = &uvd_v1_0_get_rptr,
1654         .get_wptr = &uvd_v1_0_get_wptr,
1655         .set_wptr = &uvd_v1_0_set_wptr,
1656 };
1657
1658 static struct radeon_asic cayman_asic = {
1659         .init = &cayman_init,
1660         .fini = &cayman_fini,
1661         .suspend = &cayman_suspend,
1662         .resume = &cayman_resume,
1663         .asic_reset = &cayman_asic_reset,
1664         .vga_set_state = &r600_vga_set_state,
1665         .mmio_hdp_flush = r600_mmio_hdp_flush,
1666         .gui_idle = &r600_gui_idle,
1667         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1668         .get_xclk = &rv770_get_xclk,
1669         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1670         .get_allowed_info_register = cayman_get_allowed_info_register,
1671         .gart = {
1672                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1673                 .get_page_entry = &rs600_gart_get_page_entry,
1674                 .set_page = &rs600_gart_set_page,
1675         },
1676         .vm = {
1677                 .init = &cayman_vm_init,
1678                 .fini = &cayman_vm_fini,
1679                 .copy_pages = &cayman_dma_vm_copy_pages,
1680                 .write_pages = &cayman_dma_vm_write_pages,
1681                 .set_pages = &cayman_dma_vm_set_pages,
1682                 .pad_ib = &cayman_dma_vm_pad_ib,
1683         },
1684         .ring = {
1685                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1686                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1687                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1688                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1689                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1690                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1691         },
1692         .irq = {
1693                 .set = &evergreen_irq_set,
1694                 .process = &evergreen_irq_process,
1695         },
1696         .display = {
1697                 .bandwidth_update = &evergreen_bandwidth_update,
1698                 .get_vblank_counter = &evergreen_get_vblank_counter,
1699                 .wait_for_vblank = &dce4_wait_for_vblank,
1700                 .set_backlight_level = &atombios_set_backlight_level,
1701                 .get_backlight_level = &atombios_get_backlight_level,
1702         },
1703         .copy = {
1704                 .blit = &r600_copy_cpdma,
1705                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1706                 .dma = &evergreen_copy_dma,
1707                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1708                 .copy = &evergreen_copy_dma,
1709                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1710         },
1711         .surface = {
1712                 .set_reg = r600_set_surface_reg,
1713                 .clear_reg = r600_clear_surface_reg,
1714         },
1715         .hpd = {
1716                 .init = &evergreen_hpd_init,
1717                 .fini = &evergreen_hpd_fini,
1718                 .sense = &evergreen_hpd_sense,
1719                 .set_polarity = &evergreen_hpd_set_polarity,
1720         },
1721         .pm = {
1722                 .misc = &evergreen_pm_misc,
1723                 .prepare = &evergreen_pm_prepare,
1724                 .finish = &evergreen_pm_finish,
1725                 .init_profile = &btc_pm_init_profile,
1726                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1727                 .get_engine_clock = &radeon_atom_get_engine_clock,
1728                 .set_engine_clock = &radeon_atom_set_engine_clock,
1729                 .get_memory_clock = &radeon_atom_get_memory_clock,
1730                 .set_memory_clock = &radeon_atom_set_memory_clock,
1731                 .get_pcie_lanes = &r600_get_pcie_lanes,
1732                 .set_pcie_lanes = &r600_set_pcie_lanes,
1733                 .set_clock_gating = NULL,
1734                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1735                 .get_temperature = &evergreen_get_temp,
1736         },
1737         .dpm = {
1738                 .init = &ni_dpm_init,
1739                 .setup_asic = &ni_dpm_setup_asic,
1740                 .enable = &ni_dpm_enable,
1741                 .late_enable = &rv770_dpm_late_enable,
1742                 .disable = &ni_dpm_disable,
1743                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1744                 .set_power_state = &ni_dpm_set_power_state,
1745                 .post_set_power_state = &ni_dpm_post_set_power_state,
1746                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1747                 .fini = &ni_dpm_fini,
1748                 .get_sclk = &ni_dpm_get_sclk,
1749                 .get_mclk = &ni_dpm_get_mclk,
1750                 .print_power_state = &ni_dpm_print_power_state,
1751                 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1752                 .force_performance_level = &ni_dpm_force_performance_level,
1753                 .vblank_too_short = &ni_dpm_vblank_too_short,
1754                 .get_current_sclk = &ni_dpm_get_current_sclk,
1755                 .get_current_mclk = &ni_dpm_get_current_mclk,
1756         },
1757         .pflip = {
1758                 .page_flip = &evergreen_page_flip,
1759                 .page_flip_pending = &evergreen_page_flip_pending,
1760         },
1761 };
1762
1763 static struct radeon_asic_ring trinity_vce_ring = {
1764         .ib_execute = &radeon_vce_ib_execute,
1765         .emit_fence = &radeon_vce_fence_emit,
1766         .emit_semaphore = &radeon_vce_semaphore_emit,
1767         .cs_parse = &radeon_vce_cs_parse,
1768         .ring_test = &radeon_vce_ring_test,
1769         .ib_test = &radeon_vce_ib_test,
1770         .is_lockup = &radeon_ring_test_lockup,
1771         .get_rptr = &vce_v1_0_get_rptr,
1772         .get_wptr = &vce_v1_0_get_wptr,
1773         .set_wptr = &vce_v1_0_set_wptr,
1774 };
1775
1776 static struct radeon_asic trinity_asic = {
1777         .init = &cayman_init,
1778         .fini = &cayman_fini,
1779         .suspend = &cayman_suspend,
1780         .resume = &cayman_resume,
1781         .asic_reset = &cayman_asic_reset,
1782         .vga_set_state = &r600_vga_set_state,
1783         .mmio_hdp_flush = r600_mmio_hdp_flush,
1784         .gui_idle = &r600_gui_idle,
1785         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1786         .get_xclk = &r600_get_xclk,
1787         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1788         .get_allowed_info_register = cayman_get_allowed_info_register,
1789         .gart = {
1790                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1791                 .get_page_entry = &rs600_gart_get_page_entry,
1792                 .set_page = &rs600_gart_set_page,
1793         },
1794         .vm = {
1795                 .init = &cayman_vm_init,
1796                 .fini = &cayman_vm_fini,
1797                 .copy_pages = &cayman_dma_vm_copy_pages,
1798                 .write_pages = &cayman_dma_vm_write_pages,
1799                 .set_pages = &cayman_dma_vm_set_pages,
1800                 .pad_ib = &cayman_dma_vm_pad_ib,
1801         },
1802         .ring = {
1803                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1804                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1805                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1806                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1807                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1808                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1809                 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
1810                 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
1811         },
1812         .irq = {
1813                 .set = &evergreen_irq_set,
1814                 .process = &evergreen_irq_process,
1815         },
1816         .display = {
1817                 .bandwidth_update = &dce6_bandwidth_update,
1818                 .get_vblank_counter = &evergreen_get_vblank_counter,
1819                 .wait_for_vblank = &dce4_wait_for_vblank,
1820                 .set_backlight_level = &atombios_set_backlight_level,
1821                 .get_backlight_level = &atombios_get_backlight_level,
1822         },
1823         .copy = {
1824                 .blit = &r600_copy_cpdma,
1825                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1826                 .dma = &evergreen_copy_dma,
1827                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1828                 .copy = &evergreen_copy_dma,
1829                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1830         },
1831         .surface = {
1832                 .set_reg = r600_set_surface_reg,
1833                 .clear_reg = r600_clear_surface_reg,
1834         },
1835         .hpd = {
1836                 .init = &evergreen_hpd_init,
1837                 .fini = &evergreen_hpd_fini,
1838                 .sense = &evergreen_hpd_sense,
1839                 .set_polarity = &evergreen_hpd_set_polarity,
1840         },
1841         .pm = {
1842                 .misc = &evergreen_pm_misc,
1843                 .prepare = &evergreen_pm_prepare,
1844                 .finish = &evergreen_pm_finish,
1845                 .init_profile = &sumo_pm_init_profile,
1846                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1847                 .get_engine_clock = &radeon_atom_get_engine_clock,
1848                 .set_engine_clock = &radeon_atom_set_engine_clock,
1849                 .get_memory_clock = NULL,
1850                 .set_memory_clock = NULL,
1851                 .get_pcie_lanes = NULL,
1852                 .set_pcie_lanes = NULL,
1853                 .set_clock_gating = NULL,
1854                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1855                 .set_vce_clocks = &tn_set_vce_clocks,
1856                 .get_temperature = &tn_get_temp,
1857         },
1858         .dpm = {
1859                 .init = &trinity_dpm_init,
1860                 .setup_asic = &trinity_dpm_setup_asic,
1861                 .enable = &trinity_dpm_enable,
1862                 .late_enable = &trinity_dpm_late_enable,
1863                 .disable = &trinity_dpm_disable,
1864                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1865                 .set_power_state = &trinity_dpm_set_power_state,
1866                 .post_set_power_state = &trinity_dpm_post_set_power_state,
1867                 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1868                 .fini = &trinity_dpm_fini,
1869                 .get_sclk = &trinity_dpm_get_sclk,
1870                 .get_mclk = &trinity_dpm_get_mclk,
1871                 .print_power_state = &trinity_dpm_print_power_state,
1872                 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1873                 .force_performance_level = &trinity_dpm_force_performance_level,
1874                 .enable_bapm = &trinity_dpm_enable_bapm,
1875                 .get_current_sclk = &trinity_dpm_get_current_sclk,
1876                 .get_current_mclk = &trinity_dpm_get_current_mclk,
1877         },
1878         .pflip = {
1879                 .page_flip = &evergreen_page_flip,
1880                 .page_flip_pending = &evergreen_page_flip_pending,
1881         },
1882 };
1883
1884 static struct radeon_asic_ring si_gfx_ring = {
1885         .ib_execute = &si_ring_ib_execute,
1886         .ib_parse = &si_ib_parse,
1887         .emit_fence = &si_fence_ring_emit,
1888         .emit_semaphore = &r600_semaphore_ring_emit,
1889         .cs_parse = NULL,
1890         .ring_test = &r600_ring_test,
1891         .ib_test = &r600_ib_test,
1892         .is_lockup = &si_gfx_is_lockup,
1893         .vm_flush = &si_vm_flush,
1894         .get_rptr = &cayman_gfx_get_rptr,
1895         .get_wptr = &cayman_gfx_get_wptr,
1896         .set_wptr = &cayman_gfx_set_wptr,
1897 };
1898
1899 static struct radeon_asic_ring si_dma_ring = {
1900         .ib_execute = &cayman_dma_ring_ib_execute,
1901         .ib_parse = &evergreen_dma_ib_parse,
1902         .emit_fence = &evergreen_dma_fence_ring_emit,
1903         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1904         .cs_parse = NULL,
1905         .ring_test = &r600_dma_ring_test,
1906         .ib_test = &r600_dma_ib_test,
1907         .is_lockup = &si_dma_is_lockup,
1908         .vm_flush = &si_dma_vm_flush,
1909         .get_rptr = &cayman_dma_get_rptr,
1910         .get_wptr = &cayman_dma_get_wptr,
1911         .set_wptr = &cayman_dma_set_wptr,
1912 };
1913
1914 static struct radeon_asic si_asic = {
1915         .init = &si_init,
1916         .fini = &si_fini,
1917         .suspend = &si_suspend,
1918         .resume = &si_resume,
1919         .asic_reset = &si_asic_reset,
1920         .vga_set_state = &r600_vga_set_state,
1921         .mmio_hdp_flush = r600_mmio_hdp_flush,
1922         .gui_idle = &r600_gui_idle,
1923         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1924         .get_xclk = &si_get_xclk,
1925         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1926         .get_allowed_info_register = si_get_allowed_info_register,
1927         .gart = {
1928                 .tlb_flush = &si_pcie_gart_tlb_flush,
1929                 .get_page_entry = &rs600_gart_get_page_entry,
1930                 .set_page = &rs600_gart_set_page,
1931         },
1932         .vm = {
1933                 .init = &si_vm_init,
1934                 .fini = &si_vm_fini,
1935                 .copy_pages = &si_dma_vm_copy_pages,
1936                 .write_pages = &si_dma_vm_write_pages,
1937                 .set_pages = &si_dma_vm_set_pages,
1938                 .pad_ib = &cayman_dma_vm_pad_ib,
1939         },
1940         .ring = {
1941                 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1942                 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1943                 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1944                 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1945                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1946                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1947                 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
1948                 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
1949         },
1950         .irq = {
1951                 .set = &si_irq_set,
1952                 .process = &si_irq_process,
1953         },
1954         .display = {
1955                 .bandwidth_update = &dce6_bandwidth_update,
1956                 .get_vblank_counter = &evergreen_get_vblank_counter,
1957                 .wait_for_vblank = &dce4_wait_for_vblank,
1958                 .set_backlight_level = &atombios_set_backlight_level,
1959                 .get_backlight_level = &atombios_get_backlight_level,
1960         },
1961         .copy = {
1962                 .blit = &r600_copy_cpdma,
1963                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1964                 .dma = &si_copy_dma,
1965                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1966                 .copy = &si_copy_dma,
1967                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1968         },
1969         .surface = {
1970                 .set_reg = r600_set_surface_reg,
1971                 .clear_reg = r600_clear_surface_reg,
1972         },
1973         .hpd = {
1974                 .init = &evergreen_hpd_init,
1975                 .fini = &evergreen_hpd_fini,
1976                 .sense = &evergreen_hpd_sense,
1977                 .set_polarity = &evergreen_hpd_set_polarity,
1978         },
1979         .pm = {
1980                 .misc = &evergreen_pm_misc,
1981                 .prepare = &evergreen_pm_prepare,
1982                 .finish = &evergreen_pm_finish,
1983                 .init_profile = &sumo_pm_init_profile,
1984                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1985                 .get_engine_clock = &radeon_atom_get_engine_clock,
1986                 .set_engine_clock = &radeon_atom_set_engine_clock,
1987                 .get_memory_clock = &radeon_atom_get_memory_clock,
1988                 .set_memory_clock = &radeon_atom_set_memory_clock,
1989                 .get_pcie_lanes = &r600_get_pcie_lanes,
1990                 .set_pcie_lanes = &r600_set_pcie_lanes,
1991                 .set_clock_gating = NULL,
1992                 .set_uvd_clocks = &si_set_uvd_clocks,
1993                 .set_vce_clocks = &si_set_vce_clocks,
1994                 .get_temperature = &si_get_temp,
1995         },
1996         .dpm = {
1997                 .init = &si_dpm_init,
1998                 .setup_asic = &si_dpm_setup_asic,
1999                 .enable = &si_dpm_enable,
2000                 .late_enable = &si_dpm_late_enable,
2001                 .disable = &si_dpm_disable,
2002                 .pre_set_power_state = &si_dpm_pre_set_power_state,
2003                 .set_power_state = &si_dpm_set_power_state,
2004                 .post_set_power_state = &si_dpm_post_set_power_state,
2005                 .display_configuration_changed = &si_dpm_display_configuration_changed,
2006                 .fini = &si_dpm_fini,
2007                 .get_sclk = &ni_dpm_get_sclk,
2008                 .get_mclk = &ni_dpm_get_mclk,
2009                 .print_power_state = &ni_dpm_print_power_state,
2010                 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
2011                 .force_performance_level = &si_dpm_force_performance_level,
2012                 .vblank_too_short = &ni_dpm_vblank_too_short,
2013                 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
2014                 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
2015                 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
2016                 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
2017                 .get_current_sclk = &si_dpm_get_current_sclk,
2018                 .get_current_mclk = &si_dpm_get_current_mclk,
2019         },
2020         .pflip = {
2021                 .page_flip = &evergreen_page_flip,
2022                 .page_flip_pending = &evergreen_page_flip_pending,
2023         },
2024 };
2025
2026 static struct radeon_asic_ring ci_gfx_ring = {
2027         .ib_execute = &cik_ring_ib_execute,
2028         .ib_parse = &cik_ib_parse,
2029         .emit_fence = &cik_fence_gfx_ring_emit,
2030         .emit_semaphore = &cik_semaphore_ring_emit,
2031         .cs_parse = NULL,
2032         .ring_test = &cik_ring_test,
2033         .ib_test = &cik_ib_test,
2034         .is_lockup = &cik_gfx_is_lockup,
2035         .vm_flush = &cik_vm_flush,
2036         .get_rptr = &cik_gfx_get_rptr,
2037         .get_wptr = &cik_gfx_get_wptr,
2038         .set_wptr = &cik_gfx_set_wptr,
2039 };
2040
2041 static struct radeon_asic_ring ci_cp_ring = {
2042         .ib_execute = &cik_ring_ib_execute,
2043         .ib_parse = &cik_ib_parse,
2044         .emit_fence = &cik_fence_compute_ring_emit,
2045         .emit_semaphore = &cik_semaphore_ring_emit,
2046         .cs_parse = NULL,
2047         .ring_test = &cik_ring_test,
2048         .ib_test = &cik_ib_test,
2049         .is_lockup = &cik_gfx_is_lockup,
2050         .vm_flush = &cik_vm_flush,
2051         .get_rptr = &cik_compute_get_rptr,
2052         .get_wptr = &cik_compute_get_wptr,
2053         .set_wptr = &cik_compute_set_wptr,
2054 };
2055
2056 static struct radeon_asic_ring ci_dma_ring = {
2057         .ib_execute = &cik_sdma_ring_ib_execute,
2058         .ib_parse = &cik_ib_parse,
2059         .emit_fence = &cik_sdma_fence_ring_emit,
2060         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2061         .cs_parse = NULL,
2062         .ring_test = &cik_sdma_ring_test,
2063         .ib_test = &cik_sdma_ib_test,
2064         .is_lockup = &cik_sdma_is_lockup,
2065         .vm_flush = &cik_dma_vm_flush,
2066         .get_rptr = &cik_sdma_get_rptr,
2067         .get_wptr = &cik_sdma_get_wptr,
2068         .set_wptr = &cik_sdma_set_wptr,
2069 };
2070
2071 static struct radeon_asic_ring ci_vce_ring = {
2072         .ib_execute = &radeon_vce_ib_execute,
2073         .emit_fence = &radeon_vce_fence_emit,
2074         .emit_semaphore = &radeon_vce_semaphore_emit,
2075         .cs_parse = &radeon_vce_cs_parse,
2076         .ring_test = &radeon_vce_ring_test,
2077         .ib_test = &radeon_vce_ib_test,
2078         .is_lockup = &radeon_ring_test_lockup,
2079         .get_rptr = &vce_v1_0_get_rptr,
2080         .get_wptr = &vce_v1_0_get_wptr,
2081         .set_wptr = &vce_v1_0_set_wptr,
2082 };
2083
2084 static struct radeon_asic ci_asic = {
2085         .init = &cik_init,
2086         .fini = &cik_fini,
2087         .suspend = &cik_suspend,
2088         .resume = &cik_resume,
2089         .asic_reset = &cik_asic_reset,
2090         .vga_set_state = &r600_vga_set_state,
2091         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2092         .gui_idle = &r600_gui_idle,
2093         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2094         .get_xclk = &cik_get_xclk,
2095         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2096         .get_allowed_info_register = cik_get_allowed_info_register,
2097         .gart = {
2098                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2099                 .get_page_entry = &rs600_gart_get_page_entry,
2100                 .set_page = &rs600_gart_set_page,
2101         },
2102         .vm = {
2103                 .init = &cik_vm_init,
2104                 .fini = &cik_vm_fini,
2105                 .copy_pages = &cik_sdma_vm_copy_pages,
2106                 .write_pages = &cik_sdma_vm_write_pages,
2107                 .set_pages = &cik_sdma_vm_set_pages,
2108                 .pad_ib = &cik_sdma_vm_pad_ib,
2109         },
2110         .ring = {
2111                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2112                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2113                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2114                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2115                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2116                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2117                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2118                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2119         },
2120         .irq = {
2121                 .set = &cik_irq_set,
2122                 .process = &cik_irq_process,
2123         },
2124         .display = {
2125                 .bandwidth_update = &dce8_bandwidth_update,
2126                 .get_vblank_counter = &evergreen_get_vblank_counter,
2127                 .wait_for_vblank = &dce4_wait_for_vblank,
2128                 .set_backlight_level = &atombios_set_backlight_level,
2129                 .get_backlight_level = &atombios_get_backlight_level,
2130         },
2131         .copy = {
2132                 .blit = &cik_copy_cpdma,
2133                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2134                 .dma = &cik_copy_dma,
2135                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2136                 .copy = &cik_copy_dma,
2137                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2138         },
2139         .surface = {
2140                 .set_reg = r600_set_surface_reg,
2141                 .clear_reg = r600_clear_surface_reg,
2142         },
2143         .hpd = {
2144                 .init = &evergreen_hpd_init,
2145                 .fini = &evergreen_hpd_fini,
2146                 .sense = &evergreen_hpd_sense,
2147                 .set_polarity = &evergreen_hpd_set_polarity,
2148         },
2149         .pm = {
2150                 .misc = &evergreen_pm_misc,
2151                 .prepare = &evergreen_pm_prepare,
2152                 .finish = &evergreen_pm_finish,
2153                 .init_profile = &sumo_pm_init_profile,
2154                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2155                 .get_engine_clock = &radeon_atom_get_engine_clock,
2156                 .set_engine_clock = &radeon_atom_set_engine_clock,
2157                 .get_memory_clock = &radeon_atom_get_memory_clock,
2158                 .set_memory_clock = &radeon_atom_set_memory_clock,
2159                 .get_pcie_lanes = NULL,
2160                 .set_pcie_lanes = NULL,
2161                 .set_clock_gating = NULL,
2162                 .set_uvd_clocks = &cik_set_uvd_clocks,
2163                 .set_vce_clocks = &cik_set_vce_clocks,
2164                 .get_temperature = &ci_get_temp,
2165         },
2166         .dpm = {
2167                 .init = &ci_dpm_init,
2168                 .setup_asic = &ci_dpm_setup_asic,
2169                 .enable = &ci_dpm_enable,
2170                 .late_enable = &ci_dpm_late_enable,
2171                 .disable = &ci_dpm_disable,
2172                 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2173                 .set_power_state = &ci_dpm_set_power_state,
2174                 .post_set_power_state = &ci_dpm_post_set_power_state,
2175                 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2176                 .fini = &ci_dpm_fini,
2177                 .get_sclk = &ci_dpm_get_sclk,
2178                 .get_mclk = &ci_dpm_get_mclk,
2179                 .print_power_state = &ci_dpm_print_power_state,
2180                 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2181                 .force_performance_level = &ci_dpm_force_performance_level,
2182                 .vblank_too_short = &ci_dpm_vblank_too_short,
2183                 .powergate_uvd = &ci_dpm_powergate_uvd,
2184                 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
2185                 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
2186                 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
2187                 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
2188                 .get_current_sclk = &ci_dpm_get_current_sclk,
2189                 .get_current_mclk = &ci_dpm_get_current_mclk,
2190         },
2191         .pflip = {
2192                 .page_flip = &evergreen_page_flip,
2193                 .page_flip_pending = &evergreen_page_flip_pending,
2194         },
2195 };
2196
2197 static struct radeon_asic kv_asic = {
2198         .init = &cik_init,
2199         .fini = &cik_fini,
2200         .suspend = &cik_suspend,
2201         .resume = &cik_resume,
2202         .asic_reset = &cik_asic_reset,
2203         .vga_set_state = &r600_vga_set_state,
2204         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2205         .gui_idle = &r600_gui_idle,
2206         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2207         .get_xclk = &cik_get_xclk,
2208         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2209         .get_allowed_info_register = cik_get_allowed_info_register,
2210         .gart = {
2211                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2212                 .get_page_entry = &rs600_gart_get_page_entry,
2213                 .set_page = &rs600_gart_set_page,
2214         },
2215         .vm = {
2216                 .init = &cik_vm_init,
2217                 .fini = &cik_vm_fini,
2218                 .copy_pages = &cik_sdma_vm_copy_pages,
2219                 .write_pages = &cik_sdma_vm_write_pages,
2220                 .set_pages = &cik_sdma_vm_set_pages,
2221                 .pad_ib = &cik_sdma_vm_pad_ib,
2222         },
2223         .ring = {
2224                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2225                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2226                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2227                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2228                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2229                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2230                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2231                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2232         },
2233         .irq = {
2234                 .set = &cik_irq_set,
2235                 .process = &cik_irq_process,
2236         },
2237         .display = {
2238                 .bandwidth_update = &dce8_bandwidth_update,
2239                 .get_vblank_counter = &evergreen_get_vblank_counter,
2240                 .wait_for_vblank = &dce4_wait_for_vblank,
2241                 .set_backlight_level = &atombios_set_backlight_level,
2242                 .get_backlight_level = &atombios_get_backlight_level,
2243         },
2244         .copy = {
2245                 .blit = &cik_copy_cpdma,
2246                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2247                 .dma = &cik_copy_dma,
2248                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2249                 .copy = &cik_copy_dma,
2250                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2251         },
2252         .surface = {
2253                 .set_reg = r600_set_surface_reg,
2254                 .clear_reg = r600_clear_surface_reg,
2255         },
2256         .hpd = {
2257                 .init = &evergreen_hpd_init,
2258                 .fini = &evergreen_hpd_fini,
2259                 .sense = &evergreen_hpd_sense,
2260                 .set_polarity = &evergreen_hpd_set_polarity,
2261         },
2262         .pm = {
2263                 .misc = &evergreen_pm_misc,
2264                 .prepare = &evergreen_pm_prepare,
2265                 .finish = &evergreen_pm_finish,
2266                 .init_profile = &sumo_pm_init_profile,
2267                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2268                 .get_engine_clock = &radeon_atom_get_engine_clock,
2269                 .set_engine_clock = &radeon_atom_set_engine_clock,
2270                 .get_memory_clock = &radeon_atom_get_memory_clock,
2271                 .set_memory_clock = &radeon_atom_set_memory_clock,
2272                 .get_pcie_lanes = NULL,
2273                 .set_pcie_lanes = NULL,
2274                 .set_clock_gating = NULL,
2275                 .set_uvd_clocks = &cik_set_uvd_clocks,
2276                 .set_vce_clocks = &cik_set_vce_clocks,
2277                 .get_temperature = &kv_get_temp,
2278         },
2279         .dpm = {
2280                 .init = &kv_dpm_init,
2281                 .setup_asic = &kv_dpm_setup_asic,
2282                 .enable = &kv_dpm_enable,
2283                 .late_enable = &kv_dpm_late_enable,
2284                 .disable = &kv_dpm_disable,
2285                 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2286                 .set_power_state = &kv_dpm_set_power_state,
2287                 .post_set_power_state = &kv_dpm_post_set_power_state,
2288                 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2289                 .fini = &kv_dpm_fini,
2290                 .get_sclk = &kv_dpm_get_sclk,
2291                 .get_mclk = &kv_dpm_get_mclk,
2292                 .print_power_state = &kv_dpm_print_power_state,
2293                 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2294                 .force_performance_level = &kv_dpm_force_performance_level,
2295                 .powergate_uvd = &kv_dpm_powergate_uvd,
2296                 .enable_bapm = &kv_dpm_enable_bapm,
2297                 .get_current_sclk = &kv_dpm_get_current_sclk,
2298                 .get_current_mclk = &kv_dpm_get_current_mclk,
2299         },
2300         .pflip = {
2301                 .page_flip = &evergreen_page_flip,
2302                 .page_flip_pending = &evergreen_page_flip_pending,
2303         },
2304 };
2305
2306 /**
2307  * radeon_asic_init - register asic specific callbacks
2308  *
2309  * @rdev: radeon device pointer
2310  *
2311  * Registers the appropriate asic specific callbacks for each
2312  * chip family.  Also sets other asics specific info like the number
2313  * of crtcs and the register aperture accessors (all asics).
2314  * Returns 0 for success.
2315  */
2316 int radeon_asic_init(struct radeon_device *rdev)
2317 {
2318         radeon_register_accessor_init(rdev);
2319
2320         /* set the number of crtcs */
2321         if (rdev->flags & RADEON_SINGLE_CRTC)
2322                 rdev->num_crtc = 1;
2323         else
2324                 rdev->num_crtc = 2;
2325
2326         rdev->has_uvd = false;
2327
2328         switch (rdev->family) {
2329         case CHIP_R100:
2330         case CHIP_RV100:
2331         case CHIP_RS100:
2332         case CHIP_RV200:
2333         case CHIP_RS200:
2334                 rdev->asic = &r100_asic;
2335                 break;
2336         case CHIP_R200:
2337         case CHIP_RV250:
2338         case CHIP_RS300:
2339         case CHIP_RV280:
2340                 rdev->asic = &r200_asic;
2341                 break;
2342         case CHIP_R300:
2343         case CHIP_R350:
2344         case CHIP_RV350:
2345         case CHIP_RV380:
2346                 if (rdev->flags & RADEON_IS_PCIE)
2347                         rdev->asic = &r300_asic_pcie;
2348                 else
2349                         rdev->asic = &r300_asic;
2350                 break;
2351         case CHIP_R420:
2352         case CHIP_R423:
2353         case CHIP_RV410:
2354                 rdev->asic = &r420_asic;
2355                 /* handle macs */
2356                 if (rdev->bios == NULL) {
2357                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2358                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2359                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2360                         rdev->asic->pm.set_memory_clock = NULL;
2361                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2362                 }
2363                 break;
2364         case CHIP_RS400:
2365         case CHIP_RS480:
2366                 rdev->asic = &rs400_asic;
2367                 break;
2368         case CHIP_RS600:
2369                 rdev->asic = &rs600_asic;
2370                 break;
2371         case CHIP_RS690:
2372         case CHIP_RS740:
2373                 rdev->asic = &rs690_asic;
2374                 break;
2375         case CHIP_RV515:
2376                 rdev->asic = &rv515_asic;
2377                 break;
2378         case CHIP_R520:
2379         case CHIP_RV530:
2380         case CHIP_RV560:
2381         case CHIP_RV570:
2382         case CHIP_R580:
2383                 rdev->asic = &r520_asic;
2384                 break;
2385         case CHIP_R600:
2386                 rdev->asic = &r600_asic;
2387                 break;
2388         case CHIP_RV610:
2389         case CHIP_RV630:
2390         case CHIP_RV620:
2391         case CHIP_RV635:
2392         case CHIP_RV670:
2393                 rdev->asic = &rv6xx_asic;
2394                 rdev->has_uvd = true;
2395                 break;
2396         case CHIP_RS780:
2397         case CHIP_RS880:
2398                 rdev->asic = &rs780_asic;
2399                 /* 760G/780V/880V don't have UVD */
2400                 if ((rdev->pdev->device == 0x9616)||
2401                     (rdev->pdev->device == 0x9611)||
2402                     (rdev->pdev->device == 0x9613)||
2403                     (rdev->pdev->device == 0x9711)||
2404                     (rdev->pdev->device == 0x9713))
2405                         rdev->has_uvd = false;
2406                 else
2407                         rdev->has_uvd = true;
2408                 break;
2409         case CHIP_RV770:
2410         case CHIP_RV730:
2411         case CHIP_RV710:
2412         case CHIP_RV740:
2413                 rdev->asic = &rv770_asic;
2414                 rdev->has_uvd = true;
2415                 break;
2416         case CHIP_CEDAR:
2417         case CHIP_REDWOOD:
2418         case CHIP_JUNIPER:
2419         case CHIP_CYPRESS:
2420         case CHIP_HEMLOCK:
2421                 /* set num crtcs */
2422                 if (rdev->family == CHIP_CEDAR)
2423                         rdev->num_crtc = 4;
2424                 else
2425                         rdev->num_crtc = 6;
2426                 rdev->asic = &evergreen_asic;
2427                 rdev->has_uvd = true;
2428                 break;
2429         case CHIP_PALM:
2430         case CHIP_SUMO:
2431         case CHIP_SUMO2:
2432                 rdev->asic = &sumo_asic;
2433                 rdev->has_uvd = true;
2434                 break;
2435         case CHIP_BARTS:
2436         case CHIP_TURKS:
2437         case CHIP_CAICOS:
2438                 /* set num crtcs */
2439                 if (rdev->family == CHIP_CAICOS)
2440                         rdev->num_crtc = 4;
2441                 else
2442                         rdev->num_crtc = 6;
2443                 rdev->asic = &btc_asic;
2444                 rdev->has_uvd = true;
2445                 break;
2446         case CHIP_CAYMAN:
2447                 rdev->asic = &cayman_asic;
2448                 /* set num crtcs */
2449                 rdev->num_crtc = 6;
2450                 rdev->has_uvd = true;
2451                 break;
2452         case CHIP_ARUBA:
2453                 rdev->asic = &trinity_asic;
2454                 /* set num crtcs */
2455                 rdev->num_crtc = 4;
2456                 rdev->has_uvd = true;
2457                 rdev->cg_flags =
2458                         RADEON_CG_SUPPORT_VCE_MGCG;
2459                 break;
2460         case CHIP_TAHITI:
2461         case CHIP_PITCAIRN:
2462         case CHIP_VERDE:
2463         case CHIP_OLAND:
2464         case CHIP_HAINAN:
2465                 rdev->asic = &si_asic;
2466                 /* set num crtcs */
2467                 if (rdev->family == CHIP_HAINAN)
2468                         rdev->num_crtc = 0;
2469                 else if (rdev->family == CHIP_OLAND)
2470                         rdev->num_crtc = 2;
2471                 else
2472                         rdev->num_crtc = 6;
2473                 if (rdev->family == CHIP_HAINAN)
2474                         rdev->has_uvd = false;
2475                 else
2476                         rdev->has_uvd = true;
2477                 switch (rdev->family) {
2478                 case CHIP_TAHITI:
2479                         rdev->cg_flags =
2480                                 RADEON_CG_SUPPORT_GFX_MGCG |
2481                                 RADEON_CG_SUPPORT_GFX_MGLS |
2482                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2483                                 RADEON_CG_SUPPORT_GFX_CGLS |
2484                                 RADEON_CG_SUPPORT_GFX_CGTS |
2485                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2486                                 RADEON_CG_SUPPORT_MC_MGCG |
2487                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2488                                 RADEON_CG_SUPPORT_BIF_LS |
2489                                 RADEON_CG_SUPPORT_VCE_MGCG |
2490                                 RADEON_CG_SUPPORT_UVD_MGCG |
2491                                 RADEON_CG_SUPPORT_HDP_LS |
2492                                 RADEON_CG_SUPPORT_HDP_MGCG;
2493                         rdev->pg_flags = 0;
2494                         break;
2495                 case CHIP_PITCAIRN:
2496                         rdev->cg_flags =
2497                                 RADEON_CG_SUPPORT_GFX_MGCG |
2498                                 RADEON_CG_SUPPORT_GFX_MGLS |
2499                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2500                                 RADEON_CG_SUPPORT_GFX_CGLS |
2501                                 RADEON_CG_SUPPORT_GFX_CGTS |
2502                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2503                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2504                                 RADEON_CG_SUPPORT_MC_LS |
2505                                 RADEON_CG_SUPPORT_MC_MGCG |
2506                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2507                                 RADEON_CG_SUPPORT_BIF_LS |
2508                                 RADEON_CG_SUPPORT_VCE_MGCG |
2509                                 RADEON_CG_SUPPORT_UVD_MGCG |
2510                                 RADEON_CG_SUPPORT_HDP_LS |
2511                                 RADEON_CG_SUPPORT_HDP_MGCG;
2512                         rdev->pg_flags = 0;
2513                         break;
2514                 case CHIP_VERDE:
2515                         rdev->cg_flags =
2516                                 RADEON_CG_SUPPORT_GFX_MGCG |
2517                                 RADEON_CG_SUPPORT_GFX_MGLS |
2518                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2519                                 RADEON_CG_SUPPORT_GFX_CGLS |
2520                                 RADEON_CG_SUPPORT_GFX_CGTS |
2521                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2522                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2523                                 RADEON_CG_SUPPORT_MC_LS |
2524                                 RADEON_CG_SUPPORT_MC_MGCG |
2525                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2526                                 RADEON_CG_SUPPORT_BIF_LS |
2527                                 RADEON_CG_SUPPORT_VCE_MGCG |
2528                                 RADEON_CG_SUPPORT_UVD_MGCG |
2529                                 RADEON_CG_SUPPORT_HDP_LS |
2530                                 RADEON_CG_SUPPORT_HDP_MGCG;
2531                         rdev->pg_flags = 0 |
2532                                 /*RADEON_PG_SUPPORT_GFX_PG | */
2533                                 RADEON_PG_SUPPORT_SDMA;
2534                         break;
2535                 case CHIP_OLAND:
2536                         rdev->cg_flags =
2537                                 RADEON_CG_SUPPORT_GFX_MGCG |
2538                                 RADEON_CG_SUPPORT_GFX_MGLS |
2539                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2540                                 RADEON_CG_SUPPORT_GFX_CGLS |
2541                                 RADEON_CG_SUPPORT_GFX_CGTS |
2542                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2543                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2544                                 RADEON_CG_SUPPORT_MC_LS |
2545                                 RADEON_CG_SUPPORT_MC_MGCG |
2546                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2547                                 RADEON_CG_SUPPORT_BIF_LS |
2548                                 RADEON_CG_SUPPORT_UVD_MGCG |
2549                                 RADEON_CG_SUPPORT_HDP_LS |
2550                                 RADEON_CG_SUPPORT_HDP_MGCG;
2551                         rdev->pg_flags = 0;
2552                         break;
2553                 case CHIP_HAINAN:
2554                         rdev->cg_flags =
2555                                 RADEON_CG_SUPPORT_GFX_MGCG |
2556                                 RADEON_CG_SUPPORT_GFX_MGLS |
2557                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2558                                 RADEON_CG_SUPPORT_GFX_CGLS |
2559                                 RADEON_CG_SUPPORT_GFX_CGTS |
2560                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2561                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2562                                 RADEON_CG_SUPPORT_MC_LS |
2563                                 RADEON_CG_SUPPORT_MC_MGCG |
2564                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2565                                 RADEON_CG_SUPPORT_BIF_LS |
2566                                 RADEON_CG_SUPPORT_HDP_LS |
2567                                 RADEON_CG_SUPPORT_HDP_MGCG;
2568                         rdev->pg_flags = 0;
2569                         break;
2570                 default:
2571                         rdev->cg_flags = 0;
2572                         rdev->pg_flags = 0;
2573                         break;
2574                 }
2575                 break;
2576         case CHIP_BONAIRE:
2577         case CHIP_HAWAII:
2578                 rdev->asic = &ci_asic;
2579                 rdev->num_crtc = 6;
2580                 rdev->has_uvd = true;
2581                 if (rdev->family == CHIP_BONAIRE) {
2582                         rdev->cg_flags =
2583                                 RADEON_CG_SUPPORT_GFX_MGCG |
2584                                 RADEON_CG_SUPPORT_GFX_MGLS |
2585                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2586                                 RADEON_CG_SUPPORT_GFX_CGLS |
2587                                 RADEON_CG_SUPPORT_GFX_CGTS |
2588                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2589                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2590                                 RADEON_CG_SUPPORT_MC_LS |
2591                                 RADEON_CG_SUPPORT_MC_MGCG |
2592                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2593                                 RADEON_CG_SUPPORT_SDMA_LS |
2594                                 RADEON_CG_SUPPORT_BIF_LS |
2595                                 RADEON_CG_SUPPORT_VCE_MGCG |
2596                                 RADEON_CG_SUPPORT_UVD_MGCG |
2597                                 RADEON_CG_SUPPORT_HDP_LS |
2598                                 RADEON_CG_SUPPORT_HDP_MGCG;
2599                         rdev->pg_flags = 0;
2600                 } else {
2601                         rdev->cg_flags =
2602                                 RADEON_CG_SUPPORT_GFX_MGCG |
2603                                 RADEON_CG_SUPPORT_GFX_MGLS |
2604                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2605                                 RADEON_CG_SUPPORT_GFX_CGLS |
2606                                 RADEON_CG_SUPPORT_GFX_CGTS |
2607                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2608                                 RADEON_CG_SUPPORT_MC_LS |
2609                                 RADEON_CG_SUPPORT_MC_MGCG |
2610                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2611                                 RADEON_CG_SUPPORT_SDMA_LS |
2612                                 RADEON_CG_SUPPORT_BIF_LS |
2613                                 RADEON_CG_SUPPORT_VCE_MGCG |
2614                                 RADEON_CG_SUPPORT_UVD_MGCG |
2615                                 RADEON_CG_SUPPORT_HDP_LS |
2616                                 RADEON_CG_SUPPORT_HDP_MGCG;
2617                         rdev->pg_flags = 0;
2618                 }
2619                 break;
2620         case CHIP_KAVERI:
2621         case CHIP_KABINI:
2622         case CHIP_MULLINS:
2623                 rdev->asic = &kv_asic;
2624                 /* set num crtcs */
2625                 if (rdev->family == CHIP_KAVERI) {
2626                         rdev->num_crtc = 4;
2627                         rdev->cg_flags =
2628                                 RADEON_CG_SUPPORT_GFX_MGCG |
2629                                 RADEON_CG_SUPPORT_GFX_MGLS |
2630                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2631                                 RADEON_CG_SUPPORT_GFX_CGLS |
2632                                 RADEON_CG_SUPPORT_GFX_CGTS |
2633                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2634                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2635                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2636                                 RADEON_CG_SUPPORT_SDMA_LS |
2637                                 RADEON_CG_SUPPORT_BIF_LS |
2638                                 RADEON_CG_SUPPORT_VCE_MGCG |
2639                                 RADEON_CG_SUPPORT_UVD_MGCG |
2640                                 RADEON_CG_SUPPORT_HDP_LS |
2641                                 RADEON_CG_SUPPORT_HDP_MGCG;
2642                         rdev->pg_flags = 0;
2643                                 /*RADEON_PG_SUPPORT_GFX_PG |
2644                                 RADEON_PG_SUPPORT_GFX_SMG |
2645                                 RADEON_PG_SUPPORT_GFX_DMG |
2646                                 RADEON_PG_SUPPORT_UVD |
2647                                 RADEON_PG_SUPPORT_VCE |
2648                                 RADEON_PG_SUPPORT_CP |
2649                                 RADEON_PG_SUPPORT_GDS |
2650                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2651                                 RADEON_PG_SUPPORT_ACP |
2652                                 RADEON_PG_SUPPORT_SAMU;*/
2653                 } else {
2654                         rdev->num_crtc = 2;
2655                         rdev->cg_flags =
2656                                 RADEON_CG_SUPPORT_GFX_MGCG |
2657                                 RADEON_CG_SUPPORT_GFX_MGLS |
2658                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2659                                 RADEON_CG_SUPPORT_GFX_CGLS |
2660                                 RADEON_CG_SUPPORT_GFX_CGTS |
2661                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2662                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2663                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2664                                 RADEON_CG_SUPPORT_SDMA_LS |
2665                                 RADEON_CG_SUPPORT_BIF_LS |
2666                                 RADEON_CG_SUPPORT_VCE_MGCG |
2667                                 RADEON_CG_SUPPORT_UVD_MGCG |
2668                                 RADEON_CG_SUPPORT_HDP_LS |
2669                                 RADEON_CG_SUPPORT_HDP_MGCG;
2670                         rdev->pg_flags = 0;
2671                                 /*RADEON_PG_SUPPORT_GFX_PG |
2672                                 RADEON_PG_SUPPORT_GFX_SMG |
2673                                 RADEON_PG_SUPPORT_UVD |
2674                                 RADEON_PG_SUPPORT_VCE |
2675                                 RADEON_PG_SUPPORT_CP |
2676                                 RADEON_PG_SUPPORT_GDS |
2677                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2678                                 RADEON_PG_SUPPORT_SAMU;*/
2679                 }
2680                 rdev->has_uvd = true;
2681                 break;
2682         default:
2683                 /* FIXME: not supported yet */
2684                 return -EINVAL;
2685         }
2686
2687         if (rdev->flags & RADEON_IS_IGP) {
2688                 rdev->asic->pm.get_memory_clock = NULL;
2689                 rdev->asic->pm.set_memory_clock = NULL;
2690         }
2691
2692         return 0;
2693 }
2694