drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 126                 rdev->mc_rreg = &rs780_mc_rreg;
 127                 rdev->mc_wreg = &rs780_mc_wreg;
 128         }
 129
 130         if (rdev->family >= CHIP_BONAIRE) {
 131                 rdev->pciep_rreg = &cik_pciep_rreg;
 132                 rdev->pciep_wreg = &cik_pciep_wreg;
 133         } else if (rdev->family >= CHIP_R600) {
 134                 rdev->pciep_rreg = &r600_pciep_rreg;
 135                 rdev->pciep_wreg = &r600_pciep_wreg;
 136         }
 137 }
 138
 139
 140 /* helper to disable agp */
 141 /**
 142  * radeon_agp_disable - AGP disable helper function
 143  *
 144  * @rdev: radeon device pointer
 145  *
 146  * Removes AGP flags and changes the gart callbacks on AGP
 147  * cards when using the internal gart rather than AGP (all asics).
 148  */
 149 void radeon_agp_disable(struct radeon_device *rdev)
 150 {
 151         rdev->flags &= ~RADEON_IS_AGP;
 152         if (rdev->family >= CHIP_R600) {
 153                 DRM_INFO("Forcing AGP to PCIE mode\n");
 154                 rdev->flags |= RADEON_IS_PCIE;
 155         } else if (rdev->family >= CHIP_RV515 ||
 156                         rdev->family == CHIP_RV380 ||
 157                         rdev->family == CHIP_RV410 ||
 158                         rdev->family == CHIP_R423) {
 159                 DRM_INFO("Forcing AGP to PCIE mode\n");
 160                 rdev->flags |= RADEON_IS_PCIE;
 161                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 162                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 163         } else {
 164                 DRM_INFO("Forcing AGP to PCI mode\n");
 165                 rdev->flags |= RADEON_IS_PCI;
 166                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 167                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 168         }
 169         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 170 }
 171
 172 /*
 173  * ASIC
 174  */
 175
 176 static struct radeon_asic_ring r100_gfx_ring = {
 177         .ib_execute = &r100_ring_ib_execute,
 178         .emit_fence = &r100_fence_ring_emit,
 179         .emit_semaphore = &r100_semaphore_ring_emit,
 180         .cs_parse = &r100_cs_parse,
 181         .ring_start = &r100_ring_start,
 182         .ring_test = &r100_ring_test,
 183         .ib_test = &r100_ib_test,
 184         .is_lockup = &r100_gpu_is_lockup,
 185         .get_rptr = &r100_gfx_get_rptr,
 186         .get_wptr = &r100_gfx_get_wptr,
 187         .set_wptr = &r100_gfx_set_wptr,
 188         .hdp_flush = &r100_ring_hdp_flush,
 189 };
 190
 191 static struct radeon_asic r100_asic = {
 192         .init = &r100_init,
 193         .fini = &r100_fini,
 194         .suspend = &r100_suspend,
 195         .resume = &r100_resume,
 196         .vga_set_state = &r100_vga_set_state,
 197         .asic_reset = &r100_asic_reset,
 198         .mmio_hdp_flush = NULL,
 199         .gui_idle = &r100_gui_idle,
 200         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 201         .gart = {
 202                 .tlb_flush = &r100_pci_gart_tlb_flush,
 203                 .set_page = &r100_pci_gart_set_page,
 204         },
 205         .ring = {
 206                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 207         },
 208         .irq = {
 209                 .set = &r100_irq_set,
 210                 .process = &r100_irq_process,
 211         },
 212         .display = {
 213                 .bandwidth_update = &r100_bandwidth_update,
 214                 .get_vblank_counter = &r100_get_vblank_counter,
 215                 .wait_for_vblank = &r100_wait_for_vblank,
 216                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 217                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 218         },
 219         .copy = {
 220                 .blit = &r100_copy_blit,
 221                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 222                 .dma = NULL,
 223                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 224                 .copy = &r100_copy_blit,
 225                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 226         },
 227         .surface = {
 228                 .set_reg = r100_set_surface_reg,
 229                 .clear_reg = r100_clear_surface_reg,
 230         },
 231         .hpd = {
 232                 .init = &r100_hpd_init,
 233                 .fini = &r100_hpd_fini,
 234                 .sense = &r100_hpd_sense,
 235                 .set_polarity = &r100_hpd_set_polarity,
 236         },
 237         .pm = {
 238                 .misc = &r100_pm_misc,
 239                 .prepare = &r100_pm_prepare,
 240                 .finish = &r100_pm_finish,
 241                 .init_profile = &r100_pm_init_profile,
 242                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 243                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 244                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 245                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 246                 .set_memory_clock = NULL,
 247                 .get_pcie_lanes = NULL,
 248                 .set_pcie_lanes = NULL,
 249                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 250         },
 251         .pflip = {
 252                 .page_flip = &r100_page_flip,
 253                 .page_flip_pending = &r100_page_flip_pending,
 254         },
 255 };
 256
 257 static struct radeon_asic r200_asic = {
 258         .init = &r100_init,
 259         .fini = &r100_fini,
 260         .suspend = &r100_suspend,
 261         .resume = &r100_resume,
 262         .vga_set_state = &r100_vga_set_state,
 263         .asic_reset = &r100_asic_reset,
 264         .mmio_hdp_flush = NULL,
 265         .gui_idle = &r100_gui_idle,
 266         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 267         .gart = {
 268                 .tlb_flush = &r100_pci_gart_tlb_flush,
 269                 .set_page = &r100_pci_gart_set_page,
 270         },
 271         .ring = {
 272                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 273         },
 274         .irq = {
 275                 .set = &r100_irq_set,
 276                 .process = &r100_irq_process,
 277         },
 278         .display = {
 279                 .bandwidth_update = &r100_bandwidth_update,
 280                 .get_vblank_counter = &r100_get_vblank_counter,
 281                 .wait_for_vblank = &r100_wait_for_vblank,
 282                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 283                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 284         },
 285         .copy = {
 286                 .blit = &r100_copy_blit,
 287                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 288                 .dma = &r200_copy_dma,
 289                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 290                 .copy = &r100_copy_blit,
 291                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 292         },
 293         .surface = {
 294                 .set_reg = r100_set_surface_reg,
 295                 .clear_reg = r100_clear_surface_reg,
 296         },
 297         .hpd = {
 298                 .init = &r100_hpd_init,
 299                 .fini = &r100_hpd_fini,
 300                 .sense = &r100_hpd_sense,
 301                 .set_polarity = &r100_hpd_set_polarity,
 302         },
 303         .pm = {
 304                 .misc = &r100_pm_misc,
 305                 .prepare = &r100_pm_prepare,
 306                 .finish = &r100_pm_finish,
 307                 .init_profile = &r100_pm_init_profile,
 308                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 309                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 310                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 311                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 312                 .set_memory_clock = NULL,
 313                 .get_pcie_lanes = NULL,
 314                 .set_pcie_lanes = NULL,
 315                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 316         },
 317         .pflip = {
 318                 .page_flip = &r100_page_flip,
 319                 .page_flip_pending = &r100_page_flip_pending,
 320         },
 321 };
 322
 323 static struct radeon_asic_ring r300_gfx_ring = {
 324         .ib_execute = &r100_ring_ib_execute,
 325         .emit_fence = &r300_fence_ring_emit,
 326         .emit_semaphore = &r100_semaphore_ring_emit,
 327         .cs_parse = &r300_cs_parse,
 328         .ring_start = &r300_ring_start,
 329         .ring_test = &r100_ring_test,
 330         .ib_test = &r100_ib_test,
 331         .is_lockup = &r100_gpu_is_lockup,
 332         .get_rptr = &r100_gfx_get_rptr,
 333         .get_wptr = &r100_gfx_get_wptr,
 334         .set_wptr = &r100_gfx_set_wptr,
 335         .hdp_flush = &r100_ring_hdp_flush,
 336 };
 337
 338 static struct radeon_asic r300_asic = {
 339         .init = &r300_init,
 340         .fini = &r300_fini,
 341         .suspend = &r300_suspend,
 342         .resume = &r300_resume,
 343         .vga_set_state = &r100_vga_set_state,
 344         .asic_reset = &r300_asic_reset,
 345         .mmio_hdp_flush = NULL,
 346         .gui_idle = &r100_gui_idle,
 347         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 348         .gart = {
 349                 .tlb_flush = &r100_pci_gart_tlb_flush,
 350                 .set_page = &r100_pci_gart_set_page,
 351         },
 352         .ring = {
 353                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 354         },
 355         .irq = {
 356                 .set = &r100_irq_set,
 357                 .process = &r100_irq_process,
 358         },
 359         .display = {
 360                 .bandwidth_update = &r100_bandwidth_update,
 361                 .get_vblank_counter = &r100_get_vblank_counter,
 362                 .wait_for_vblank = &r100_wait_for_vblank,
 363                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 364                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 365         },
 366         .copy = {
 367                 .blit = &r100_copy_blit,
 368                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 369                 .dma = &r200_copy_dma,
 370                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 371                 .copy = &r100_copy_blit,
 372                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 373         },
 374         .surface = {
 375                 .set_reg = r100_set_surface_reg,
 376                 .clear_reg = r100_clear_surface_reg,
 377         },
 378         .hpd = {
 379                 .init = &r100_hpd_init,
 380                 .fini = &r100_hpd_fini,
 381                 .sense = &r100_hpd_sense,
 382                 .set_polarity = &r100_hpd_set_polarity,
 383         },
 384         .pm = {
 385                 .misc = &r100_pm_misc,
 386                 .prepare = &r100_pm_prepare,
 387                 .finish = &r100_pm_finish,
 388                 .init_profile = &r100_pm_init_profile,
 389                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 390                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 391                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 392                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 393                 .set_memory_clock = NULL,
 394                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 395                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 396                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 397         },
 398         .pflip = {
 399                 .page_flip = &r100_page_flip,
 400                 .page_flip_pending = &r100_page_flip_pending,
 401         },
 402 };
 403
 404 static struct radeon_asic r300_asic_pcie = {
 405         .init = &r300_init,
 406         .fini = &r300_fini,
 407         .suspend = &r300_suspend,
 408         .resume = &r300_resume,
 409         .vga_set_state = &r100_vga_set_state,
 410         .asic_reset = &r300_asic_reset,
 411         .mmio_hdp_flush = NULL,
 412         .gui_idle = &r100_gui_idle,
 413         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 414         .gart = {
 415                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 416                 .set_page = &rv370_pcie_gart_set_page,
 417         },
 418         .ring = {
 419                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 420         },
 421         .irq = {
 422                 .set = &r100_irq_set,
 423                 .process = &r100_irq_process,
 424         },
 425         .display = {
 426                 .bandwidth_update = &r100_bandwidth_update,
 427                 .get_vblank_counter = &r100_get_vblank_counter,
 428                 .wait_for_vblank = &r100_wait_for_vblank,
 429                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 430                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 431         },
 432         .copy = {
 433                 .blit = &r100_copy_blit,
 434                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 435                 .dma = &r200_copy_dma,
 436                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 437                 .copy = &r100_copy_blit,
 438                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 439         },
 440         .surface = {
 441                 .set_reg = r100_set_surface_reg,
 442                 .clear_reg = r100_clear_surface_reg,
 443         },
 444         .hpd = {
 445                 .init = &r100_hpd_init,
 446                 .fini = &r100_hpd_fini,
 447                 .sense = &r100_hpd_sense,
 448                 .set_polarity = &r100_hpd_set_polarity,
 449         },
 450         .pm = {
 451                 .misc = &r100_pm_misc,
 452                 .prepare = &r100_pm_prepare,
 453                 .finish = &r100_pm_finish,
 454                 .init_profile = &r100_pm_init_profile,
 455                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 456                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 457                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 458                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 459                 .set_memory_clock = NULL,
 460                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 461                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 462                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 463         },
 464         .pflip = {
 465                 .page_flip = &r100_page_flip,
 466                 .page_flip_pending = &r100_page_flip_pending,
 467         },
 468 };
 469
 470 static struct radeon_asic r420_asic = {
 471         .init = &r420_init,
 472         .fini = &r420_fini,
 473         .suspend = &r420_suspend,
 474         .resume = &r420_resume,
 475         .vga_set_state = &r100_vga_set_state,
 476         .asic_reset = &r300_asic_reset,
 477         .mmio_hdp_flush = NULL,
 478         .gui_idle = &r100_gui_idle,
 479         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 480         .gart = {
 481                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 482                 .set_page = &rv370_pcie_gart_set_page,
 483         },
 484         .ring = {
 485                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 486         },
 487         .irq = {
 488                 .set = &r100_irq_set,
 489                 .process = &r100_irq_process,
 490         },
 491         .display = {
 492                 .bandwidth_update = &r100_bandwidth_update,
 493                 .get_vblank_counter = &r100_get_vblank_counter,
 494                 .wait_for_vblank = &r100_wait_for_vblank,
 495                 .set_backlight_level = &atombios_set_backlight_level,
 496                 .get_backlight_level = &atombios_get_backlight_level,
 497         },
 498         .copy = {
 499                 .blit = &r100_copy_blit,
 500                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 501                 .dma = &r200_copy_dma,
 502                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 503                 .copy = &r100_copy_blit,
 504                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 505         },
 506         .surface = {
 507                 .set_reg = r100_set_surface_reg,
 508                 .clear_reg = r100_clear_surface_reg,
 509         },
 510         .hpd = {
 511                 .init = &r100_hpd_init,
 512                 .fini = &r100_hpd_fini,
 513                 .sense = &r100_hpd_sense,
 514                 .set_polarity = &r100_hpd_set_polarity,
 515         },
 516         .pm = {
 517                 .misc = &r100_pm_misc,
 518                 .prepare = &r100_pm_prepare,
 519                 .finish = &r100_pm_finish,
 520                 .init_profile = &r420_pm_init_profile,
 521                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 522                 .get_engine_clock = &radeon_atom_get_engine_clock,
 523                 .set_engine_clock = &radeon_atom_set_engine_clock,
 524                 .get_memory_clock = &radeon_atom_get_memory_clock,
 525                 .set_memory_clock = &radeon_atom_set_memory_clock,
 526                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 527                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 528                 .set_clock_gating = &radeon_atom_set_clock_gating,
 529         },
 530         .pflip = {
 531                 .page_flip = &r100_page_flip,
 532                 .page_flip_pending = &r100_page_flip_pending,
 533         },
 534 };
 535
 536 static struct radeon_asic rs400_asic = {
 537         .init = &rs400_init,
 538         .fini = &rs400_fini,
 539         .suspend = &rs400_suspend,
 540         .resume = &rs400_resume,
 541         .vga_set_state = &r100_vga_set_state,
 542         .asic_reset = &r300_asic_reset,
 543         .mmio_hdp_flush = NULL,
 544         .gui_idle = &r100_gui_idle,
 545         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 546         .gart = {
 547                 .tlb_flush = &rs400_gart_tlb_flush,
 548                 .set_page = &rs400_gart_set_page,
 549         },
 550         .ring = {
 551                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 552         },
 553         .irq = {
 554                 .set = &r100_irq_set,
 555                 .process = &r100_irq_process,
 556         },
 557         .display = {
 558                 .bandwidth_update = &r100_bandwidth_update,
 559                 .get_vblank_counter = &r100_get_vblank_counter,
 560                 .wait_for_vblank = &r100_wait_for_vblank,
 561                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 562                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 563         },
 564         .copy = {
 565                 .blit = &r100_copy_blit,
 566                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 567                 .dma = &r200_copy_dma,
 568                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 569                 .copy = &r100_copy_blit,
 570                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 571         },
 572         .surface = {
 573                 .set_reg = r100_set_surface_reg,
 574                 .clear_reg = r100_clear_surface_reg,
 575         },
 576         .hpd = {
 577                 .init = &r100_hpd_init,
 578                 .fini = &r100_hpd_fini,
 579                 .sense = &r100_hpd_sense,
 580                 .set_polarity = &r100_hpd_set_polarity,
 581         },
 582         .pm = {
 583                 .misc = &r100_pm_misc,
 584                 .prepare = &r100_pm_prepare,
 585                 .finish = &r100_pm_finish,
 586                 .init_profile = &r100_pm_init_profile,
 587                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 588                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 589                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 590                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 591                 .set_memory_clock = NULL,
 592                 .get_pcie_lanes = NULL,
 593                 .set_pcie_lanes = NULL,
 594                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 595         },
 596         .pflip = {
 597                 .page_flip = &r100_page_flip,
 598                 .page_flip_pending = &r100_page_flip_pending,
 599         },
 600 };
 601
 602 static struct radeon_asic rs600_asic = {
 603         .init = &rs600_init,
 604         .fini = &rs600_fini,
 605         .suspend = &rs600_suspend,
 606         .resume = &rs600_resume,
 607         .vga_set_state = &r100_vga_set_state,
 608         .asic_reset = &rs600_asic_reset,
 609         .mmio_hdp_flush = NULL,
 610         .gui_idle = &r100_gui_idle,
 611         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 612         .gart = {
 613                 .tlb_flush = &rs600_gart_tlb_flush,
 614                 .set_page = &rs600_gart_set_page,
 615         },
 616         .ring = {
 617                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 618         },
 619         .irq = {
 620                 .set = &rs600_irq_set,
 621                 .process = &rs600_irq_process,
 622         },
 623         .display = {
 624                 .bandwidth_update = &rs600_bandwidth_update,
 625                 .get_vblank_counter = &rs600_get_vblank_counter,
 626                 .wait_for_vblank = &avivo_wait_for_vblank,
 627                 .set_backlight_level = &atombios_set_backlight_level,
 628                 .get_backlight_level = &atombios_get_backlight_level,
 629                 .hdmi_enable = &r600_hdmi_enable,
 630                 .hdmi_setmode = &r600_hdmi_setmode,
 631         },
 632         .copy = {
 633                 .blit = &r100_copy_blit,
 634                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 635                 .dma = &r200_copy_dma,
 636                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 637                 .copy = &r100_copy_blit,
 638                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 639         },
 640         .surface = {
 641                 .set_reg = r100_set_surface_reg,
 642                 .clear_reg = r100_clear_surface_reg,
 643         },
 644         .hpd = {
 645                 .init = &rs600_hpd_init,
 646                 .fini = &rs600_hpd_fini,
 647                 .sense = &rs600_hpd_sense,
 648                 .set_polarity = &rs600_hpd_set_polarity,
 649         },
 650         .pm = {
 651                 .misc = &rs600_pm_misc,
 652                 .prepare = &rs600_pm_prepare,
 653                 .finish = &rs600_pm_finish,
 654                 .init_profile = &r420_pm_init_profile,
 655                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 656                 .get_engine_clock = &radeon_atom_get_engine_clock,
 657                 .set_engine_clock = &radeon_atom_set_engine_clock,
 658                 .get_memory_clock = &radeon_atom_get_memory_clock,
 659                 .set_memory_clock = &radeon_atom_set_memory_clock,
 660                 .get_pcie_lanes = NULL,
 661                 .set_pcie_lanes = NULL,
 662                 .set_clock_gating = &radeon_atom_set_clock_gating,
 663         },
 664         .pflip = {
 665                 .page_flip = &rs600_page_flip,
 666                 .page_flip_pending = &rs600_page_flip_pending,
 667         },
 668 };
 669
 670 static struct radeon_asic rs690_asic = {
 671         .init = &rs690_init,
 672         .fini = &rs690_fini,
 673         .suspend = &rs690_suspend,
 674         .resume = &rs690_resume,
 675         .vga_set_state = &r100_vga_set_state,
 676         .asic_reset = &rs600_asic_reset,
 677         .mmio_hdp_flush = NULL,
 678         .gui_idle = &r100_gui_idle,
 679         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 680         .gart = {
 681                 .tlb_flush = &rs400_gart_tlb_flush,
 682                 .set_page = &rs400_gart_set_page,
 683         },
 684         .ring = {
 685                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 686         },
 687         .irq = {
 688                 .set = &rs600_irq_set,
 689                 .process = &rs600_irq_process,
 690         },
 691         .display = {
 692                 .get_vblank_counter = &rs600_get_vblank_counter,
 693                 .bandwidth_update = &rs690_bandwidth_update,
 694                 .wait_for_vblank = &avivo_wait_for_vblank,
 695                 .set_backlight_level = &atombios_set_backlight_level,
 696                 .get_backlight_level = &atombios_get_backlight_level,
 697                 .hdmi_enable = &r600_hdmi_enable,
 698                 .hdmi_setmode = &r600_hdmi_setmode,
 699         },
 700         .copy = {
 701                 .blit = &r100_copy_blit,
 702                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 703                 .dma = &r200_copy_dma,
 704                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 705                 .copy = &r200_copy_dma,
 706                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 707         },
 708         .surface = {
 709                 .set_reg = r100_set_surface_reg,
 710                 .clear_reg = r100_clear_surface_reg,
 711         },
 712         .hpd = {
 713                 .init = &rs600_hpd_init,
 714                 .fini = &rs600_hpd_fini,
 715                 .sense = &rs600_hpd_sense,
 716                 .set_polarity = &rs600_hpd_set_polarity,
 717         },
 718         .pm = {
 719                 .misc = &rs600_pm_misc,
 720                 .prepare = &rs600_pm_prepare,
 721                 .finish = &rs600_pm_finish,
 722                 .init_profile = &r420_pm_init_profile,
 723                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 724                 .get_engine_clock = &radeon_atom_get_engine_clock,
 725                 .set_engine_clock = &radeon_atom_set_engine_clock,
 726                 .get_memory_clock = &radeon_atom_get_memory_clock,
 727                 .set_memory_clock = &radeon_atom_set_memory_clock,
 728                 .get_pcie_lanes = NULL,
 729                 .set_pcie_lanes = NULL,
 730                 .set_clock_gating = &radeon_atom_set_clock_gating,
 731         },
 732         .pflip = {
 733                 .page_flip = &rs600_page_flip,
 734                 .page_flip_pending = &rs600_page_flip_pending,
 735         },
 736 };
 737
 738 static struct radeon_asic rv515_asic = {
 739         .init = &rv515_init,
 740         .fini = &rv515_fini,
 741         .suspend = &rv515_suspend,
 742         .resume = &rv515_resume,
 743         .vga_set_state = &r100_vga_set_state,
 744         .asic_reset = &rs600_asic_reset,
 745         .mmio_hdp_flush = NULL,
 746         .gui_idle = &r100_gui_idle,
 747         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 748         .gart = {
 749                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 750                 .set_page = &rv370_pcie_gart_set_page,
 751         },
 752         .ring = {
 753                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 754         },
 755         .irq = {
 756                 .set = &rs600_irq_set,
 757                 .process = &rs600_irq_process,
 758         },
 759         .display = {
 760                 .get_vblank_counter = &rs600_get_vblank_counter,
 761                 .bandwidth_update = &rv515_bandwidth_update,
 762                 .wait_for_vblank = &avivo_wait_for_vblank,
 763                 .set_backlight_level = &atombios_set_backlight_level,
 764                 .get_backlight_level = &atombios_get_backlight_level,
 765         },
 766         .copy = {
 767                 .blit = &r100_copy_blit,
 768                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 769                 .dma = &r200_copy_dma,
 770                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 771                 .copy = &r100_copy_blit,
 772                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 773         },
 774         .surface = {
 775                 .set_reg = r100_set_surface_reg,
 776                 .clear_reg = r100_clear_surface_reg,
 777         },
 778         .hpd = {
 779                 .init = &rs600_hpd_init,
 780                 .fini = &rs600_hpd_fini,
 781                 .sense = &rs600_hpd_sense,
 782                 .set_polarity = &rs600_hpd_set_polarity,
 783         },
 784         .pm = {
 785                 .misc = &rs600_pm_misc,
 786                 .prepare = &rs600_pm_prepare,
 787                 .finish = &rs600_pm_finish,
 788                 .init_profile = &r420_pm_init_profile,
 789                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 790                 .get_engine_clock = &radeon_atom_get_engine_clock,
 791                 .set_engine_clock = &radeon_atom_set_engine_clock,
 792                 .get_memory_clock = &radeon_atom_get_memory_clock,
 793                 .set_memory_clock = &radeon_atom_set_memory_clock,
 794                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 795                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 796                 .set_clock_gating = &radeon_atom_set_clock_gating,
 797         },
 798         .pflip = {
 799                 .page_flip = &rs600_page_flip,
 800                 .page_flip_pending = &rs600_page_flip_pending,
 801         },
 802 };
 803
 804 static struct radeon_asic r520_asic = {
 805         .init = &r520_init,
 806         .fini = &rv515_fini,
 807         .suspend = &rv515_suspend,
 808         .resume = &r520_resume,
 809         .vga_set_state = &r100_vga_set_state,
 810         .asic_reset = &rs600_asic_reset,
 811         .mmio_hdp_flush = NULL,
 812         .gui_idle = &r100_gui_idle,
 813         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 814         .gart = {
 815                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 816                 .set_page = &rv370_pcie_gart_set_page,
 817         },
 818         .ring = {
 819                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 820         },
 821         .irq = {
 822                 .set = &rs600_irq_set,
 823                 .process = &rs600_irq_process,
 824         },
 825         .display = {
 826                 .bandwidth_update = &rv515_bandwidth_update,
 827                 .get_vblank_counter = &rs600_get_vblank_counter,
 828                 .wait_for_vblank = &avivo_wait_for_vblank,
 829                 .set_backlight_level = &atombios_set_backlight_level,
 830                 .get_backlight_level = &atombios_get_backlight_level,
 831         },
 832         .copy = {
 833                 .blit = &r100_copy_blit,
 834                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 835                 .dma = &r200_copy_dma,
 836                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 837                 .copy = &r100_copy_blit,
 838                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 839         },
 840         .surface = {
 841                 .set_reg = r100_set_surface_reg,
 842                 .clear_reg = r100_clear_surface_reg,
 843         },
 844         .hpd = {
 845                 .init = &rs600_hpd_init,
 846                 .fini = &rs600_hpd_fini,
 847                 .sense = &rs600_hpd_sense,
 848                 .set_polarity = &rs600_hpd_set_polarity,
 849         },
 850         .pm = {
 851                 .misc = &rs600_pm_misc,
 852                 .prepare = &rs600_pm_prepare,
 853                 .finish = &rs600_pm_finish,
 854                 .init_profile = &r420_pm_init_profile,
 855                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 856                 .get_engine_clock = &radeon_atom_get_engine_clock,
 857                 .set_engine_clock = &radeon_atom_set_engine_clock,
 858                 .get_memory_clock = &radeon_atom_get_memory_clock,
 859                 .set_memory_clock = &radeon_atom_set_memory_clock,
 860                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 861                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 862                 .set_clock_gating = &radeon_atom_set_clock_gating,
 863         },
 864         .pflip = {
 865                 .page_flip = &rs600_page_flip,
 866                 .page_flip_pending = &rs600_page_flip_pending,
 867         },
 868 };
 869
 870 static struct radeon_asic_ring r600_gfx_ring = {
 871         .ib_execute = &r600_ring_ib_execute,
 872         .emit_fence = &r600_fence_ring_emit,
 873         .emit_semaphore = &r600_semaphore_ring_emit,
 874         .cs_parse = &r600_cs_parse,
 875         .ring_test = &r600_ring_test,
 876         .ib_test = &r600_ib_test,
 877         .is_lockup = &r600_gfx_is_lockup,
 878         .get_rptr = &r600_gfx_get_rptr,
 879         .get_wptr = &r600_gfx_get_wptr,
 880         .set_wptr = &r600_gfx_set_wptr,
 881 };
 882
 883 static struct radeon_asic_ring r600_dma_ring = {
 884         .ib_execute = &r600_dma_ring_ib_execute,
 885         .emit_fence = &r600_dma_fence_ring_emit,
 886         .emit_semaphore = &r600_dma_semaphore_ring_emit,
 887         .cs_parse = &r600_dma_cs_parse,
 888         .ring_test = &r600_dma_ring_test,
 889         .ib_test = &r600_dma_ib_test,
 890         .is_lockup = &r600_dma_is_lockup,
 891         .get_rptr = &r600_dma_get_rptr,
 892         .get_wptr = &r600_dma_get_wptr,
 893         .set_wptr = &r600_dma_set_wptr,
 894 };
 895
 896 static struct radeon_asic r600_asic = {
 897         .init = &r600_init,
 898         .fini = &r600_fini,
 899         .suspend = &r600_suspend,
 900         .resume = &r600_resume,
 901         .vga_set_state = &r600_vga_set_state,
 902         .asic_reset = &r600_asic_reset,
 903         .mmio_hdp_flush = r600_mmio_hdp_flush,
 904         .gui_idle = &r600_gui_idle,
 905         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 906         .get_xclk = &r600_get_xclk,
 907         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 908         .gart = {
 909                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 910                 .set_page = &rs600_gart_set_page,
 911         },
 912         .ring = {
 913                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
 914                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
 915         },
 916         .irq = {
 917                 .set = &r600_irq_set,
 918                 .process = &r600_irq_process,
 919         },
 920         .display = {
 921                 .bandwidth_update = &rv515_bandwidth_update,
 922                 .get_vblank_counter = &rs600_get_vblank_counter,
 923                 .wait_for_vblank = &avivo_wait_for_vblank,
 924                 .set_backlight_level = &atombios_set_backlight_level,
 925                 .get_backlight_level = &atombios_get_backlight_level,
 926                 .hdmi_enable = &r600_hdmi_enable,
 927                 .hdmi_setmode = &r600_hdmi_setmode,
 928         },
 929         .copy = {
 930                 .blit = &r600_copy_cpdma,
 931                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 932                 .dma = &r600_copy_dma,
 933                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 934                 .copy = &r600_copy_cpdma,
 935                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 936         },
 937         .surface = {
 938                 .set_reg = r600_set_surface_reg,
 939                 .clear_reg = r600_clear_surface_reg,
 940         },
 941         .hpd = {
 942                 .init = &r600_hpd_init,
 943                 .fini = &r600_hpd_fini,
 944                 .sense = &r600_hpd_sense,
 945                 .set_polarity = &r600_hpd_set_polarity,
 946         },
 947         .pm = {
 948                 .misc = &r600_pm_misc,
 949                 .prepare = &rs600_pm_prepare,
 950                 .finish = &rs600_pm_finish,
 951                 .init_profile = &r600_pm_init_profile,
 952                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 953                 .get_engine_clock = &radeon_atom_get_engine_clock,
 954                 .set_engine_clock = &radeon_atom_set_engine_clock,
 955                 .get_memory_clock = &radeon_atom_get_memory_clock,
 956                 .set_memory_clock = &radeon_atom_set_memory_clock,
 957                 .get_pcie_lanes = &r600_get_pcie_lanes,
 958                 .set_pcie_lanes = &r600_set_pcie_lanes,
 959                 .set_clock_gating = NULL,
 960                 .get_temperature = &rv6xx_get_temp,
 961         },
 962         .pflip = {
 963                 .page_flip = &rs600_page_flip,
 964                 .page_flip_pending = &rs600_page_flip_pending,
 965         },
 966 };
 967
 968 static struct radeon_asic rv6xx_asic = {
 969         .init = &r600_init,
 970         .fini = &r600_fini,
 971         .suspend = &r600_suspend,
 972         .resume = &r600_resume,
 973         .vga_set_state = &r600_vga_set_state,
 974         .asic_reset = &r600_asic_reset,
 975         .mmio_hdp_flush = r600_mmio_hdp_flush,
 976         .gui_idle = &r600_gui_idle,
 977         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 978         .get_xclk = &r600_get_xclk,
 979         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 980         .gart = {
 981                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 982                 .set_page = &rs600_gart_set_page,
 983         },
 984         .ring = {
 985                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
 986                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
 987         },
 988         .irq = {
 989                 .set = &r600_irq_set,
 990                 .process = &r600_irq_process,
 991         },
 992         .display = {
 993                 .bandwidth_update = &rv515_bandwidth_update,
 994                 .get_vblank_counter = &rs600_get_vblank_counter,
 995                 .wait_for_vblank = &avivo_wait_for_vblank,
 996                 .set_backlight_level = &atombios_set_backlight_level,
 997                 .get_backlight_level = &atombios_get_backlight_level,
 998                 .hdmi_enable = &r600_hdmi_enable,
 999                 .hdmi_setmode = &r600_hdmi_setmode,
1000         },
1001         .copy = {
1002                 .blit = &r600_copy_cpdma,
1003                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1004                 .dma = &r600_copy_dma,
1005                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1006                 .copy = &r600_copy_cpdma,
1007                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1008         },
1009         .surface = {
1010                 .set_reg = r600_set_surface_reg,
1011                 .clear_reg = r600_clear_surface_reg,
1012         },
1013         .hpd = {
1014                 .init = &r600_hpd_init,
1015                 .fini = &r600_hpd_fini,
1016                 .sense = &r600_hpd_sense,
1017                 .set_polarity = &r600_hpd_set_polarity,
1018         },
1019         .pm = {
1020                 .misc = &r600_pm_misc,
1021                 .prepare = &rs600_pm_prepare,
1022                 .finish = &rs600_pm_finish,
1023                 .init_profile = &r600_pm_init_profile,
1024                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1025                 .get_engine_clock = &radeon_atom_get_engine_clock,
1026                 .set_engine_clock = &radeon_atom_set_engine_clock,
1027                 .get_memory_clock = &radeon_atom_get_memory_clock,
1028                 .set_memory_clock = &radeon_atom_set_memory_clock,
1029                 .get_pcie_lanes = &r600_get_pcie_lanes,
1030                 .set_pcie_lanes = &r600_set_pcie_lanes,
1031                 .set_clock_gating = NULL,
1032                 .get_temperature = &rv6xx_get_temp,
1033                 .set_uvd_clocks = &r600_set_uvd_clocks,
1034         },
1035         .dpm = {
1036                 .init = &rv6xx_dpm_init,
1037                 .setup_asic = &rv6xx_setup_asic,
1038                 .enable = &rv6xx_dpm_enable,
1039                 .late_enable = &r600_dpm_late_enable,
1040                 .disable = &rv6xx_dpm_disable,
1041                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1042                 .set_power_state = &rv6xx_dpm_set_power_state,
1043                 .post_set_power_state = &r600_dpm_post_set_power_state,
1044                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1045                 .fini = &rv6xx_dpm_fini,
1046                 .get_sclk = &rv6xx_dpm_get_sclk,
1047                 .get_mclk = &rv6xx_dpm_get_mclk,
1048                 .print_power_state = &rv6xx_dpm_print_power_state,
1049                 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1050                 .force_performance_level = &rv6xx_dpm_force_performance_level,
1051         },
1052         .pflip = {
1053                 .page_flip = &rs600_page_flip,
1054                 .page_flip_pending = &rs600_page_flip_pending,
1055         },
1056 };
1057
1058 static struct radeon_asic rs780_asic = {
1059         .init = &r600_init,
1060         .fini = &r600_fini,
1061         .suspend = &r600_suspend,
1062         .resume = &r600_resume,
1063         .vga_set_state = &r600_vga_set_state,
1064         .asic_reset = &r600_asic_reset,
1065         .mmio_hdp_flush = r600_mmio_hdp_flush,
1066         .gui_idle = &r600_gui_idle,
1067         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1068         .get_xclk = &r600_get_xclk,
1069         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1070         .gart = {
1071                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1072                 .set_page = &rs600_gart_set_page,
1073         },
1074         .ring = {
1075                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1076                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1077         },
1078         .irq = {
1079                 .set = &r600_irq_set,
1080                 .process = &r600_irq_process,
1081         },
1082         .display = {
1083                 .bandwidth_update = &rs690_bandwidth_update,
1084                 .get_vblank_counter = &rs600_get_vblank_counter,
1085                 .wait_for_vblank = &avivo_wait_for_vblank,
1086                 .set_backlight_level = &atombios_set_backlight_level,
1087                 .get_backlight_level = &atombios_get_backlight_level,
1088                 .hdmi_enable = &r600_hdmi_enable,
1089                 .hdmi_setmode = &r600_hdmi_setmode,
1090         },
1091         .copy = {
1092                 .blit = &r600_copy_cpdma,
1093                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1094                 .dma = &r600_copy_dma,
1095                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1096                 .copy = &r600_copy_cpdma,
1097                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1098         },
1099         .surface = {
1100                 .set_reg = r600_set_surface_reg,
1101                 .clear_reg = r600_clear_surface_reg,
1102         },
1103         .hpd = {
1104                 .init = &r600_hpd_init,
1105                 .fini = &r600_hpd_fini,
1106                 .sense = &r600_hpd_sense,
1107                 .set_polarity = &r600_hpd_set_polarity,
1108         },
1109         .pm = {
1110                 .misc = &r600_pm_misc,
1111                 .prepare = &rs600_pm_prepare,
1112                 .finish = &rs600_pm_finish,
1113                 .init_profile = &rs780_pm_init_profile,
1114                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1115                 .get_engine_clock = &radeon_atom_get_engine_clock,
1116                 .set_engine_clock = &radeon_atom_set_engine_clock,
1117                 .get_memory_clock = NULL,
1118                 .set_memory_clock = NULL,
1119                 .get_pcie_lanes = NULL,
1120                 .set_pcie_lanes = NULL,
1121                 .set_clock_gating = NULL,
1122                 .get_temperature = &rv6xx_get_temp,
1123                 .set_uvd_clocks = &r600_set_uvd_clocks,
1124         },
1125         .dpm = {
1126                 .init = &rs780_dpm_init,
1127                 .setup_asic = &rs780_dpm_setup_asic,
1128                 .enable = &rs780_dpm_enable,
1129                 .late_enable = &r600_dpm_late_enable,
1130                 .disable = &rs780_dpm_disable,
1131                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1132                 .set_power_state = &rs780_dpm_set_power_state,
1133                 .post_set_power_state = &r600_dpm_post_set_power_state,
1134                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1135                 .fini = &rs780_dpm_fini,
1136                 .get_sclk = &rs780_dpm_get_sclk,
1137                 .get_mclk = &rs780_dpm_get_mclk,
1138                 .print_power_state = &rs780_dpm_print_power_state,
1139                 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1140                 .force_performance_level = &rs780_dpm_force_performance_level,
1141         },
1142         .pflip = {
1143                 .page_flip = &rs600_page_flip,
1144                 .page_flip_pending = &rs600_page_flip_pending,
1145         },
1146 };
1147
1148 static struct radeon_asic_ring rv770_uvd_ring = {
1149         .ib_execute = &uvd_v1_0_ib_execute,
1150         .emit_fence = &uvd_v2_2_fence_emit,
1151         .emit_semaphore = &uvd_v1_0_semaphore_emit,
1152         .cs_parse = &radeon_uvd_cs_parse,
1153         .ring_test = &uvd_v1_0_ring_test,
1154         .ib_test = &uvd_v1_0_ib_test,
1155         .is_lockup = &radeon_ring_test_lockup,
1156         .get_rptr = &uvd_v1_0_get_rptr,
1157         .get_wptr = &uvd_v1_0_get_wptr,
1158         .set_wptr = &uvd_v1_0_set_wptr,
1159 };
1160
1161 static struct radeon_asic rv770_asic = {
1162         .init = &rv770_init,
1163         .fini = &rv770_fini,
1164         .suspend = &rv770_suspend,
1165         .resume = &rv770_resume,
1166         .asic_reset = &r600_asic_reset,
1167         .vga_set_state = &r600_vga_set_state,
1168         .mmio_hdp_flush = r600_mmio_hdp_flush,
1169         .gui_idle = &r600_gui_idle,
1170         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1171         .get_xclk = &rv770_get_xclk,
1172         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1173         .gart = {
1174                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1175                 .set_page = &rs600_gart_set_page,
1176         },
1177         .ring = {
1178                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1179                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1180                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1181         },
1182         .irq = {
1183                 .set = &r600_irq_set,
1184                 .process = &r600_irq_process,
1185         },
1186         .display = {
1187                 .bandwidth_update = &rv515_bandwidth_update,
1188                 .get_vblank_counter = &rs600_get_vblank_counter,
1189                 .wait_for_vblank = &avivo_wait_for_vblank,
1190                 .set_backlight_level = &atombios_set_backlight_level,
1191                 .get_backlight_level = &atombios_get_backlight_level,
1192                 .hdmi_enable = &r600_hdmi_enable,
1193                 .hdmi_setmode = &dce3_1_hdmi_setmode,
1194         },
1195         .copy = {
1196                 .blit = &r600_copy_cpdma,
1197                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1198                 .dma = &rv770_copy_dma,
1199                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1200                 .copy = &rv770_copy_dma,
1201                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1202         },
1203         .surface = {
1204                 .set_reg = r600_set_surface_reg,
1205                 .clear_reg = r600_clear_surface_reg,
1206         },
1207         .hpd = {
1208                 .init = &r600_hpd_init,
1209                 .fini = &r600_hpd_fini,
1210                 .sense = &r600_hpd_sense,
1211                 .set_polarity = &r600_hpd_set_polarity,
1212         },
1213         .pm = {
1214                 .misc = &rv770_pm_misc,
1215                 .prepare = &rs600_pm_prepare,
1216                 .finish = &rs600_pm_finish,
1217                 .init_profile = &r600_pm_init_profile,
1218                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1219                 .get_engine_clock = &radeon_atom_get_engine_clock,
1220                 .set_engine_clock = &radeon_atom_set_engine_clock,
1221                 .get_memory_clock = &radeon_atom_get_memory_clock,
1222                 .set_memory_clock = &radeon_atom_set_memory_clock,
1223                 .get_pcie_lanes = &r600_get_pcie_lanes,
1224                 .set_pcie_lanes = &r600_set_pcie_lanes,
1225                 .set_clock_gating = &radeon_atom_set_clock_gating,
1226                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1227                 .get_temperature = &rv770_get_temp,
1228         },
1229         .dpm = {
1230                 .init = &rv770_dpm_init,
1231                 .setup_asic = &rv770_dpm_setup_asic,
1232                 .enable = &rv770_dpm_enable,
1233                 .late_enable = &rv770_dpm_late_enable,
1234                 .disable = &rv770_dpm_disable,
1235                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1236                 .set_power_state = &rv770_dpm_set_power_state,
1237                 .post_set_power_state = &r600_dpm_post_set_power_state,
1238                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1239                 .fini = &rv770_dpm_fini,
1240                 .get_sclk = &rv770_dpm_get_sclk,
1241                 .get_mclk = &rv770_dpm_get_mclk,
1242                 .print_power_state = &rv770_dpm_print_power_state,
1243                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1244                 .force_performance_level = &rv770_dpm_force_performance_level,
1245                 .vblank_too_short = &rv770_dpm_vblank_too_short,
1246         },
1247         .pflip = {
1248                 .page_flip = &rv770_page_flip,
1249                 .page_flip_pending = &rv770_page_flip_pending,
1250         },
1251 };
1252
1253 static struct radeon_asic_ring evergreen_gfx_ring = {
1254         .ib_execute = &evergreen_ring_ib_execute,
1255         .emit_fence = &r600_fence_ring_emit,
1256         .emit_semaphore = &r600_semaphore_ring_emit,
1257         .cs_parse = &evergreen_cs_parse,
1258         .ring_test = &r600_ring_test,
1259         .ib_test = &r600_ib_test,
1260         .is_lockup = &evergreen_gfx_is_lockup,
1261         .get_rptr = &r600_gfx_get_rptr,
1262         .get_wptr = &r600_gfx_get_wptr,
1263         .set_wptr = &r600_gfx_set_wptr,
1264 };
1265
1266 static struct radeon_asic_ring evergreen_dma_ring = {
1267         .ib_execute = &evergreen_dma_ring_ib_execute,
1268         .emit_fence = &evergreen_dma_fence_ring_emit,
1269         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1270         .cs_parse = &evergreen_dma_cs_parse,
1271         .ring_test = &r600_dma_ring_test,
1272         .ib_test = &r600_dma_ib_test,
1273         .is_lockup = &evergreen_dma_is_lockup,
1274         .get_rptr = &r600_dma_get_rptr,
1275         .get_wptr = &r600_dma_get_wptr,
1276         .set_wptr = &r600_dma_set_wptr,
1277 };
1278
1279 static struct radeon_asic evergreen_asic = {
1280         .init = &evergreen_init,
1281         .fini = &evergreen_fini,
1282         .suspend = &evergreen_suspend,
1283         .resume = &evergreen_resume,
1284         .asic_reset = &evergreen_asic_reset,
1285         .vga_set_state = &r600_vga_set_state,
1286         .mmio_hdp_flush = r600_mmio_hdp_flush,
1287         .gui_idle = &r600_gui_idle,
1288         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1289         .get_xclk = &rv770_get_xclk,
1290         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1291         .gart = {
1292                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1293                 .set_page = &rs600_gart_set_page,
1294         },
1295         .ring = {
1296                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1297                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1298                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1299         },
1300         .irq = {
1301                 .set = &evergreen_irq_set,
1302                 .process = &evergreen_irq_process,
1303         },
1304         .display = {
1305                 .bandwidth_update = &evergreen_bandwidth_update,
1306                 .get_vblank_counter = &evergreen_get_vblank_counter,
1307                 .wait_for_vblank = &dce4_wait_for_vblank,
1308                 .set_backlight_level = &atombios_set_backlight_level,
1309                 .get_backlight_level = &atombios_get_backlight_level,
1310                 .hdmi_enable = &evergreen_hdmi_enable,
1311                 .hdmi_setmode = &evergreen_hdmi_setmode,
1312         },
1313         .copy = {
1314                 .blit = &r600_copy_cpdma,
1315                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1316                 .dma = &evergreen_copy_dma,
1317                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1318                 .copy = &evergreen_copy_dma,
1319                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1320         },
1321         .surface = {
1322                 .set_reg = r600_set_surface_reg,
1323                 .clear_reg = r600_clear_surface_reg,
1324         },
1325         .hpd = {
1326                 .init = &evergreen_hpd_init,
1327                 .fini = &evergreen_hpd_fini,
1328                 .sense = &evergreen_hpd_sense,
1329                 .set_polarity = &evergreen_hpd_set_polarity,
1330         },
1331         .pm = {
1332                 .misc = &evergreen_pm_misc,
1333                 .prepare = &evergreen_pm_prepare,
1334                 .finish = &evergreen_pm_finish,
1335                 .init_profile = &r600_pm_init_profile,
1336                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1337                 .get_engine_clock = &radeon_atom_get_engine_clock,
1338                 .set_engine_clock = &radeon_atom_set_engine_clock,
1339                 .get_memory_clock = &radeon_atom_get_memory_clock,
1340                 .set_memory_clock = &radeon_atom_set_memory_clock,
1341                 .get_pcie_lanes = &r600_get_pcie_lanes,
1342                 .set_pcie_lanes = &r600_set_pcie_lanes,
1343                 .set_clock_gating = NULL,
1344                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1345                 .get_temperature = &evergreen_get_temp,
1346         },
1347         .dpm = {
1348                 .init = &cypress_dpm_init,
1349                 .setup_asic = &cypress_dpm_setup_asic,
1350                 .enable = &cypress_dpm_enable,
1351                 .late_enable = &rv770_dpm_late_enable,
1352                 .disable = &cypress_dpm_disable,
1353                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1354                 .set_power_state = &cypress_dpm_set_power_state,
1355                 .post_set_power_state = &r600_dpm_post_set_power_state,
1356                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1357                 .fini = &cypress_dpm_fini,
1358                 .get_sclk = &rv770_dpm_get_sclk,
1359                 .get_mclk = &rv770_dpm_get_mclk,
1360                 .print_power_state = &rv770_dpm_print_power_state,
1361                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1362                 .force_performance_level = &rv770_dpm_force_performance_level,
1363                 .vblank_too_short = &cypress_dpm_vblank_too_short,
1364         },
1365         .pflip = {
1366                 .page_flip = &evergreen_page_flip,
1367                 .page_flip_pending = &evergreen_page_flip_pending,
1368         },
1369 };
1370
1371 static struct radeon_asic sumo_asic = {
1372         .init = &evergreen_init,
1373         .fini = &evergreen_fini,
1374         .suspend = &evergreen_suspend,
1375         .resume = &evergreen_resume,
1376         .asic_reset = &evergreen_asic_reset,
1377         .vga_set_state = &r600_vga_set_state,
1378         .mmio_hdp_flush = r600_mmio_hdp_flush,
1379         .gui_idle = &r600_gui_idle,
1380         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1381         .get_xclk = &r600_get_xclk,
1382         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1383         .gart = {
1384                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1385                 .set_page = &rs600_gart_set_page,
1386         },
1387         .ring = {
1388                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1389                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1390                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1391         },
1392         .irq = {
1393                 .set = &evergreen_irq_set,
1394                 .process = &evergreen_irq_process,
1395         },
1396         .display = {
1397                 .bandwidth_update = &evergreen_bandwidth_update,
1398                 .get_vblank_counter = &evergreen_get_vblank_counter,
1399                 .wait_for_vblank = &dce4_wait_for_vblank,
1400                 .set_backlight_level = &atombios_set_backlight_level,
1401                 .get_backlight_level = &atombios_get_backlight_level,
1402                 .hdmi_enable = &evergreen_hdmi_enable,
1403                 .hdmi_setmode = &evergreen_hdmi_setmode,
1404         },
1405         .copy = {
1406                 .blit = &r600_copy_cpdma,
1407                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1408                 .dma = &evergreen_copy_dma,
1409                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1410                 .copy = &evergreen_copy_dma,
1411                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1412         },
1413         .surface = {
1414                 .set_reg = r600_set_surface_reg,
1415                 .clear_reg = r600_clear_surface_reg,
1416         },
1417         .hpd = {
1418                 .init = &evergreen_hpd_init,
1419                 .fini = &evergreen_hpd_fini,
1420                 .sense = &evergreen_hpd_sense,
1421                 .set_polarity = &evergreen_hpd_set_polarity,
1422         },
1423         .pm = {
1424                 .misc = &evergreen_pm_misc,
1425                 .prepare = &evergreen_pm_prepare,
1426                 .finish = &evergreen_pm_finish,
1427                 .init_profile = &sumo_pm_init_profile,
1428                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1429                 .get_engine_clock = &radeon_atom_get_engine_clock,
1430                 .set_engine_clock = &radeon_atom_set_engine_clock,
1431                 .get_memory_clock = NULL,
1432                 .set_memory_clock = NULL,
1433                 .get_pcie_lanes = NULL,
1434                 .set_pcie_lanes = NULL,
1435                 .set_clock_gating = NULL,
1436                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1437                 .get_temperature = &sumo_get_temp,
1438         },
1439         .dpm = {
1440                 .init = &sumo_dpm_init,
1441                 .setup_asic = &sumo_dpm_setup_asic,
1442                 .enable = &sumo_dpm_enable,
1443                 .late_enable = &sumo_dpm_late_enable,
1444                 .disable = &sumo_dpm_disable,
1445                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1446                 .set_power_state = &sumo_dpm_set_power_state,
1447                 .post_set_power_state = &sumo_dpm_post_set_power_state,
1448                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1449                 .fini = &sumo_dpm_fini,
1450                 .get_sclk = &sumo_dpm_get_sclk,
1451                 .get_mclk = &sumo_dpm_get_mclk,
1452                 .print_power_state = &sumo_dpm_print_power_state,
1453                 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1454                 .force_performance_level = &sumo_dpm_force_performance_level,
1455         },
1456         .pflip = {
1457                 .page_flip = &evergreen_page_flip,
1458                 .page_flip_pending = &evergreen_page_flip_pending,
1459         },
1460 };
1461
1462 static struct radeon_asic btc_asic = {
1463         .init = &evergreen_init,
1464         .fini = &evergreen_fini,
1465         .suspend = &evergreen_suspend,
1466         .resume = &evergreen_resume,
1467         .asic_reset = &evergreen_asic_reset,
1468         .vga_set_state = &r600_vga_set_state,
1469         .mmio_hdp_flush = r600_mmio_hdp_flush,
1470         .gui_idle = &r600_gui_idle,
1471         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1472         .get_xclk = &rv770_get_xclk,
1473         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1474         .gart = {
1475                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1476                 .set_page = &rs600_gart_set_page,
1477         },
1478         .ring = {
1479                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1480                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1481                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1482         },
1483         .irq = {
1484                 .set = &evergreen_irq_set,
1485                 .process = &evergreen_irq_process,
1486         },
1487         .display = {
1488                 .bandwidth_update = &evergreen_bandwidth_update,
1489                 .get_vblank_counter = &evergreen_get_vblank_counter,
1490                 .wait_for_vblank = &dce4_wait_for_vblank,
1491                 .set_backlight_level = &atombios_set_backlight_level,
1492                 .get_backlight_level = &atombios_get_backlight_level,
1493                 .hdmi_enable = &evergreen_hdmi_enable,
1494                 .hdmi_setmode = &evergreen_hdmi_setmode,
1495         },
1496         .copy = {
1497                 .blit = &r600_copy_cpdma,
1498                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1499                 .dma = &evergreen_copy_dma,
1500                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1501                 .copy = &evergreen_copy_dma,
1502                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1503         },
1504         .surface = {
1505                 .set_reg = r600_set_surface_reg,
1506                 .clear_reg = r600_clear_surface_reg,
1507         },
1508         .hpd = {
1509                 .init = &evergreen_hpd_init,
1510                 .fini = &evergreen_hpd_fini,
1511                 .sense = &evergreen_hpd_sense,
1512                 .set_polarity = &evergreen_hpd_set_polarity,
1513         },
1514         .pm = {
1515                 .misc = &evergreen_pm_misc,
1516                 .prepare = &evergreen_pm_prepare,
1517                 .finish = &evergreen_pm_finish,
1518                 .init_profile = &btc_pm_init_profile,
1519                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1520                 .get_engine_clock = &radeon_atom_get_engine_clock,
1521                 .set_engine_clock = &radeon_atom_set_engine_clock,
1522                 .get_memory_clock = &radeon_atom_get_memory_clock,
1523                 .set_memory_clock = &radeon_atom_set_memory_clock,
1524                 .get_pcie_lanes = &r600_get_pcie_lanes,
1525                 .set_pcie_lanes = &r600_set_pcie_lanes,
1526                 .set_clock_gating = NULL,
1527                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1528                 .get_temperature = &evergreen_get_temp,
1529         },
1530         .dpm = {
1531                 .init = &btc_dpm_init,
1532                 .setup_asic = &btc_dpm_setup_asic,
1533                 .enable = &btc_dpm_enable,
1534                 .late_enable = &rv770_dpm_late_enable,
1535                 .disable = &btc_dpm_disable,
1536                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1537                 .set_power_state = &btc_dpm_set_power_state,
1538                 .post_set_power_state = &btc_dpm_post_set_power_state,
1539                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1540                 .fini = &btc_dpm_fini,
1541                 .get_sclk = &btc_dpm_get_sclk,
1542                 .get_mclk = &btc_dpm_get_mclk,
1543                 .print_power_state = &rv770_dpm_print_power_state,
1544                 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1545                 .force_performance_level = &rv770_dpm_force_performance_level,
1546                 .vblank_too_short = &btc_dpm_vblank_too_short,
1547         },
1548         .pflip = {
1549                 .page_flip = &evergreen_page_flip,
1550                 .page_flip_pending = &evergreen_page_flip_pending,
1551         },
1552 };
1553
1554 static struct radeon_asic_ring cayman_gfx_ring = {
1555         .ib_execute = &cayman_ring_ib_execute,
1556         .ib_parse = &evergreen_ib_parse,
1557         .emit_fence = &cayman_fence_ring_emit,
1558         .emit_semaphore = &r600_semaphore_ring_emit,
1559         .cs_parse = &evergreen_cs_parse,
1560         .ring_test = &r600_ring_test,
1561         .ib_test = &r600_ib_test,
1562         .is_lockup = &cayman_gfx_is_lockup,
1563         .vm_flush = &cayman_vm_flush,
1564         .get_rptr = &cayman_gfx_get_rptr,
1565         .get_wptr = &cayman_gfx_get_wptr,
1566         .set_wptr = &cayman_gfx_set_wptr,
1567 };
1568
1569 static struct radeon_asic_ring cayman_dma_ring = {
1570         .ib_execute = &cayman_dma_ring_ib_execute,
1571         .ib_parse = &evergreen_dma_ib_parse,
1572         .emit_fence = &evergreen_dma_fence_ring_emit,
1573         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1574         .cs_parse = &evergreen_dma_cs_parse,
1575         .ring_test = &r600_dma_ring_test,
1576         .ib_test = &r600_dma_ib_test,
1577         .is_lockup = &cayman_dma_is_lockup,
1578         .vm_flush = &cayman_dma_vm_flush,
1579         .get_rptr = &cayman_dma_get_rptr,
1580         .get_wptr = &cayman_dma_get_wptr,
1581         .set_wptr = &cayman_dma_set_wptr
1582 };
1583
1584 static struct radeon_asic_ring cayman_uvd_ring = {
1585         .ib_execute = &uvd_v1_0_ib_execute,
1586         .emit_fence = &uvd_v2_2_fence_emit,
1587         .emit_semaphore = &uvd_v3_1_semaphore_emit,
1588         .cs_parse = &radeon_uvd_cs_parse,
1589         .ring_test = &uvd_v1_0_ring_test,
1590         .ib_test = &uvd_v1_0_ib_test,
1591         .is_lockup = &radeon_ring_test_lockup,
1592         .get_rptr = &uvd_v1_0_get_rptr,
1593         .get_wptr = &uvd_v1_0_get_wptr,
1594         .set_wptr = &uvd_v1_0_set_wptr,
1595 };
1596
1597 static struct radeon_asic cayman_asic = {
1598         .init = &cayman_init,
1599         .fini = &cayman_fini,
1600         .suspend = &cayman_suspend,
1601         .resume = &cayman_resume,
1602         .asic_reset = &cayman_asic_reset,
1603         .vga_set_state = &r600_vga_set_state,
1604         .mmio_hdp_flush = r600_mmio_hdp_flush,
1605         .gui_idle = &r600_gui_idle,
1606         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1607         .get_xclk = &rv770_get_xclk,
1608         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1609         .gart = {
1610                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1611                 .set_page = &rs600_gart_set_page,
1612         },
1613         .vm = {
1614                 .init = &cayman_vm_init,
1615                 .fini = &cayman_vm_fini,
1616                 .copy_pages = &cayman_dma_vm_copy_pages,
1617                 .write_pages = &cayman_dma_vm_write_pages,
1618                 .set_pages = &cayman_dma_vm_set_pages,
1619                 .pad_ib = &cayman_dma_vm_pad_ib,
1620         },
1621         .ring = {
1622                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1623                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1624                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1625                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1626                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1627                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1628         },
1629         .irq = {
1630                 .set = &evergreen_irq_set,
1631                 .process = &evergreen_irq_process,
1632         },
1633         .display = {
1634                 .bandwidth_update = &evergreen_bandwidth_update,
1635                 .get_vblank_counter = &evergreen_get_vblank_counter,
1636                 .wait_for_vblank = &dce4_wait_for_vblank,
1637                 .set_backlight_level = &atombios_set_backlight_level,
1638                 .get_backlight_level = &atombios_get_backlight_level,
1639                 .hdmi_enable = &evergreen_hdmi_enable,
1640                 .hdmi_setmode = &evergreen_hdmi_setmode,
1641         },
1642         .copy = {
1643                 .blit = &r600_copy_cpdma,
1644                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1645                 .dma = &evergreen_copy_dma,
1646                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1647                 .copy = &evergreen_copy_dma,
1648                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1649         },
1650         .surface = {
1651                 .set_reg = r600_set_surface_reg,
1652                 .clear_reg = r600_clear_surface_reg,
1653         },
1654         .hpd = {
1655                 .init = &evergreen_hpd_init,
1656                 .fini = &evergreen_hpd_fini,
1657                 .sense = &evergreen_hpd_sense,
1658                 .set_polarity = &evergreen_hpd_set_polarity,
1659         },
1660         .pm = {
1661                 .misc = &evergreen_pm_misc,
1662                 .prepare = &evergreen_pm_prepare,
1663                 .finish = &evergreen_pm_finish,
1664                 .init_profile = &btc_pm_init_profile,
1665                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1666                 .get_engine_clock = &radeon_atom_get_engine_clock,
1667                 .set_engine_clock = &radeon_atom_set_engine_clock,
1668                 .get_memory_clock = &radeon_atom_get_memory_clock,
1669                 .set_memory_clock = &radeon_atom_set_memory_clock,
1670                 .get_pcie_lanes = &r600_get_pcie_lanes,
1671                 .set_pcie_lanes = &r600_set_pcie_lanes,
1672                 .set_clock_gating = NULL,
1673                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1674                 .get_temperature = &evergreen_get_temp,
1675         },
1676         .dpm = {
1677                 .init = &ni_dpm_init,
1678                 .setup_asic = &ni_dpm_setup_asic,
1679                 .enable = &ni_dpm_enable,
1680                 .late_enable = &rv770_dpm_late_enable,
1681                 .disable = &ni_dpm_disable,
1682                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1683                 .set_power_state = &ni_dpm_set_power_state,
1684                 .post_set_power_state = &ni_dpm_post_set_power_state,
1685                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1686                 .fini = &ni_dpm_fini,
1687                 .get_sclk = &ni_dpm_get_sclk,
1688                 .get_mclk = &ni_dpm_get_mclk,
1689                 .print_power_state = &ni_dpm_print_power_state,
1690                 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1691                 .force_performance_level = &ni_dpm_force_performance_level,
1692                 .vblank_too_short = &ni_dpm_vblank_too_short,
1693         },
1694         .pflip = {
1695                 .page_flip = &evergreen_page_flip,
1696                 .page_flip_pending = &evergreen_page_flip_pending,
1697         },
1698 };
1699
1700 static struct radeon_asic trinity_asic = {
1701         .init = &cayman_init,
1702         .fini = &cayman_fini,
1703         .suspend = &cayman_suspend,
1704         .resume = &cayman_resume,
1705         .asic_reset = &cayman_asic_reset,
1706         .vga_set_state = &r600_vga_set_state,
1707         .mmio_hdp_flush = r600_mmio_hdp_flush,
1708         .gui_idle = &r600_gui_idle,
1709         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1710         .get_xclk = &r600_get_xclk,
1711         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1712         .gart = {
1713                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1714                 .set_page = &rs600_gart_set_page,
1715         },
1716         .vm = {
1717                 .init = &cayman_vm_init,
1718                 .fini = &cayman_vm_fini,
1719                 .copy_pages = &cayman_dma_vm_copy_pages,
1720                 .write_pages = &cayman_dma_vm_write_pages,
1721                 .set_pages = &cayman_dma_vm_set_pages,
1722                 .pad_ib = &cayman_dma_vm_pad_ib,
1723         },
1724         .ring = {
1725                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1726                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1727                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1728                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1729                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1730                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1731         },
1732         .irq = {
1733                 .set = &evergreen_irq_set,
1734                 .process = &evergreen_irq_process,
1735         },
1736         .display = {
1737                 .bandwidth_update = &dce6_bandwidth_update,
1738                 .get_vblank_counter = &evergreen_get_vblank_counter,
1739                 .wait_for_vblank = &dce4_wait_for_vblank,
1740                 .set_backlight_level = &atombios_set_backlight_level,
1741                 .get_backlight_level = &atombios_get_backlight_level,
1742                 .hdmi_enable = &evergreen_hdmi_enable,
1743                 .hdmi_setmode = &evergreen_hdmi_setmode,
1744         },
1745         .copy = {
1746                 .blit = &r600_copy_cpdma,
1747                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1748                 .dma = &evergreen_copy_dma,
1749                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1750                 .copy = &evergreen_copy_dma,
1751                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1752         },
1753         .surface = {
1754                 .set_reg = r600_set_surface_reg,
1755                 .clear_reg = r600_clear_surface_reg,
1756         },
1757         .hpd = {
1758                 .init = &evergreen_hpd_init,
1759                 .fini = &evergreen_hpd_fini,
1760                 .sense = &evergreen_hpd_sense,
1761                 .set_polarity = &evergreen_hpd_set_polarity,
1762         },
1763         .pm = {
1764                 .misc = &evergreen_pm_misc,
1765                 .prepare = &evergreen_pm_prepare,
1766                 .finish = &evergreen_pm_finish,
1767                 .init_profile = &sumo_pm_init_profile,
1768                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1769                 .get_engine_clock = &radeon_atom_get_engine_clock,
1770                 .set_engine_clock = &radeon_atom_set_engine_clock,
1771                 .get_memory_clock = NULL,
1772                 .set_memory_clock = NULL,
1773                 .get_pcie_lanes = NULL,
1774                 .set_pcie_lanes = NULL,
1775                 .set_clock_gating = NULL,
1776                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1777                 .get_temperature = &tn_get_temp,
1778         },
1779         .dpm = {
1780                 .init = &trinity_dpm_init,
1781                 .setup_asic = &trinity_dpm_setup_asic,
1782                 .enable = &trinity_dpm_enable,
1783                 .late_enable = &trinity_dpm_late_enable,
1784                 .disable = &trinity_dpm_disable,
1785                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1786                 .set_power_state = &trinity_dpm_set_power_state,
1787                 .post_set_power_state = &trinity_dpm_post_set_power_state,
1788                 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1789                 .fini = &trinity_dpm_fini,
1790                 .get_sclk = &trinity_dpm_get_sclk,
1791                 .get_mclk = &trinity_dpm_get_mclk,
1792                 .print_power_state = &trinity_dpm_print_power_state,
1793                 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1794                 .force_performance_level = &trinity_dpm_force_performance_level,
1795                 .enable_bapm = &trinity_dpm_enable_bapm,
1796         },
1797         .pflip = {
1798                 .page_flip = &evergreen_page_flip,
1799                 .page_flip_pending = &evergreen_page_flip_pending,
1800         },
1801 };
1802
1803 static struct radeon_asic_ring si_gfx_ring = {
1804         .ib_execute = &si_ring_ib_execute,
1805         .ib_parse = &si_ib_parse,
1806         .emit_fence = &si_fence_ring_emit,
1807         .emit_semaphore = &r600_semaphore_ring_emit,
1808         .cs_parse = NULL,
1809         .ring_test = &r600_ring_test,
1810         .ib_test = &r600_ib_test,
1811         .is_lockup = &si_gfx_is_lockup,
1812         .vm_flush = &si_vm_flush,
1813         .get_rptr = &cayman_gfx_get_rptr,
1814         .get_wptr = &cayman_gfx_get_wptr,
1815         .set_wptr = &cayman_gfx_set_wptr,
1816 };
1817
1818 static struct radeon_asic_ring si_dma_ring = {
1819         .ib_execute = &cayman_dma_ring_ib_execute,
1820         .ib_parse = &evergreen_dma_ib_parse,
1821         .emit_fence = &evergreen_dma_fence_ring_emit,
1822         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1823         .cs_parse = NULL,
1824         .ring_test = &r600_dma_ring_test,
1825         .ib_test = &r600_dma_ib_test,
1826         .is_lockup = &si_dma_is_lockup,
1827         .vm_flush = &si_dma_vm_flush,
1828         .get_rptr = &cayman_dma_get_rptr,
1829         .get_wptr = &cayman_dma_get_wptr,
1830         .set_wptr = &cayman_dma_set_wptr,
1831 };
1832
1833 static struct radeon_asic si_asic = {
1834         .init = &si_init,
1835         .fini = &si_fini,
1836         .suspend = &si_suspend,
1837         .resume = &si_resume,
1838         .asic_reset = &si_asic_reset,
1839         .vga_set_state = &r600_vga_set_state,
1840         .mmio_hdp_flush = r600_mmio_hdp_flush,
1841         .gui_idle = &r600_gui_idle,
1842         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1843         .get_xclk = &si_get_xclk,
1844         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1845         .gart = {
1846                 .tlb_flush = &si_pcie_gart_tlb_flush,
1847                 .set_page = &rs600_gart_set_page,
1848         },
1849         .vm = {
1850                 .init = &si_vm_init,
1851                 .fini = &si_vm_fini,
1852                 .copy_pages = &si_dma_vm_copy_pages,
1853                 .write_pages = &si_dma_vm_write_pages,
1854                 .set_pages = &si_dma_vm_set_pages,
1855                 .pad_ib = &cayman_dma_vm_pad_ib,
1856         },
1857         .ring = {
1858                 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1859                 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1860                 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1861                 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1862                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1863                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1864         },
1865         .irq = {
1866                 .set = &si_irq_set,
1867                 .process = &si_irq_process,
1868         },
1869         .display = {
1870                 .bandwidth_update = &dce6_bandwidth_update,
1871                 .get_vblank_counter = &evergreen_get_vblank_counter,
1872                 .wait_for_vblank = &dce4_wait_for_vblank,
1873                 .set_backlight_level = &atombios_set_backlight_level,
1874                 .get_backlight_level = &atombios_get_backlight_level,
1875                 .hdmi_enable = &evergreen_hdmi_enable,
1876                 .hdmi_setmode = &evergreen_hdmi_setmode,
1877         },
1878         .copy = {
1879                 .blit = &r600_copy_cpdma,
1880                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1881                 .dma = &si_copy_dma,
1882                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1883                 .copy = &si_copy_dma,
1884                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1885         },
1886         .surface = {
1887                 .set_reg = r600_set_surface_reg,
1888                 .clear_reg = r600_clear_surface_reg,
1889         },
1890         .hpd = {
1891                 .init = &evergreen_hpd_init,
1892                 .fini = &evergreen_hpd_fini,
1893                 .sense = &evergreen_hpd_sense,
1894                 .set_polarity = &evergreen_hpd_set_polarity,
1895         },
1896         .pm = {
1897                 .misc = &evergreen_pm_misc,
1898                 .prepare = &evergreen_pm_prepare,
1899                 .finish = &evergreen_pm_finish,
1900                 .init_profile = &sumo_pm_init_profile,
1901                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1902                 .get_engine_clock = &radeon_atom_get_engine_clock,
1903                 .set_engine_clock = &radeon_atom_set_engine_clock,
1904                 .get_memory_clock = &radeon_atom_get_memory_clock,
1905                 .set_memory_clock = &radeon_atom_set_memory_clock,
1906                 .get_pcie_lanes = &r600_get_pcie_lanes,
1907                 .set_pcie_lanes = &r600_set_pcie_lanes,
1908                 .set_clock_gating = NULL,
1909                 .set_uvd_clocks = &si_set_uvd_clocks,
1910                 .get_temperature = &si_get_temp,
1911         },
1912         .dpm = {
1913                 .init = &si_dpm_init,
1914                 .setup_asic = &si_dpm_setup_asic,
1915                 .enable = &si_dpm_enable,
1916                 .late_enable = &si_dpm_late_enable,
1917                 .disable = &si_dpm_disable,
1918                 .pre_set_power_state = &si_dpm_pre_set_power_state,
1919                 .set_power_state = &si_dpm_set_power_state,
1920                 .post_set_power_state = &si_dpm_post_set_power_state,
1921                 .display_configuration_changed = &si_dpm_display_configuration_changed,
1922                 .fini = &si_dpm_fini,
1923                 .get_sclk = &ni_dpm_get_sclk,
1924                 .get_mclk = &ni_dpm_get_mclk,
1925                 .print_power_state = &ni_dpm_print_power_state,
1926                 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1927                 .force_performance_level = &si_dpm_force_performance_level,
1928                 .vblank_too_short = &ni_dpm_vblank_too_short,
1929         },
1930         .pflip = {
1931                 .page_flip = &evergreen_page_flip,
1932                 .page_flip_pending = &evergreen_page_flip_pending,
1933         },
1934 };
1935
1936 static struct radeon_asic_ring ci_gfx_ring = {
1937         .ib_execute = &cik_ring_ib_execute,
1938         .ib_parse = &cik_ib_parse,
1939         .emit_fence = &cik_fence_gfx_ring_emit,
1940         .emit_semaphore = &cik_semaphore_ring_emit,
1941         .cs_parse = NULL,
1942         .ring_test = &cik_ring_test,
1943         .ib_test = &cik_ib_test,
1944         .is_lockup = &cik_gfx_is_lockup,
1945         .vm_flush = &cik_vm_flush,
1946         .get_rptr = &cik_gfx_get_rptr,
1947         .get_wptr = &cik_gfx_get_wptr,
1948         .set_wptr = &cik_gfx_set_wptr,
1949 };
1950
1951 static struct radeon_asic_ring ci_cp_ring = {
1952         .ib_execute = &cik_ring_ib_execute,
1953         .ib_parse = &cik_ib_parse,
1954         .emit_fence = &cik_fence_compute_ring_emit,
1955         .emit_semaphore = &cik_semaphore_ring_emit,
1956         .cs_parse = NULL,
1957         .ring_test = &cik_ring_test,
1958         .ib_test = &cik_ib_test,
1959         .is_lockup = &cik_gfx_is_lockup,
1960         .vm_flush = &cik_vm_flush,
1961         .get_rptr = &cik_compute_get_rptr,
1962         .get_wptr = &cik_compute_get_wptr,
1963         .set_wptr = &cik_compute_set_wptr,
1964 };
1965
1966 static struct radeon_asic_ring ci_dma_ring = {
1967         .ib_execute = &cik_sdma_ring_ib_execute,
1968         .ib_parse = &cik_ib_parse,
1969         .emit_fence = &cik_sdma_fence_ring_emit,
1970         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1971         .cs_parse = NULL,
1972         .ring_test = &cik_sdma_ring_test,
1973         .ib_test = &cik_sdma_ib_test,
1974         .is_lockup = &cik_sdma_is_lockup,
1975         .vm_flush = &cik_dma_vm_flush,
1976         .get_rptr = &cik_sdma_get_rptr,
1977         .get_wptr = &cik_sdma_get_wptr,
1978         .set_wptr = &cik_sdma_set_wptr,
1979 };
1980
1981 static struct radeon_asic_ring ci_vce_ring = {
1982         .ib_execute = &radeon_vce_ib_execute,
1983         .emit_fence = &radeon_vce_fence_emit,
1984         .emit_semaphore = &radeon_vce_semaphore_emit,
1985         .cs_parse = &radeon_vce_cs_parse,
1986         .ring_test = &radeon_vce_ring_test,
1987         .ib_test = &radeon_vce_ib_test,
1988         .is_lockup = &radeon_ring_test_lockup,
1989         .get_rptr = &vce_v1_0_get_rptr,
1990         .get_wptr = &vce_v1_0_get_wptr,
1991         .set_wptr = &vce_v1_0_set_wptr,
1992 };
1993
1994 static struct radeon_asic ci_asic = {
1995         .init = &cik_init,
1996         .fini = &cik_fini,
1997         .suspend = &cik_suspend,
1998         .resume = &cik_resume,
1999         .asic_reset = &cik_asic_reset,
2000         .vga_set_state = &r600_vga_set_state,
2001         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2002         .gui_idle = &r600_gui_idle,
2003         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2004         .get_xclk = &cik_get_xclk,
2005         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2006         .gart = {
2007                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2008                 .set_page = &rs600_gart_set_page,
2009         },
2010         .vm = {
2011                 .init = &cik_vm_init,
2012                 .fini = &cik_vm_fini,
2013                 .copy_pages = &cik_sdma_vm_copy_pages,
2014                 .write_pages = &cik_sdma_vm_write_pages,
2015                 .set_pages = &cik_sdma_vm_set_pages,
2016                 .pad_ib = &cik_sdma_vm_pad_ib,
2017         },
2018         .ring = {
2019                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2020                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2021                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2022                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2023                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2024                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2025                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2026                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2027         },
2028         .irq = {
2029                 .set = &cik_irq_set,
2030                 .process = &cik_irq_process,
2031         },
2032         .display = {
2033                 .bandwidth_update = &dce8_bandwidth_update,
2034                 .get_vblank_counter = &evergreen_get_vblank_counter,
2035                 .wait_for_vblank = &dce4_wait_for_vblank,
2036                 .set_backlight_level = &atombios_set_backlight_level,
2037                 .get_backlight_level = &atombios_get_backlight_level,
2038                 .hdmi_enable = &evergreen_hdmi_enable,
2039                 .hdmi_setmode = &evergreen_hdmi_setmode,
2040         },
2041         .copy = {
2042                 .blit = &cik_copy_cpdma,
2043                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2044                 .dma = &cik_copy_dma,
2045                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2046                 .copy = &cik_copy_dma,
2047                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2048         },
2049         .surface = {
2050                 .set_reg = r600_set_surface_reg,
2051                 .clear_reg = r600_clear_surface_reg,
2052         },
2053         .hpd = {
2054                 .init = &evergreen_hpd_init,
2055                 .fini = &evergreen_hpd_fini,
2056                 .sense = &evergreen_hpd_sense,
2057                 .set_polarity = &evergreen_hpd_set_polarity,
2058         },
2059         .pm = {
2060                 .misc = &evergreen_pm_misc,
2061                 .prepare = &evergreen_pm_prepare,
2062                 .finish = &evergreen_pm_finish,
2063                 .init_profile = &sumo_pm_init_profile,
2064                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2065                 .get_engine_clock = &radeon_atom_get_engine_clock,
2066                 .set_engine_clock = &radeon_atom_set_engine_clock,
2067                 .get_memory_clock = &radeon_atom_get_memory_clock,
2068                 .set_memory_clock = &radeon_atom_set_memory_clock,
2069                 .get_pcie_lanes = NULL,
2070                 .set_pcie_lanes = NULL,
2071                 .set_clock_gating = NULL,
2072                 .set_uvd_clocks = &cik_set_uvd_clocks,
2073                 .set_vce_clocks = &cik_set_vce_clocks,
2074                 .get_temperature = &ci_get_temp,
2075         },
2076         .dpm = {
2077                 .init = &ci_dpm_init,
2078                 .setup_asic = &ci_dpm_setup_asic,
2079                 .enable = &ci_dpm_enable,
2080                 .late_enable = &ci_dpm_late_enable,
2081                 .disable = &ci_dpm_disable,
2082                 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2083                 .set_power_state = &ci_dpm_set_power_state,
2084                 .post_set_power_state = &ci_dpm_post_set_power_state,
2085                 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2086                 .fini = &ci_dpm_fini,
2087                 .get_sclk = &ci_dpm_get_sclk,
2088                 .get_mclk = &ci_dpm_get_mclk,
2089                 .print_power_state = &ci_dpm_print_power_state,
2090                 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2091                 .force_performance_level = &ci_dpm_force_performance_level,
2092                 .vblank_too_short = &ci_dpm_vblank_too_short,
2093                 .powergate_uvd = &ci_dpm_powergate_uvd,
2094         },
2095         .pflip = {
2096                 .page_flip = &evergreen_page_flip,
2097                 .page_flip_pending = &evergreen_page_flip_pending,
2098         },
2099 };
2100
2101 static struct radeon_asic kv_asic = {
2102         .init = &cik_init,
2103         .fini = &cik_fini,
2104         .suspend = &cik_suspend,
2105         .resume = &cik_resume,
2106         .asic_reset = &cik_asic_reset,
2107         .vga_set_state = &r600_vga_set_state,
2108         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2109         .gui_idle = &r600_gui_idle,
2110         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2111         .get_xclk = &cik_get_xclk,
2112         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2113         .gart = {
2114                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2115                 .set_page = &rs600_gart_set_page,
2116         },
2117         .vm = {
2118                 .init = &cik_vm_init,
2119                 .fini = &cik_vm_fini,
2120                 .copy_pages = &cik_sdma_vm_copy_pages,
2121                 .write_pages = &cik_sdma_vm_write_pages,
2122                 .set_pages = &cik_sdma_vm_set_pages,
2123                 .pad_ib = &cik_sdma_vm_pad_ib,
2124         },
2125         .ring = {
2126                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2127                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2128                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2129                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2130                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2131                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2132                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2133                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2134         },
2135         .irq = {
2136                 .set = &cik_irq_set,
2137                 .process = &cik_irq_process,
2138         },
2139         .display = {
2140                 .bandwidth_update = &dce8_bandwidth_update,
2141                 .get_vblank_counter = &evergreen_get_vblank_counter,
2142                 .wait_for_vblank = &dce4_wait_for_vblank,
2143                 .set_backlight_level = &atombios_set_backlight_level,
2144                 .get_backlight_level = &atombios_get_backlight_level,
2145                 .hdmi_enable = &evergreen_hdmi_enable,
2146                 .hdmi_setmode = &evergreen_hdmi_setmode,
2147         },
2148         .copy = {
2149                 .blit = &cik_copy_cpdma,
2150                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2151                 .dma = &cik_copy_dma,
2152                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2153                 .copy = &cik_copy_dma,
2154                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2155         },
2156         .surface = {
2157                 .set_reg = r600_set_surface_reg,
2158                 .clear_reg = r600_clear_surface_reg,
2159         },
2160         .hpd = {
2161                 .init = &evergreen_hpd_init,
2162                 .fini = &evergreen_hpd_fini,
2163                 .sense = &evergreen_hpd_sense,
2164                 .set_polarity = &evergreen_hpd_set_polarity,
2165         },
2166         .pm = {
2167                 .misc = &evergreen_pm_misc,
2168                 .prepare = &evergreen_pm_prepare,
2169                 .finish = &evergreen_pm_finish,
2170                 .init_profile = &sumo_pm_init_profile,
2171                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2172                 .get_engine_clock = &radeon_atom_get_engine_clock,
2173                 .set_engine_clock = &radeon_atom_set_engine_clock,
2174                 .get_memory_clock = &radeon_atom_get_memory_clock,
2175                 .set_memory_clock = &radeon_atom_set_memory_clock,
2176                 .get_pcie_lanes = NULL,
2177                 .set_pcie_lanes = NULL,
2178                 .set_clock_gating = NULL,
2179                 .set_uvd_clocks = &cik_set_uvd_clocks,
2180                 .set_vce_clocks = &cik_set_vce_clocks,
2181                 .get_temperature = &kv_get_temp,
2182         },
2183         .dpm = {
2184                 .init = &kv_dpm_init,
2185                 .setup_asic = &kv_dpm_setup_asic,
2186                 .enable = &kv_dpm_enable,
2187                 .late_enable = &kv_dpm_late_enable,
2188                 .disable = &kv_dpm_disable,
2189                 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2190                 .set_power_state = &kv_dpm_set_power_state,
2191                 .post_set_power_state = &kv_dpm_post_set_power_state,
2192                 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2193                 .fini = &kv_dpm_fini,
2194                 .get_sclk = &kv_dpm_get_sclk,
2195                 .get_mclk = &kv_dpm_get_mclk,
2196                 .print_power_state = &kv_dpm_print_power_state,
2197                 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2198                 .force_performance_level = &kv_dpm_force_performance_level,
2199                 .powergate_uvd = &kv_dpm_powergate_uvd,
2200                 .enable_bapm = &kv_dpm_enable_bapm,
2201         },
2202         .pflip = {
2203                 .page_flip = &evergreen_page_flip,
2204                 .page_flip_pending = &evergreen_page_flip_pending,
2205         },
2206 };
2207
2208 /**
2209  * radeon_asic_init - register asic specific callbacks
2210  *
2211  * @rdev: radeon device pointer
2212  *
2213  * Registers the appropriate asic specific callbacks for each
2214  * chip family.  Also sets other asics specific info like the number
2215  * of crtcs and the register aperture accessors (all asics).
2216  * Returns 0 for success.
2217  */
2218 int radeon_asic_init(struct radeon_device *rdev)
2219 {
2220         radeon_register_accessor_init(rdev);
2221
2222         /* set the number of crtcs */
2223         if (rdev->flags & RADEON_SINGLE_CRTC)
2224                 rdev->num_crtc = 1;
2225         else
2226                 rdev->num_crtc = 2;
2227
2228         rdev->has_uvd = false;
2229
2230         switch (rdev->family) {
2231         case CHIP_R100:
2232         case CHIP_RV100:
2233         case CHIP_RS100:
2234         case CHIP_RV200:
2235         case CHIP_RS200:
2236                 rdev->asic = &r100_asic;
2237                 break;
2238         case CHIP_R200:
2239         case CHIP_RV250:
2240         case CHIP_RS300:
2241         case CHIP_RV280:
2242                 rdev->asic = &r200_asic;
2243                 break;
2244         case CHIP_R300:
2245         case CHIP_R350:
2246         case CHIP_RV350:
2247         case CHIP_RV380:
2248                 if (rdev->flags & RADEON_IS_PCIE)
2249                         rdev->asic = &r300_asic_pcie;
2250                 else
2251                         rdev->asic = &r300_asic;
2252                 break;
2253         case CHIP_R420:
2254         case CHIP_R423:
2255         case CHIP_RV410:
2256                 rdev->asic = &r420_asic;
2257                 /* handle macs */
2258                 if (rdev->bios == NULL) {
2259                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2260                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2261                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2262                         rdev->asic->pm.set_memory_clock = NULL;
2263                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2264                 }
2265                 break;
2266         case CHIP_RS400:
2267         case CHIP_RS480:
2268                 rdev->asic = &rs400_asic;
2269                 break;
2270         case CHIP_RS600:
2271                 rdev->asic = &rs600_asic;
2272                 break;
2273         case CHIP_RS690:
2274         case CHIP_RS740:
2275                 rdev->asic = &rs690_asic;
2276                 break;
2277         case CHIP_RV515:
2278                 rdev->asic = &rv515_asic;
2279                 break;
2280         case CHIP_R520:
2281         case CHIP_RV530:
2282         case CHIP_RV560:
2283         case CHIP_RV570:
2284         case CHIP_R580:
2285                 rdev->asic = &r520_asic;
2286                 break;
2287         case CHIP_R600:
2288                 rdev->asic = &r600_asic;
2289                 break;
2290         case CHIP_RV610:
2291         case CHIP_RV630:
2292         case CHIP_RV620:
2293         case CHIP_RV635:
2294         case CHIP_RV670:
2295                 rdev->asic = &rv6xx_asic;
2296                 rdev->has_uvd = true;
2297                 break;
2298         case CHIP_RS780:
2299         case CHIP_RS880:
2300                 rdev->asic = &rs780_asic;
2301                 rdev->has_uvd = true;
2302                 break;
2303         case CHIP_RV770:
2304         case CHIP_RV730:
2305         case CHIP_RV710:
2306         case CHIP_RV740:
2307                 rdev->asic = &rv770_asic;
2308                 rdev->has_uvd = true;
2309                 break;
2310         case CHIP_CEDAR:
2311         case CHIP_REDWOOD:
2312         case CHIP_JUNIPER:
2313         case CHIP_CYPRESS:
2314         case CHIP_HEMLOCK:
2315                 /* set num crtcs */
2316                 if (rdev->family == CHIP_CEDAR)
2317                         rdev->num_crtc = 4;
2318                 else
2319                         rdev->num_crtc = 6;
2320                 rdev->asic = &evergreen_asic;
2321                 rdev->has_uvd = true;
2322                 break;
2323         case CHIP_PALM:
2324         case CHIP_SUMO:
2325         case CHIP_SUMO2:
2326                 rdev->asic = &sumo_asic;
2327                 rdev->has_uvd = true;
2328                 break;
2329         case CHIP_BARTS:
2330         case CHIP_TURKS:
2331         case CHIP_CAICOS:
2332                 /* set num crtcs */
2333                 if (rdev->family == CHIP_CAICOS)
2334                         rdev->num_crtc = 4;
2335                 else
2336                         rdev->num_crtc = 6;
2337                 rdev->asic = &btc_asic;
2338                 rdev->has_uvd = true;
2339                 break;
2340         case CHIP_CAYMAN:
2341                 rdev->asic = &cayman_asic;
2342                 /* set num crtcs */
2343                 rdev->num_crtc = 6;
2344                 rdev->has_uvd = true;
2345                 break;
2346         case CHIP_ARUBA:
2347                 rdev->asic = &trinity_asic;
2348                 /* set num crtcs */
2349                 rdev->num_crtc = 4;
2350                 rdev->has_uvd = true;
2351                 break;
2352         case CHIP_TAHITI:
2353         case CHIP_PITCAIRN:
2354         case CHIP_VERDE:
2355         case CHIP_OLAND:
2356         case CHIP_HAINAN:
2357                 rdev->asic = &si_asic;
2358                 /* set num crtcs */
2359                 if (rdev->family == CHIP_HAINAN)
2360                         rdev->num_crtc = 0;
2361                 else if (rdev->family == CHIP_OLAND)
2362                         rdev->num_crtc = 2;
2363                 else
2364                         rdev->num_crtc = 6;
2365                 if (rdev->family == CHIP_HAINAN)
2366                         rdev->has_uvd = false;
2367                 else
2368                         rdev->has_uvd = true;
2369                 switch (rdev->family) {
2370                 case CHIP_TAHITI:
2371                         rdev->cg_flags =
2372                                 RADEON_CG_SUPPORT_GFX_MGCG |
2373                                 RADEON_CG_SUPPORT_GFX_MGLS |
2374                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2375                                 RADEON_CG_SUPPORT_GFX_CGLS |
2376                                 RADEON_CG_SUPPORT_GFX_CGTS |
2377                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2378                                 RADEON_CG_SUPPORT_MC_MGCG |
2379                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2380                                 RADEON_CG_SUPPORT_BIF_LS |
2381                                 RADEON_CG_SUPPORT_VCE_MGCG |
2382                                 RADEON_CG_SUPPORT_UVD_MGCG |
2383                                 RADEON_CG_SUPPORT_HDP_LS |
2384                                 RADEON_CG_SUPPORT_HDP_MGCG;
2385                         rdev->pg_flags = 0;
2386                         break;
2387                 case CHIP_PITCAIRN:
2388                         rdev->cg_flags =
2389                                 RADEON_CG_SUPPORT_GFX_MGCG |
2390                                 RADEON_CG_SUPPORT_GFX_MGLS |
2391                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2392                                 RADEON_CG_SUPPORT_GFX_CGLS |
2393                                 RADEON_CG_SUPPORT_GFX_CGTS |
2394                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2395                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2396                                 RADEON_CG_SUPPORT_MC_LS |
2397                                 RADEON_CG_SUPPORT_MC_MGCG |
2398                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2399                                 RADEON_CG_SUPPORT_BIF_LS |
2400                                 RADEON_CG_SUPPORT_VCE_MGCG |
2401                                 RADEON_CG_SUPPORT_UVD_MGCG |
2402                                 RADEON_CG_SUPPORT_HDP_LS |
2403                                 RADEON_CG_SUPPORT_HDP_MGCG;
2404                         rdev->pg_flags = 0;
2405                         break;
2406                 case CHIP_VERDE:
2407                         rdev->cg_flags =
2408                                 RADEON_CG_SUPPORT_GFX_MGCG |
2409                                 RADEON_CG_SUPPORT_GFX_MGLS |
2410                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2411                                 RADEON_CG_SUPPORT_GFX_CGLS |
2412                                 RADEON_CG_SUPPORT_GFX_CGTS |
2413                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2414                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2415                                 RADEON_CG_SUPPORT_MC_LS |
2416                                 RADEON_CG_SUPPORT_MC_MGCG |
2417                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2418                                 RADEON_CG_SUPPORT_BIF_LS |
2419                                 RADEON_CG_SUPPORT_VCE_MGCG |
2420                                 RADEON_CG_SUPPORT_UVD_MGCG |
2421                                 RADEON_CG_SUPPORT_HDP_LS |
2422                                 RADEON_CG_SUPPORT_HDP_MGCG;
2423                         rdev->pg_flags = 0 |
2424                                 /*RADEON_PG_SUPPORT_GFX_PG | */
2425                                 RADEON_PG_SUPPORT_SDMA;
2426                         break;
2427                 case CHIP_OLAND:
2428                         rdev->cg_flags =
2429                                 RADEON_CG_SUPPORT_GFX_MGCG |
2430                                 RADEON_CG_SUPPORT_GFX_MGLS |
2431                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2432                                 RADEON_CG_SUPPORT_GFX_CGLS |
2433                                 RADEON_CG_SUPPORT_GFX_CGTS |
2434                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2435                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2436                                 RADEON_CG_SUPPORT_MC_LS |
2437                                 RADEON_CG_SUPPORT_MC_MGCG |
2438                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2439                                 RADEON_CG_SUPPORT_BIF_LS |
2440                                 RADEON_CG_SUPPORT_UVD_MGCG |
2441                                 RADEON_CG_SUPPORT_HDP_LS |
2442                                 RADEON_CG_SUPPORT_HDP_MGCG;
2443                         rdev->pg_flags = 0;
2444                         break;
2445                 case CHIP_HAINAN:
2446                         rdev->cg_flags =
2447                                 RADEON_CG_SUPPORT_GFX_MGCG |
2448                                 RADEON_CG_SUPPORT_GFX_MGLS |
2449                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2450                                 RADEON_CG_SUPPORT_GFX_CGLS |
2451                                 RADEON_CG_SUPPORT_GFX_CGTS |
2452                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2453                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2454                                 RADEON_CG_SUPPORT_MC_LS |
2455                                 RADEON_CG_SUPPORT_MC_MGCG |
2456                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2457                                 RADEON_CG_SUPPORT_BIF_LS |
2458                                 RADEON_CG_SUPPORT_HDP_LS |
2459                                 RADEON_CG_SUPPORT_HDP_MGCG;
2460                         rdev->pg_flags = 0;
2461                         break;
2462                 default:
2463                         rdev->cg_flags = 0;
2464                         rdev->pg_flags = 0;
2465                         break;
2466                 }
2467                 break;
2468         case CHIP_BONAIRE:
2469         case CHIP_HAWAII:
2470                 rdev->asic = &ci_asic;
2471                 rdev->num_crtc = 6;
2472                 rdev->has_uvd = true;
2473                 if (rdev->family == CHIP_BONAIRE) {
2474                         rdev->cg_flags =
2475                                 RADEON_CG_SUPPORT_GFX_MGCG |
2476                                 RADEON_CG_SUPPORT_GFX_MGLS |
2477                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2478                                 RADEON_CG_SUPPORT_GFX_CGLS |
2479                                 RADEON_CG_SUPPORT_GFX_CGTS |
2480                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2481                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2482                                 RADEON_CG_SUPPORT_MC_LS |
2483                                 RADEON_CG_SUPPORT_MC_MGCG |
2484                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2485                                 RADEON_CG_SUPPORT_SDMA_LS |
2486                                 RADEON_CG_SUPPORT_BIF_LS |
2487                                 RADEON_CG_SUPPORT_VCE_MGCG |
2488                                 RADEON_CG_SUPPORT_UVD_MGCG |
2489                                 RADEON_CG_SUPPORT_HDP_LS |
2490                                 RADEON_CG_SUPPORT_HDP_MGCG;
2491                         rdev->pg_flags = 0;
2492                 } else {
2493                         rdev->cg_flags =
2494                                 RADEON_CG_SUPPORT_GFX_MGCG |
2495                                 RADEON_CG_SUPPORT_GFX_MGLS |
2496                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2497                                 RADEON_CG_SUPPORT_GFX_CGLS |
2498                                 RADEON_CG_SUPPORT_GFX_CGTS |
2499                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2500                                 RADEON_CG_SUPPORT_MC_LS |
2501                                 RADEON_CG_SUPPORT_MC_MGCG |
2502                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2503                                 RADEON_CG_SUPPORT_SDMA_LS |
2504                                 RADEON_CG_SUPPORT_BIF_LS |
2505                                 RADEON_CG_SUPPORT_VCE_MGCG |
2506                                 RADEON_CG_SUPPORT_UVD_MGCG |
2507                                 RADEON_CG_SUPPORT_HDP_LS |
2508                                 RADEON_CG_SUPPORT_HDP_MGCG;
2509                         rdev->pg_flags = 0;
2510                 }
2511                 break;
2512         case CHIP_KAVERI:
2513         case CHIP_KABINI:
2514         case CHIP_MULLINS:
2515                 rdev->asic = &kv_asic;
2516                 /* set num crtcs */
2517                 if (rdev->family == CHIP_KAVERI) {
2518                         rdev->num_crtc = 4;
2519                         rdev->cg_flags =
2520                                 RADEON_CG_SUPPORT_GFX_MGCG |
2521                                 RADEON_CG_SUPPORT_GFX_MGLS |
2522                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2523                                 RADEON_CG_SUPPORT_GFX_CGLS |
2524                                 RADEON_CG_SUPPORT_GFX_CGTS |
2525                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2526                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2527                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2528                                 RADEON_CG_SUPPORT_SDMA_LS |
2529                                 RADEON_CG_SUPPORT_BIF_LS |
2530                                 RADEON_CG_SUPPORT_VCE_MGCG |
2531                                 RADEON_CG_SUPPORT_UVD_MGCG |
2532                                 RADEON_CG_SUPPORT_HDP_LS |
2533                                 RADEON_CG_SUPPORT_HDP_MGCG;
2534                         rdev->pg_flags = 0;
2535                                 /*RADEON_PG_SUPPORT_GFX_PG |
2536                                 RADEON_PG_SUPPORT_GFX_SMG |
2537                                 RADEON_PG_SUPPORT_GFX_DMG |
2538                                 RADEON_PG_SUPPORT_UVD |
2539                                 RADEON_PG_SUPPORT_VCE |
2540                                 RADEON_PG_SUPPORT_CP |
2541                                 RADEON_PG_SUPPORT_GDS |
2542                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2543                                 RADEON_PG_SUPPORT_ACP |
2544                                 RADEON_PG_SUPPORT_SAMU;*/
2545                 } else {
2546                         rdev->num_crtc = 2;
2547                         rdev->cg_flags =
2548                                 RADEON_CG_SUPPORT_GFX_MGCG |
2549                                 RADEON_CG_SUPPORT_GFX_MGLS |
2550                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2551                                 RADEON_CG_SUPPORT_GFX_CGLS |
2552                                 RADEON_CG_SUPPORT_GFX_CGTS |
2553                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2554                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2555                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2556                                 RADEON_CG_SUPPORT_SDMA_LS |
2557                                 RADEON_CG_SUPPORT_BIF_LS |
2558                                 RADEON_CG_SUPPORT_VCE_MGCG |
2559                                 RADEON_CG_SUPPORT_UVD_MGCG |
2560                                 RADEON_CG_SUPPORT_HDP_LS |
2561                                 RADEON_CG_SUPPORT_HDP_MGCG;
2562                         rdev->pg_flags = 0;
2563                                 /*RADEON_PG_SUPPORT_GFX_PG |
2564                                 RADEON_PG_SUPPORT_GFX_SMG |
2565                                 RADEON_PG_SUPPORT_UVD |
2566                                 RADEON_PG_SUPPORT_VCE |
2567                                 RADEON_PG_SUPPORT_CP |
2568                                 RADEON_PG_SUPPORT_GDS |
2569                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2570                                 RADEON_PG_SUPPORT_SAMU;*/
2571                 }
2572                 rdev->has_uvd = true;
2573                 break;
2574         default:
2575                 /* FIXME: not supported yet */
2576                 return -EINVAL;
2577         }
2578
2579         if (rdev->flags & RADEON_IS_IGP) {
2580                 rdev->asic->pm.get_memory_clock = NULL;
2581                 rdev->asic->pm.set_memory_clock = NULL;
2582         }
2583
2584         return 0;
2585 }
2586