2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
102 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
103 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
105 #define RADEON_IB_POOL_SIZE 16
106 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
107 #define RADEONFB_CONN_LIMIT 4
108 #define RADEON_BIOS_NUM_SCRATCH 8
110 /* max number of rings */
111 #define RADEON_NUM_RINGS 3
113 /* internal ring indices */
114 /* r1xx+ has gfx CP ring */
115 #define RADEON_RING_TYPE_GFX_INDEX 0
117 /* cayman has 2 compute CP rings */
118 #define CAYMAN_RING_TYPE_CP1_INDEX 1
119 #define CAYMAN_RING_TYPE_CP2_INDEX 2
121 /* hardcode those limit for now */
122 #define RADEON_VA_RESERVED_SIZE (8 << 20)
123 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
126 * Errata workarounds.
128 enum radeon_pll_errata {
129 CHIP_ERRATA_R300_CG = 0x00000001,
130 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
131 CHIP_ERRATA_PLL_DELAY = 0x00000004
135 struct radeon_device;
141 #define ATRM_BIOS_PAGE 4096
143 #if defined(CONFIG_VGA_SWITCHEROO)
144 bool radeon_atrm_supported(struct pci_dev *pdev);
145 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
147 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
152 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
156 bool radeon_get_bios(struct radeon_device *rdev);
160 * Mutex which allows recursive locking from the same process.
162 struct radeon_mutex {
164 struct task_struct *owner;
168 static inline void radeon_mutex_init(struct radeon_mutex *mutex)
170 mutex_init(&mutex->mutex);
175 static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
177 if (mutex_trylock(&mutex->mutex)) {
178 /* The mutex was unlocked before, so it's ours now */
179 mutex->owner = current;
180 } else if (mutex->owner != current) {
181 /* Another process locked the mutex, take it */
182 mutex_lock(&mutex->mutex);
183 mutex->owner = current;
185 /* Otherwise the mutex was already locked by this process */
190 static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
192 if (--mutex->level > 0)
196 mutex_unlock(&mutex->mutex);
203 struct radeon_dummy_page {
207 int radeon_dummy_page_init(struct radeon_device *rdev);
208 void radeon_dummy_page_fini(struct radeon_device *rdev);
214 struct radeon_clock {
215 struct radeon_pll p1pll;
216 struct radeon_pll p2pll;
217 struct radeon_pll dcpll;
218 struct radeon_pll spll;
219 struct radeon_pll mpll;
221 uint32_t default_mclk;
222 uint32_t default_sclk;
223 uint32_t default_dispclk;
225 uint32_t max_pixel_clock;
231 int radeon_pm_init(struct radeon_device *rdev);
232 void radeon_pm_fini(struct radeon_device *rdev);
233 void radeon_pm_compute_clocks(struct radeon_device *rdev);
234 void radeon_pm_suspend(struct radeon_device *rdev);
235 void radeon_pm_resume(struct radeon_device *rdev);
236 void radeon_combios_get_power_modes(struct radeon_device *rdev);
237 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
238 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
239 void rs690_pm_info(struct radeon_device *rdev);
240 extern int rv6xx_get_temp(struct radeon_device *rdev);
241 extern int rv770_get_temp(struct radeon_device *rdev);
242 extern int evergreen_get_temp(struct radeon_device *rdev);
243 extern int sumo_get_temp(struct radeon_device *rdev);
244 extern int si_get_temp(struct radeon_device *rdev);
245 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
246 unsigned *bankh, unsigned *mtaspect,
247 unsigned *tile_split);
252 struct radeon_fence_driver {
253 uint32_t scratch_reg;
255 volatile uint32_t *cpu_addr;
258 unsigned long last_jiffies;
259 unsigned long last_timeout;
260 wait_queue_head_t queue;
261 struct list_head created;
262 struct list_head emitted;
263 struct list_head signaled;
267 struct radeon_fence {
268 struct radeon_device *rdev;
270 struct list_head list;
271 /* protected by radeon_fence.lock */
277 struct radeon_semaphore *semaphore;
280 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
281 int radeon_fence_driver_init(struct radeon_device *rdev);
282 void radeon_fence_driver_fini(struct radeon_device *rdev);
283 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
284 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
285 void radeon_fence_process(struct radeon_device *rdev, int ring);
286 bool radeon_fence_signaled(struct radeon_fence *fence);
287 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
288 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
289 int radeon_fence_wait_last(struct radeon_device *rdev, int ring);
290 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
291 void radeon_fence_unref(struct radeon_fence **fence);
292 int radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
297 struct radeon_surface_reg {
298 struct radeon_bo *bo;
301 #define RADEON_GEM_MAX_SURFACES 8
307 struct ttm_bo_global_ref bo_global_ref;
308 struct drm_global_reference mem_global_ref;
309 struct ttm_bo_device bdev;
310 bool mem_global_referenced;
314 /* bo virtual address in a specific vm */
315 struct radeon_bo_va {
316 /* bo list is protected by bo being reserved */
317 struct list_head bo_list;
318 /* vm list is protected by vm mutex */
319 struct list_head vm_list;
320 /* constant after initialization */
321 struct radeon_vm *vm;
322 struct radeon_bo *bo;
330 /* Protected by gem.mutex */
331 struct list_head list;
332 /* Protected by tbo.reserved */
334 struct ttm_placement placement;
335 struct ttm_buffer_object tbo;
336 struct ttm_bo_kmap_obj kmap;
342 /* list of all virtual address to which this bo
346 /* Constant after initialization */
347 struct radeon_device *rdev;
348 struct drm_gem_object gem_base;
350 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
352 struct radeon_bo_list {
353 struct ttm_validate_buffer tv;
354 struct radeon_bo *bo;
361 /* sub-allocation manager, it has to be protected by another lock.
362 * By conception this is an helper for other part of the driver
363 * like the indirect buffer or semaphore, which both have their
366 * Principe is simple, we keep a list of sub allocation in offset
367 * order (first entry has offset == 0, last entry has the highest
370 * When allocating new object we first check if there is room at
371 * the end total_size - (last_object_offset + last_object_size) >=
372 * alloc_size. If so we allocate new object there.
374 * When there is not enough room at the end, we start waiting for
375 * each sub object until we reach object_offset+object_size >=
376 * alloc_size, this object then become the sub object we return.
378 * Alignment can't be bigger than page size.
380 * Hole are not considered for allocation to keep things simple.
381 * Assumption is that there won't be hole (all object on same
384 struct radeon_sa_manager {
385 struct radeon_bo *bo;
386 struct list_head sa_bo;
395 /* sub-allocation buffer */
396 struct radeon_sa_bo {
397 struct list_head list;
398 struct radeon_sa_manager *manager;
408 struct list_head objects;
411 int radeon_gem_init(struct radeon_device *rdev);
412 void radeon_gem_fini(struct radeon_device *rdev);
413 int radeon_gem_object_create(struct radeon_device *rdev, int size,
414 int alignment, int initial_domain,
415 bool discardable, bool kernel,
416 struct drm_gem_object **obj);
418 int radeon_mode_dumb_create(struct drm_file *file_priv,
419 struct drm_device *dev,
420 struct drm_mode_create_dumb *args);
421 int radeon_mode_dumb_mmap(struct drm_file *filp,
422 struct drm_device *dev,
423 uint32_t handle, uint64_t *offset_p);
424 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
425 struct drm_device *dev,
433 #define RADEON_SEMAPHORE_BO_SIZE 256
435 struct radeon_semaphore_driver {
440 struct radeon_semaphore_bo;
442 /* everything here is constant */
443 struct radeon_semaphore {
444 struct list_head list;
447 struct radeon_semaphore_bo *bo;
450 struct radeon_semaphore_bo {
451 struct list_head list;
452 struct radeon_ib *ib;
453 struct list_head free;
454 struct radeon_semaphore semaphores[RADEON_SEMAPHORE_BO_SIZE/8];
458 void radeon_semaphore_driver_fini(struct radeon_device *rdev);
459 int radeon_semaphore_create(struct radeon_device *rdev,
460 struct radeon_semaphore **semaphore);
461 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
462 struct radeon_semaphore *semaphore);
463 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
464 struct radeon_semaphore *semaphore);
465 void radeon_semaphore_free(struct radeon_device *rdev,
466 struct radeon_semaphore *semaphore);
469 * GART structures, functions & helpers
473 #define RADEON_GPU_PAGE_SIZE 4096
474 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
475 #define RADEON_GPU_PAGE_SHIFT 12
476 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
479 dma_addr_t table_addr;
480 struct radeon_bo *robj;
482 unsigned num_gpu_pages;
483 unsigned num_cpu_pages;
486 dma_addr_t *pages_addr;
490 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
491 void radeon_gart_table_ram_free(struct radeon_device *rdev);
492 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
493 void radeon_gart_table_vram_free(struct radeon_device *rdev);
494 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
495 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
496 int radeon_gart_init(struct radeon_device *rdev);
497 void radeon_gart_fini(struct radeon_device *rdev);
498 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
500 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
501 int pages, struct page **pagelist,
502 dma_addr_t *dma_addr);
503 void radeon_gart_restore(struct radeon_device *rdev);
507 * GPU MC structures, functions & helpers
510 resource_size_t aper_size;
511 resource_size_t aper_base;
512 resource_size_t agp_base;
513 /* for some chips with <= 32MB we need to lie
514 * about vram size near mc fb location */
516 u64 visible_vram_size;
526 bool igp_sideport_enabled;
530 bool radeon_combios_sideport_present(struct radeon_device *rdev);
531 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
534 * GPU scratch registers structures, functions & helpers
536 struct radeon_scratch {
543 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
544 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
551 struct radeon_unpin_work {
552 struct work_struct work;
553 struct radeon_device *rdev;
555 struct radeon_fence *fence;
556 struct drm_pending_vblank_event *event;
557 struct radeon_bo *old_rbo;
561 struct r500_irq_stat_regs {
565 struct r600_irq_stat_regs {
573 struct evergreen_irq_stat_regs {
588 union radeon_irq_stat_regs {
589 struct r500_irq_stat_regs r500;
590 struct r600_irq_stat_regs r600;
591 struct evergreen_irq_stat_regs evergreen;
594 #define RADEON_MAX_HPD_PINS 6
595 #define RADEON_MAX_CRTCS 6
596 #define RADEON_MAX_HDMI_BLOCKS 2
600 bool sw_int[RADEON_NUM_RINGS];
601 bool crtc_vblank_int[RADEON_MAX_CRTCS];
602 bool pflip[RADEON_MAX_CRTCS];
603 wait_queue_head_t vblank_queue;
604 bool hpd[RADEON_MAX_HPD_PINS];
607 wait_queue_head_t idle_queue;
608 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
610 int sw_refcount[RADEON_NUM_RINGS];
611 union radeon_irq_stat_regs stat_regs;
612 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
613 int pflip_refcount[RADEON_MAX_CRTCS];
616 int radeon_irq_kms_init(struct radeon_device *rdev);
617 void radeon_irq_kms_fini(struct radeon_device *rdev);
618 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
619 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
620 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
621 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
628 struct radeon_sa_bo sa_bo;
633 struct radeon_fence *fence;
640 * mutex protects scheduled_ibs, ready, alloc_bm
642 struct radeon_ib_pool {
643 struct radeon_mutex mutex;
644 struct radeon_sa_manager sa_manager;
645 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
651 struct radeon_bo *ring_obj;
652 volatile uint32_t *ring;
660 unsigned ring_free_dw;
676 struct list_head list;
682 struct radeon_sa_bo sa_bo;
684 /* last fence for cs using this vm */
685 struct radeon_fence *fence;
688 struct radeon_vm_funcs {
689 int (*init)(struct radeon_device *rdev);
690 void (*fini)(struct radeon_device *rdev);
691 /* cs mutex must be lock for schedule_ib */
692 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
693 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
694 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
695 uint32_t (*page_flags)(struct radeon_device *rdev,
696 struct radeon_vm *vm,
698 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
699 unsigned pfn, uint64_t addr, uint32_t flags);
702 struct radeon_vm_manager {
703 struct list_head lru_vm;
705 struct radeon_sa_manager sa_manager;
707 /* fields constant after init */
708 const struct radeon_vm_funcs *funcs;
709 /* number of VMIDs */
711 /* vram base address for page table entry */
712 u64 vram_base_offset;
718 * file private structure
720 struct radeon_fpriv {
728 struct radeon_bo *ring_obj;
729 volatile uint32_t *ring;
741 struct r600_blit_cp_primitives {
742 void (*set_render_target)(struct radeon_device *rdev, int format,
743 int w, int h, u64 gpu_addr);
744 void (*cp_set_surface_sync)(struct radeon_device *rdev,
745 u32 sync_type, u32 size,
747 void (*set_shaders)(struct radeon_device *rdev);
748 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
749 void (*set_tex_resource)(struct radeon_device *rdev,
750 int format, int w, int h, int pitch,
751 u64 gpu_addr, u32 size);
752 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
754 void (*draw_auto)(struct radeon_device *rdev);
755 void (*set_default_state)(struct radeon_device *rdev);
760 struct radeon_bo *shader_obj;
761 struct r600_blit_cp_primitives primitives;
763 int ring_size_common;
764 int ring_size_per_loop;
766 u32 vs_offset, ps_offset;
769 u32 vb_used, vb_total;
770 struct radeon_ib *vb_ib;
773 void r600_blit_suspend(struct radeon_device *rdev);
779 /* for power gating */
780 struct radeon_bo *save_restore_obj;
781 uint64_t save_restore_gpu_addr;
782 /* for clear state */
783 struct radeon_bo *clear_state_obj;
784 uint64_t clear_state_gpu_addr;
787 int radeon_ib_get(struct radeon_device *rdev, int ring,
788 struct radeon_ib **ib, unsigned size);
789 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
790 bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib);
791 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
792 int radeon_ib_pool_init(struct radeon_device *rdev);
793 void radeon_ib_pool_fini(struct radeon_device *rdev);
794 int radeon_ib_pool_start(struct radeon_device *rdev);
795 int radeon_ib_pool_suspend(struct radeon_device *rdev);
796 /* Ring access between begin & end cannot sleep */
797 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
798 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
799 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
800 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
801 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
802 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
803 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
804 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
805 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
806 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
807 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
808 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
814 struct radeon_cs_reloc {
815 struct drm_gem_object *gobj;
816 struct radeon_bo *robj;
817 struct radeon_bo_list lobj;
822 struct radeon_cs_chunk {
828 void __user *user_ptr;
829 int last_copied_page;
833 struct radeon_cs_parser {
835 struct radeon_device *rdev;
836 struct drm_file *filp;
839 struct radeon_cs_chunk *chunks;
840 uint64_t *chunks_array;
845 struct radeon_cs_reloc *relocs;
846 struct radeon_cs_reloc **relocs_ptr;
847 struct list_head validated;
848 /* indices of various chunks */
850 int chunk_relocs_idx;
852 int chunk_const_ib_idx;
853 struct radeon_ib *ib;
854 struct radeon_ib *const_ib;
863 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
864 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
865 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
867 struct radeon_cs_packet {
876 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
877 struct radeon_cs_packet *pkt,
878 unsigned idx, unsigned reg);
879 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
880 struct radeon_cs_packet *pkt);
886 int radeon_agp_init(struct radeon_device *rdev);
887 void radeon_agp_resume(struct radeon_device *rdev);
888 void radeon_agp_suspend(struct radeon_device *rdev);
889 void radeon_agp_fini(struct radeon_device *rdev);
896 struct radeon_bo *wb_obj;
897 volatile uint32_t *wb;
903 #define RADEON_WB_SCRATCH_OFFSET 0
904 #define RADEON_WB_CP_RPTR_OFFSET 1024
905 #define RADEON_WB_CP1_RPTR_OFFSET 1280
906 #define RADEON_WB_CP2_RPTR_OFFSET 1536
907 #define R600_WB_IH_WPTR_OFFSET 2048
908 #define R600_WB_EVENT_OFFSET 3072
911 * struct radeon_pm - power management datas
912 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
913 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
914 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
915 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
916 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
917 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
918 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
919 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
920 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
921 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
922 * @needed_bandwidth: current bandwidth needs
924 * It keeps track of various data needed to take powermanagement decision.
925 * Bandwidth need is used to determine minimun clock of the GPU and memory.
926 * Equation between gpu/memory clock and available bandwidth is hw dependent
927 * (type of memory, bus size, efficiency, ...)
930 enum radeon_pm_method {
935 enum radeon_dynpm_state {
936 DYNPM_STATE_DISABLED,
940 DYNPM_STATE_SUSPENDED,
942 enum radeon_dynpm_action {
944 DYNPM_ACTION_MINIMUM,
945 DYNPM_ACTION_DOWNCLOCK,
946 DYNPM_ACTION_UPCLOCK,
950 enum radeon_voltage_type {
957 enum radeon_pm_state_type {
958 POWER_STATE_TYPE_DEFAULT,
959 POWER_STATE_TYPE_POWERSAVE,
960 POWER_STATE_TYPE_BATTERY,
961 POWER_STATE_TYPE_BALANCED,
962 POWER_STATE_TYPE_PERFORMANCE,
965 enum radeon_pm_profile_type {
973 #define PM_PROFILE_DEFAULT_IDX 0
974 #define PM_PROFILE_LOW_SH_IDX 1
975 #define PM_PROFILE_MID_SH_IDX 2
976 #define PM_PROFILE_HIGH_SH_IDX 3
977 #define PM_PROFILE_LOW_MH_IDX 4
978 #define PM_PROFILE_MID_MH_IDX 5
979 #define PM_PROFILE_HIGH_MH_IDX 6
980 #define PM_PROFILE_MAX 7
982 struct radeon_pm_profile {
989 enum radeon_int_thermal_type {
993 THERMAL_TYPE_EVERGREEN,
999 struct radeon_voltage {
1000 enum radeon_voltage_type type;
1002 struct radeon_gpio_rec gpio;
1003 u32 delay; /* delay in usec from voltage drop to sclk change */
1004 bool active_high; /* voltage drop is active when bit is high */
1006 u8 vddc_id; /* index into vddc voltage table */
1007 u8 vddci_id; /* index into vddci voltage table */
1011 /* evergreen+ vddci */
1015 /* clock mode flags */
1016 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1018 struct radeon_pm_clock_info {
1024 struct radeon_voltage voltage;
1025 /* standardized clock flags */
1030 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1032 struct radeon_power_state {
1033 enum radeon_pm_state_type type;
1034 struct radeon_pm_clock_info *clock_info;
1035 /* number of valid clock modes in this power state */
1036 int num_clock_modes;
1037 struct radeon_pm_clock_info *default_clock_mode;
1038 /* standardized state flags */
1040 u32 misc; /* vbios specific flags */
1041 u32 misc2; /* vbios specific flags */
1042 int pcie_lanes; /* pcie lanes */
1046 * Some modes are overclocked by very low value, accept them
1048 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1053 int active_crtc_count;
1057 fixed20_12 max_bandwidth;
1058 fixed20_12 igp_sideport_mclk;
1059 fixed20_12 igp_system_mclk;
1060 fixed20_12 igp_ht_link_clk;
1061 fixed20_12 igp_ht_link_width;
1062 fixed20_12 k8_bandwidth;
1063 fixed20_12 sideport_bandwidth;
1064 fixed20_12 ht_bandwidth;
1065 fixed20_12 core_bandwidth;
1068 fixed20_12 needed_bandwidth;
1069 struct radeon_power_state *power_state;
1070 /* number of valid power states */
1071 int num_power_states;
1072 int current_power_state_index;
1073 int current_clock_mode_index;
1074 int requested_power_state_index;
1075 int requested_clock_mode_index;
1076 int default_power_state_index;
1085 struct radeon_i2c_chan *i2c_bus;
1086 /* selected pm method */
1087 enum radeon_pm_method pm_method;
1088 /* dynpm power management */
1089 struct delayed_work dynpm_idle_work;
1090 enum radeon_dynpm_state dynpm_state;
1091 enum radeon_dynpm_action dynpm_planned_action;
1092 unsigned long dynpm_action_timeout;
1093 bool dynpm_can_upclock;
1094 bool dynpm_can_downclock;
1095 /* profile-based power management */
1096 enum radeon_pm_profile_type profile;
1098 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1099 /* internal thermal controller on rv6xx+ */
1100 enum radeon_int_thermal_type int_thermal_type;
1101 struct device *int_hwmon_dev;
1104 int radeon_pm_get_type_index(struct radeon_device *rdev,
1105 enum radeon_pm_state_type ps_type,
1111 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1117 void radeon_test_moves(struct radeon_device *rdev);
1118 void radeon_test_ring_sync(struct radeon_device *rdev,
1119 struct radeon_ring *cpA,
1120 struct radeon_ring *cpB);
1121 void radeon_test_syncing(struct radeon_device *rdev);
1127 struct radeon_debugfs {
1128 struct drm_info_list *files;
1132 int radeon_debugfs_add_files(struct radeon_device *rdev,
1133 struct drm_info_list *files,
1135 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1139 * ASIC specific functions.
1141 struct radeon_asic {
1142 int (*init)(struct radeon_device *rdev);
1143 void (*fini)(struct radeon_device *rdev);
1144 int (*resume)(struct radeon_device *rdev);
1145 int (*suspend)(struct radeon_device *rdev);
1146 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1147 bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1148 int (*asic_reset)(struct radeon_device *rdev);
1149 /* ioctl hw specific callback. Some hw might want to perform special
1150 * operation on specific ioctl. For instance on wait idle some hw
1151 * might want to perform and HDP flush through MMIO as it seems that
1152 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1155 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1156 /* check if 3D engine is idle */
1157 bool (*gui_idle)(struct radeon_device *rdev);
1158 /* wait for mc_idle */
1159 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1162 void (*tlb_flush)(struct radeon_device *rdev);
1163 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1165 /* ring specific callbacks */
1167 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1168 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1169 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1170 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1171 struct radeon_semaphore *semaphore, bool emit_wait);
1172 int (*cs_parse)(struct radeon_cs_parser *p);
1173 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1174 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1175 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1176 } ring[RADEON_NUM_RINGS];
1179 int (*set)(struct radeon_device *rdev);
1180 int (*process)(struct radeon_device *rdev);
1184 /* display watermarks */
1185 void (*bandwidth_update)(struct radeon_device *rdev);
1186 /* get frame count */
1187 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1188 /* wait for vblank */
1189 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1191 /* copy functions for bo handling */
1193 int (*blit)(struct radeon_device *rdev,
1194 uint64_t src_offset,
1195 uint64_t dst_offset,
1196 unsigned num_gpu_pages,
1197 struct radeon_fence *fence);
1198 u32 blit_ring_index;
1199 int (*dma)(struct radeon_device *rdev,
1200 uint64_t src_offset,
1201 uint64_t dst_offset,
1202 unsigned num_gpu_pages,
1203 struct radeon_fence *fence);
1205 /* method used for bo copy */
1206 int (*copy)(struct radeon_device *rdev,
1207 uint64_t src_offset,
1208 uint64_t dst_offset,
1209 unsigned num_gpu_pages,
1210 struct radeon_fence *fence);
1211 /* ring used for bo copies */
1212 u32 copy_ring_index;
1216 int (*set_reg)(struct radeon_device *rdev, int reg,
1217 uint32_t tiling_flags, uint32_t pitch,
1218 uint32_t offset, uint32_t obj_size);
1219 void (*clear_reg)(struct radeon_device *rdev, int reg);
1221 /* hotplug detect */
1223 void (*init)(struct radeon_device *rdev);
1224 void (*fini)(struct radeon_device *rdev);
1225 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1226 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1228 /* power management */
1230 void (*misc)(struct radeon_device *rdev);
1231 void (*prepare)(struct radeon_device *rdev);
1232 void (*finish)(struct radeon_device *rdev);
1233 void (*init_profile)(struct radeon_device *rdev);
1234 void (*get_dynpm_state)(struct radeon_device *rdev);
1235 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1236 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1237 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1238 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1239 int (*get_pcie_lanes)(struct radeon_device *rdev);
1240 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1241 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1245 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1246 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1247 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1254 struct r100_gpu_lockup {
1255 unsigned long last_jiffies;
1260 const unsigned *reg_safe_bm;
1261 unsigned reg_safe_bm_size;
1263 struct r100_gpu_lockup lockup;
1267 const unsigned *reg_safe_bm;
1268 unsigned reg_safe_bm_size;
1271 struct r100_gpu_lockup lockup;
1276 unsigned max_tile_pipes;
1278 unsigned max_backends;
1280 unsigned max_threads;
1281 unsigned max_stack_entries;
1282 unsigned max_hw_contexts;
1283 unsigned max_gs_threads;
1284 unsigned sx_max_export_size;
1285 unsigned sx_max_export_pos_size;
1286 unsigned sx_max_export_smx_size;
1287 unsigned sq_num_cf_insts;
1288 unsigned tiling_nbanks;
1289 unsigned tiling_npipes;
1290 unsigned tiling_group_size;
1291 unsigned tile_config;
1292 unsigned backend_map;
1293 struct r100_gpu_lockup lockup;
1298 unsigned max_tile_pipes;
1300 unsigned max_backends;
1302 unsigned max_threads;
1303 unsigned max_stack_entries;
1304 unsigned max_hw_contexts;
1305 unsigned max_gs_threads;
1306 unsigned sx_max_export_size;
1307 unsigned sx_max_export_pos_size;
1308 unsigned sx_max_export_smx_size;
1309 unsigned sq_num_cf_insts;
1310 unsigned sx_num_of_sets;
1311 unsigned sc_prim_fifo_size;
1312 unsigned sc_hiz_tile_fifo_size;
1313 unsigned sc_earlyz_tile_fifo_fize;
1314 unsigned tiling_nbanks;
1315 unsigned tiling_npipes;
1316 unsigned tiling_group_size;
1317 unsigned tile_config;
1318 unsigned backend_map;
1319 struct r100_gpu_lockup lockup;
1322 struct evergreen_asic {
1325 unsigned max_tile_pipes;
1327 unsigned max_backends;
1329 unsigned max_threads;
1330 unsigned max_stack_entries;
1331 unsigned max_hw_contexts;
1332 unsigned max_gs_threads;
1333 unsigned sx_max_export_size;
1334 unsigned sx_max_export_pos_size;
1335 unsigned sx_max_export_smx_size;
1336 unsigned sq_num_cf_insts;
1337 unsigned sx_num_of_sets;
1338 unsigned sc_prim_fifo_size;
1339 unsigned sc_hiz_tile_fifo_size;
1340 unsigned sc_earlyz_tile_fifo_size;
1341 unsigned tiling_nbanks;
1342 unsigned tiling_npipes;
1343 unsigned tiling_group_size;
1344 unsigned tile_config;
1345 unsigned backend_map;
1346 struct r100_gpu_lockup lockup;
1349 struct cayman_asic {
1350 unsigned max_shader_engines;
1351 unsigned max_pipes_per_simd;
1352 unsigned max_tile_pipes;
1353 unsigned max_simds_per_se;
1354 unsigned max_backends_per_se;
1355 unsigned max_texture_channel_caches;
1357 unsigned max_threads;
1358 unsigned max_gs_threads;
1359 unsigned max_stack_entries;
1360 unsigned sx_num_of_sets;
1361 unsigned sx_max_export_size;
1362 unsigned sx_max_export_pos_size;
1363 unsigned sx_max_export_smx_size;
1364 unsigned max_hw_contexts;
1365 unsigned sq_num_cf_insts;
1366 unsigned sc_prim_fifo_size;
1367 unsigned sc_hiz_tile_fifo_size;
1368 unsigned sc_earlyz_tile_fifo_size;
1370 unsigned num_shader_engines;
1371 unsigned num_shader_pipes_per_simd;
1372 unsigned num_tile_pipes;
1373 unsigned num_simds_per_se;
1374 unsigned num_backends_per_se;
1375 unsigned backend_disable_mask_per_asic;
1376 unsigned backend_map;
1377 unsigned num_texture_channel_caches;
1378 unsigned mem_max_burst_length_bytes;
1379 unsigned mem_row_size_in_kb;
1380 unsigned shader_engine_tile_size;
1382 unsigned multi_gpu_tile_size;
1384 unsigned tile_config;
1385 struct r100_gpu_lockup lockup;
1389 unsigned max_shader_engines;
1390 unsigned max_pipes_per_simd;
1391 unsigned max_tile_pipes;
1392 unsigned max_simds_per_se;
1393 unsigned max_backends_per_se;
1394 unsigned max_texture_channel_caches;
1396 unsigned max_gs_threads;
1397 unsigned max_hw_contexts;
1398 unsigned sc_prim_fifo_size_frontend;
1399 unsigned sc_prim_fifo_size_backend;
1400 unsigned sc_hiz_tile_fifo_size;
1401 unsigned sc_earlyz_tile_fifo_size;
1403 unsigned num_shader_engines;
1404 unsigned num_tile_pipes;
1405 unsigned num_backends_per_se;
1406 unsigned backend_disable_mask_per_asic;
1407 unsigned backend_map;
1408 unsigned num_texture_channel_caches;
1409 unsigned mem_max_burst_length_bytes;
1410 unsigned mem_row_size_in_kb;
1411 unsigned shader_engine_tile_size;
1413 unsigned multi_gpu_tile_size;
1415 unsigned tile_config;
1416 struct r100_gpu_lockup lockup;
1419 union radeon_asic_config {
1420 struct r300_asic r300;
1421 struct r100_asic r100;
1422 struct r600_asic r600;
1423 struct rv770_asic rv770;
1424 struct evergreen_asic evergreen;
1425 struct cayman_asic cayman;
1430 * asic initizalization from radeon_asic.c
1432 void radeon_agp_disable(struct radeon_device *rdev);
1433 int radeon_asic_init(struct radeon_device *rdev);
1439 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1440 struct drm_file *filp);
1441 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1442 struct drm_file *filp);
1443 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1444 struct drm_file *file_priv);
1445 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1446 struct drm_file *file_priv);
1447 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1448 struct drm_file *file_priv);
1449 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1450 struct drm_file *file_priv);
1451 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1452 struct drm_file *filp);
1453 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1454 struct drm_file *filp);
1455 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1456 struct drm_file *filp);
1457 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1458 struct drm_file *filp);
1459 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1460 struct drm_file *filp);
1461 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1462 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1463 struct drm_file *filp);
1464 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1465 struct drm_file *filp);
1467 /* VRAM scratch page for HDP bug, default vram page */
1468 struct r600_vram_scratch {
1469 struct radeon_bo *robj;
1470 volatile uint32_t *ptr;
1476 * Core structure, functions and helpers.
1478 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1479 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1481 struct radeon_device {
1483 struct drm_device *ddev;
1484 struct pci_dev *pdev;
1486 union radeon_asic_config config;
1487 enum radeon_family family;
1488 unsigned long flags;
1490 enum radeon_pll_errata pll_errata;
1497 uint16_t bios_header_start;
1498 struct radeon_bo *stollen_vga_memory;
1500 resource_size_t rmmio_base;
1501 resource_size_t rmmio_size;
1502 void __iomem *rmmio;
1503 radeon_rreg_t mc_rreg;
1504 radeon_wreg_t mc_wreg;
1505 radeon_rreg_t pll_rreg;
1506 radeon_wreg_t pll_wreg;
1507 uint32_t pcie_reg_mask;
1508 radeon_rreg_t pciep_rreg;
1509 radeon_wreg_t pciep_wreg;
1511 void __iomem *rio_mem;
1512 resource_size_t rio_mem_size;
1513 struct radeon_clock clock;
1514 struct radeon_mc mc;
1515 struct radeon_gart gart;
1516 struct radeon_mode_info mode_info;
1517 struct radeon_scratch scratch;
1518 struct radeon_mman mman;
1519 rwlock_t fence_lock;
1520 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1521 struct radeon_semaphore_driver semaphore_drv;
1522 struct radeon_ring ring[RADEON_NUM_RINGS];
1523 struct radeon_ib_pool ib_pool;
1524 struct radeon_irq irq;
1525 struct radeon_asic *asic;
1526 struct radeon_gem gem;
1527 struct radeon_pm pm;
1528 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1529 struct radeon_mutex cs_mutex;
1530 struct radeon_wb wb;
1531 struct radeon_dummy_page dummy_page;
1537 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1538 const struct firmware *me_fw; /* all family ME firmware */
1539 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1540 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1541 const struct firmware *mc_fw; /* NI MC firmware */
1542 const struct firmware *ce_fw; /* SI CE firmware */
1543 struct r600_blit r600_blit;
1544 struct r600_vram_scratch vram_scratch;
1545 int msi_enabled; /* msi enabled */
1546 struct r600_ih ih; /* r6/700 interrupt ring */
1548 struct work_struct hotplug_work;
1549 int num_crtc; /* number of crtcs */
1550 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1551 struct mutex vram_mutex;
1555 struct timer_list audio_timer;
1558 int audio_bits_per_sample;
1559 uint8_t audio_status_bits;
1560 uint8_t audio_category_code;
1562 struct notifier_block acpi_nb;
1563 /* only one userspace can use Hyperz features or CMASK at a time */
1564 struct drm_file *hyperz_filp;
1565 struct drm_file *cmask_filp;
1567 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1569 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1570 unsigned debugfs_count;
1571 /* virtual memory */
1572 struct radeon_vm_manager vm_manager;
1575 int radeon_device_init(struct radeon_device *rdev,
1576 struct drm_device *ddev,
1577 struct pci_dev *pdev,
1579 void radeon_device_fini(struct radeon_device *rdev);
1580 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1582 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1583 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1584 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1585 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1590 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1593 * Registers read & write functions.
1595 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1596 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1597 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1598 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1599 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1600 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1601 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1602 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1603 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1604 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1605 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1606 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1607 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1608 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1609 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1610 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1611 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1612 #define WREG32_P(reg, val, mask) \
1614 uint32_t tmp_ = RREG32(reg); \
1616 tmp_ |= ((val) & ~(mask)); \
1617 WREG32(reg, tmp_); \
1619 #define WREG32_PLL_P(reg, val, mask) \
1621 uint32_t tmp_ = RREG32_PLL(reg); \
1623 tmp_ |= ((val) & ~(mask)); \
1624 WREG32_PLL(reg, tmp_); \
1626 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1627 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1628 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1631 * Indirect registers accessor
1633 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1637 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1638 r = RREG32(RADEON_PCIE_DATA);
1642 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1644 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1645 WREG32(RADEON_PCIE_DATA, (v));
1648 void r100_pll_errata_after_index(struct radeon_device *rdev);
1654 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1655 (rdev->pdev->device == 0x5969))
1656 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1657 (rdev->family == CHIP_RV200) || \
1658 (rdev->family == CHIP_RS100) || \
1659 (rdev->family == CHIP_RS200) || \
1660 (rdev->family == CHIP_RV250) || \
1661 (rdev->family == CHIP_RV280) || \
1662 (rdev->family == CHIP_RS300))
1663 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1664 (rdev->family == CHIP_RV350) || \
1665 (rdev->family == CHIP_R350) || \
1666 (rdev->family == CHIP_RV380) || \
1667 (rdev->family == CHIP_R420) || \
1668 (rdev->family == CHIP_R423) || \
1669 (rdev->family == CHIP_RV410) || \
1670 (rdev->family == CHIP_RS400) || \
1671 (rdev->family == CHIP_RS480))
1672 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1673 (rdev->ddev->pdev->device == 0x9443) || \
1674 (rdev->ddev->pdev->device == 0x944B) || \
1675 (rdev->ddev->pdev->device == 0x9506) || \
1676 (rdev->ddev->pdev->device == 0x9509) || \
1677 (rdev->ddev->pdev->device == 0x950F) || \
1678 (rdev->ddev->pdev->device == 0x689C) || \
1679 (rdev->ddev->pdev->device == 0x689D))
1680 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1681 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1682 (rdev->family == CHIP_RS690) || \
1683 (rdev->family == CHIP_RS740) || \
1684 (rdev->family >= CHIP_R600))
1685 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1686 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1687 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1688 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1689 (rdev->flags & RADEON_IS_IGP))
1690 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1691 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1692 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1693 (rdev->flags & RADEON_IS_IGP))
1698 #define RBIOS8(i) (rdev->bios[i])
1699 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1700 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1702 int radeon_combios_init(struct radeon_device *rdev);
1703 void radeon_combios_fini(struct radeon_device *rdev);
1704 int radeon_atombios_init(struct radeon_device *rdev);
1705 void radeon_atombios_fini(struct radeon_device *rdev);
1711 #if DRM_DEBUG_CODE == 0
1712 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1714 ring->ring[ring->wptr++] = v;
1715 ring->wptr &= ring->ptr_mask;
1717 ring->ring_free_dw--;
1720 /* With debugging this is just too big to inline */
1721 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1727 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1728 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1729 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1730 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1731 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1732 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1733 #define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
1734 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1735 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1736 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1737 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1738 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1739 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1740 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1741 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1742 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1743 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1744 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1745 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1746 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1747 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1748 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1749 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1750 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1751 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1752 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1753 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1754 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1755 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1756 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1757 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1758 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1759 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1760 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1761 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1762 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1763 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1764 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1765 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1766 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1767 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1768 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1769 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1770 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1771 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1772 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1773 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1774 #define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1775 #define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1776 #define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1777 #define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1779 /* Common functions */
1781 extern int radeon_gpu_reset(struct radeon_device *rdev);
1782 extern void radeon_agp_disable(struct radeon_device *rdev);
1783 extern int radeon_modeset_init(struct radeon_device *rdev);
1784 extern void radeon_modeset_fini(struct radeon_device *rdev);
1785 extern bool radeon_card_posted(struct radeon_device *rdev);
1786 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1787 extern void radeon_update_display_priority(struct radeon_device *rdev);
1788 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1789 extern void radeon_scratch_init(struct radeon_device *rdev);
1790 extern void radeon_wb_fini(struct radeon_device *rdev);
1791 extern int radeon_wb_init(struct radeon_device *rdev);
1792 extern void radeon_wb_disable(struct radeon_device *rdev);
1793 extern void radeon_surface_init(struct radeon_device *rdev);
1794 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1795 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1796 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1797 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1798 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1799 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1800 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1801 extern int radeon_resume_kms(struct drm_device *dev);
1802 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1803 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1808 int radeon_vm_manager_init(struct radeon_device *rdev);
1809 void radeon_vm_manager_fini(struct radeon_device *rdev);
1810 int radeon_vm_manager_start(struct radeon_device *rdev);
1811 int radeon_vm_manager_suspend(struct radeon_device *rdev);
1812 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1813 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1814 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1815 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1816 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1817 struct radeon_vm *vm,
1818 struct radeon_bo *bo,
1819 struct ttm_mem_reg *mem);
1820 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1821 struct radeon_bo *bo);
1822 int radeon_vm_bo_add(struct radeon_device *rdev,
1823 struct radeon_vm *vm,
1824 struct radeon_bo *bo,
1827 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1828 struct radeon_vm *vm,
1829 struct radeon_bo *bo);
1833 * R600 vram scratch functions
1835 int r600_vram_scratch_init(struct radeon_device *rdev);
1836 void r600_vram_scratch_fini(struct radeon_device *rdev);
1839 * r600 cs checking helper
1841 unsigned r600_mip_minify(unsigned size, unsigned level);
1842 bool r600_fmt_is_valid_color(u32 format);
1843 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1844 int r600_fmt_get_blocksize(u32 format);
1845 int r600_fmt_get_nblocksx(u32 format, u32 w);
1846 int r600_fmt_get_nblocksy(u32 format, u32 h);
1849 * r600 functions used by radeon_encoder.c
1851 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1852 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1853 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1855 extern int ni_init_microcode(struct radeon_device *rdev);
1856 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1859 #if defined(CONFIG_ACPI)
1860 extern int radeon_acpi_init(struct radeon_device *rdev);
1862 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1865 #include "radeon_object.h"