2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
103 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
108 /* RADEON_IB_POOL_SIZE must be a power of 2 */
109 #define RADEON_IB_POOL_SIZE 16
110 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
111 #define RADEONFB_CONN_LIMIT 4
112 #define RADEON_BIOS_NUM_SCRATCH 8
114 /* max number of rings */
115 #define RADEON_NUM_RINGS 6
117 /* fence seq are set to this number when signaled */
118 #define RADEON_FENCE_SIGNALED_SEQ 0LL
120 /* internal ring indices */
121 /* r1xx+ has gfx CP ring */
122 #define RADEON_RING_TYPE_GFX_INDEX 0
124 /* cayman has 2 compute CP rings */
125 #define CAYMAN_RING_TYPE_CP1_INDEX 1
126 #define CAYMAN_RING_TYPE_CP2_INDEX 2
128 /* R600+ has an async dma ring */
129 #define R600_RING_TYPE_DMA_INDEX 3
130 /* cayman add a second async dma ring */
131 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
134 #define R600_RING_TYPE_UVD_INDEX 5
136 /* hardcode those limit for now */
137 #define RADEON_VA_IB_OFFSET (1 << 20)
138 #define RADEON_VA_RESERVED_SIZE (8 << 20)
139 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
142 #define RADEON_RESET_GFX (1 << 0)
143 #define RADEON_RESET_COMPUTE (1 << 1)
144 #define RADEON_RESET_DMA (1 << 2)
145 #define RADEON_RESET_CP (1 << 3)
146 #define RADEON_RESET_GRBM (1 << 4)
147 #define RADEON_RESET_DMA1 (1 << 5)
148 #define RADEON_RESET_RLC (1 << 6)
149 #define RADEON_RESET_SEM (1 << 7)
150 #define RADEON_RESET_IH (1 << 8)
151 #define RADEON_RESET_VMC (1 << 9)
152 #define RADEON_RESET_MC (1 << 10)
153 #define RADEON_RESET_DISPLAY (1 << 11)
156 #define RADEON_CG_BLOCK_GFX (1 << 0)
157 #define RADEON_CG_BLOCK_MC (1 << 1)
158 #define RADEON_CG_BLOCK_SDMA (1 << 2)
159 #define RADEON_CG_BLOCK_UVD (1 << 3)
160 #define RADEON_CG_BLOCK_VCE (1 << 4)
161 #define RADEON_CG_BLOCK_HDP (1 << 5)
163 /* max cursor sizes (in pixels) */
164 #define CURSOR_WIDTH 64
165 #define CURSOR_HEIGHT 64
167 #define CIK_CURSOR_WIDTH 128
168 #define CIK_CURSOR_HEIGHT 128
171 * Errata workarounds.
173 enum radeon_pll_errata {
174 CHIP_ERRATA_R300_CG = 0x00000001,
175 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
176 CHIP_ERRATA_PLL_DELAY = 0x00000004
180 struct radeon_device;
186 bool radeon_get_bios(struct radeon_device *rdev);
191 struct radeon_dummy_page {
195 int radeon_dummy_page_init(struct radeon_device *rdev);
196 void radeon_dummy_page_fini(struct radeon_device *rdev);
202 struct radeon_clock {
203 struct radeon_pll p1pll;
204 struct radeon_pll p2pll;
205 struct radeon_pll dcpll;
206 struct radeon_pll spll;
207 struct radeon_pll mpll;
209 uint32_t default_mclk;
210 uint32_t default_sclk;
211 uint32_t default_dispclk;
212 uint32_t current_dispclk;
214 uint32_t max_pixel_clock;
220 int radeon_pm_init(struct radeon_device *rdev);
221 void radeon_pm_fini(struct radeon_device *rdev);
222 void radeon_pm_compute_clocks(struct radeon_device *rdev);
223 void radeon_pm_suspend(struct radeon_device *rdev);
224 void radeon_pm_resume(struct radeon_device *rdev);
225 void radeon_combios_get_power_modes(struct radeon_device *rdev);
226 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
227 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
231 struct atom_clock_dividers *dividers);
232 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
235 struct atom_mpll_param *mpll_param);
236 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
237 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
238 u16 voltage_level, u8 voltage_type,
239 u32 *gpio_value, u32 *gpio_mask);
240 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
241 u32 eng_clock, u32 mem_clock);
242 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
243 u8 voltage_type, u16 *voltage_step);
244 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
245 u16 voltage_id, u16 *voltage);
246 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
249 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
253 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
254 u8 voltage_type, u16 *min_voltage);
255 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
256 u8 voltage_type, u16 *max_voltage);
257 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
258 u8 voltage_type, u8 voltage_mode,
259 struct atom_voltage_table *voltage_table);
260 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
261 u8 voltage_type, u8 voltage_mode);
262 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
264 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
266 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
268 struct atom_mc_reg_table *reg_table);
269 int radeon_atom_get_memory_info(struct radeon_device *rdev,
270 u8 module_index, struct atom_memory_info *mem_info);
271 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
272 bool gddr5, u8 module_index,
273 struct atom_memory_clock_range_table *mclk_range_table);
274 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
275 u16 voltage_id, u16 *voltage);
276 void rs690_pm_info(struct radeon_device *rdev);
277 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
278 unsigned *bankh, unsigned *mtaspect,
279 unsigned *tile_split);
284 struct radeon_fence_driver {
285 uint32_t scratch_reg;
287 volatile uint32_t *cpu_addr;
288 /* sync_seq is protected by ring emission lock */
289 uint64_t sync_seq[RADEON_NUM_RINGS];
291 unsigned long last_activity;
295 struct radeon_fence {
296 struct radeon_device *rdev;
298 /* protected by radeon_fence.lock */
304 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
305 int radeon_fence_driver_init(struct radeon_device *rdev);
306 void radeon_fence_driver_fini(struct radeon_device *rdev);
307 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
308 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
309 void radeon_fence_process(struct radeon_device *rdev, int ring);
310 bool radeon_fence_signaled(struct radeon_fence *fence);
311 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
312 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
313 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
314 int radeon_fence_wait_any(struct radeon_device *rdev,
315 struct radeon_fence **fences,
317 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
318 void radeon_fence_unref(struct radeon_fence **fence);
319 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
320 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
321 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
322 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
323 struct radeon_fence *b)
333 BUG_ON(a->ring != b->ring);
335 if (a->seq > b->seq) {
342 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
343 struct radeon_fence *b)
353 BUG_ON(a->ring != b->ring);
355 return a->seq < b->seq;
361 struct radeon_surface_reg {
362 struct radeon_bo *bo;
365 #define RADEON_GEM_MAX_SURFACES 8
371 struct ttm_bo_global_ref bo_global_ref;
372 struct drm_global_reference mem_global_ref;
373 struct ttm_bo_device bdev;
374 bool mem_global_referenced;
378 /* bo virtual address in a specific vm */
379 struct radeon_bo_va {
380 /* protected by bo being reserved */
381 struct list_head bo_list;
388 /* protected by vm mutex */
389 struct list_head vm_list;
391 /* constant after initialization */
392 struct radeon_vm *vm;
393 struct radeon_bo *bo;
397 /* Protected by gem.mutex */
398 struct list_head list;
399 /* Protected by tbo.reserved */
401 struct ttm_placement placement;
402 struct ttm_buffer_object tbo;
403 struct ttm_bo_kmap_obj kmap;
409 /* list of all virtual address to which this bo
413 /* Constant after initialization */
414 struct radeon_device *rdev;
415 struct drm_gem_object gem_base;
417 struct ttm_bo_kmap_obj dma_buf_vmap;
420 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
422 struct radeon_bo_list {
423 struct ttm_validate_buffer tv;
424 struct radeon_bo *bo;
432 int radeon_gem_debugfs_init(struct radeon_device *rdev);
434 /* sub-allocation manager, it has to be protected by another lock.
435 * By conception this is an helper for other part of the driver
436 * like the indirect buffer or semaphore, which both have their
439 * Principe is simple, we keep a list of sub allocation in offset
440 * order (first entry has offset == 0, last entry has the highest
443 * When allocating new object we first check if there is room at
444 * the end total_size - (last_object_offset + last_object_size) >=
445 * alloc_size. If so we allocate new object there.
447 * When there is not enough room at the end, we start waiting for
448 * each sub object until we reach object_offset+object_size >=
449 * alloc_size, this object then become the sub object we return.
451 * Alignment can't be bigger than page size.
453 * Hole are not considered for allocation to keep things simple.
454 * Assumption is that there won't be hole (all object on same
457 struct radeon_sa_manager {
458 wait_queue_head_t wq;
459 struct radeon_bo *bo;
460 struct list_head *hole;
461 struct list_head flist[RADEON_NUM_RINGS];
462 struct list_head olist;
472 /* sub-allocation buffer */
473 struct radeon_sa_bo {
474 struct list_head olist;
475 struct list_head flist;
476 struct radeon_sa_manager *manager;
479 struct radeon_fence *fence;
487 struct list_head objects;
490 int radeon_gem_init(struct radeon_device *rdev);
491 void radeon_gem_fini(struct radeon_device *rdev);
492 int radeon_gem_object_create(struct radeon_device *rdev, int size,
493 int alignment, int initial_domain,
494 bool discardable, bool kernel,
495 struct drm_gem_object **obj);
497 int radeon_mode_dumb_create(struct drm_file *file_priv,
498 struct drm_device *dev,
499 struct drm_mode_create_dumb *args);
500 int radeon_mode_dumb_mmap(struct drm_file *filp,
501 struct drm_device *dev,
502 uint32_t handle, uint64_t *offset_p);
503 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
504 struct drm_device *dev,
510 /* everything here is constant */
511 struct radeon_semaphore {
512 struct radeon_sa_bo *sa_bo;
517 int radeon_semaphore_create(struct radeon_device *rdev,
518 struct radeon_semaphore **semaphore);
519 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
520 struct radeon_semaphore *semaphore);
521 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
522 struct radeon_semaphore *semaphore);
523 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
524 struct radeon_semaphore *semaphore,
525 int signaler, int waiter);
526 void radeon_semaphore_free(struct radeon_device *rdev,
527 struct radeon_semaphore **semaphore,
528 struct radeon_fence *fence);
531 * GART structures, functions & helpers
535 #define RADEON_GPU_PAGE_SIZE 4096
536 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
537 #define RADEON_GPU_PAGE_SHIFT 12
538 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
541 dma_addr_t table_addr;
542 struct radeon_bo *robj;
544 unsigned num_gpu_pages;
545 unsigned num_cpu_pages;
548 dma_addr_t *pages_addr;
552 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
553 void radeon_gart_table_ram_free(struct radeon_device *rdev);
554 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
555 void radeon_gart_table_vram_free(struct radeon_device *rdev);
556 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
557 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
558 int radeon_gart_init(struct radeon_device *rdev);
559 void radeon_gart_fini(struct radeon_device *rdev);
560 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
562 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
563 int pages, struct page **pagelist,
564 dma_addr_t *dma_addr);
565 void radeon_gart_restore(struct radeon_device *rdev);
569 * GPU MC structures, functions & helpers
572 resource_size_t aper_size;
573 resource_size_t aper_base;
574 resource_size_t agp_base;
575 /* for some chips with <= 32MB we need to lie
576 * about vram size near mc fb location */
578 u64 visible_vram_size;
588 bool igp_sideport_enabled;
593 bool radeon_combios_sideport_present(struct radeon_device *rdev);
594 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
597 * GPU scratch registers structures, functions & helpers
599 struct radeon_scratch {
606 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
607 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
610 * GPU doorbell structures, functions & helpers
612 struct radeon_doorbell {
616 resource_size_t base;
617 resource_size_t size;
621 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
622 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
628 struct radeon_unpin_work {
629 struct work_struct work;
630 struct radeon_device *rdev;
632 struct radeon_fence *fence;
633 struct drm_pending_vblank_event *event;
634 struct radeon_bo *old_rbo;
638 struct r500_irq_stat_regs {
643 struct r600_irq_stat_regs {
653 struct evergreen_irq_stat_regs {
674 struct cik_irq_stat_regs {
684 union radeon_irq_stat_regs {
685 struct r500_irq_stat_regs r500;
686 struct r600_irq_stat_regs r600;
687 struct evergreen_irq_stat_regs evergreen;
688 struct cik_irq_stat_regs cik;
691 #define RADEON_MAX_HPD_PINS 6
692 #define RADEON_MAX_CRTCS 6
693 #define RADEON_MAX_AFMT_BLOCKS 6
698 atomic_t ring_int[RADEON_NUM_RINGS];
699 bool crtc_vblank_int[RADEON_MAX_CRTCS];
700 atomic_t pflip[RADEON_MAX_CRTCS];
701 wait_queue_head_t vblank_queue;
702 bool hpd[RADEON_MAX_HPD_PINS];
703 bool afmt[RADEON_MAX_AFMT_BLOCKS];
704 union radeon_irq_stat_regs stat_regs;
708 int radeon_irq_kms_init(struct radeon_device *rdev);
709 void radeon_irq_kms_fini(struct radeon_device *rdev);
710 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
711 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
712 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
713 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
714 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
715 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
716 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
717 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
724 struct radeon_sa_bo *sa_bo;
729 struct radeon_fence *fence;
730 struct radeon_vm *vm;
732 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
733 struct radeon_semaphore *semaphore;
737 struct radeon_bo *ring_obj;
738 volatile uint32_t *ring;
742 unsigned rptr_save_reg;
743 u64 next_rptr_gpu_addr;
744 volatile u32 *next_rptr_cpu_addr;
749 unsigned ring_free_dw;
751 unsigned long last_activity;
761 u64 last_semaphore_signal_addr;
762 u64 last_semaphore_wait_addr;
767 struct radeon_bo *mqd_obj;
768 u32 doorbell_page_num;
774 struct radeon_bo *hpd_eop_obj;
775 u64 hpd_eop_gpu_addr;
785 /* maximum number of VMIDs */
786 #define RADEON_NUM_VM 16
788 /* defines number of bits in page table versus page directory,
789 * a page is 4KB so we have 12 bits offset, 9 bits in the page
790 * table and the remaining 19 bits are in the page directory */
791 #define RADEON_VM_BLOCK_SIZE 9
793 /* number of entries in page table */
794 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
796 /* PTBs (Page Table Blocks) need to be aligned to 32K */
797 #define RADEON_VM_PTB_ALIGN_SIZE 32768
798 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
799 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
802 struct list_head list;
806 /* contains the page directory */
807 struct radeon_sa_bo *page_directory;
808 uint64_t pd_gpu_addr;
810 /* array of page tables, one for each page directory entry */
811 struct radeon_sa_bo **page_tables;
814 /* last fence for cs using this vm */
815 struct radeon_fence *fence;
816 /* last flush or NULL if we still need to flush */
817 struct radeon_fence *last_flush;
820 struct radeon_vm_manager {
822 struct list_head lru_vm;
823 struct radeon_fence *active[RADEON_NUM_VM];
824 struct radeon_sa_manager sa_manager;
826 /* number of VMIDs */
828 /* vram base address for page table entry */
829 u64 vram_base_offset;
835 * file private structure
837 struct radeon_fpriv {
845 struct radeon_bo *ring_obj;
846 volatile uint32_t *ring;
858 #include "clearstate_defs.h"
861 /* for power gating */
862 struct radeon_bo *save_restore_obj;
863 uint64_t save_restore_gpu_addr;
864 volatile uint32_t *sr_ptr;
867 /* for clear state */
868 struct radeon_bo *clear_state_obj;
869 uint64_t clear_state_gpu_addr;
870 volatile uint32_t *cs_ptr;
871 const struct cs_section_def *cs_data;
872 u32 clear_state_size;
874 struct radeon_bo *cp_table_obj;
875 uint64_t cp_table_gpu_addr;
876 volatile uint32_t *cp_table_ptr;
880 int radeon_ib_get(struct radeon_device *rdev, int ring,
881 struct radeon_ib *ib, struct radeon_vm *vm,
883 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
884 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
885 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
886 struct radeon_ib *const_ib);
887 int radeon_ib_pool_init(struct radeon_device *rdev);
888 void radeon_ib_pool_fini(struct radeon_device *rdev);
889 int radeon_ib_ring_tests(struct radeon_device *rdev);
890 /* Ring access between begin & end cannot sleep */
891 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
892 struct radeon_ring *ring);
893 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
894 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
895 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
896 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
897 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
898 void radeon_ring_undo(struct radeon_ring *ring);
899 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
900 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
901 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
902 void radeon_ring_lockup_update(struct radeon_ring *ring);
903 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
904 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
906 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
907 unsigned size, uint32_t *data);
908 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
909 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
910 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
911 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
915 void r600_dma_stop(struct radeon_device *rdev);
916 int r600_dma_resume(struct radeon_device *rdev);
917 void r600_dma_fini(struct radeon_device *rdev);
919 void cayman_dma_stop(struct radeon_device *rdev);
920 int cayman_dma_resume(struct radeon_device *rdev);
921 void cayman_dma_fini(struct radeon_device *rdev);
926 struct radeon_cs_reloc {
927 struct drm_gem_object *gobj;
928 struct radeon_bo *robj;
929 struct radeon_bo_list lobj;
934 struct radeon_cs_chunk {
940 void __user *user_ptr;
941 int last_copied_page;
945 struct radeon_cs_parser {
947 struct radeon_device *rdev;
948 struct drm_file *filp;
951 struct radeon_cs_chunk *chunks;
952 uint64_t *chunks_array;
957 struct radeon_cs_reloc *relocs;
958 struct radeon_cs_reloc **relocs_ptr;
959 struct list_head validated;
960 unsigned dma_reloc_idx;
961 /* indices of various chunks */
963 int chunk_relocs_idx;
965 int chunk_const_ib_idx;
967 struct radeon_ib const_ib;
974 struct ww_acquire_ctx ticket;
977 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
978 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
980 struct radeon_cs_packet {
989 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
990 struct radeon_cs_packet *pkt,
991 unsigned idx, unsigned reg);
992 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
993 struct radeon_cs_packet *pkt);
999 int radeon_agp_init(struct radeon_device *rdev);
1000 void radeon_agp_resume(struct radeon_device *rdev);
1001 void radeon_agp_suspend(struct radeon_device *rdev);
1002 void radeon_agp_fini(struct radeon_device *rdev);
1009 struct radeon_bo *wb_obj;
1010 volatile uint32_t *wb;
1016 #define RADEON_WB_SCRATCH_OFFSET 0
1017 #define RADEON_WB_RING0_NEXT_RPTR 256
1018 #define RADEON_WB_CP_RPTR_OFFSET 1024
1019 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1020 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1021 #define R600_WB_DMA_RPTR_OFFSET 1792
1022 #define R600_WB_IH_WPTR_OFFSET 2048
1023 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1024 #define R600_WB_UVD_RPTR_OFFSET 2560
1025 #define R600_WB_EVENT_OFFSET 3072
1026 #define CIK_WB_CP1_WPTR_OFFSET 3328
1027 #define CIK_WB_CP2_WPTR_OFFSET 3584
1030 * struct radeon_pm - power management datas
1031 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1032 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1033 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1034 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1035 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1036 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1037 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1038 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1039 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1040 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1041 * @needed_bandwidth: current bandwidth needs
1043 * It keeps track of various data needed to take powermanagement decision.
1044 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1045 * Equation between gpu/memory clock and available bandwidth is hw dependent
1046 * (type of memory, bus size, efficiency, ...)
1049 enum radeon_pm_method {
1055 enum radeon_dynpm_state {
1056 DYNPM_STATE_DISABLED,
1057 DYNPM_STATE_MINIMUM,
1060 DYNPM_STATE_SUSPENDED,
1062 enum radeon_dynpm_action {
1064 DYNPM_ACTION_MINIMUM,
1065 DYNPM_ACTION_DOWNCLOCK,
1066 DYNPM_ACTION_UPCLOCK,
1067 DYNPM_ACTION_DEFAULT
1070 enum radeon_voltage_type {
1077 enum radeon_pm_state_type {
1078 /* not used for dpm */
1079 POWER_STATE_TYPE_DEFAULT,
1080 POWER_STATE_TYPE_POWERSAVE,
1081 /* user selectable states */
1082 POWER_STATE_TYPE_BATTERY,
1083 POWER_STATE_TYPE_BALANCED,
1084 POWER_STATE_TYPE_PERFORMANCE,
1085 /* internal states */
1086 POWER_STATE_TYPE_INTERNAL_UVD,
1087 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1088 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1089 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1090 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1091 POWER_STATE_TYPE_INTERNAL_BOOT,
1092 POWER_STATE_TYPE_INTERNAL_THERMAL,
1093 POWER_STATE_TYPE_INTERNAL_ACPI,
1094 POWER_STATE_TYPE_INTERNAL_ULV,
1095 POWER_STATE_TYPE_INTERNAL_3DPERF,
1098 enum radeon_pm_profile_type {
1106 #define PM_PROFILE_DEFAULT_IDX 0
1107 #define PM_PROFILE_LOW_SH_IDX 1
1108 #define PM_PROFILE_MID_SH_IDX 2
1109 #define PM_PROFILE_HIGH_SH_IDX 3
1110 #define PM_PROFILE_LOW_MH_IDX 4
1111 #define PM_PROFILE_MID_MH_IDX 5
1112 #define PM_PROFILE_HIGH_MH_IDX 6
1113 #define PM_PROFILE_MAX 7
1115 struct radeon_pm_profile {
1116 int dpms_off_ps_idx;
1118 int dpms_off_cm_idx;
1122 enum radeon_int_thermal_type {
1124 THERMAL_TYPE_EXTERNAL,
1125 THERMAL_TYPE_EXTERNAL_GPIO,
1128 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1129 THERMAL_TYPE_EVERGREEN,
1133 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1138 struct radeon_voltage {
1139 enum radeon_voltage_type type;
1141 struct radeon_gpio_rec gpio;
1142 u32 delay; /* delay in usec from voltage drop to sclk change */
1143 bool active_high; /* voltage drop is active when bit is high */
1145 u8 vddc_id; /* index into vddc voltage table */
1146 u8 vddci_id; /* index into vddci voltage table */
1150 /* evergreen+ vddci */
1154 /* clock mode flags */
1155 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1157 struct radeon_pm_clock_info {
1163 struct radeon_voltage voltage;
1164 /* standardized clock flags */
1169 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1171 struct radeon_power_state {
1172 enum radeon_pm_state_type type;
1173 struct radeon_pm_clock_info *clock_info;
1174 /* number of valid clock modes in this power state */
1175 int num_clock_modes;
1176 struct radeon_pm_clock_info *default_clock_mode;
1177 /* standardized state flags */
1179 u32 misc; /* vbios specific flags */
1180 u32 misc2; /* vbios specific flags */
1181 int pcie_lanes; /* pcie lanes */
1185 * Some modes are overclocked by very low value, accept them
1187 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1189 enum radeon_dpm_auto_throttle_src {
1190 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1191 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1194 enum radeon_dpm_event_src {
1195 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1196 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1197 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1198 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1199 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1203 u32 caps; /* vbios flags */
1204 u32 class; /* vbios flags */
1205 u32 class2; /* vbios flags */
1213 struct radeon_dpm_thermal {
1214 /* thermal interrupt work */
1215 struct work_struct work;
1216 /* low temperature threshold */
1218 /* high temperature threshold */
1220 /* was interrupt low to high or high to low */
1224 enum radeon_clk_action
1230 struct radeon_blacklist_clocks
1234 enum radeon_clk_action action;
1237 struct radeon_clock_and_voltage_limits {
1244 struct radeon_clock_array {
1249 struct radeon_clock_voltage_dependency_entry {
1254 struct radeon_clock_voltage_dependency_table {
1256 struct radeon_clock_voltage_dependency_entry *entries;
1259 union radeon_cac_leakage_entry {
1271 struct radeon_cac_leakage_table {
1273 union radeon_cac_leakage_entry *entries;
1276 struct radeon_phase_shedding_limits_entry {
1282 struct radeon_phase_shedding_limits_table {
1284 struct radeon_phase_shedding_limits_entry *entries;
1287 struct radeon_uvd_clock_voltage_dependency_entry {
1293 struct radeon_uvd_clock_voltage_dependency_table {
1295 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1298 struct radeon_vce_clock_voltage_dependency_entry {
1304 struct radeon_vce_clock_voltage_dependency_table {
1306 struct radeon_vce_clock_voltage_dependency_entry *entries;
1309 struct radeon_ppm_table {
1311 u16 cpu_core_number;
1313 u32 small_ac_platform_tdp;
1315 u32 small_ac_platform_tdc;
1322 struct radeon_cac_tdp_table {
1324 u16 configurable_tdp;
1326 u16 battery_power_limit;
1327 u16 small_power_limit;
1328 u16 low_cac_leakage;
1329 u16 high_cac_leakage;
1330 u16 maximum_power_delivery_limit;
1333 struct radeon_dpm_dynamic_state {
1334 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1335 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1336 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1337 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1338 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1339 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1340 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1341 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1342 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1343 struct radeon_clock_array valid_sclk_values;
1344 struct radeon_clock_array valid_mclk_values;
1345 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1346 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1347 u32 mclk_sclk_ratio;
1348 u32 sclk_mclk_delta;
1349 u16 vddc_vddci_delta;
1350 u16 min_vddc_for_pcie_gen2;
1351 struct radeon_cac_leakage_table cac_leakage_table;
1352 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1353 struct radeon_ppm_table *ppm_table;
1354 struct radeon_cac_tdp_table *cac_tdp_table;
1357 struct radeon_dpm_fan {
1367 bool ucode_fan_control;
1370 enum radeon_pcie_gen {
1371 RADEON_PCIE_GEN1 = 0,
1372 RADEON_PCIE_GEN2 = 1,
1373 RADEON_PCIE_GEN3 = 2,
1374 RADEON_PCIE_GEN_INVALID = 0xffff
1377 enum radeon_dpm_forced_level {
1378 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1379 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1380 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1384 struct radeon_ps *ps;
1385 /* number of valid power states */
1387 /* current power state that is active */
1388 struct radeon_ps *current_ps;
1389 /* requested power state */
1390 struct radeon_ps *requested_ps;
1391 /* boot up power state */
1392 struct radeon_ps *boot_ps;
1393 /* default uvd power state */
1394 struct radeon_ps *uvd_ps;
1395 enum radeon_pm_state_type state;
1396 enum radeon_pm_state_type user_state;
1398 u32 voltage_response_time;
1399 u32 backbias_response_time;
1401 u32 new_active_crtcs;
1402 int new_active_crtc_count;
1403 u32 current_active_crtcs;
1404 int current_active_crtc_count;
1405 struct radeon_dpm_dynamic_state dyn_state;
1406 struct radeon_dpm_fan fan;
1409 u32 near_tdp_limit_adjusted;
1410 u32 sq_ramping_threshold;
1414 u16 load_line_slope;
1417 /* special states active */
1418 bool thermal_active;
1420 /* thermal handling */
1421 struct radeon_dpm_thermal thermal;
1423 enum radeon_dpm_forced_level forced_level;
1424 /* track UVD streams */
1429 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1433 /* write locked while reprogramming mclk */
1434 struct rw_semaphore mclk_lock;
1436 int active_crtc_count;
1439 fixed20_12 max_bandwidth;
1440 fixed20_12 igp_sideport_mclk;
1441 fixed20_12 igp_system_mclk;
1442 fixed20_12 igp_ht_link_clk;
1443 fixed20_12 igp_ht_link_width;
1444 fixed20_12 k8_bandwidth;
1445 fixed20_12 sideport_bandwidth;
1446 fixed20_12 ht_bandwidth;
1447 fixed20_12 core_bandwidth;
1450 fixed20_12 needed_bandwidth;
1451 struct radeon_power_state *power_state;
1452 /* number of valid power states */
1453 int num_power_states;
1454 int current_power_state_index;
1455 int current_clock_mode_index;
1456 int requested_power_state_index;
1457 int requested_clock_mode_index;
1458 int default_power_state_index;
1467 struct radeon_i2c_chan *i2c_bus;
1468 /* selected pm method */
1469 enum radeon_pm_method pm_method;
1470 /* dynpm power management */
1471 struct delayed_work dynpm_idle_work;
1472 enum radeon_dynpm_state dynpm_state;
1473 enum radeon_dynpm_action dynpm_planned_action;
1474 unsigned long dynpm_action_timeout;
1475 bool dynpm_can_upclock;
1476 bool dynpm_can_downclock;
1477 /* profile-based power management */
1478 enum radeon_pm_profile_type profile;
1480 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1481 /* internal thermal controller on rv6xx+ */
1482 enum radeon_int_thermal_type int_thermal_type;
1483 struct device *int_hwmon_dev;
1486 struct radeon_dpm dpm;
1489 int radeon_pm_get_type_index(struct radeon_device *rdev,
1490 enum radeon_pm_state_type ps_type,
1495 #define RADEON_MAX_UVD_HANDLES 10
1496 #define RADEON_UVD_STACK_SIZE (1024*1024)
1497 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1500 struct radeon_bo *vcpu_bo;
1504 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1505 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1506 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1507 struct delayed_work idle_work;
1510 int radeon_uvd_init(struct radeon_device *rdev);
1511 void radeon_uvd_fini(struct radeon_device *rdev);
1512 int radeon_uvd_suspend(struct radeon_device *rdev);
1513 int radeon_uvd_resume(struct radeon_device *rdev);
1514 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1515 uint32_t handle, struct radeon_fence **fence);
1516 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1517 uint32_t handle, struct radeon_fence **fence);
1518 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1519 void radeon_uvd_free_handles(struct radeon_device *rdev,
1520 struct drm_file *filp);
1521 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1522 void radeon_uvd_note_usage(struct radeon_device *rdev);
1523 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1524 unsigned vclk, unsigned dclk,
1525 unsigned vco_min, unsigned vco_max,
1526 unsigned fb_factor, unsigned fb_mask,
1527 unsigned pd_min, unsigned pd_max,
1529 unsigned *optimal_fb_div,
1530 unsigned *optimal_vclk_div,
1531 unsigned *optimal_dclk_div);
1532 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1533 unsigned cg_upll_func_cntl);
1538 int bits_per_sample;
1546 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1552 void radeon_test_moves(struct radeon_device *rdev);
1553 void radeon_test_ring_sync(struct radeon_device *rdev,
1554 struct radeon_ring *cpA,
1555 struct radeon_ring *cpB);
1556 void radeon_test_syncing(struct radeon_device *rdev);
1562 struct radeon_debugfs {
1563 struct drm_info_list *files;
1567 int radeon_debugfs_add_files(struct radeon_device *rdev,
1568 struct drm_info_list *files,
1570 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1574 * ASIC specific functions.
1576 struct radeon_asic {
1577 int (*init)(struct radeon_device *rdev);
1578 void (*fini)(struct radeon_device *rdev);
1579 int (*resume)(struct radeon_device *rdev);
1580 int (*suspend)(struct radeon_device *rdev);
1581 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1582 int (*asic_reset)(struct radeon_device *rdev);
1583 /* ioctl hw specific callback. Some hw might want to perform special
1584 * operation on specific ioctl. For instance on wait idle some hw
1585 * might want to perform and HDP flush through MMIO as it seems that
1586 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1589 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1590 /* check if 3D engine is idle */
1591 bool (*gui_idle)(struct radeon_device *rdev);
1592 /* wait for mc_idle */
1593 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1594 /* get the reference clock */
1595 u32 (*get_xclk)(struct radeon_device *rdev);
1596 /* get the gpu clock counter */
1597 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1600 void (*tlb_flush)(struct radeon_device *rdev);
1601 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1604 int (*init)(struct radeon_device *rdev);
1605 void (*fini)(struct radeon_device *rdev);
1608 void (*set_page)(struct radeon_device *rdev,
1609 struct radeon_ib *ib,
1611 uint64_t addr, unsigned count,
1612 uint32_t incr, uint32_t flags);
1614 /* ring specific callbacks */
1616 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1617 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1618 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1619 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1620 struct radeon_semaphore *semaphore, bool emit_wait);
1621 int (*cs_parse)(struct radeon_cs_parser *p);
1622 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1623 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1624 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1625 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1626 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1628 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1629 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1630 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1631 } ring[RADEON_NUM_RINGS];
1634 int (*set)(struct radeon_device *rdev);
1635 int (*process)(struct radeon_device *rdev);
1639 /* display watermarks */
1640 void (*bandwidth_update)(struct radeon_device *rdev);
1641 /* get frame count */
1642 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1643 /* wait for vblank */
1644 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1645 /* set backlight level */
1646 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1647 /* get backlight level */
1648 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1649 /* audio callbacks */
1650 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1651 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1653 /* copy functions for bo handling */
1655 int (*blit)(struct radeon_device *rdev,
1656 uint64_t src_offset,
1657 uint64_t dst_offset,
1658 unsigned num_gpu_pages,
1659 struct radeon_fence **fence);
1660 u32 blit_ring_index;
1661 int (*dma)(struct radeon_device *rdev,
1662 uint64_t src_offset,
1663 uint64_t dst_offset,
1664 unsigned num_gpu_pages,
1665 struct radeon_fence **fence);
1667 /* method used for bo copy */
1668 int (*copy)(struct radeon_device *rdev,
1669 uint64_t src_offset,
1670 uint64_t dst_offset,
1671 unsigned num_gpu_pages,
1672 struct radeon_fence **fence);
1673 /* ring used for bo copies */
1674 u32 copy_ring_index;
1678 int (*set_reg)(struct radeon_device *rdev, int reg,
1679 uint32_t tiling_flags, uint32_t pitch,
1680 uint32_t offset, uint32_t obj_size);
1681 void (*clear_reg)(struct radeon_device *rdev, int reg);
1683 /* hotplug detect */
1685 void (*init)(struct radeon_device *rdev);
1686 void (*fini)(struct radeon_device *rdev);
1687 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1688 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1690 /* static power management */
1692 void (*misc)(struct radeon_device *rdev);
1693 void (*prepare)(struct radeon_device *rdev);
1694 void (*finish)(struct radeon_device *rdev);
1695 void (*init_profile)(struct radeon_device *rdev);
1696 void (*get_dynpm_state)(struct radeon_device *rdev);
1697 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1698 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1699 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1700 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1701 int (*get_pcie_lanes)(struct radeon_device *rdev);
1702 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1703 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1704 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1705 int (*get_temperature)(struct radeon_device *rdev);
1707 /* dynamic power management */
1709 int (*init)(struct radeon_device *rdev);
1710 void (*setup_asic)(struct radeon_device *rdev);
1711 int (*enable)(struct radeon_device *rdev);
1712 void (*disable)(struct radeon_device *rdev);
1713 int (*pre_set_power_state)(struct radeon_device *rdev);
1714 int (*set_power_state)(struct radeon_device *rdev);
1715 void (*post_set_power_state)(struct radeon_device *rdev);
1716 void (*display_configuration_changed)(struct radeon_device *rdev);
1717 void (*fini)(struct radeon_device *rdev);
1718 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1719 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1720 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1721 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1722 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1723 bool (*vblank_too_short)(struct radeon_device *rdev);
1727 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1728 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1729 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1737 const unsigned *reg_safe_bm;
1738 unsigned reg_safe_bm_size;
1743 const unsigned *reg_safe_bm;
1744 unsigned reg_safe_bm_size;
1751 unsigned max_tile_pipes;
1753 unsigned max_backends;
1755 unsigned max_threads;
1756 unsigned max_stack_entries;
1757 unsigned max_hw_contexts;
1758 unsigned max_gs_threads;
1759 unsigned sx_max_export_size;
1760 unsigned sx_max_export_pos_size;
1761 unsigned sx_max_export_smx_size;
1762 unsigned sq_num_cf_insts;
1763 unsigned tiling_nbanks;
1764 unsigned tiling_npipes;
1765 unsigned tiling_group_size;
1766 unsigned tile_config;
1767 unsigned backend_map;
1772 unsigned max_tile_pipes;
1774 unsigned max_backends;
1776 unsigned max_threads;
1777 unsigned max_stack_entries;
1778 unsigned max_hw_contexts;
1779 unsigned max_gs_threads;
1780 unsigned sx_max_export_size;
1781 unsigned sx_max_export_pos_size;
1782 unsigned sx_max_export_smx_size;
1783 unsigned sq_num_cf_insts;
1784 unsigned sx_num_of_sets;
1785 unsigned sc_prim_fifo_size;
1786 unsigned sc_hiz_tile_fifo_size;
1787 unsigned sc_earlyz_tile_fifo_fize;
1788 unsigned tiling_nbanks;
1789 unsigned tiling_npipes;
1790 unsigned tiling_group_size;
1791 unsigned tile_config;
1792 unsigned backend_map;
1795 struct evergreen_asic {
1798 unsigned max_tile_pipes;
1800 unsigned max_backends;
1802 unsigned max_threads;
1803 unsigned max_stack_entries;
1804 unsigned max_hw_contexts;
1805 unsigned max_gs_threads;
1806 unsigned sx_max_export_size;
1807 unsigned sx_max_export_pos_size;
1808 unsigned sx_max_export_smx_size;
1809 unsigned sq_num_cf_insts;
1810 unsigned sx_num_of_sets;
1811 unsigned sc_prim_fifo_size;
1812 unsigned sc_hiz_tile_fifo_size;
1813 unsigned sc_earlyz_tile_fifo_size;
1814 unsigned tiling_nbanks;
1815 unsigned tiling_npipes;
1816 unsigned tiling_group_size;
1817 unsigned tile_config;
1818 unsigned backend_map;
1821 struct cayman_asic {
1822 unsigned max_shader_engines;
1823 unsigned max_pipes_per_simd;
1824 unsigned max_tile_pipes;
1825 unsigned max_simds_per_se;
1826 unsigned max_backends_per_se;
1827 unsigned max_texture_channel_caches;
1829 unsigned max_threads;
1830 unsigned max_gs_threads;
1831 unsigned max_stack_entries;
1832 unsigned sx_num_of_sets;
1833 unsigned sx_max_export_size;
1834 unsigned sx_max_export_pos_size;
1835 unsigned sx_max_export_smx_size;
1836 unsigned max_hw_contexts;
1837 unsigned sq_num_cf_insts;
1838 unsigned sc_prim_fifo_size;
1839 unsigned sc_hiz_tile_fifo_size;
1840 unsigned sc_earlyz_tile_fifo_size;
1842 unsigned num_shader_engines;
1843 unsigned num_shader_pipes_per_simd;
1844 unsigned num_tile_pipes;
1845 unsigned num_simds_per_se;
1846 unsigned num_backends_per_se;
1847 unsigned backend_disable_mask_per_asic;
1848 unsigned backend_map;
1849 unsigned num_texture_channel_caches;
1850 unsigned mem_max_burst_length_bytes;
1851 unsigned mem_row_size_in_kb;
1852 unsigned shader_engine_tile_size;
1854 unsigned multi_gpu_tile_size;
1856 unsigned tile_config;
1860 unsigned max_shader_engines;
1861 unsigned max_tile_pipes;
1862 unsigned max_cu_per_sh;
1863 unsigned max_sh_per_se;
1864 unsigned max_backends_per_se;
1865 unsigned max_texture_channel_caches;
1867 unsigned max_gs_threads;
1868 unsigned max_hw_contexts;
1869 unsigned sc_prim_fifo_size_frontend;
1870 unsigned sc_prim_fifo_size_backend;
1871 unsigned sc_hiz_tile_fifo_size;
1872 unsigned sc_earlyz_tile_fifo_size;
1874 unsigned num_tile_pipes;
1875 unsigned num_backends_per_se;
1876 unsigned backend_disable_mask_per_asic;
1877 unsigned backend_map;
1878 unsigned num_texture_channel_caches;
1879 unsigned mem_max_burst_length_bytes;
1880 unsigned mem_row_size_in_kb;
1881 unsigned shader_engine_tile_size;
1883 unsigned multi_gpu_tile_size;
1885 unsigned tile_config;
1886 uint32_t tile_mode_array[32];
1890 unsigned max_shader_engines;
1891 unsigned max_tile_pipes;
1892 unsigned max_cu_per_sh;
1893 unsigned max_sh_per_se;
1894 unsigned max_backends_per_se;
1895 unsigned max_texture_channel_caches;
1897 unsigned max_gs_threads;
1898 unsigned max_hw_contexts;
1899 unsigned sc_prim_fifo_size_frontend;
1900 unsigned sc_prim_fifo_size_backend;
1901 unsigned sc_hiz_tile_fifo_size;
1902 unsigned sc_earlyz_tile_fifo_size;
1904 unsigned num_tile_pipes;
1905 unsigned num_backends_per_se;
1906 unsigned backend_disable_mask_per_asic;
1907 unsigned backend_map;
1908 unsigned num_texture_channel_caches;
1909 unsigned mem_max_burst_length_bytes;
1910 unsigned mem_row_size_in_kb;
1911 unsigned shader_engine_tile_size;
1913 unsigned multi_gpu_tile_size;
1915 unsigned tile_config;
1916 uint32_t tile_mode_array[32];
1919 union radeon_asic_config {
1920 struct r300_asic r300;
1921 struct r100_asic r100;
1922 struct r600_asic r600;
1923 struct rv770_asic rv770;
1924 struct evergreen_asic evergreen;
1925 struct cayman_asic cayman;
1927 struct cik_asic cik;
1931 * asic initizalization from radeon_asic.c
1933 void radeon_agp_disable(struct radeon_device *rdev);
1934 int radeon_asic_init(struct radeon_device *rdev);
1940 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1941 struct drm_file *filp);
1942 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1943 struct drm_file *filp);
1944 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1945 struct drm_file *file_priv);
1946 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1947 struct drm_file *file_priv);
1948 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1949 struct drm_file *file_priv);
1950 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1951 struct drm_file *file_priv);
1952 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1953 struct drm_file *filp);
1954 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1955 struct drm_file *filp);
1956 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1957 struct drm_file *filp);
1958 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1959 struct drm_file *filp);
1960 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1961 struct drm_file *filp);
1962 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1963 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1964 struct drm_file *filp);
1965 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1966 struct drm_file *filp);
1968 /* VRAM scratch page for HDP bug, default vram page */
1969 struct r600_vram_scratch {
1970 struct radeon_bo *robj;
1971 volatile uint32_t *ptr;
1978 struct radeon_atif_notification_cfg {
1983 struct radeon_atif_notifications {
1984 bool display_switch;
1985 bool expansion_mode_change;
1987 bool forced_power_state;
1988 bool system_power_state;
1989 bool display_conf_change;
1991 bool brightness_change;
1992 bool dgpu_display_event;
1995 struct radeon_atif_functions {
1997 bool sbios_requests;
1998 bool select_active_disp;
2000 bool get_tv_standard;
2001 bool set_tv_standard;
2002 bool get_panel_expansion_mode;
2003 bool set_panel_expansion_mode;
2004 bool temperature_change;
2005 bool graphics_device_types;
2008 struct radeon_atif {
2009 struct radeon_atif_notifications notifications;
2010 struct radeon_atif_functions functions;
2011 struct radeon_atif_notification_cfg notification_cfg;
2012 struct radeon_encoder *encoder_for_bl;
2015 struct radeon_atcs_functions {
2019 bool pcie_bus_width;
2022 struct radeon_atcs {
2023 struct radeon_atcs_functions functions;
2027 * Core structure, functions and helpers.
2029 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2030 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2032 struct radeon_device {
2034 struct drm_device *ddev;
2035 struct pci_dev *pdev;
2036 struct rw_semaphore exclusive_lock;
2038 union radeon_asic_config config;
2039 enum radeon_family family;
2040 unsigned long flags;
2042 enum radeon_pll_errata pll_errata;
2049 uint16_t bios_header_start;
2050 struct radeon_bo *stollen_vga_memory;
2052 resource_size_t rmmio_base;
2053 resource_size_t rmmio_size;
2054 /* protects concurrent MM_INDEX/DATA based register access */
2055 spinlock_t mmio_idx_lock;
2056 void __iomem *rmmio;
2057 radeon_rreg_t mc_rreg;
2058 radeon_wreg_t mc_wreg;
2059 radeon_rreg_t pll_rreg;
2060 radeon_wreg_t pll_wreg;
2061 uint32_t pcie_reg_mask;
2062 radeon_rreg_t pciep_rreg;
2063 radeon_wreg_t pciep_wreg;
2065 void __iomem *rio_mem;
2066 resource_size_t rio_mem_size;
2067 struct radeon_clock clock;
2068 struct radeon_mc mc;
2069 struct radeon_gart gart;
2070 struct radeon_mode_info mode_info;
2071 struct radeon_scratch scratch;
2072 struct radeon_doorbell doorbell;
2073 struct radeon_mman mman;
2074 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2075 wait_queue_head_t fence_queue;
2076 struct mutex ring_lock;
2077 struct radeon_ring ring[RADEON_NUM_RINGS];
2079 struct radeon_sa_manager ring_tmp_bo;
2080 struct radeon_irq irq;
2081 struct radeon_asic *asic;
2082 struct radeon_gem gem;
2083 struct radeon_pm pm;
2084 struct radeon_uvd uvd;
2085 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2086 struct radeon_wb wb;
2087 struct radeon_dummy_page dummy_page;
2092 bool fastfb_working; /* IGP feature*/
2093 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2094 const struct firmware *me_fw; /* all family ME firmware */
2095 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2096 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2097 const struct firmware *mc_fw; /* NI MC firmware */
2098 const struct firmware *ce_fw; /* SI CE firmware */
2099 const struct firmware *mec_fw; /* CIK MEC firmware */
2100 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2101 const struct firmware *smc_fw; /* SMC firmware */
2102 const struct firmware *uvd_fw; /* UVD firmware */
2103 struct r600_vram_scratch vram_scratch;
2104 int msi_enabled; /* msi enabled */
2105 struct r600_ih ih; /* r6/700 interrupt ring */
2106 struct radeon_rlc rlc;
2107 struct radeon_mec mec;
2108 struct work_struct hotplug_work;
2109 struct work_struct audio_work;
2110 struct work_struct reset_work;
2111 int num_crtc; /* number of crtcs */
2112 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2115 struct r600_audio audio_status; /* audio stuff */
2116 struct notifier_block acpi_nb;
2117 /* only one userspace can use Hyperz features or CMASK at a time */
2118 struct drm_file *hyperz_filp;
2119 struct drm_file *cmask_filp;
2121 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2123 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2124 unsigned debugfs_count;
2125 /* virtual memory */
2126 struct radeon_vm_manager vm_manager;
2127 struct mutex gpu_clock_mutex;
2128 /* ACPI interface */
2129 struct radeon_atif atif;
2130 struct radeon_atcs atcs;
2131 /* srbm instance registers */
2132 struct mutex srbm_mutex;
2135 int radeon_device_init(struct radeon_device *rdev,
2136 struct drm_device *ddev,
2137 struct pci_dev *pdev,
2139 void radeon_device_fini(struct radeon_device *rdev);
2140 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2142 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2143 bool always_indirect);
2144 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2145 bool always_indirect);
2146 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2147 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2149 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2150 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2155 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2158 * Registers read & write functions.
2160 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2161 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2162 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2163 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2164 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2165 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2166 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2167 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2168 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2169 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2170 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2171 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2172 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2173 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2174 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2175 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2176 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2177 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2178 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2179 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2180 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2181 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2182 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2183 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2184 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2185 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2186 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2187 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2188 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2189 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2190 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2191 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2192 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2193 #define WREG32_P(reg, val, mask) \
2195 uint32_t tmp_ = RREG32(reg); \
2197 tmp_ |= ((val) & ~(mask)); \
2198 WREG32(reg, tmp_); \
2200 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2201 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2202 #define WREG32_PLL_P(reg, val, mask) \
2204 uint32_t tmp_ = RREG32_PLL(reg); \
2206 tmp_ |= ((val) & ~(mask)); \
2207 WREG32_PLL(reg, tmp_); \
2209 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2210 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2211 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2213 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2214 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2217 * Indirect registers accessor
2219 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2223 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2224 r = RREG32(RADEON_PCIE_DATA);
2228 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2230 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2231 WREG32(RADEON_PCIE_DATA, (v));
2234 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2238 WREG32(TN_SMC_IND_INDEX_0, (reg));
2239 r = RREG32(TN_SMC_IND_DATA_0);
2243 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2245 WREG32(TN_SMC_IND_INDEX_0, (reg));
2246 WREG32(TN_SMC_IND_DATA_0, (v));
2249 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2253 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2254 r = RREG32(R600_RCU_DATA);
2258 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2260 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2261 WREG32(R600_RCU_DATA, (v));
2264 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2268 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2269 r = RREG32(EVERGREEN_CG_IND_DATA);
2273 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2275 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2276 WREG32(EVERGREEN_CG_IND_DATA, (v));
2279 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2283 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2284 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2288 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2290 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2291 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2294 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2298 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2299 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2303 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2305 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2306 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2309 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2313 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2314 r = RREG32(R600_UVD_CTX_DATA);
2318 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2320 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2321 WREG32(R600_UVD_CTX_DATA, (v));
2325 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2329 WREG32(CIK_DIDT_IND_INDEX, (reg));
2330 r = RREG32(CIK_DIDT_IND_DATA);
2334 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2336 WREG32(CIK_DIDT_IND_INDEX, (reg));
2337 WREG32(CIK_DIDT_IND_DATA, (v));
2340 void r100_pll_errata_after_index(struct radeon_device *rdev);
2346 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2347 (rdev->pdev->device == 0x5969))
2348 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2349 (rdev->family == CHIP_RV200) || \
2350 (rdev->family == CHIP_RS100) || \
2351 (rdev->family == CHIP_RS200) || \
2352 (rdev->family == CHIP_RV250) || \
2353 (rdev->family == CHIP_RV280) || \
2354 (rdev->family == CHIP_RS300))
2355 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2356 (rdev->family == CHIP_RV350) || \
2357 (rdev->family == CHIP_R350) || \
2358 (rdev->family == CHIP_RV380) || \
2359 (rdev->family == CHIP_R420) || \
2360 (rdev->family == CHIP_R423) || \
2361 (rdev->family == CHIP_RV410) || \
2362 (rdev->family == CHIP_RS400) || \
2363 (rdev->family == CHIP_RS480))
2364 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2365 (rdev->ddev->pdev->device == 0x9443) || \
2366 (rdev->ddev->pdev->device == 0x944B) || \
2367 (rdev->ddev->pdev->device == 0x9506) || \
2368 (rdev->ddev->pdev->device == 0x9509) || \
2369 (rdev->ddev->pdev->device == 0x950F) || \
2370 (rdev->ddev->pdev->device == 0x689C) || \
2371 (rdev->ddev->pdev->device == 0x689D))
2372 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2373 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2374 (rdev->family == CHIP_RS690) || \
2375 (rdev->family == CHIP_RS740) || \
2376 (rdev->family >= CHIP_R600))
2377 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2378 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2379 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2380 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2381 (rdev->flags & RADEON_IS_IGP))
2382 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2383 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2384 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2385 (rdev->flags & RADEON_IS_IGP))
2386 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2387 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2388 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2390 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2391 (rdev->ddev->pdev->device == 0x6850) || \
2392 (rdev->ddev->pdev->device == 0x6858) || \
2393 (rdev->ddev->pdev->device == 0x6859) || \
2394 (rdev->ddev->pdev->device == 0x6840) || \
2395 (rdev->ddev->pdev->device == 0x6841) || \
2396 (rdev->ddev->pdev->device == 0x6842) || \
2397 (rdev->ddev->pdev->device == 0x6843))
2402 #define RBIOS8(i) (rdev->bios[i])
2403 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2404 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2406 int radeon_combios_init(struct radeon_device *rdev);
2407 void radeon_combios_fini(struct radeon_device *rdev);
2408 int radeon_atombios_init(struct radeon_device *rdev);
2409 void radeon_atombios_fini(struct radeon_device *rdev);
2415 #if DRM_DEBUG_CODE == 0
2416 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2418 ring->ring[ring->wptr++] = v;
2419 ring->wptr &= ring->ptr_mask;
2421 ring->ring_free_dw--;
2424 /* With debugging this is just too big to inline */
2425 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2431 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2432 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2433 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2434 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2435 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
2436 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2437 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2438 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2439 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2440 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2441 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2442 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2443 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2444 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2445 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
2446 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
2447 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
2448 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
2449 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
2450 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2451 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2452 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
2453 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2454 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2455 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2456 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2457 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2458 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2459 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2460 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2461 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2462 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2463 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2464 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2465 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2466 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2467 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2468 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2469 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2470 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2471 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2472 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2473 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2474 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2475 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2476 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2477 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2478 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2479 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2480 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2481 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2482 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2483 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2484 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2485 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2486 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2487 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2488 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2489 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2490 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2491 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2492 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2493 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2494 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2495 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2496 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2497 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2498 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2499 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2500 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2501 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2502 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2503 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2504 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2505 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2506 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2507 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2508 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2509 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2510 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2511 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2513 /* Common functions */
2515 extern int radeon_gpu_reset(struct radeon_device *rdev);
2516 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2517 extern void radeon_agp_disable(struct radeon_device *rdev);
2518 extern int radeon_modeset_init(struct radeon_device *rdev);
2519 extern void radeon_modeset_fini(struct radeon_device *rdev);
2520 extern bool radeon_card_posted(struct radeon_device *rdev);
2521 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2522 extern void radeon_update_display_priority(struct radeon_device *rdev);
2523 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2524 extern void radeon_scratch_init(struct radeon_device *rdev);
2525 extern void radeon_wb_fini(struct radeon_device *rdev);
2526 extern int radeon_wb_init(struct radeon_device *rdev);
2527 extern void radeon_wb_disable(struct radeon_device *rdev);
2528 extern void radeon_surface_init(struct radeon_device *rdev);
2529 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2530 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2531 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2532 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2533 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2534 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2535 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2536 extern int radeon_resume_kms(struct drm_device *dev);
2537 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
2538 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2539 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2540 const u32 *registers,
2541 const u32 array_size);
2546 int radeon_vm_manager_init(struct radeon_device *rdev);
2547 void radeon_vm_manager_fini(struct radeon_device *rdev);
2548 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2549 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2550 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2551 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2552 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2553 struct radeon_vm *vm, int ring);
2554 void radeon_vm_fence(struct radeon_device *rdev,
2555 struct radeon_vm *vm,
2556 struct radeon_fence *fence);
2557 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2558 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2559 struct radeon_vm *vm,
2560 struct radeon_bo *bo,
2561 struct ttm_mem_reg *mem);
2562 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2563 struct radeon_bo *bo);
2564 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2565 struct radeon_bo *bo);
2566 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2567 struct radeon_vm *vm,
2568 struct radeon_bo *bo);
2569 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2570 struct radeon_bo_va *bo_va,
2573 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2574 struct radeon_bo_va *bo_va);
2577 void r600_audio_update_hdmi(struct work_struct *work);
2580 * R600 vram scratch functions
2582 int r600_vram_scratch_init(struct radeon_device *rdev);
2583 void r600_vram_scratch_fini(struct radeon_device *rdev);
2586 * r600 cs checking helper
2588 unsigned r600_mip_minify(unsigned size, unsigned level);
2589 bool r600_fmt_is_valid_color(u32 format);
2590 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2591 int r600_fmt_get_blocksize(u32 format);
2592 int r600_fmt_get_nblocksx(u32 format, u32 w);
2593 int r600_fmt_get_nblocksy(u32 format, u32 h);
2596 * r600 functions used by radeon_encoder.c
2598 struct radeon_hdmi_acr {
2612 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2614 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2615 u32 tiling_pipe_num,
2617 u32 total_max_rb_num,
2618 u32 enabled_rb_mask);
2621 * evergreen functions used by radeon_encoder.c
2624 extern int ni_init_microcode(struct radeon_device *rdev);
2625 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2628 #if defined(CONFIG_ACPI)
2629 extern int radeon_acpi_init(struct radeon_device *rdev);
2630 extern void radeon_acpi_fini(struct radeon_device *rdev);
2631 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2632 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2633 u8 perf_req, bool advertise);
2634 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2636 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2637 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2640 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2641 struct radeon_cs_packet *pkt,
2643 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2644 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2645 struct radeon_cs_packet *pkt);
2646 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2647 struct radeon_cs_reloc **cs_reloc,
2649 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2650 uint32_t *vline_start_end,
2651 uint32_t *vline_status);
2653 #include "radeon_object.h"