2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
32 #include <linux/module.h>
34 #include <drm/radeon_drm.h>
36 #include "radeon_asic.h"
37 #include "radeon_mode.h"
42 #define PFP_UCODE_SIZE 576
43 #define PM4_UCODE_SIZE 1792
44 #define RLC_UCODE_SIZE 768
45 #define R700_PFP_UCODE_SIZE 848
46 #define R700_PM4_UCODE_SIZE 1360
47 #define R700_RLC_UCODE_SIZE 1024
48 #define EVERGREEN_PFP_UCODE_SIZE 1120
49 #define EVERGREEN_PM4_UCODE_SIZE 1376
50 #define EVERGREEN_RLC_UCODE_SIZE 768
51 #define CAYMAN_RLC_UCODE_SIZE 1024
52 #define ARUBA_RLC_UCODE_SIZE 1536
55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
56 MODULE_FIRMWARE("radeon/R600_me.bin");
57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV610_me.bin");
59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV630_me.bin");
61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV620_me.bin");
63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV635_me.bin");
65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV670_me.bin");
67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68 MODULE_FIRMWARE("radeon/RS780_me.bin");
69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70 MODULE_FIRMWARE("radeon/RV770_me.bin");
71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72 MODULE_FIRMWARE("radeon/RV730_me.bin");
73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74 MODULE_FIRMWARE("radeon/RV710_me.bin");
75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90 MODULE_FIRMWARE("radeon/PALM_me.bin");
91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
97 static const u32 crtc_offsets[2] =
100 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
103 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
105 /* r600,rv610,rv630,rv620,rv635,rv670 */
106 int r600_mc_wait_for_idle(struct radeon_device *rdev);
107 static void r600_gpu_init(struct radeon_device *rdev);
108 void r600_fini(struct radeon_device *rdev);
109 void r600_irq_disable(struct radeon_device *rdev);
110 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
113 * r600_get_xclk - get the xclk
115 * @rdev: radeon_device pointer
117 * Returns the reference clock used by the gfx engine
118 * (r6xx, IGPs, APUs).
120 u32 r600_get_xclk(struct radeon_device *rdev)
122 return rdev->clock.spll.reference_freq;
125 /* get temperature in millidegrees */
126 int rv6xx_get_temp(struct radeon_device *rdev)
128 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
130 int actual_temp = temp & 0xff;
135 return actual_temp * 1000;
138 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
142 rdev->pm.dynpm_can_upclock = true;
143 rdev->pm.dynpm_can_downclock = true;
145 /* power state array is low to high, default is first */
146 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
147 int min_power_state_index = 0;
149 if (rdev->pm.num_power_states > 2)
150 min_power_state_index = 1;
152 switch (rdev->pm.dynpm_planned_action) {
153 case DYNPM_ACTION_MINIMUM:
154 rdev->pm.requested_power_state_index = min_power_state_index;
155 rdev->pm.requested_clock_mode_index = 0;
156 rdev->pm.dynpm_can_downclock = false;
158 case DYNPM_ACTION_DOWNCLOCK:
159 if (rdev->pm.current_power_state_index == min_power_state_index) {
160 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
161 rdev->pm.dynpm_can_downclock = false;
163 if (rdev->pm.active_crtc_count > 1) {
164 for (i = 0; i < rdev->pm.num_power_states; i++) {
165 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
167 else if (i >= rdev->pm.current_power_state_index) {
168 rdev->pm.requested_power_state_index =
169 rdev->pm.current_power_state_index;
172 rdev->pm.requested_power_state_index = i;
177 if (rdev->pm.current_power_state_index == 0)
178 rdev->pm.requested_power_state_index =
179 rdev->pm.num_power_states - 1;
181 rdev->pm.requested_power_state_index =
182 rdev->pm.current_power_state_index - 1;
185 rdev->pm.requested_clock_mode_index = 0;
186 /* don't use the power state if crtcs are active and no display flag is set */
187 if ((rdev->pm.active_crtc_count > 0) &&
188 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
189 clock_info[rdev->pm.requested_clock_mode_index].flags &
190 RADEON_PM_MODE_NO_DISPLAY)) {
191 rdev->pm.requested_power_state_index++;
194 case DYNPM_ACTION_UPCLOCK:
195 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
196 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
197 rdev->pm.dynpm_can_upclock = false;
199 if (rdev->pm.active_crtc_count > 1) {
200 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
201 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
203 else if (i <= rdev->pm.current_power_state_index) {
204 rdev->pm.requested_power_state_index =
205 rdev->pm.current_power_state_index;
208 rdev->pm.requested_power_state_index = i;
213 rdev->pm.requested_power_state_index =
214 rdev->pm.current_power_state_index + 1;
216 rdev->pm.requested_clock_mode_index = 0;
218 case DYNPM_ACTION_DEFAULT:
219 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
220 rdev->pm.requested_clock_mode_index = 0;
221 rdev->pm.dynpm_can_upclock = false;
223 case DYNPM_ACTION_NONE:
225 DRM_ERROR("Requested mode for not defined action\n");
229 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
230 /* for now just select the first power state and switch between clock modes */
231 /* power state array is low to high, default is first (0) */
232 if (rdev->pm.active_crtc_count > 1) {
233 rdev->pm.requested_power_state_index = -1;
234 /* start at 1 as we don't want the default mode */
235 for (i = 1; i < rdev->pm.num_power_states; i++) {
236 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
238 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
239 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
240 rdev->pm.requested_power_state_index = i;
244 /* if nothing selected, grab the default state. */
245 if (rdev->pm.requested_power_state_index == -1)
246 rdev->pm.requested_power_state_index = 0;
248 rdev->pm.requested_power_state_index = 1;
250 switch (rdev->pm.dynpm_planned_action) {
251 case DYNPM_ACTION_MINIMUM:
252 rdev->pm.requested_clock_mode_index = 0;
253 rdev->pm.dynpm_can_downclock = false;
255 case DYNPM_ACTION_DOWNCLOCK:
256 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
257 if (rdev->pm.current_clock_mode_index == 0) {
258 rdev->pm.requested_clock_mode_index = 0;
259 rdev->pm.dynpm_can_downclock = false;
261 rdev->pm.requested_clock_mode_index =
262 rdev->pm.current_clock_mode_index - 1;
264 rdev->pm.requested_clock_mode_index = 0;
265 rdev->pm.dynpm_can_downclock = false;
267 /* don't use the power state if crtcs are active and no display flag is set */
268 if ((rdev->pm.active_crtc_count > 0) &&
269 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
270 clock_info[rdev->pm.requested_clock_mode_index].flags &
271 RADEON_PM_MODE_NO_DISPLAY)) {
272 rdev->pm.requested_clock_mode_index++;
275 case DYNPM_ACTION_UPCLOCK:
276 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
277 if (rdev->pm.current_clock_mode_index ==
278 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
279 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
280 rdev->pm.dynpm_can_upclock = false;
282 rdev->pm.requested_clock_mode_index =
283 rdev->pm.current_clock_mode_index + 1;
285 rdev->pm.requested_clock_mode_index =
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
287 rdev->pm.dynpm_can_upclock = false;
290 case DYNPM_ACTION_DEFAULT:
291 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
292 rdev->pm.requested_clock_mode_index = 0;
293 rdev->pm.dynpm_can_upclock = false;
295 case DYNPM_ACTION_NONE:
297 DRM_ERROR("Requested mode for not defined action\n");
302 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
303 rdev->pm.power_state[rdev->pm.requested_power_state_index].
304 clock_info[rdev->pm.requested_clock_mode_index].sclk,
305 rdev->pm.power_state[rdev->pm.requested_power_state_index].
306 clock_info[rdev->pm.requested_clock_mode_index].mclk,
307 rdev->pm.power_state[rdev->pm.requested_power_state_index].
311 void rs780_pm_init_profile(struct radeon_device *rdev)
313 if (rdev->pm.num_power_states == 2) {
315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
349 } else if (rdev->pm.num_power_states == 3) {
351 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
352 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
353 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
356 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
357 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
358 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
359 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
362 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
363 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
364 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
366 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
367 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
368 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
369 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
372 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
373 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
374 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
377 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
378 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
379 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
382 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
384 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
388 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
389 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
392 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
393 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
394 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
397 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
398 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
399 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
400 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
402 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
403 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
404 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
405 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
407 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
408 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
409 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
410 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
412 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
413 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
414 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
415 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
417 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
418 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
419 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
420 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
424 void r600_pm_init_profile(struct radeon_device *rdev)
428 if (rdev->family == CHIP_R600) {
431 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
432 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
434 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
436 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
437 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
439 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
441 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
442 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
444 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
446 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
447 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
448 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
449 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
451 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
452 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
453 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
454 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
456 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
457 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
458 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
459 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
461 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
462 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
463 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
464 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
466 if (rdev->pm.num_power_states < 4) {
468 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
469 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
470 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
471 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
473 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
474 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
475 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
476 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
478 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
479 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
480 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
481 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
483 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
484 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
485 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
486 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
488 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
489 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
490 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
491 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
493 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
494 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
495 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
496 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
498 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
499 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
500 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
501 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
504 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
505 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
506 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
507 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
509 if (rdev->flags & RADEON_IS_MOBILITY)
510 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
512 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
513 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
514 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
515 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
516 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
518 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
519 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
520 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
523 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
524 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
525 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
526 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
527 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
529 if (rdev->flags & RADEON_IS_MOBILITY)
530 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
532 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
533 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
534 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
535 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
536 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
538 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
539 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
540 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
541 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
543 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
544 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
545 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
546 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
547 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
552 void r600_pm_misc(struct radeon_device *rdev)
554 int req_ps_idx = rdev->pm.requested_power_state_index;
555 int req_cm_idx = rdev->pm.requested_clock_mode_index;
556 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
557 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
559 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
560 /* 0xff01 is a flag rather then an actual voltage */
561 if (voltage->voltage == 0xff01)
563 if (voltage->voltage != rdev->pm.current_vddc) {
564 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
565 rdev->pm.current_vddc = voltage->voltage;
566 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
571 bool r600_gui_idle(struct radeon_device *rdev)
573 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
579 /* hpd for digital panel detect/disconnect */
580 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
582 bool connected = false;
584 if (ASIC_IS_DCE3(rdev)) {
587 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
591 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
595 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
599 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
604 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
608 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
617 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
621 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
625 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
635 void r600_hpd_set_polarity(struct radeon_device *rdev,
636 enum radeon_hpd_id hpd)
639 bool connected = r600_hpd_sense(rdev, hpd);
641 if (ASIC_IS_DCE3(rdev)) {
644 tmp = RREG32(DC_HPD1_INT_CONTROL);
646 tmp &= ~DC_HPDx_INT_POLARITY;
648 tmp |= DC_HPDx_INT_POLARITY;
649 WREG32(DC_HPD1_INT_CONTROL, tmp);
652 tmp = RREG32(DC_HPD2_INT_CONTROL);
654 tmp &= ~DC_HPDx_INT_POLARITY;
656 tmp |= DC_HPDx_INT_POLARITY;
657 WREG32(DC_HPD2_INT_CONTROL, tmp);
660 tmp = RREG32(DC_HPD3_INT_CONTROL);
662 tmp &= ~DC_HPDx_INT_POLARITY;
664 tmp |= DC_HPDx_INT_POLARITY;
665 WREG32(DC_HPD3_INT_CONTROL, tmp);
668 tmp = RREG32(DC_HPD4_INT_CONTROL);
670 tmp &= ~DC_HPDx_INT_POLARITY;
672 tmp |= DC_HPDx_INT_POLARITY;
673 WREG32(DC_HPD4_INT_CONTROL, tmp);
676 tmp = RREG32(DC_HPD5_INT_CONTROL);
678 tmp &= ~DC_HPDx_INT_POLARITY;
680 tmp |= DC_HPDx_INT_POLARITY;
681 WREG32(DC_HPD5_INT_CONTROL, tmp);
685 tmp = RREG32(DC_HPD6_INT_CONTROL);
687 tmp &= ~DC_HPDx_INT_POLARITY;
689 tmp |= DC_HPDx_INT_POLARITY;
690 WREG32(DC_HPD6_INT_CONTROL, tmp);
698 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
700 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
702 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
703 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
706 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
708 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
710 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
711 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
714 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
716 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
718 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
719 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
727 void r600_hpd_init(struct radeon_device *rdev)
729 struct drm_device *dev = rdev->ddev;
730 struct drm_connector *connector;
733 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
734 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
736 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
737 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
738 /* don't try to enable hpd on eDP or LVDS avoid breaking the
739 * aux dp channel on imac and help (but not completely fix)
740 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
744 if (ASIC_IS_DCE3(rdev)) {
745 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
746 if (ASIC_IS_DCE32(rdev))
749 switch (radeon_connector->hpd.hpd) {
751 WREG32(DC_HPD1_CONTROL, tmp);
754 WREG32(DC_HPD2_CONTROL, tmp);
757 WREG32(DC_HPD3_CONTROL, tmp);
760 WREG32(DC_HPD4_CONTROL, tmp);
764 WREG32(DC_HPD5_CONTROL, tmp);
767 WREG32(DC_HPD6_CONTROL, tmp);
773 switch (radeon_connector->hpd.hpd) {
775 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
778 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
781 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
787 enable |= 1 << radeon_connector->hpd.hpd;
788 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
790 radeon_irq_kms_enable_hpd(rdev, enable);
793 void r600_hpd_fini(struct radeon_device *rdev)
795 struct drm_device *dev = rdev->ddev;
796 struct drm_connector *connector;
797 unsigned disable = 0;
799 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
800 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
801 if (ASIC_IS_DCE3(rdev)) {
802 switch (radeon_connector->hpd.hpd) {
804 WREG32(DC_HPD1_CONTROL, 0);
807 WREG32(DC_HPD2_CONTROL, 0);
810 WREG32(DC_HPD3_CONTROL, 0);
813 WREG32(DC_HPD4_CONTROL, 0);
817 WREG32(DC_HPD5_CONTROL, 0);
820 WREG32(DC_HPD6_CONTROL, 0);
826 switch (radeon_connector->hpd.hpd) {
828 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
831 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
834 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
840 disable |= 1 << radeon_connector->hpd.hpd;
842 radeon_irq_kms_disable_hpd(rdev, disable);
848 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
853 /* flush hdp cache so updates hit vram */
854 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
855 !(rdev->flags & RADEON_IS_AGP)) {
856 void __iomem *ptr = (void *)rdev->gart.ptr;
859 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
860 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
861 * This seems to cause problems on some AGP cards. Just use the old
864 WREG32(HDP_DEBUG1, 0);
865 tmp = readl((void __iomem *)ptr);
867 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
869 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
870 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
871 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
872 for (i = 0; i < rdev->usec_timeout; i++) {
874 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
875 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
877 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
887 int r600_pcie_gart_init(struct radeon_device *rdev)
891 if (rdev->gart.robj) {
892 WARN(1, "R600 PCIE GART already initialized\n");
895 /* Initialize common gart structure */
896 r = radeon_gart_init(rdev);
899 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
900 return radeon_gart_table_vram_alloc(rdev);
903 static int r600_pcie_gart_enable(struct radeon_device *rdev)
908 if (rdev->gart.robj == NULL) {
909 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
912 r = radeon_gart_table_vram_pin(rdev);
915 radeon_gart_restore(rdev);
918 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
919 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
920 EFFECTIVE_L2_QUEUE_SIZE(7));
921 WREG32(VM_L2_CNTL2, 0);
922 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
923 /* Setup TLB control */
924 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
925 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
926 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
927 ENABLE_WAIT_L2_QUERY;
928 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
929 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
930 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
931 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
932 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
933 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
934 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
935 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
936 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
937 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
938 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
939 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
940 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
941 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
942 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
943 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
944 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
945 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
946 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
947 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
948 (u32)(rdev->dummy_page.addr >> 12));
949 for (i = 1; i < 7; i++)
950 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
952 r600_pcie_gart_tlb_flush(rdev);
953 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
954 (unsigned)(rdev->mc.gtt_size >> 20),
955 (unsigned long long)rdev->gart.table_addr);
956 rdev->gart.ready = true;
960 static void r600_pcie_gart_disable(struct radeon_device *rdev)
965 /* Disable all tables */
966 for (i = 0; i < 7; i++)
967 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
969 /* Disable L2 cache */
970 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
971 EFFECTIVE_L2_QUEUE_SIZE(7));
972 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
973 /* Setup L1 TLB control */
974 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
975 ENABLE_WAIT_L2_QUERY;
976 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
980 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
981 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
982 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
983 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
984 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
985 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
986 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
987 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
988 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
989 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
990 radeon_gart_table_vram_unpin(rdev);
993 static void r600_pcie_gart_fini(struct radeon_device *rdev)
995 radeon_gart_fini(rdev);
996 r600_pcie_gart_disable(rdev);
997 radeon_gart_table_vram_free(rdev);
1000 static void r600_agp_enable(struct radeon_device *rdev)
1005 /* Setup L2 cache */
1006 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1007 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1008 EFFECTIVE_L2_QUEUE_SIZE(7));
1009 WREG32(VM_L2_CNTL2, 0);
1010 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1011 /* Setup TLB control */
1012 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1013 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1014 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1015 ENABLE_WAIT_L2_QUERY;
1016 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1017 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1018 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1019 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1020 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1021 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1022 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1023 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1024 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1025 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1026 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1027 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1028 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1029 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1030 for (i = 0; i < 7; i++)
1031 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1034 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1039 for (i = 0; i < rdev->usec_timeout; i++) {
1040 /* read MC_STATUS */
1041 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1049 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1053 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1054 r = RREG32(R_0028FC_MC_DATA);
1055 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1059 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1061 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1062 S_0028F8_MC_IND_WR_EN(1));
1063 WREG32(R_0028FC_MC_DATA, v);
1064 WREG32(R_0028F8_MC_INDEX, 0x7F);
1067 static void r600_mc_program(struct radeon_device *rdev)
1069 struct rv515_mc_save save;
1073 /* Initialize HDP */
1074 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1075 WREG32((0x2c14 + j), 0x00000000);
1076 WREG32((0x2c18 + j), 0x00000000);
1077 WREG32((0x2c1c + j), 0x00000000);
1078 WREG32((0x2c20 + j), 0x00000000);
1079 WREG32((0x2c24 + j), 0x00000000);
1081 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1083 rv515_mc_stop(rdev, &save);
1084 if (r600_mc_wait_for_idle(rdev)) {
1085 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1087 /* Lockout access through VGA aperture (doesn't exist before R600) */
1088 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1089 /* Update configuration */
1090 if (rdev->flags & RADEON_IS_AGP) {
1091 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1092 /* VRAM before AGP */
1093 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1094 rdev->mc.vram_start >> 12);
1095 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1096 rdev->mc.gtt_end >> 12);
1098 /* VRAM after AGP */
1099 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1100 rdev->mc.gtt_start >> 12);
1101 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1102 rdev->mc.vram_end >> 12);
1105 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1106 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1108 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1109 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1110 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1111 WREG32(MC_VM_FB_LOCATION, tmp);
1112 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1113 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1114 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1115 if (rdev->flags & RADEON_IS_AGP) {
1116 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1117 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1118 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1120 WREG32(MC_VM_AGP_BASE, 0);
1121 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1122 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1124 if (r600_mc_wait_for_idle(rdev)) {
1125 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1127 rv515_mc_resume(rdev, &save);
1128 /* we need to own VRAM, so turn off the VGA renderer here
1129 * to stop it overwriting our objects */
1130 rv515_vga_render_disable(rdev);
1134 * r600_vram_gtt_location - try to find VRAM & GTT location
1135 * @rdev: radeon device structure holding all necessary informations
1136 * @mc: memory controller structure holding memory informations
1138 * Function will place try to place VRAM at same place as in CPU (PCI)
1139 * address space as some GPU seems to have issue when we reprogram at
1140 * different address space.
1142 * If there is not enough space to fit the unvisible VRAM after the
1143 * aperture then we limit the VRAM size to the aperture.
1145 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1146 * them to be in one from GPU point of view so that we can program GPU to
1147 * catch access outside them (weird GPU policy see ??).
1149 * This function will never fails, worst case are limiting VRAM or GTT.
1151 * Note: GTT start, end, size should be initialized before calling this
1152 * function on AGP platform.
1154 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1156 u64 size_bf, size_af;
1158 if (mc->mc_vram_size > 0xE0000000) {
1159 /* leave room for at least 512M GTT */
1160 dev_warn(rdev->dev, "limiting VRAM\n");
1161 mc->real_vram_size = 0xE0000000;
1162 mc->mc_vram_size = 0xE0000000;
1164 if (rdev->flags & RADEON_IS_AGP) {
1165 size_bf = mc->gtt_start;
1166 size_af = mc->mc_mask - mc->gtt_end;
1167 if (size_bf > size_af) {
1168 if (mc->mc_vram_size > size_bf) {
1169 dev_warn(rdev->dev, "limiting VRAM\n");
1170 mc->real_vram_size = size_bf;
1171 mc->mc_vram_size = size_bf;
1173 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1175 if (mc->mc_vram_size > size_af) {
1176 dev_warn(rdev->dev, "limiting VRAM\n");
1177 mc->real_vram_size = size_af;
1178 mc->mc_vram_size = size_af;
1180 mc->vram_start = mc->gtt_end + 1;
1182 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1183 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1184 mc->mc_vram_size >> 20, mc->vram_start,
1185 mc->vram_end, mc->real_vram_size >> 20);
1188 if (rdev->flags & RADEON_IS_IGP) {
1189 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1192 radeon_vram_location(rdev, &rdev->mc, base);
1193 rdev->mc.gtt_base_align = 0;
1194 radeon_gtt_location(rdev, mc);
1198 static int r600_mc_init(struct radeon_device *rdev)
1201 int chansize, numchan;
1202 uint32_t h_addr, l_addr;
1203 unsigned long long k8_addr;
1205 /* Get VRAM informations */
1206 rdev->mc.vram_is_ddr = true;
1207 tmp = RREG32(RAMCFG);
1208 if (tmp & CHANSIZE_OVERRIDE) {
1210 } else if (tmp & CHANSIZE_MASK) {
1215 tmp = RREG32(CHMAP);
1216 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1231 rdev->mc.vram_width = numchan * chansize;
1232 /* Could aper size report 0 ? */
1233 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1234 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1235 /* Setup GPU memory space */
1236 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1237 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1238 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1239 r600_vram_gtt_location(rdev, &rdev->mc);
1241 if (rdev->flags & RADEON_IS_IGP) {
1242 rs690_pm_info(rdev);
1243 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1245 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1246 /* Use K8 direct mapping for fast fb access. */
1247 rdev->fastfb_working = false;
1248 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1249 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1250 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1251 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1252 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1255 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1256 * memory is present.
1258 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1259 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1260 (unsigned long long)rdev->mc.aper_base, k8_addr);
1261 rdev->mc.aper_base = (resource_size_t)k8_addr;
1262 rdev->fastfb_working = true;
1268 radeon_update_bandwidth_info(rdev);
1272 int r600_vram_scratch_init(struct radeon_device *rdev)
1276 if (rdev->vram_scratch.robj == NULL) {
1277 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1278 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1279 NULL, &rdev->vram_scratch.robj);
1285 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1286 if (unlikely(r != 0))
1288 r = radeon_bo_pin(rdev->vram_scratch.robj,
1289 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1291 radeon_bo_unreserve(rdev->vram_scratch.robj);
1294 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1295 (void **)&rdev->vram_scratch.ptr);
1297 radeon_bo_unpin(rdev->vram_scratch.robj);
1298 radeon_bo_unreserve(rdev->vram_scratch.robj);
1303 void r600_vram_scratch_fini(struct radeon_device *rdev)
1307 if (rdev->vram_scratch.robj == NULL) {
1310 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1311 if (likely(r == 0)) {
1312 radeon_bo_kunmap(rdev->vram_scratch.robj);
1313 radeon_bo_unpin(rdev->vram_scratch.robj);
1314 radeon_bo_unreserve(rdev->vram_scratch.robj);
1316 radeon_bo_unref(&rdev->vram_scratch.robj);
1319 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1321 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1324 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1326 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1328 WREG32(R600_BIOS_3_SCRATCH, tmp);
1331 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1333 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1334 RREG32(R_008010_GRBM_STATUS));
1335 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1336 RREG32(R_008014_GRBM_STATUS2));
1337 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1338 RREG32(R_000E50_SRBM_STATUS));
1339 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1340 RREG32(CP_STALLED_STAT1));
1341 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1342 RREG32(CP_STALLED_STAT2));
1343 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1344 RREG32(CP_BUSY_STAT));
1345 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1347 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1348 RREG32(DMA_STATUS_REG));
1351 static bool r600_is_display_hung(struct radeon_device *rdev)
1357 for (i = 0; i < rdev->num_crtc; i++) {
1358 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1359 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1360 crtc_hung |= (1 << i);
1364 for (j = 0; j < 10; j++) {
1365 for (i = 0; i < rdev->num_crtc; i++) {
1366 if (crtc_hung & (1 << i)) {
1367 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1368 if (tmp != crtc_status[i])
1369 crtc_hung &= ~(1 << i);
1380 static u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1386 tmp = RREG32(R_008010_GRBM_STATUS);
1387 if (rdev->family >= CHIP_RV770) {
1388 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1389 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1390 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1391 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1392 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1393 reset_mask |= RADEON_RESET_GFX;
1395 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1396 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1397 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1398 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1399 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1400 reset_mask |= RADEON_RESET_GFX;
1403 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1404 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1405 reset_mask |= RADEON_RESET_CP;
1407 if (G_008010_GRBM_EE_BUSY(tmp))
1408 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1410 /* DMA_STATUS_REG */
1411 tmp = RREG32(DMA_STATUS_REG);
1412 if (!(tmp & DMA_IDLE))
1413 reset_mask |= RADEON_RESET_DMA;
1416 tmp = RREG32(R_000E50_SRBM_STATUS);
1417 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1418 reset_mask |= RADEON_RESET_RLC;
1420 if (G_000E50_IH_BUSY(tmp))
1421 reset_mask |= RADEON_RESET_IH;
1423 if (G_000E50_SEM_BUSY(tmp))
1424 reset_mask |= RADEON_RESET_SEM;
1426 if (G_000E50_GRBM_RQ_PENDING(tmp))
1427 reset_mask |= RADEON_RESET_GRBM;
1429 if (G_000E50_VMC_BUSY(tmp))
1430 reset_mask |= RADEON_RESET_VMC;
1432 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1433 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1434 G_000E50_MCDW_BUSY(tmp))
1435 reset_mask |= RADEON_RESET_MC;
1437 if (r600_is_display_hung(rdev))
1438 reset_mask |= RADEON_RESET_DISPLAY;
1440 /* Skip MC reset as it's mostly likely not hung, just busy */
1441 if (reset_mask & RADEON_RESET_MC) {
1442 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1443 reset_mask &= ~RADEON_RESET_MC;
1449 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1451 struct rv515_mc_save save;
1452 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1455 if (reset_mask == 0)
1458 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1460 r600_print_gpu_status_regs(rdev);
1462 /* Disable CP parsing/prefetching */
1463 if (rdev->family >= CHIP_RV770)
1464 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1466 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1468 /* disable the RLC */
1469 WREG32(RLC_CNTL, 0);
1471 if (reset_mask & RADEON_RESET_DMA) {
1473 tmp = RREG32(DMA_RB_CNTL);
1474 tmp &= ~DMA_RB_ENABLE;
1475 WREG32(DMA_RB_CNTL, tmp);
1480 rv515_mc_stop(rdev, &save);
1481 if (r600_mc_wait_for_idle(rdev)) {
1482 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1485 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1486 if (rdev->family >= CHIP_RV770)
1487 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1488 S_008020_SOFT_RESET_CB(1) |
1489 S_008020_SOFT_RESET_PA(1) |
1490 S_008020_SOFT_RESET_SC(1) |
1491 S_008020_SOFT_RESET_SPI(1) |
1492 S_008020_SOFT_RESET_SX(1) |
1493 S_008020_SOFT_RESET_SH(1) |
1494 S_008020_SOFT_RESET_TC(1) |
1495 S_008020_SOFT_RESET_TA(1) |
1496 S_008020_SOFT_RESET_VC(1) |
1497 S_008020_SOFT_RESET_VGT(1);
1499 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1500 S_008020_SOFT_RESET_DB(1) |
1501 S_008020_SOFT_RESET_CB(1) |
1502 S_008020_SOFT_RESET_PA(1) |
1503 S_008020_SOFT_RESET_SC(1) |
1504 S_008020_SOFT_RESET_SMX(1) |
1505 S_008020_SOFT_RESET_SPI(1) |
1506 S_008020_SOFT_RESET_SX(1) |
1507 S_008020_SOFT_RESET_SH(1) |
1508 S_008020_SOFT_RESET_TC(1) |
1509 S_008020_SOFT_RESET_TA(1) |
1510 S_008020_SOFT_RESET_VC(1) |
1511 S_008020_SOFT_RESET_VGT(1);
1514 if (reset_mask & RADEON_RESET_CP) {
1515 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1516 S_008020_SOFT_RESET_VGT(1);
1518 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1521 if (reset_mask & RADEON_RESET_DMA) {
1522 if (rdev->family >= CHIP_RV770)
1523 srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1525 srbm_soft_reset |= SOFT_RESET_DMA;
1528 if (reset_mask & RADEON_RESET_RLC)
1529 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1531 if (reset_mask & RADEON_RESET_SEM)
1532 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1534 if (reset_mask & RADEON_RESET_IH)
1535 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1537 if (reset_mask & RADEON_RESET_GRBM)
1538 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1540 if (!(rdev->flags & RADEON_IS_IGP)) {
1541 if (reset_mask & RADEON_RESET_MC)
1542 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1545 if (reset_mask & RADEON_RESET_VMC)
1546 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1548 if (grbm_soft_reset) {
1549 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1550 tmp |= grbm_soft_reset;
1551 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1552 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1553 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1557 tmp &= ~grbm_soft_reset;
1558 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1559 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1562 if (srbm_soft_reset) {
1563 tmp = RREG32(SRBM_SOFT_RESET);
1564 tmp |= srbm_soft_reset;
1565 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1566 WREG32(SRBM_SOFT_RESET, tmp);
1567 tmp = RREG32(SRBM_SOFT_RESET);
1571 tmp &= ~srbm_soft_reset;
1572 WREG32(SRBM_SOFT_RESET, tmp);
1573 tmp = RREG32(SRBM_SOFT_RESET);
1576 /* Wait a little for things to settle down */
1579 rv515_mc_resume(rdev, &save);
1582 r600_print_gpu_status_regs(rdev);
1585 int r600_asic_reset(struct radeon_device *rdev)
1589 reset_mask = r600_gpu_check_soft_reset(rdev);
1592 r600_set_bios_scratch_engine_hung(rdev, true);
1594 r600_gpu_soft_reset(rdev, reset_mask);
1596 reset_mask = r600_gpu_check_soft_reset(rdev);
1599 r600_set_bios_scratch_engine_hung(rdev, false);
1605 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1607 * @rdev: radeon_device pointer
1608 * @ring: radeon_ring structure holding ring information
1610 * Check if the GFX engine is locked up.
1611 * Returns true if the engine appears to be locked up, false if not.
1613 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1615 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1617 if (!(reset_mask & (RADEON_RESET_GFX |
1618 RADEON_RESET_COMPUTE |
1619 RADEON_RESET_CP))) {
1620 radeon_ring_lockup_update(ring);
1623 /* force CP activities */
1624 radeon_ring_force_activity(rdev, ring);
1625 return radeon_ring_test_lockup(rdev, ring);
1629 * r600_dma_is_lockup - Check if the DMA engine is locked up
1631 * @rdev: radeon_device pointer
1632 * @ring: radeon_ring structure holding ring information
1634 * Check if the async DMA engine is locked up.
1635 * Returns true if the engine appears to be locked up, false if not.
1637 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1639 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1641 if (!(reset_mask & RADEON_RESET_DMA)) {
1642 radeon_ring_lockup_update(ring);
1645 /* force ring activities */
1646 radeon_ring_force_activity(rdev, ring);
1647 return radeon_ring_test_lockup(rdev, ring);
1650 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1651 u32 tiling_pipe_num,
1653 u32 total_max_rb_num,
1654 u32 disabled_rb_mask)
1656 u32 rendering_pipe_num, rb_num_width, req_rb_num;
1657 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1658 u32 data = 0, mask = 1 << (max_rb_num - 1);
1661 /* mask out the RBs that don't exist on that asic */
1662 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1663 /* make sure at least one RB is available */
1664 if ((tmp & 0xff) != 0xff)
1665 disabled_rb_mask = tmp;
1667 rendering_pipe_num = 1 << tiling_pipe_num;
1668 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1669 BUG_ON(rendering_pipe_num < req_rb_num);
1671 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1672 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1674 if (rdev->family <= CHIP_RV740) {
1682 for (i = 0; i < max_rb_num; i++) {
1683 if (!(mask & disabled_rb_mask)) {
1684 for (j = 0; j < pipe_rb_ratio; j++) {
1685 data <<= rb_num_width;
1686 data |= max_rb_num - i - 1;
1688 if (pipe_rb_remain) {
1689 data <<= rb_num_width;
1690 data |= max_rb_num - i - 1;
1700 int r600_count_pipe_bits(uint32_t val)
1702 return hweight32(val);
1705 static void r600_gpu_init(struct radeon_device *rdev)
1709 u32 cc_rb_backend_disable;
1710 u32 cc_gc_shader_pipe_config;
1714 u32 sq_gpr_resource_mgmt_1 = 0;
1715 u32 sq_gpr_resource_mgmt_2 = 0;
1716 u32 sq_thread_resource_mgmt = 0;
1717 u32 sq_stack_resource_mgmt_1 = 0;
1718 u32 sq_stack_resource_mgmt_2 = 0;
1719 u32 disabled_rb_mask;
1721 rdev->config.r600.tiling_group_size = 256;
1722 switch (rdev->family) {
1724 rdev->config.r600.max_pipes = 4;
1725 rdev->config.r600.max_tile_pipes = 8;
1726 rdev->config.r600.max_simds = 4;
1727 rdev->config.r600.max_backends = 4;
1728 rdev->config.r600.max_gprs = 256;
1729 rdev->config.r600.max_threads = 192;
1730 rdev->config.r600.max_stack_entries = 256;
1731 rdev->config.r600.max_hw_contexts = 8;
1732 rdev->config.r600.max_gs_threads = 16;
1733 rdev->config.r600.sx_max_export_size = 128;
1734 rdev->config.r600.sx_max_export_pos_size = 16;
1735 rdev->config.r600.sx_max_export_smx_size = 128;
1736 rdev->config.r600.sq_num_cf_insts = 2;
1740 rdev->config.r600.max_pipes = 2;
1741 rdev->config.r600.max_tile_pipes = 2;
1742 rdev->config.r600.max_simds = 3;
1743 rdev->config.r600.max_backends = 1;
1744 rdev->config.r600.max_gprs = 128;
1745 rdev->config.r600.max_threads = 192;
1746 rdev->config.r600.max_stack_entries = 128;
1747 rdev->config.r600.max_hw_contexts = 8;
1748 rdev->config.r600.max_gs_threads = 4;
1749 rdev->config.r600.sx_max_export_size = 128;
1750 rdev->config.r600.sx_max_export_pos_size = 16;
1751 rdev->config.r600.sx_max_export_smx_size = 128;
1752 rdev->config.r600.sq_num_cf_insts = 2;
1758 rdev->config.r600.max_pipes = 1;
1759 rdev->config.r600.max_tile_pipes = 1;
1760 rdev->config.r600.max_simds = 2;
1761 rdev->config.r600.max_backends = 1;
1762 rdev->config.r600.max_gprs = 128;
1763 rdev->config.r600.max_threads = 192;
1764 rdev->config.r600.max_stack_entries = 128;
1765 rdev->config.r600.max_hw_contexts = 4;
1766 rdev->config.r600.max_gs_threads = 4;
1767 rdev->config.r600.sx_max_export_size = 128;
1768 rdev->config.r600.sx_max_export_pos_size = 16;
1769 rdev->config.r600.sx_max_export_smx_size = 128;
1770 rdev->config.r600.sq_num_cf_insts = 1;
1773 rdev->config.r600.max_pipes = 4;
1774 rdev->config.r600.max_tile_pipes = 4;
1775 rdev->config.r600.max_simds = 4;
1776 rdev->config.r600.max_backends = 4;
1777 rdev->config.r600.max_gprs = 192;
1778 rdev->config.r600.max_threads = 192;
1779 rdev->config.r600.max_stack_entries = 256;
1780 rdev->config.r600.max_hw_contexts = 8;
1781 rdev->config.r600.max_gs_threads = 16;
1782 rdev->config.r600.sx_max_export_size = 128;
1783 rdev->config.r600.sx_max_export_pos_size = 16;
1784 rdev->config.r600.sx_max_export_smx_size = 128;
1785 rdev->config.r600.sq_num_cf_insts = 2;
1791 /* Initialize HDP */
1792 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1793 WREG32((0x2c14 + j), 0x00000000);
1794 WREG32((0x2c18 + j), 0x00000000);
1795 WREG32((0x2c1c + j), 0x00000000);
1796 WREG32((0x2c20 + j), 0x00000000);
1797 WREG32((0x2c24 + j), 0x00000000);
1800 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1804 ramcfg = RREG32(RAMCFG);
1805 switch (rdev->config.r600.max_tile_pipes) {
1807 tiling_config |= PIPE_TILING(0);
1810 tiling_config |= PIPE_TILING(1);
1813 tiling_config |= PIPE_TILING(2);
1816 tiling_config |= PIPE_TILING(3);
1821 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1822 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1823 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1824 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1826 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1828 tiling_config |= ROW_TILING(3);
1829 tiling_config |= SAMPLE_SPLIT(3);
1831 tiling_config |= ROW_TILING(tmp);
1832 tiling_config |= SAMPLE_SPLIT(tmp);
1834 tiling_config |= BANK_SWAPS(1);
1836 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1837 tmp = R6XX_MAX_BACKENDS -
1838 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1839 if (tmp < rdev->config.r600.max_backends) {
1840 rdev->config.r600.max_backends = tmp;
1843 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1844 tmp = R6XX_MAX_PIPES -
1845 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1846 if (tmp < rdev->config.r600.max_pipes) {
1847 rdev->config.r600.max_pipes = tmp;
1849 tmp = R6XX_MAX_SIMDS -
1850 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1851 if (tmp < rdev->config.r600.max_simds) {
1852 rdev->config.r600.max_simds = tmp;
1855 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1856 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1857 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1858 R6XX_MAX_BACKENDS, disabled_rb_mask);
1859 tiling_config |= tmp << 16;
1860 rdev->config.r600.backend_map = tmp;
1862 rdev->config.r600.tile_config = tiling_config;
1863 WREG32(GB_TILING_CONFIG, tiling_config);
1864 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1865 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1866 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
1868 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1869 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1870 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1872 /* Setup some CP states */
1873 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1874 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1876 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1877 SYNC_WALKER | SYNC_ALIGNER));
1878 /* Setup various GPU states */
1879 if (rdev->family == CHIP_RV670)
1880 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1882 tmp = RREG32(SX_DEBUG_1);
1883 tmp |= SMX_EVENT_RELEASE;
1884 if ((rdev->family > CHIP_R600))
1885 tmp |= ENABLE_NEW_SMX_ADDRESS;
1886 WREG32(SX_DEBUG_1, tmp);
1888 if (((rdev->family) == CHIP_R600) ||
1889 ((rdev->family) == CHIP_RV630) ||
1890 ((rdev->family) == CHIP_RV610) ||
1891 ((rdev->family) == CHIP_RV620) ||
1892 ((rdev->family) == CHIP_RS780) ||
1893 ((rdev->family) == CHIP_RS880)) {
1894 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1896 WREG32(DB_DEBUG, 0);
1898 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1899 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1901 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1902 WREG32(VGT_NUM_INSTANCES, 0);
1904 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1905 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1907 tmp = RREG32(SQ_MS_FIFO_SIZES);
1908 if (((rdev->family) == CHIP_RV610) ||
1909 ((rdev->family) == CHIP_RV620) ||
1910 ((rdev->family) == CHIP_RS780) ||
1911 ((rdev->family) == CHIP_RS880)) {
1912 tmp = (CACHE_FIFO_SIZE(0xa) |
1913 FETCH_FIFO_HIWATER(0xa) |
1914 DONE_FIFO_HIWATER(0xe0) |
1915 ALU_UPDATE_FIFO_HIWATER(0x8));
1916 } else if (((rdev->family) == CHIP_R600) ||
1917 ((rdev->family) == CHIP_RV630)) {
1918 tmp &= ~DONE_FIFO_HIWATER(0xff);
1919 tmp |= DONE_FIFO_HIWATER(0x4);
1921 WREG32(SQ_MS_FIFO_SIZES, tmp);
1923 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1924 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1926 sq_config = RREG32(SQ_CONFIG);
1927 sq_config &= ~(PS_PRIO(3) |
1931 sq_config |= (DX9_CONSTS |
1938 if ((rdev->family) == CHIP_R600) {
1939 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1941 NUM_CLAUSE_TEMP_GPRS(4));
1942 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1944 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1945 NUM_VS_THREADS(48) |
1948 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1949 NUM_VS_STACK_ENTRIES(128));
1950 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1951 NUM_ES_STACK_ENTRIES(0));
1952 } else if (((rdev->family) == CHIP_RV610) ||
1953 ((rdev->family) == CHIP_RV620) ||
1954 ((rdev->family) == CHIP_RS780) ||
1955 ((rdev->family) == CHIP_RS880)) {
1956 /* no vertex cache */
1957 sq_config &= ~VC_ENABLE;
1959 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1961 NUM_CLAUSE_TEMP_GPRS(2));
1962 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1964 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1965 NUM_VS_THREADS(78) |
1967 NUM_ES_THREADS(31));
1968 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1969 NUM_VS_STACK_ENTRIES(40));
1970 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1971 NUM_ES_STACK_ENTRIES(16));
1972 } else if (((rdev->family) == CHIP_RV630) ||
1973 ((rdev->family) == CHIP_RV635)) {
1974 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1976 NUM_CLAUSE_TEMP_GPRS(2));
1977 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1979 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1980 NUM_VS_THREADS(78) |
1982 NUM_ES_THREADS(31));
1983 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1984 NUM_VS_STACK_ENTRIES(40));
1985 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1986 NUM_ES_STACK_ENTRIES(16));
1987 } else if ((rdev->family) == CHIP_RV670) {
1988 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1990 NUM_CLAUSE_TEMP_GPRS(2));
1991 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1993 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1994 NUM_VS_THREADS(78) |
1996 NUM_ES_THREADS(31));
1997 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1998 NUM_VS_STACK_ENTRIES(64));
1999 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2000 NUM_ES_STACK_ENTRIES(64));
2003 WREG32(SQ_CONFIG, sq_config);
2004 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2005 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2006 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2007 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2008 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2010 if (((rdev->family) == CHIP_RV610) ||
2011 ((rdev->family) == CHIP_RV620) ||
2012 ((rdev->family) == CHIP_RS780) ||
2013 ((rdev->family) == CHIP_RS880)) {
2014 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2016 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2019 /* More default values. 2D/3D driver should adjust as needed */
2020 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2021 S1_X(0x4) | S1_Y(0xc)));
2022 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2023 S1_X(0x2) | S1_Y(0x2) |
2024 S2_X(0xa) | S2_Y(0x6) |
2025 S3_X(0x6) | S3_Y(0xa)));
2026 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2027 S1_X(0x4) | S1_Y(0xc) |
2028 S2_X(0x1) | S2_Y(0x6) |
2029 S3_X(0xa) | S3_Y(0xe)));
2030 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2031 S5_X(0x0) | S5_Y(0x0) |
2032 S6_X(0xb) | S6_Y(0x4) |
2033 S7_X(0x7) | S7_Y(0x8)));
2035 WREG32(VGT_STRMOUT_EN, 0);
2036 tmp = rdev->config.r600.max_pipes * 16;
2037 switch (rdev->family) {
2053 WREG32(VGT_ES_PER_GS, 128);
2054 WREG32(VGT_GS_PER_ES, tmp);
2055 WREG32(VGT_GS_PER_VS, 2);
2056 WREG32(VGT_GS_VERTEX_REUSE, 16);
2058 /* more default values. 2D/3D driver should adjust as needed */
2059 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2060 WREG32(VGT_STRMOUT_EN, 0);
2062 WREG32(PA_SC_MODE_CNTL, 0);
2063 WREG32(PA_SC_AA_CONFIG, 0);
2064 WREG32(PA_SC_LINE_STIPPLE, 0);
2065 WREG32(SPI_INPUT_Z, 0);
2066 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2067 WREG32(CB_COLOR7_FRAG, 0);
2069 /* Clear render buffer base addresses */
2070 WREG32(CB_COLOR0_BASE, 0);
2071 WREG32(CB_COLOR1_BASE, 0);
2072 WREG32(CB_COLOR2_BASE, 0);
2073 WREG32(CB_COLOR3_BASE, 0);
2074 WREG32(CB_COLOR4_BASE, 0);
2075 WREG32(CB_COLOR5_BASE, 0);
2076 WREG32(CB_COLOR6_BASE, 0);
2077 WREG32(CB_COLOR7_BASE, 0);
2078 WREG32(CB_COLOR7_FRAG, 0);
2080 switch (rdev->family) {
2085 tmp = TC_L2_SIZE(8);
2089 tmp = TC_L2_SIZE(4);
2092 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2095 tmp = TC_L2_SIZE(0);
2098 WREG32(TC_CNTL, tmp);
2100 tmp = RREG32(HDP_HOST_PATH_CNTL);
2101 WREG32(HDP_HOST_PATH_CNTL, tmp);
2103 tmp = RREG32(ARB_POP);
2104 tmp |= ENABLE_TC128;
2105 WREG32(ARB_POP, tmp);
2107 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2108 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2110 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2111 WREG32(VC_ENHANCE, 0);
2116 * Indirect registers accessor
2118 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2122 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2123 (void)RREG32(PCIE_PORT_INDEX);
2124 r = RREG32(PCIE_PORT_DATA);
2128 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2130 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2131 (void)RREG32(PCIE_PORT_INDEX);
2132 WREG32(PCIE_PORT_DATA, (v));
2133 (void)RREG32(PCIE_PORT_DATA);
2139 void r600_cp_stop(struct radeon_device *rdev)
2141 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2142 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2143 WREG32(SCRATCH_UMSK, 0);
2144 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2147 int r600_init_microcode(struct radeon_device *rdev)
2149 struct platform_device *pdev;
2150 const char *chip_name;
2151 const char *rlc_chip_name;
2152 size_t pfp_req_size, me_req_size, rlc_req_size;
2158 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
2161 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
2165 switch (rdev->family) {
2168 rlc_chip_name = "R600";
2171 chip_name = "RV610";
2172 rlc_chip_name = "R600";
2175 chip_name = "RV630";
2176 rlc_chip_name = "R600";
2179 chip_name = "RV620";
2180 rlc_chip_name = "R600";
2183 chip_name = "RV635";
2184 rlc_chip_name = "R600";
2187 chip_name = "RV670";
2188 rlc_chip_name = "R600";
2192 chip_name = "RS780";
2193 rlc_chip_name = "R600";
2196 chip_name = "RV770";
2197 rlc_chip_name = "R700";
2201 chip_name = "RV730";
2202 rlc_chip_name = "R700";
2205 chip_name = "RV710";
2206 rlc_chip_name = "R700";
2209 chip_name = "CEDAR";
2210 rlc_chip_name = "CEDAR";
2213 chip_name = "REDWOOD";
2214 rlc_chip_name = "REDWOOD";
2217 chip_name = "JUNIPER";
2218 rlc_chip_name = "JUNIPER";
2222 chip_name = "CYPRESS";
2223 rlc_chip_name = "CYPRESS";
2227 rlc_chip_name = "SUMO";
2231 rlc_chip_name = "SUMO";
2234 chip_name = "SUMO2";
2235 rlc_chip_name = "SUMO";
2240 if (rdev->family >= CHIP_CEDAR) {
2241 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2242 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2243 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2244 } else if (rdev->family >= CHIP_RV770) {
2245 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2246 me_req_size = R700_PM4_UCODE_SIZE * 4;
2247 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2249 pfp_req_size = PFP_UCODE_SIZE * 4;
2250 me_req_size = PM4_UCODE_SIZE * 12;
2251 rlc_req_size = RLC_UCODE_SIZE * 4;
2254 DRM_INFO("Loading %s Microcode\n", chip_name);
2256 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2257 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2260 if (rdev->pfp_fw->size != pfp_req_size) {
2262 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2263 rdev->pfp_fw->size, fw_name);
2268 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2269 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2272 if (rdev->me_fw->size != me_req_size) {
2274 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2275 rdev->me_fw->size, fw_name);
2279 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2280 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2283 if (rdev->rlc_fw->size != rlc_req_size) {
2285 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2286 rdev->rlc_fw->size, fw_name);
2291 platform_device_unregister(pdev);
2296 "r600_cp: Failed to load firmware \"%s\"\n",
2298 release_firmware(rdev->pfp_fw);
2299 rdev->pfp_fw = NULL;
2300 release_firmware(rdev->me_fw);
2302 release_firmware(rdev->rlc_fw);
2303 rdev->rlc_fw = NULL;
2308 static int r600_cp_load_microcode(struct radeon_device *rdev)
2310 const __be32 *fw_data;
2313 if (!rdev->me_fw || !rdev->pfp_fw)
2322 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2325 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2326 RREG32(GRBM_SOFT_RESET);
2328 WREG32(GRBM_SOFT_RESET, 0);
2330 WREG32(CP_ME_RAM_WADDR, 0);
2332 fw_data = (const __be32 *)rdev->me_fw->data;
2333 WREG32(CP_ME_RAM_WADDR, 0);
2334 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2335 WREG32(CP_ME_RAM_DATA,
2336 be32_to_cpup(fw_data++));
2338 fw_data = (const __be32 *)rdev->pfp_fw->data;
2339 WREG32(CP_PFP_UCODE_ADDR, 0);
2340 for (i = 0; i < PFP_UCODE_SIZE; i++)
2341 WREG32(CP_PFP_UCODE_DATA,
2342 be32_to_cpup(fw_data++));
2344 WREG32(CP_PFP_UCODE_ADDR, 0);
2345 WREG32(CP_ME_RAM_WADDR, 0);
2346 WREG32(CP_ME_RAM_RADDR, 0);
2350 int r600_cp_start(struct radeon_device *rdev)
2352 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2356 r = radeon_ring_lock(rdev, ring, 7);
2358 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2361 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2362 radeon_ring_write(ring, 0x1);
2363 if (rdev->family >= CHIP_RV770) {
2364 radeon_ring_write(ring, 0x0);
2365 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2367 radeon_ring_write(ring, 0x3);
2368 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2370 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2371 radeon_ring_write(ring, 0);
2372 radeon_ring_write(ring, 0);
2373 radeon_ring_unlock_commit(rdev, ring);
2376 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2380 int r600_cp_resume(struct radeon_device *rdev)
2382 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2388 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2389 RREG32(GRBM_SOFT_RESET);
2391 WREG32(GRBM_SOFT_RESET, 0);
2393 /* Set ring buffer size */
2394 rb_bufsz = drm_order(ring->ring_size / 8);
2395 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2397 tmp |= BUF_SWAP_32BIT;
2399 WREG32(CP_RB_CNTL, tmp);
2400 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2402 /* Set the write pointer delay */
2403 WREG32(CP_RB_WPTR_DELAY, 0);
2405 /* Initialize the ring buffer's read and write pointers */
2406 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2407 WREG32(CP_RB_RPTR_WR, 0);
2409 WREG32(CP_RB_WPTR, ring->wptr);
2411 /* set the wb address whether it's enabled or not */
2412 WREG32(CP_RB_RPTR_ADDR,
2413 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2414 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2415 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2417 if (rdev->wb.enabled)
2418 WREG32(SCRATCH_UMSK, 0xff);
2420 tmp |= RB_NO_UPDATE;
2421 WREG32(SCRATCH_UMSK, 0);
2425 WREG32(CP_RB_CNTL, tmp);
2427 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2428 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2430 ring->rptr = RREG32(CP_RB_RPTR);
2432 r600_cp_start(rdev);
2434 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2436 ring->ready = false;
2442 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2447 /* Align ring size */
2448 rb_bufsz = drm_order(ring_size / 8);
2449 ring_size = (1 << (rb_bufsz + 1)) * 4;
2450 ring->ring_size = ring_size;
2451 ring->align_mask = 16 - 1;
2453 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2454 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2456 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2457 ring->rptr_save_reg = 0;
2462 void r600_cp_fini(struct radeon_device *rdev)
2464 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2466 radeon_ring_fini(rdev, ring);
2467 radeon_scratch_free(rdev, ring->rptr_save_reg);
2472 * Starting with R600, the GPU has an asynchronous
2473 * DMA engine. The programming model is very similar
2474 * to the 3D engine (ring buffer, IBs, etc.), but the
2475 * DMA controller has it's own packet format that is
2476 * different form the PM4 format used by the 3D engine.
2477 * It supports copying data, writing embedded data,
2478 * solid fills, and a number of other things. It also
2479 * has support for tiling/detiling of buffers.
2482 * r600_dma_stop - stop the async dma engine
2484 * @rdev: radeon_device pointer
2486 * Stop the async dma engine (r6xx-evergreen).
2488 void r600_dma_stop(struct radeon_device *rdev)
2490 u32 rb_cntl = RREG32(DMA_RB_CNTL);
2492 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2494 rb_cntl &= ~DMA_RB_ENABLE;
2495 WREG32(DMA_RB_CNTL, rb_cntl);
2497 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2501 * r600_dma_resume - setup and start the async dma engine
2503 * @rdev: radeon_device pointer
2505 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2506 * Returns 0 for success, error for failure.
2508 int r600_dma_resume(struct radeon_device *rdev)
2510 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2511 u32 rb_cntl, dma_cntl, ib_cntl;
2516 if (rdev->family >= CHIP_RV770)
2517 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2519 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2520 RREG32(SRBM_SOFT_RESET);
2522 WREG32(SRBM_SOFT_RESET, 0);
2524 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2525 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2527 /* Set ring buffer size in dwords */
2528 rb_bufsz = drm_order(ring->ring_size / 4);
2529 rb_cntl = rb_bufsz << 1;
2531 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2533 WREG32(DMA_RB_CNTL, rb_cntl);
2535 /* Initialize the ring buffer's read and write pointers */
2536 WREG32(DMA_RB_RPTR, 0);
2537 WREG32(DMA_RB_WPTR, 0);
2539 /* set the wb address whether it's enabled or not */
2540 WREG32(DMA_RB_RPTR_ADDR_HI,
2541 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2542 WREG32(DMA_RB_RPTR_ADDR_LO,
2543 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2545 if (rdev->wb.enabled)
2546 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2548 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2550 /* enable DMA IBs */
2551 ib_cntl = DMA_IB_ENABLE;
2553 ib_cntl |= DMA_IB_SWAP_ENABLE;
2555 WREG32(DMA_IB_CNTL, ib_cntl);
2557 dma_cntl = RREG32(DMA_CNTL);
2558 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2559 WREG32(DMA_CNTL, dma_cntl);
2561 if (rdev->family >= CHIP_RV770)
2562 WREG32(DMA_MODE, 1);
2565 WREG32(DMA_RB_WPTR, ring->wptr << 2);
2567 ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2569 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2573 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2575 ring->ready = false;
2579 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2585 * r600_dma_fini - tear down the async dma engine
2587 * @rdev: radeon_device pointer
2589 * Stop the async dma engine and free the ring (r6xx-evergreen).
2591 void r600_dma_fini(struct radeon_device *rdev)
2593 r600_dma_stop(rdev);
2594 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2600 int r600_uvd_rbc_start(struct radeon_device *rdev)
2602 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2604 uint32_t rb_bufsz, tmp;
2607 rptr_addr = rdev->wb.gpu_addr + R600_WB_UVD_RPTR_OFFSET;
2609 if (upper_32_bits(rptr_addr) != upper_32_bits(ring->gpu_addr)) {
2610 DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n");
2614 /* force RBC into idle state */
2615 WREG32(UVD_RBC_RB_CNTL, 0x11010101);
2617 /* Set the write pointer delay */
2618 WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
2620 /* set the wb address */
2621 WREG32(UVD_RBC_RB_RPTR_ADDR, rptr_addr >> 2);
2623 /* programm the 4GB memory segment for rptr and ring buffer */
2624 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(rptr_addr) |
2625 (0x7 << 16) | (0x1 << 31));
2627 /* Initialize the ring buffer's read and write pointers */
2628 WREG32(UVD_RBC_RB_RPTR, 0x0);
2630 ring->wptr = ring->rptr = RREG32(UVD_RBC_RB_RPTR);
2631 WREG32(UVD_RBC_RB_WPTR, ring->wptr);
2633 /* set the ring address */
2634 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
2636 /* Set ring buffer size */
2637 rb_bufsz = drm_order(ring->ring_size);
2638 rb_bufsz = (0x1 << 8) | rb_bufsz;
2639 WREG32(UVD_RBC_RB_CNTL, rb_bufsz);
2642 r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);
2644 ring->ready = false;
2648 r = radeon_ring_lock(rdev, ring, 10);
2650 DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);
2654 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
2655 radeon_ring_write(ring, tmp);
2656 radeon_ring_write(ring, 0xFFFFF);
2658 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
2659 radeon_ring_write(ring, tmp);
2660 radeon_ring_write(ring, 0xFFFFF);
2662 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
2663 radeon_ring_write(ring, tmp);
2664 radeon_ring_write(ring, 0xFFFFF);
2666 /* Clear timeout status bits */
2667 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));
2668 radeon_ring_write(ring, 0x8);
2670 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
2671 radeon_ring_write(ring, 3);
2673 radeon_ring_unlock_commit(rdev, ring);
2678 void r600_uvd_stop(struct radeon_device *rdev)
2680 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2682 /* force RBC into idle state */
2683 WREG32(UVD_RBC_RB_CNTL, 0x11010101);
2685 /* Stall UMC and register bus before resetting VCPU */
2686 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
2687 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
2690 /* put VCPU into reset */
2691 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
2694 /* disable VCPU clock */
2695 WREG32(UVD_VCPU_CNTL, 0x0);
2697 /* Unstall UMC and register bus */
2698 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
2699 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
2701 ring->ready = false;
2704 int r600_uvd_init(struct radeon_device *rdev)
2707 /* disable byte swapping */
2708 u32 lmi_swap_cntl = 0;
2709 u32 mp_swap_cntl = 0;
2711 /* raise clocks while booting up the VCPU */
2712 radeon_set_uvd_clocks(rdev, 53300, 40000);
2714 /* disable clock gating */
2715 WREG32(UVD_CGC_GATE, 0);
2717 /* disable interupt */
2718 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
2720 /* Stall UMC and register bus before resetting VCPU */
2721 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
2722 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
2725 /* put LMI, VCPU, RBC etc... into reset */
2726 WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
2727 LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET |
2728 CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET);
2731 /* take UVD block out of reset */
2732 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);
2735 /* initialize UVD memory controller */
2736 WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
2737 (1 << 21) | (1 << 9) | (1 << 20));
2740 /* swap (8 in 32) RB and IB */
2741 lmi_swap_cntl = 0xa;
2744 WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);
2745 WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);
2747 WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
2748 WREG32(UVD_MPC_SET_MUXA1, 0x0);
2749 WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);
2750 WREG32(UVD_MPC_SET_MUXB1, 0x0);
2751 WREG32(UVD_MPC_SET_ALU, 0);
2752 WREG32(UVD_MPC_SET_MUX, 0x88);
2754 /* take all subblocks out of reset, except VCPU */
2755 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
2758 /* enable VCPU clock */
2759 WREG32(UVD_VCPU_CNTL, 1 << 9);
2762 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
2764 /* boot up the VCPU */
2765 WREG32(UVD_SOFT_RESET, 0);
2768 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
2770 for (i = 0; i < 10; ++i) {
2772 for (j = 0; j < 100; ++j) {
2773 status = RREG32(UVD_STATUS);
2782 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
2783 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);
2785 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);
2791 DRM_ERROR("UVD not responding, giving up!!!\n");
2792 radeon_set_uvd_clocks(rdev, 0, 0);
2796 /* enable interupt */
2797 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
2799 r = r600_uvd_rbc_start(rdev);
2801 DRM_INFO("UVD initialized successfully.\n");
2803 /* lower clocks again */
2804 radeon_set_uvd_clocks(rdev, 0, 0);
2810 * GPU scratch registers helpers function.
2812 void r600_scratch_init(struct radeon_device *rdev)
2816 rdev->scratch.num_reg = 7;
2817 rdev->scratch.reg_base = SCRATCH_REG0;
2818 for (i = 0; i < rdev->scratch.num_reg; i++) {
2819 rdev->scratch.free[i] = true;
2820 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2824 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2831 r = radeon_scratch_get(rdev, &scratch);
2833 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2836 WREG32(scratch, 0xCAFEDEAD);
2837 r = radeon_ring_lock(rdev, ring, 3);
2839 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2840 radeon_scratch_free(rdev, scratch);
2843 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2844 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2845 radeon_ring_write(ring, 0xDEADBEEF);
2846 radeon_ring_unlock_commit(rdev, ring);
2847 for (i = 0; i < rdev->usec_timeout; i++) {
2848 tmp = RREG32(scratch);
2849 if (tmp == 0xDEADBEEF)
2853 if (i < rdev->usec_timeout) {
2854 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2856 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2857 ring->idx, scratch, tmp);
2860 radeon_scratch_free(rdev, scratch);
2865 * r600_dma_ring_test - simple async dma engine test
2867 * @rdev: radeon_device pointer
2868 * @ring: radeon_ring structure holding ring information
2870 * Test the DMA engine by writing using it to write an
2871 * value to memory. (r6xx-SI).
2872 * Returns 0 for success, error for failure.
2874 int r600_dma_ring_test(struct radeon_device *rdev,
2875 struct radeon_ring *ring)
2879 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2883 DRM_ERROR("invalid vram scratch pointer\n");
2890 r = radeon_ring_lock(rdev, ring, 4);
2892 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2895 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2896 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2897 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2898 radeon_ring_write(ring, 0xDEADBEEF);
2899 radeon_ring_unlock_commit(rdev, ring);
2901 for (i = 0; i < rdev->usec_timeout; i++) {
2903 if (tmp == 0xDEADBEEF)
2908 if (i < rdev->usec_timeout) {
2909 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2911 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2918 int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2924 WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);
2925 r = radeon_ring_lock(rdev, ring, 3);
2927 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",
2931 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
2932 radeon_ring_write(ring, 0xDEADBEEF);
2933 radeon_ring_unlock_commit(rdev, ring);
2934 for (i = 0; i < rdev->usec_timeout; i++) {
2935 tmp = RREG32(UVD_CONTEXT_ID);
2936 if (tmp == 0xDEADBEEF)
2941 if (i < rdev->usec_timeout) {
2942 DRM_INFO("ring test on %d succeeded in %d usecs\n",
2945 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2953 * CP fences/semaphores
2956 void r600_fence_ring_emit(struct radeon_device *rdev,
2957 struct radeon_fence *fence)
2959 struct radeon_ring *ring = &rdev->ring[fence->ring];
2961 if (rdev->wb.use_event) {
2962 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2963 /* flush read cache over gart */
2964 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2965 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2966 PACKET3_VC_ACTION_ENA |
2967 PACKET3_SH_ACTION_ENA);
2968 radeon_ring_write(ring, 0xFFFFFFFF);
2969 radeon_ring_write(ring, 0);
2970 radeon_ring_write(ring, 10); /* poll interval */
2971 /* EVENT_WRITE_EOP - flush caches, send int */
2972 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2973 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2974 radeon_ring_write(ring, addr & 0xffffffff);
2975 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2976 radeon_ring_write(ring, fence->seq);
2977 radeon_ring_write(ring, 0);
2979 /* flush read cache over gart */
2980 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2981 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2982 PACKET3_VC_ACTION_ENA |
2983 PACKET3_SH_ACTION_ENA);
2984 radeon_ring_write(ring, 0xFFFFFFFF);
2985 radeon_ring_write(ring, 0);
2986 radeon_ring_write(ring, 10); /* poll interval */
2987 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2988 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2989 /* wait for 3D idle clean */
2990 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2991 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2992 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2993 /* Emit fence sequence & fire IRQ */
2994 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2995 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2996 radeon_ring_write(ring, fence->seq);
2997 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2998 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2999 radeon_ring_write(ring, RB_INT_STAT);
3003 void r600_uvd_fence_emit(struct radeon_device *rdev,
3004 struct radeon_fence *fence)
3006 struct radeon_ring *ring = &rdev->ring[fence->ring];
3007 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
3009 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
3010 radeon_ring_write(ring, fence->seq);
3011 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
3012 radeon_ring_write(ring, addr & 0xffffffff);
3013 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
3014 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
3015 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
3016 radeon_ring_write(ring, 0);
3018 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
3019 radeon_ring_write(ring, 0);
3020 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
3021 radeon_ring_write(ring, 0);
3022 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
3023 radeon_ring_write(ring, 2);
3027 void r600_semaphore_ring_emit(struct radeon_device *rdev,
3028 struct radeon_ring *ring,
3029 struct radeon_semaphore *semaphore,
3032 uint64_t addr = semaphore->gpu_addr;
3033 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3035 if (rdev->family < CHIP_CAYMAN)
3036 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
3038 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3039 radeon_ring_write(ring, addr & 0xffffffff);
3040 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
3044 * DMA fences/semaphores
3048 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
3050 * @rdev: radeon_device pointer
3051 * @fence: radeon fence object
3053 * Add a DMA fence packet to the ring to write
3054 * the fence seq number and DMA trap packet to generate
3055 * an interrupt if needed (r6xx-r7xx).
3057 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
3058 struct radeon_fence *fence)
3060 struct radeon_ring *ring = &rdev->ring[fence->ring];
3061 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3063 /* write the fence */
3064 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
3065 radeon_ring_write(ring, addr & 0xfffffffc);
3066 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3067 radeon_ring_write(ring, lower_32_bits(fence->seq));
3068 /* generate an interrupt */
3069 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
3073 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
3075 * @rdev: radeon_device pointer
3076 * @ring: radeon_ring structure holding ring information
3077 * @semaphore: radeon semaphore object
3078 * @emit_wait: wait or signal semaphore
3080 * Add a DMA semaphore packet to the ring wait on or signal
3081 * other rings (r6xx-SI).
3083 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
3084 struct radeon_ring *ring,
3085 struct radeon_semaphore *semaphore,
3088 u64 addr = semaphore->gpu_addr;
3089 u32 s = emit_wait ? 0 : 1;
3091 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
3092 radeon_ring_write(ring, addr & 0xfffffffc);
3093 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
3096 void r600_uvd_semaphore_emit(struct radeon_device *rdev,
3097 struct radeon_ring *ring,
3098 struct radeon_semaphore *semaphore,
3101 uint64_t addr = semaphore->gpu_addr;
3103 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
3104 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
3106 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
3107 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
3109 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
3110 radeon_ring_write(ring, emit_wait ? 1 : 0);
3113 int r600_copy_blit(struct radeon_device *rdev,
3114 uint64_t src_offset,
3115 uint64_t dst_offset,
3116 unsigned num_gpu_pages,
3117 struct radeon_fence **fence)
3119 struct radeon_semaphore *sem = NULL;
3120 struct radeon_sa_bo *vb = NULL;
3123 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
3127 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
3128 r600_blit_done_copy(rdev, fence, vb, sem);
3133 * r600_copy_dma - copy pages using the DMA engine
3135 * @rdev: radeon_device pointer
3136 * @src_offset: src GPU address
3137 * @dst_offset: dst GPU address
3138 * @num_gpu_pages: number of GPU pages to xfer
3139 * @fence: radeon fence object
3141 * Copy GPU paging using the DMA engine (r6xx).
3142 * Used by the radeon ttm implementation to move pages if
3143 * registered as the asic copy callback.
3145 int r600_copy_dma(struct radeon_device *rdev,
3146 uint64_t src_offset, uint64_t dst_offset,
3147 unsigned num_gpu_pages,
3148 struct radeon_fence **fence)
3150 struct radeon_semaphore *sem = NULL;
3151 int ring_index = rdev->asic->copy.dma_ring_index;
3152 struct radeon_ring *ring = &rdev->ring[ring_index];
3153 u32 size_in_dw, cur_size_in_dw;
3157 r = radeon_semaphore_create(rdev, &sem);
3159 DRM_ERROR("radeon: moving bo (%d).\n", r);
3163 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
3164 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
3165 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
3167 DRM_ERROR("radeon: moving bo (%d).\n", r);
3168 radeon_semaphore_free(rdev, &sem, NULL);
3172 if (radeon_fence_need_sync(*fence, ring->idx)) {
3173 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3175 radeon_fence_note_sync(*fence, ring->idx);
3177 radeon_semaphore_free(rdev, &sem, NULL);
3180 for (i = 0; i < num_loops; i++) {
3181 cur_size_in_dw = size_in_dw;
3182 if (cur_size_in_dw > 0xFFFE)
3183 cur_size_in_dw = 0xFFFE;
3184 size_in_dw -= cur_size_in_dw;
3185 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
3186 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3187 radeon_ring_write(ring, src_offset & 0xfffffffc);
3188 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
3189 (upper_32_bits(src_offset) & 0xff)));
3190 src_offset += cur_size_in_dw * 4;
3191 dst_offset += cur_size_in_dw * 4;
3194 r = radeon_fence_emit(rdev, fence, ring->idx);
3196 radeon_ring_unlock_undo(rdev, ring);
3200 radeon_ring_unlock_commit(rdev, ring);
3201 radeon_semaphore_free(rdev, &sem, *fence);
3206 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
3207 uint32_t tiling_flags, uint32_t pitch,
3208 uint32_t offset, uint32_t obj_size)
3210 /* FIXME: implement */
3214 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
3216 /* FIXME: implement */
3219 static int r600_startup(struct radeon_device *rdev)
3221 struct radeon_ring *ring;
3224 /* enable pcie gen2 link */
3225 r600_pcie_gen2_enable(rdev);
3227 r600_mc_program(rdev);
3229 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3230 r = r600_init_microcode(rdev);
3232 DRM_ERROR("Failed to load firmware!\n");
3237 r = r600_vram_scratch_init(rdev);
3241 if (rdev->flags & RADEON_IS_AGP) {
3242 r600_agp_enable(rdev);
3244 r = r600_pcie_gart_enable(rdev);
3248 r600_gpu_init(rdev);
3249 r = r600_blit_init(rdev);
3251 r600_blit_fini(rdev);
3252 rdev->asic->copy.copy = NULL;
3253 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3256 /* allocate wb buffer */
3257 r = radeon_wb_init(rdev);
3261 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3263 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3267 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
3269 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3274 if (!rdev->irq.installed) {
3275 r = radeon_irq_kms_init(rdev);
3280 r = r600_irq_init(rdev);
3282 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3283 radeon_irq_kms_fini(rdev);
3288 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3289 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3290 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3291 0, 0xfffff, RADEON_CP_PACKET2);
3295 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3296 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3297 DMA_RB_RPTR, DMA_RB_WPTR,
3298 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3302 r = r600_cp_load_microcode(rdev);
3305 r = r600_cp_resume(rdev);
3309 r = r600_dma_resume(rdev);
3313 r = radeon_ib_pool_init(rdev);
3315 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3319 r = r600_audio_init(rdev);
3321 DRM_ERROR("radeon: audio init failed\n");
3328 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3332 temp = RREG32(CONFIG_CNTL);
3333 if (state == false) {
3339 WREG32(CONFIG_CNTL, temp);
3342 int r600_resume(struct radeon_device *rdev)
3346 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3347 * posting will perform necessary task to bring back GPU into good
3351 atom_asic_init(rdev->mode_info.atom_context);
3353 rdev->accel_working = true;
3354 r = r600_startup(rdev);
3356 DRM_ERROR("r600 startup failed on resume\n");
3357 rdev->accel_working = false;
3364 int r600_suspend(struct radeon_device *rdev)
3366 r600_audio_fini(rdev);
3368 r600_dma_stop(rdev);
3369 r600_irq_suspend(rdev);
3370 radeon_wb_disable(rdev);
3371 r600_pcie_gart_disable(rdev);
3376 /* Plan is to move initialization in that function and use
3377 * helper function so that radeon_device_init pretty much
3378 * do nothing more than calling asic specific function. This
3379 * should also allow to remove a bunch of callback function
3382 int r600_init(struct radeon_device *rdev)
3386 if (r600_debugfs_mc_info_init(rdev)) {
3387 DRM_ERROR("Failed to register debugfs file for mc !\n");
3390 if (!radeon_get_bios(rdev)) {
3391 if (ASIC_IS_AVIVO(rdev))
3394 /* Must be an ATOMBIOS */
3395 if (!rdev->is_atom_bios) {
3396 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3399 r = radeon_atombios_init(rdev);
3402 /* Post card if necessary */
3403 if (!radeon_card_posted(rdev)) {
3405 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3408 DRM_INFO("GPU not posted. posting now...\n");
3409 atom_asic_init(rdev->mode_info.atom_context);
3411 /* Initialize scratch registers */
3412 r600_scratch_init(rdev);
3413 /* Initialize surface registers */
3414 radeon_surface_init(rdev);
3415 /* Initialize clocks */
3416 radeon_get_clock_info(rdev->ddev);
3418 r = radeon_fence_driver_init(rdev);
3421 if (rdev->flags & RADEON_IS_AGP) {
3422 r = radeon_agp_init(rdev);
3424 radeon_agp_disable(rdev);
3426 r = r600_mc_init(rdev);
3429 /* Memory manager */
3430 r = radeon_bo_init(rdev);
3434 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3435 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3437 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3438 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3440 rdev->ih.ring_obj = NULL;
3441 r600_ih_ring_init(rdev, 64 * 1024);
3443 r = r600_pcie_gart_init(rdev);
3447 rdev->accel_working = true;
3448 r = r600_startup(rdev);
3450 dev_err(rdev->dev, "disabling GPU acceleration\n");
3452 r600_dma_fini(rdev);
3453 r600_irq_fini(rdev);
3454 radeon_wb_fini(rdev);
3455 radeon_ib_pool_fini(rdev);
3456 radeon_irq_kms_fini(rdev);
3457 r600_pcie_gart_fini(rdev);
3458 rdev->accel_working = false;
3464 void r600_fini(struct radeon_device *rdev)
3466 r600_audio_fini(rdev);
3467 r600_blit_fini(rdev);
3469 r600_dma_fini(rdev);
3470 r600_irq_fini(rdev);
3471 radeon_wb_fini(rdev);
3472 radeon_ib_pool_fini(rdev);
3473 radeon_irq_kms_fini(rdev);
3474 r600_pcie_gart_fini(rdev);
3475 r600_vram_scratch_fini(rdev);
3476 radeon_agp_fini(rdev);
3477 radeon_gem_fini(rdev);
3478 radeon_fence_driver_fini(rdev);
3479 radeon_bo_fini(rdev);
3480 radeon_atombios_fini(rdev);
3489 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3491 struct radeon_ring *ring = &rdev->ring[ib->ring];
3494 if (ring->rptr_save_reg) {
3495 next_rptr = ring->wptr + 3 + 4;
3496 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3497 radeon_ring_write(ring, ((ring->rptr_save_reg -
3498 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3499 radeon_ring_write(ring, next_rptr);
3500 } else if (rdev->wb.enabled) {
3501 next_rptr = ring->wptr + 5 + 4;
3502 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3503 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3504 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3505 radeon_ring_write(ring, next_rptr);
3506 radeon_ring_write(ring, 0);
3509 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3510 radeon_ring_write(ring,
3514 (ib->gpu_addr & 0xFFFFFFFC));
3515 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3516 radeon_ring_write(ring, ib->length_dw);
3519 void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3521 struct radeon_ring *ring = &rdev->ring[ib->ring];
3523 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));
3524 radeon_ring_write(ring, ib->gpu_addr);
3525 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));
3526 radeon_ring_write(ring, ib->length_dw);
3529 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3531 struct radeon_ib ib;
3537 r = radeon_scratch_get(rdev, &scratch);
3539 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3542 WREG32(scratch, 0xCAFEDEAD);
3543 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3545 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3548 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3549 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3550 ib.ptr[2] = 0xDEADBEEF;
3552 r = radeon_ib_schedule(rdev, &ib, NULL);
3554 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3557 r = radeon_fence_wait(ib.fence, false);
3559 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3562 for (i = 0; i < rdev->usec_timeout; i++) {
3563 tmp = RREG32(scratch);
3564 if (tmp == 0xDEADBEEF)
3568 if (i < rdev->usec_timeout) {
3569 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3571 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3576 radeon_ib_free(rdev, &ib);
3578 radeon_scratch_free(rdev, scratch);
3583 * r600_dma_ib_test - test an IB on the DMA engine
3585 * @rdev: radeon_device pointer
3586 * @ring: radeon_ring structure holding ring information
3588 * Test a simple IB in the DMA ring (r6xx-SI).
3589 * Returns 0 on success, error on failure.
3591 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3593 struct radeon_ib ib;
3596 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3600 DRM_ERROR("invalid vram scratch pointer\n");
3607 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3609 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3613 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3614 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3615 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3616 ib.ptr[3] = 0xDEADBEEF;
3619 r = radeon_ib_schedule(rdev, &ib, NULL);
3621 radeon_ib_free(rdev, &ib);
3622 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3625 r = radeon_fence_wait(ib.fence, false);
3627 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3630 for (i = 0; i < rdev->usec_timeout; i++) {
3632 if (tmp == 0xDEADBEEF)
3636 if (i < rdev->usec_timeout) {
3637 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3639 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3642 radeon_ib_free(rdev, &ib);
3646 int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3648 struct radeon_fence *fence = NULL;
3651 r = radeon_set_uvd_clocks(rdev, 53300, 40000);
3653 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r);
3657 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
3659 DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
3663 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);
3665 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
3669 r = radeon_fence_wait(fence, false);
3671 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3674 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
3676 radeon_fence_unref(&fence);
3677 radeon_set_uvd_clocks(rdev, 0, 0);
3682 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3684 * @rdev: radeon_device pointer
3685 * @ib: IB object to schedule
3687 * Schedule an IB in the DMA ring (r6xx-r7xx).
3689 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3691 struct radeon_ring *ring = &rdev->ring[ib->ring];
3693 if (rdev->wb.enabled) {
3694 u32 next_rptr = ring->wptr + 4;
3695 while ((next_rptr & 7) != 5)
3698 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3699 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3700 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3701 radeon_ring_write(ring, next_rptr);
3704 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3705 * Pad as necessary with NOPs.
3707 while ((ring->wptr & 7) != 5)
3708 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3709 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3710 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3711 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3718 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3719 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3720 * writing to the ring and the GPU consuming, the GPU writes to the ring
3721 * and host consumes. As the host irq handler processes interrupts, it
3722 * increments the rptr. When the rptr catches up with the wptr, all the
3723 * current interrupts have been processed.
3726 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3730 /* Align ring size */
3731 rb_bufsz = drm_order(ring_size / 4);
3732 ring_size = (1 << rb_bufsz) * 4;
3733 rdev->ih.ring_size = ring_size;
3734 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3738 int r600_ih_ring_alloc(struct radeon_device *rdev)
3742 /* Allocate ring buffer */
3743 if (rdev->ih.ring_obj == NULL) {
3744 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3746 RADEON_GEM_DOMAIN_GTT,
3747 NULL, &rdev->ih.ring_obj);
3749 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3752 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3753 if (unlikely(r != 0))
3755 r = radeon_bo_pin(rdev->ih.ring_obj,
3756 RADEON_GEM_DOMAIN_GTT,
3757 &rdev->ih.gpu_addr);
3759 radeon_bo_unreserve(rdev->ih.ring_obj);
3760 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3763 r = radeon_bo_kmap(rdev->ih.ring_obj,
3764 (void **)&rdev->ih.ring);
3765 radeon_bo_unreserve(rdev->ih.ring_obj);
3767 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3774 void r600_ih_ring_fini(struct radeon_device *rdev)
3777 if (rdev->ih.ring_obj) {
3778 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3779 if (likely(r == 0)) {
3780 radeon_bo_kunmap(rdev->ih.ring_obj);
3781 radeon_bo_unpin(rdev->ih.ring_obj);
3782 radeon_bo_unreserve(rdev->ih.ring_obj);
3784 radeon_bo_unref(&rdev->ih.ring_obj);
3785 rdev->ih.ring = NULL;
3786 rdev->ih.ring_obj = NULL;
3790 void r600_rlc_stop(struct radeon_device *rdev)
3793 if ((rdev->family >= CHIP_RV770) &&
3794 (rdev->family <= CHIP_RV740)) {
3795 /* r7xx asics need to soft reset RLC before halting */
3796 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3797 RREG32(SRBM_SOFT_RESET);
3799 WREG32(SRBM_SOFT_RESET, 0);
3800 RREG32(SRBM_SOFT_RESET);
3803 WREG32(RLC_CNTL, 0);
3806 static void r600_rlc_start(struct radeon_device *rdev)
3808 WREG32(RLC_CNTL, RLC_ENABLE);
3811 static int r600_rlc_init(struct radeon_device *rdev)
3814 const __be32 *fw_data;
3819 r600_rlc_stop(rdev);
3821 WREG32(RLC_HB_CNTL, 0);
3823 if (rdev->family == CHIP_ARUBA) {
3824 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3825 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3827 if (rdev->family <= CHIP_CAYMAN) {
3828 WREG32(RLC_HB_BASE, 0);
3829 WREG32(RLC_HB_RPTR, 0);
3830 WREG32(RLC_HB_WPTR, 0);
3832 if (rdev->family <= CHIP_CAICOS) {
3833 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3834 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3836 WREG32(RLC_MC_CNTL, 0);
3837 WREG32(RLC_UCODE_CNTL, 0);
3839 fw_data = (const __be32 *)rdev->rlc_fw->data;
3840 if (rdev->family >= CHIP_ARUBA) {
3841 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3842 WREG32(RLC_UCODE_ADDR, i);
3843 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3845 } else if (rdev->family >= CHIP_CAYMAN) {
3846 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3847 WREG32(RLC_UCODE_ADDR, i);
3848 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3850 } else if (rdev->family >= CHIP_CEDAR) {
3851 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3852 WREG32(RLC_UCODE_ADDR, i);
3853 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3855 } else if (rdev->family >= CHIP_RV770) {
3856 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3857 WREG32(RLC_UCODE_ADDR, i);
3858 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3861 for (i = 0; i < RLC_UCODE_SIZE; i++) {
3862 WREG32(RLC_UCODE_ADDR, i);
3863 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3866 WREG32(RLC_UCODE_ADDR, 0);
3868 r600_rlc_start(rdev);
3873 static void r600_enable_interrupts(struct radeon_device *rdev)
3875 u32 ih_cntl = RREG32(IH_CNTL);
3876 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3878 ih_cntl |= ENABLE_INTR;
3879 ih_rb_cntl |= IH_RB_ENABLE;
3880 WREG32(IH_CNTL, ih_cntl);
3881 WREG32(IH_RB_CNTL, ih_rb_cntl);
3882 rdev->ih.enabled = true;
3885 void r600_disable_interrupts(struct radeon_device *rdev)
3887 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3888 u32 ih_cntl = RREG32(IH_CNTL);
3890 ih_rb_cntl &= ~IH_RB_ENABLE;
3891 ih_cntl &= ~ENABLE_INTR;
3892 WREG32(IH_RB_CNTL, ih_rb_cntl);
3893 WREG32(IH_CNTL, ih_cntl);
3894 /* set rptr, wptr to 0 */
3895 WREG32(IH_RB_RPTR, 0);
3896 WREG32(IH_RB_WPTR, 0);
3897 rdev->ih.enabled = false;
3901 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3905 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3906 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3907 WREG32(DMA_CNTL, tmp);
3908 WREG32(GRBM_INT_CNTL, 0);
3909 WREG32(DxMODE_INT_MASK, 0);
3910 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3911 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3912 if (ASIC_IS_DCE3(rdev)) {
3913 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3914 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3915 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3916 WREG32(DC_HPD1_INT_CONTROL, tmp);
3917 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3918 WREG32(DC_HPD2_INT_CONTROL, tmp);
3919 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3920 WREG32(DC_HPD3_INT_CONTROL, tmp);
3921 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3922 WREG32(DC_HPD4_INT_CONTROL, tmp);
3923 if (ASIC_IS_DCE32(rdev)) {
3924 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3925 WREG32(DC_HPD5_INT_CONTROL, tmp);
3926 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3927 WREG32(DC_HPD6_INT_CONTROL, tmp);
3928 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3929 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3930 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3931 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3933 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3934 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3935 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3936 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3939 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3940 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3941 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3942 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3943 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3944 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3945 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3946 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3947 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3948 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3949 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3950 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3954 int r600_irq_init(struct radeon_device *rdev)
3958 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3961 ret = r600_ih_ring_alloc(rdev);
3966 r600_disable_interrupts(rdev);
3969 ret = r600_rlc_init(rdev);
3971 r600_ih_ring_fini(rdev);
3975 /* setup interrupt control */
3976 /* set dummy read address to ring address */
3977 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3978 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3979 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3980 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3982 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3983 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3984 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3985 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3987 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3988 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3990 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3991 IH_WPTR_OVERFLOW_CLEAR |
3994 if (rdev->wb.enabled)
3995 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3997 /* set the writeback address whether it's enabled or not */
3998 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3999 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
4001 WREG32(IH_RB_CNTL, ih_rb_cntl);
4003 /* set rptr, wptr to 0 */
4004 WREG32(IH_RB_RPTR, 0);
4005 WREG32(IH_RB_WPTR, 0);
4007 /* Default settings for IH_CNTL (disabled at first) */
4008 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
4009 /* RPTR_REARM only works if msi's are enabled */
4010 if (rdev->msi_enabled)
4011 ih_cntl |= RPTR_REARM;
4012 WREG32(IH_CNTL, ih_cntl);
4014 /* force the active interrupt state to all disabled */
4015 if (rdev->family >= CHIP_CEDAR)
4016 evergreen_disable_interrupt_state(rdev);
4018 r600_disable_interrupt_state(rdev);
4020 /* at this point everything should be setup correctly to enable master */
4021 pci_set_master(rdev->pdev);
4024 r600_enable_interrupts(rdev);
4029 void r600_irq_suspend(struct radeon_device *rdev)
4031 r600_irq_disable(rdev);
4032 r600_rlc_stop(rdev);
4035 void r600_irq_fini(struct radeon_device *rdev)
4037 r600_irq_suspend(rdev);
4038 r600_ih_ring_fini(rdev);
4041 int r600_irq_set(struct radeon_device *rdev)
4043 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
4045 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
4046 u32 grbm_int_cntl = 0;
4048 u32 d1grph = 0, d2grph = 0;
4051 if (!rdev->irq.installed) {
4052 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
4055 /* don't enable anything if the ih is disabled */
4056 if (!rdev->ih.enabled) {
4057 r600_disable_interrupts(rdev);
4058 /* force the active interrupt state to all disabled */
4059 r600_disable_interrupt_state(rdev);
4063 if (ASIC_IS_DCE3(rdev)) {
4064 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
4065 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
4066 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
4067 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
4068 if (ASIC_IS_DCE32(rdev)) {
4069 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
4070 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
4071 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
4072 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
4074 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4075 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4078 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
4079 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
4080 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
4081 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4082 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4084 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
4086 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
4087 DRM_DEBUG("r600_irq_set: sw int\n");
4088 cp_int_cntl |= RB_INT_ENABLE;
4089 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
4092 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
4093 DRM_DEBUG("r600_irq_set: sw int dma\n");
4094 dma_cntl |= TRAP_ENABLE;
4097 if (rdev->irq.crtc_vblank_int[0] ||
4098 atomic_read(&rdev->irq.pflip[0])) {
4099 DRM_DEBUG("r600_irq_set: vblank 0\n");
4100 mode_int |= D1MODE_VBLANK_INT_MASK;
4102 if (rdev->irq.crtc_vblank_int[1] ||
4103 atomic_read(&rdev->irq.pflip[1])) {
4104 DRM_DEBUG("r600_irq_set: vblank 1\n");
4105 mode_int |= D2MODE_VBLANK_INT_MASK;
4107 if (rdev->irq.hpd[0]) {
4108 DRM_DEBUG("r600_irq_set: hpd 1\n");
4109 hpd1 |= DC_HPDx_INT_EN;
4111 if (rdev->irq.hpd[1]) {
4112 DRM_DEBUG("r600_irq_set: hpd 2\n");
4113 hpd2 |= DC_HPDx_INT_EN;
4115 if (rdev->irq.hpd[2]) {
4116 DRM_DEBUG("r600_irq_set: hpd 3\n");
4117 hpd3 |= DC_HPDx_INT_EN;
4119 if (rdev->irq.hpd[3]) {
4120 DRM_DEBUG("r600_irq_set: hpd 4\n");
4121 hpd4 |= DC_HPDx_INT_EN;
4123 if (rdev->irq.hpd[4]) {
4124 DRM_DEBUG("r600_irq_set: hpd 5\n");
4125 hpd5 |= DC_HPDx_INT_EN;
4127 if (rdev->irq.hpd[5]) {
4128 DRM_DEBUG("r600_irq_set: hpd 6\n");
4129 hpd6 |= DC_HPDx_INT_EN;
4131 if (rdev->irq.afmt[0]) {
4132 DRM_DEBUG("r600_irq_set: hdmi 0\n");
4133 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
4135 if (rdev->irq.afmt[1]) {
4136 DRM_DEBUG("r600_irq_set: hdmi 0\n");
4137 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
4140 WREG32(CP_INT_CNTL, cp_int_cntl);
4141 WREG32(DMA_CNTL, dma_cntl);
4142 WREG32(DxMODE_INT_MASK, mode_int);
4143 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
4144 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
4145 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
4146 if (ASIC_IS_DCE3(rdev)) {
4147 WREG32(DC_HPD1_INT_CONTROL, hpd1);
4148 WREG32(DC_HPD2_INT_CONTROL, hpd2);
4149 WREG32(DC_HPD3_INT_CONTROL, hpd3);
4150 WREG32(DC_HPD4_INT_CONTROL, hpd4);
4151 if (ASIC_IS_DCE32(rdev)) {
4152 WREG32(DC_HPD5_INT_CONTROL, hpd5);
4153 WREG32(DC_HPD6_INT_CONTROL, hpd6);
4154 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
4155 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
4157 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
4158 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
4161 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
4162 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
4163 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
4164 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
4165 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
4171 static void r600_irq_ack(struct radeon_device *rdev)
4175 if (ASIC_IS_DCE3(rdev)) {
4176 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
4177 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
4178 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
4179 if (ASIC_IS_DCE32(rdev)) {
4180 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
4181 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
4183 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
4184 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
4187 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
4188 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
4189 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
4190 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
4191 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
4193 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
4194 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
4196 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
4197 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
4198 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
4199 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
4200 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
4201 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
4202 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
4203 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
4204 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
4205 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
4206 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
4207 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
4208 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
4209 if (ASIC_IS_DCE3(rdev)) {
4210 tmp = RREG32(DC_HPD1_INT_CONTROL);
4211 tmp |= DC_HPDx_INT_ACK;
4212 WREG32(DC_HPD1_INT_CONTROL, tmp);
4214 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
4215 tmp |= DC_HPDx_INT_ACK;
4216 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
4219 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
4220 if (ASIC_IS_DCE3(rdev)) {
4221 tmp = RREG32(DC_HPD2_INT_CONTROL);
4222 tmp |= DC_HPDx_INT_ACK;
4223 WREG32(DC_HPD2_INT_CONTROL, tmp);
4225 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
4226 tmp |= DC_HPDx_INT_ACK;
4227 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
4230 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
4231 if (ASIC_IS_DCE3(rdev)) {
4232 tmp = RREG32(DC_HPD3_INT_CONTROL);
4233 tmp |= DC_HPDx_INT_ACK;
4234 WREG32(DC_HPD3_INT_CONTROL, tmp);
4236 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
4237 tmp |= DC_HPDx_INT_ACK;
4238 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
4241 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
4242 tmp = RREG32(DC_HPD4_INT_CONTROL);
4243 tmp |= DC_HPDx_INT_ACK;
4244 WREG32(DC_HPD4_INT_CONTROL, tmp);
4246 if (ASIC_IS_DCE32(rdev)) {
4247 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4248 tmp = RREG32(DC_HPD5_INT_CONTROL);
4249 tmp |= DC_HPDx_INT_ACK;
4250 WREG32(DC_HPD5_INT_CONTROL, tmp);
4252 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4253 tmp = RREG32(DC_HPD5_INT_CONTROL);
4254 tmp |= DC_HPDx_INT_ACK;
4255 WREG32(DC_HPD6_INT_CONTROL, tmp);
4257 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
4258 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
4259 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4260 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
4262 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
4263 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
4264 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4265 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
4268 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4269 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
4270 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4271 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
4273 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4274 if (ASIC_IS_DCE3(rdev)) {
4275 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
4276 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4277 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
4279 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
4280 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4281 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
4287 void r600_irq_disable(struct radeon_device *rdev)
4289 r600_disable_interrupts(rdev);
4290 /* Wait and acknowledge irq */
4293 r600_disable_interrupt_state(rdev);
4296 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
4300 if (rdev->wb.enabled)
4301 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
4303 wptr = RREG32(IH_RB_WPTR);
4305 if (wptr & RB_OVERFLOW) {
4306 /* When a ring buffer overflow happen start parsing interrupt
4307 * from the last not overwritten vector (wptr + 16). Hopefully
4308 * this should allow us to catchup.
4310 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
4311 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
4312 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4313 tmp = RREG32(IH_RB_CNTL);
4314 tmp |= IH_WPTR_OVERFLOW_CLEAR;
4315 WREG32(IH_RB_CNTL, tmp);
4317 return (wptr & rdev->ih.ptr_mask);
4321 * Each IV ring entry is 128 bits:
4322 * [7:0] - interrupt source id
4324 * [59:32] - interrupt source data
4325 * [127:60] - reserved
4327 * The basic interrupt vector entries
4328 * are decoded as follows:
4329 * src_id src_data description
4334 * 19 0 FP Hot plug detection A
4335 * 19 1 FP Hot plug detection B
4336 * 19 2 DAC A auto-detection
4337 * 19 3 DAC B auto-detection
4343 * 181 - EOP Interrupt
4346 * Note, these are based on r600 and may need to be
4347 * adjusted or added to on newer asics
4350 int r600_irq_process(struct radeon_device *rdev)
4354 u32 src_id, src_data;
4356 bool queue_hotplug = false;
4357 bool queue_hdmi = false;
4359 if (!rdev->ih.enabled || rdev->shutdown)
4362 /* No MSIs, need a dummy read to flush PCI DMAs */
4363 if (!rdev->msi_enabled)
4366 wptr = r600_get_ih_wptr(rdev);
4369 /* is somebody else already processing irqs? */
4370 if (atomic_xchg(&rdev->ih.lock, 1))
4373 rptr = rdev->ih.rptr;
4374 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4376 /* Order reading of wptr vs. reading of IH ring data */
4379 /* display interrupts */
4382 while (rptr != wptr) {
4383 /* wptr/rptr are in bytes! */
4384 ring_index = rptr / 4;
4385 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4386 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4389 case 1: /* D1 vblank/vline */
4391 case 0: /* D1 vblank */
4392 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
4393 if (rdev->irq.crtc_vblank_int[0]) {
4394 drm_handle_vblank(rdev->ddev, 0);
4395 rdev->pm.vblank_sync = true;
4396 wake_up(&rdev->irq.vblank_queue);
4398 if (atomic_read(&rdev->irq.pflip[0]))
4399 radeon_crtc_handle_flip(rdev, 0);
4400 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4401 DRM_DEBUG("IH: D1 vblank\n");
4404 case 1: /* D1 vline */
4405 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
4406 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4407 DRM_DEBUG("IH: D1 vline\n");
4411 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4415 case 5: /* D2 vblank/vline */
4417 case 0: /* D2 vblank */
4418 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
4419 if (rdev->irq.crtc_vblank_int[1]) {
4420 drm_handle_vblank(rdev->ddev, 1);
4421 rdev->pm.vblank_sync = true;
4422 wake_up(&rdev->irq.vblank_queue);
4424 if (atomic_read(&rdev->irq.pflip[1]))
4425 radeon_crtc_handle_flip(rdev, 1);
4426 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4427 DRM_DEBUG("IH: D2 vblank\n");
4430 case 1: /* D1 vline */
4431 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
4432 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4433 DRM_DEBUG("IH: D2 vline\n");
4437 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4441 case 19: /* HPD/DAC hotplug */
4444 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
4445 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4446 queue_hotplug = true;
4447 DRM_DEBUG("IH: HPD1\n");
4451 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
4452 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4453 queue_hotplug = true;
4454 DRM_DEBUG("IH: HPD2\n");
4458 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
4459 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4460 queue_hotplug = true;
4461 DRM_DEBUG("IH: HPD3\n");
4465 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
4466 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4467 queue_hotplug = true;
4468 DRM_DEBUG("IH: HPD4\n");
4472 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4473 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4474 queue_hotplug = true;
4475 DRM_DEBUG("IH: HPD5\n");
4479 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4480 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4481 queue_hotplug = true;
4482 DRM_DEBUG("IH: HPD6\n");
4486 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4493 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4494 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4496 DRM_DEBUG("IH: HDMI0\n");
4500 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4501 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4503 DRM_DEBUG("IH: HDMI1\n");
4507 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4511 case 176: /* CP_INT in ring buffer */
4512 case 177: /* CP_INT in IB1 */
4513 case 178: /* CP_INT in IB2 */
4514 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4515 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4517 case 181: /* CP EOP event */
4518 DRM_DEBUG("IH: CP EOP\n");
4519 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4521 case 224: /* DMA trap event */
4522 DRM_DEBUG("IH: DMA trap\n");
4523 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4525 case 233: /* GUI IDLE */
4526 DRM_DEBUG("IH: GUI idle\n");
4529 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4533 /* wptr/rptr are in bytes! */
4535 rptr &= rdev->ih.ptr_mask;
4538 schedule_work(&rdev->hotplug_work);
4540 schedule_work(&rdev->audio_work);
4541 rdev->ih.rptr = rptr;
4542 WREG32(IH_RB_RPTR, rdev->ih.rptr);
4543 atomic_set(&rdev->ih.lock, 0);
4545 /* make sure wptr hasn't changed while processing */
4546 wptr = r600_get_ih_wptr(rdev);
4556 #if defined(CONFIG_DEBUG_FS)
4558 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4560 struct drm_info_node *node = (struct drm_info_node *) m->private;
4561 struct drm_device *dev = node->minor->dev;
4562 struct radeon_device *rdev = dev->dev_private;
4564 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4565 DREG32_SYS(m, rdev, VM_L2_STATUS);
4569 static struct drm_info_list r600_mc_info_list[] = {
4570 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4574 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4576 #if defined(CONFIG_DEBUG_FS)
4577 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4584 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4585 * rdev: radeon device structure
4586 * bo: buffer object struct which userspace is waiting for idle
4588 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4589 * through ring buffer, this leads to corruption in rendering, see
4590 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4591 * directly perform HDP flush by writing register through MMIO.
4593 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4595 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
4596 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4597 * This seems to cause problems on some AGP cards. Just use the old
4600 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4601 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4602 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4605 WREG32(HDP_DEBUG1, 0);
4606 tmp = readl((void __iomem *)ptr);
4608 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4611 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4613 u32 link_width_cntl, mask;
4615 if (rdev->flags & RADEON_IS_IGP)
4618 if (!(rdev->flags & RADEON_IS_PCIE))
4621 /* x2 cards have a special sequence */
4622 if (ASIC_IS_X2(rdev))
4625 radeon_gui_idle(rdev);
4629 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4632 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4635 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4638 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4641 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4644 /* not actually supported */
4645 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4648 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4651 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4655 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4656 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4657 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4658 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4659 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4661 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4664 int r600_get_pcie_lanes(struct radeon_device *rdev)
4666 u32 link_width_cntl;
4668 if (rdev->flags & RADEON_IS_IGP)
4671 if (!(rdev->flags & RADEON_IS_PCIE))
4674 /* x2 cards have a special sequence */
4675 if (ASIC_IS_X2(rdev))
4678 radeon_gui_idle(rdev);
4680 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4682 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4683 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4685 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4687 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4689 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4691 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4692 /* not actually supported */
4694 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4695 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4701 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4703 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4706 if (radeon_pcie_gen2 == 0)
4709 if (rdev->flags & RADEON_IS_IGP)
4712 if (!(rdev->flags & RADEON_IS_PCIE))
4715 /* x2 cards have a special sequence */
4716 if (ASIC_IS_X2(rdev))
4719 /* only RV6xx+ chips are supported */
4720 if (rdev->family <= CHIP_R600)
4723 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4724 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4727 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4728 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4729 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4733 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4735 /* 55 nm r6xx asics */
4736 if ((rdev->family == CHIP_RV670) ||
4737 (rdev->family == CHIP_RV620) ||
4738 (rdev->family == CHIP_RV635)) {
4739 /* advertise upconfig capability */
4740 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4741 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4742 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4743 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4744 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4745 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4746 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4747 LC_RECONFIG_ARC_MISSING_ESCAPE);
4748 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4749 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4751 link_width_cntl |= LC_UPCONFIGURE_DIS;
4752 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4756 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4757 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4758 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4760 /* 55 nm r6xx asics */
4761 if ((rdev->family == CHIP_RV670) ||
4762 (rdev->family == CHIP_RV620) ||
4763 (rdev->family == CHIP_RV635)) {
4764 WREG32(MM_CFGREGS_CNTL, 0x8);
4765 link_cntl2 = RREG32(0x4088);
4766 WREG32(MM_CFGREGS_CNTL, 0);
4767 /* not supported yet */
4768 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4772 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4773 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4774 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4775 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4776 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4777 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4779 tmp = RREG32(0x541c);
4780 WREG32(0x541c, tmp | 0x8);
4781 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4782 link_cntl2 = RREG16(0x4088);
4783 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4785 WREG16(0x4088, link_cntl2);
4786 WREG32(MM_CFGREGS_CNTL, 0);
4788 if ((rdev->family == CHIP_RV670) ||
4789 (rdev->family == CHIP_RV620) ||
4790 (rdev->family == CHIP_RV635)) {
4791 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4792 training_cntl &= ~LC_POINT_7_PLUS_EN;
4793 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4795 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4796 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4797 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4800 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4801 speed_cntl |= LC_GEN2_EN_STRAP;
4802 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4805 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4806 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4808 link_width_cntl |= LC_UPCONFIGURE_DIS;
4810 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4811 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4816 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4818 * @rdev: radeon_device pointer
4820 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4821 * Returns the 64 bit clock counter snapshot.
4823 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4827 mutex_lock(&rdev->gpu_clock_mutex);
4828 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4829 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4830 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4831 mutex_unlock(&rdev->gpu_clock_mutex);