drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/module.h>
  33 #include "drmP.h"
  34 #include "radeon_drm.h"
  35 #include "radeon.h"
  36 #include "radeon_asic.h"
  37 #include "radeon_mode.h"
  38 #include "r600d.h"
  39 #include "atom.h"
  40 #include "avivod.h"
  41
  42 #define PFP_UCODE_SIZE 576
  43 #define PM4_UCODE_SIZE 1792
  44 #define RLC_UCODE_SIZE 768
  45 #define R700_PFP_UCODE_SIZE 848
  46 #define R700_PM4_UCODE_SIZE 1360
  47 #define R700_RLC_UCODE_SIZE 1024
  48 #define EVERGREEN_PFP_UCODE_SIZE 1120
  49 #define EVERGREEN_PM4_UCODE_SIZE 1376
  50 #define EVERGREEN_RLC_UCODE_SIZE 768
  51 #define CAYMAN_RLC_UCODE_SIZE 1024
  52 #define ARUBA_RLC_UCODE_SIZE 1536
  53
  54 /* Firmware Names */
  55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  56 MODULE_FIRMWARE("radeon/R600_me.bin");
  57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV610_me.bin");
  59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RV630_me.bin");
  61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV620_me.bin");
  63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV635_me.bin");
  65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RV670_me.bin");
  67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  68 MODULE_FIRMWARE("radeon/RS780_me.bin");
  69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  70 MODULE_FIRMWARE("radeon/RV770_me.bin");
  71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  72 MODULE_FIRMWARE("radeon/RV730_me.bin");
  73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  74 MODULE_FIRMWARE("radeon/RV710_me.bin");
  75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  90 MODULE_FIRMWARE("radeon/PALM_me.bin");
  91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  96
  97 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  98
  99 /* r600,rv610,rv630,rv620,rv635,rv670 */
 100 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 101 void r600_gpu_init(struct radeon_device *rdev);
 102 void r600_fini(struct radeon_device *rdev);
 103 void r600_irq_disable(struct radeon_device *rdev);
 104 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 105
 106 /* get temperature in millidegrees */
 107 int rv6xx_get_temp(struct radeon_device *rdev)
 108 {
 109         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 110                 ASIC_T_SHIFT;
 111         int actual_temp = temp & 0xff;
 112
 113         if (temp & 0x100)
 114                 actual_temp -= 256;
 115
 116         return actual_temp * 1000;
 117 }
 118
 119 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 120 {
 121         int i;
 122
 123         rdev->pm.dynpm_can_upclock = true;
 124         rdev->pm.dynpm_can_downclock = true;
 125
 126         /* power state array is low to high, default is first */
 127         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 128                 int min_power_state_index = 0;
 129
 130                 if (rdev->pm.num_power_states > 2)
 131                         min_power_state_index = 1;
 132
 133                 switch (rdev->pm.dynpm_planned_action) {
 134                 case DYNPM_ACTION_MINIMUM:
 135                         rdev->pm.requested_power_state_index = min_power_state_index;
 136                         rdev->pm.requested_clock_mode_index = 0;
 137                         rdev->pm.dynpm_can_downclock = false;
 138                         break;
 139                 case DYNPM_ACTION_DOWNCLOCK:
 140                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 141                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 142                                 rdev->pm.dynpm_can_downclock = false;
 143                         } else {
 144                                 if (rdev->pm.active_crtc_count > 1) {
 145                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 146                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 147                                                         continue;
 148                                                 else if (i >= rdev->pm.current_power_state_index) {
 149                                                         rdev->pm.requested_power_state_index =
 150                                                                 rdev->pm.current_power_state_index;
 151                                                         break;
 152                                                 } else {
 153                                                         rdev->pm.requested_power_state_index = i;
 154                                                         break;
 155                                                 }
 156                                         }
 157                                 } else {
 158                                         if (rdev->pm.current_power_state_index == 0)
 159                                                 rdev->pm.requested_power_state_index =
 160                                                         rdev->pm.num_power_states - 1;
 161                                         else
 162                                                 rdev->pm.requested_power_state_index =
 163                                                         rdev->pm.current_power_state_index - 1;
 164                                 }
 165                         }
 166                         rdev->pm.requested_clock_mode_index = 0;
 167                         /* don't use the power state if crtcs are active and no display flag is set */
 168                         if ((rdev->pm.active_crtc_count > 0) &&
 169                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 170                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 171                              RADEON_PM_MODE_NO_DISPLAY)) {
 172                                 rdev->pm.requested_power_state_index++;
 173                         }
 174                         break;
 175                 case DYNPM_ACTION_UPCLOCK:
 176                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 177                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 178                                 rdev->pm.dynpm_can_upclock = false;
 179                         } else {
 180                                 if (rdev->pm.active_crtc_count > 1) {
 181                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 182                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 183                                                         continue;
 184                                                 else if (i <= rdev->pm.current_power_state_index) {
 185                                                         rdev->pm.requested_power_state_index =
 186                                                                 rdev->pm.current_power_state_index;
 187                                                         break;
 188                                                 } else {
 189                                                         rdev->pm.requested_power_state_index = i;
 190                                                         break;
 191                                                 }
 192                                         }
 193                                 } else
 194                                         rdev->pm.requested_power_state_index =
 195                                                 rdev->pm.current_power_state_index + 1;
 196                         }
 197                         rdev->pm.requested_clock_mode_index = 0;
 198                         break;
 199                 case DYNPM_ACTION_DEFAULT:
 200                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 201                         rdev->pm.requested_clock_mode_index = 0;
 202                         rdev->pm.dynpm_can_upclock = false;
 203                         break;
 204                 case DYNPM_ACTION_NONE:
 205                 default:
 206                         DRM_ERROR("Requested mode for not defined action\n");
 207                         return;
 208                 }
 209         } else {
 210                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 211                 /* for now just select the first power state and switch between clock modes */
 212                 /* power state array is low to high, default is first (0) */
 213                 if (rdev->pm.active_crtc_count > 1) {
 214                         rdev->pm.requested_power_state_index = -1;
 215                         /* start at 1 as we don't want the default mode */
 216                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 217                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 218                                         continue;
 219                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 220                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 221                                         rdev->pm.requested_power_state_index = i;
 222                                         break;
 223                                 }
 224                         }
 225                         /* if nothing selected, grab the default state. */
 226                         if (rdev->pm.requested_power_state_index == -1)
 227                                 rdev->pm.requested_power_state_index = 0;
 228                 } else
 229                         rdev->pm.requested_power_state_index = 1;
 230
 231                 switch (rdev->pm.dynpm_planned_action) {
 232                 case DYNPM_ACTION_MINIMUM:
 233                         rdev->pm.requested_clock_mode_index = 0;
 234                         rdev->pm.dynpm_can_downclock = false;
 235                         break;
 236                 case DYNPM_ACTION_DOWNCLOCK:
 237                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 238                                 if (rdev->pm.current_clock_mode_index == 0) {
 239                                         rdev->pm.requested_clock_mode_index = 0;
 240                                         rdev->pm.dynpm_can_downclock = false;
 241                                 } else
 242                                         rdev->pm.requested_clock_mode_index =
 243                                                 rdev->pm.current_clock_mode_index - 1;
 244                         } else {
 245                                 rdev->pm.requested_clock_mode_index = 0;
 246                                 rdev->pm.dynpm_can_downclock = false;
 247                         }
 248                         /* don't use the power state if crtcs are active and no display flag is set */
 249                         if ((rdev->pm.active_crtc_count > 0) &&
 250                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 251                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 252                              RADEON_PM_MODE_NO_DISPLAY)) {
 253                                 rdev->pm.requested_clock_mode_index++;
 254                         }
 255                         break;
 256                 case DYNPM_ACTION_UPCLOCK:
 257                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 258                                 if (rdev->pm.current_clock_mode_index ==
 259                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 260                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 261                                         rdev->pm.dynpm_can_upclock = false;
 262                                 } else
 263                                         rdev->pm.requested_clock_mode_index =
 264                                                 rdev->pm.current_clock_mode_index + 1;
 265                         } else {
 266                                 rdev->pm.requested_clock_mode_index =
 267                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 268                                 rdev->pm.dynpm_can_upclock = false;
 269                         }
 270                         break;
 271                 case DYNPM_ACTION_DEFAULT:
 272                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 273                         rdev->pm.requested_clock_mode_index = 0;
 274                         rdev->pm.dynpm_can_upclock = false;
 275                         break;
 276                 case DYNPM_ACTION_NONE:
 277                 default:
 278                         DRM_ERROR("Requested mode for not defined action\n");
 279                         return;
 280                 }
 281         }
 282
 283         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 284                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 285                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 286                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 287                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 288                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 289                   pcie_lanes);
 290 }
 291
 292 void rs780_pm_init_profile(struct radeon_device *rdev)
 293 {
 294         if (rdev->pm.num_power_states == 2) {
 295                 /* default */
 296                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 297                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 298                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 299                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 300                 /* low sh */
 301                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 302                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 303                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 304                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 305                 /* mid sh */
 306                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 307                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 309                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 310                 /* high sh */
 311                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 312                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 313                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 314                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 315                 /* low mh */
 316                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 317                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 319                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 320                 /* mid mh */
 321                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 322                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 325                 /* high mh */
 326                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 327                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 328                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 330         } else if (rdev->pm.num_power_states == 3) {
 331                 /* default */
 332                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 333                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 334                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 335                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 336                 /* low sh */
 337                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 338                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 339                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 340                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 341                 /* mid sh */
 342                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 343                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 344                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 345                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 346                 /* high sh */
 347                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 348                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 349                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 350                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 351                 /* low mh */
 352                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 353                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 354                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 355                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 356                 /* mid mh */
 357                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 358                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 359                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 360                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 361                 /* high mh */
 362                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 363                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 364                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 365                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 366         } else {
 367                 /* default */
 368                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 369                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 370                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 371                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 372                 /* low sh */
 373                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 374                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 375                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 376                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 377                 /* mid sh */
 378                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 379                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 380                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 381                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 382                 /* high sh */
 383                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 384                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 385                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 386                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 387                 /* low mh */
 388                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 389                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 390                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 391                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 392                 /* mid mh */
 393                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 394                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 395                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 396                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 397                 /* high mh */
 398                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 399                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 400                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 401                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 402         }
 403 }
 404
 405 void r600_pm_init_profile(struct radeon_device *rdev)
 406 {
 407         int idx;
 408
 409         if (rdev->family == CHIP_R600) {
 410                 /* XXX */
 411                 /* default */
 412                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 413                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 414                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 415                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 416                 /* low sh */
 417                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 418                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 419                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 420                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 421                 /* mid sh */
 422                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 423                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 424                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 425                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 426                 /* high sh */
 427                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 428                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 429                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 430                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 431                 /* low mh */
 432                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 433                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 434                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 435                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 436                 /* mid mh */
 437                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 438                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 439                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 440                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 441                 /* high mh */
 442                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 443                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 444                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 445                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 446         } else {
 447                 if (rdev->pm.num_power_states < 4) {
 448                         /* default */
 449                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 450                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 451                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 452                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 453                         /* low sh */
 454                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 455                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 456                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 457                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 458                         /* mid sh */
 459                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 460                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 461                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 462                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 463                         /* high sh */
 464                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 465                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 466                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 467                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 468                         /* low mh */
 469                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 470                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 471                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 472                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 473                         /* low mh */
 474                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 475                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 476                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 477                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 478                         /* high mh */
 479                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 480                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 481                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 482                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 483                 } else {
 484                         /* default */
 485                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 486                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 487                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 488                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 489                         /* low sh */
 490                         if (rdev->flags & RADEON_IS_MOBILITY)
 491                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 492                         else
 493                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 494                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 495                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 496                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 497                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 498                         /* mid sh */
 499                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 500                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 501                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 502                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 503                         /* high sh */
 504                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 505                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 506                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 507                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 508                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 509                         /* low mh */
 510                         if (rdev->flags & RADEON_IS_MOBILITY)
 511                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 512                         else
 513                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 514                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 515                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 516                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 517                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 518                         /* mid mh */
 519                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 520                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 521                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 522                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 523                         /* high mh */
 524                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 525                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 526                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 527                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 528                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 529                 }
 530         }
 531 }
 532
 533 void r600_pm_misc(struct radeon_device *rdev)
 534 {
 535         int req_ps_idx = rdev->pm.requested_power_state_index;
 536         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 537         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 538         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 539
 540         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 541                 /* 0xff01 is a flag rather then an actual voltage */
 542                 if (voltage->voltage == 0xff01)
 543                         return;
 544                 if (voltage->voltage != rdev->pm.current_vddc) {
 545                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 546                         rdev->pm.current_vddc = voltage->voltage;
 547                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 548                 }
 549         }
 550 }
 551
 552 bool r600_gui_idle(struct radeon_device *rdev)
 553 {
 554         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 555                 return false;
 556         else
 557                 return true;
 558 }
 559
 560 /* hpd for digital panel detect/disconnect */
 561 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 562 {
 563         bool connected = false;
 564
 565         if (ASIC_IS_DCE3(rdev)) {
 566                 switch (hpd) {
 567                 case RADEON_HPD_1:
 568                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 569                                 connected = true;
 570                         break;
 571                 case RADEON_HPD_2:
 572                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 573                                 connected = true;
 574                         break;
 575                 case RADEON_HPD_3:
 576                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 577                                 connected = true;
 578                         break;
 579                 case RADEON_HPD_4:
 580                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 581                                 connected = true;
 582                         break;
 583                         /* DCE 3.2 */
 584                 case RADEON_HPD_5:
 585                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 586                                 connected = true;
 587                         break;
 588                 case RADEON_HPD_6:
 589                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 590                                 connected = true;
 591                         break;
 592                 default:
 593                         break;
 594                 }
 595         } else {
 596                 switch (hpd) {
 597                 case RADEON_HPD_1:
 598                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 599                                 connected = true;
 600                         break;
 601                 case RADEON_HPD_2:
 602                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 603                                 connected = true;
 604                         break;
 605                 case RADEON_HPD_3:
 606                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 607                                 connected = true;
 608                         break;
 609                 default:
 610                         break;
 611                 }
 612         }
 613         return connected;
 614 }
 615
 616 void r600_hpd_set_polarity(struct radeon_device *rdev,
 617                            enum radeon_hpd_id hpd)
 618 {
 619         u32 tmp;
 620         bool connected = r600_hpd_sense(rdev, hpd);
 621
 622         if (ASIC_IS_DCE3(rdev)) {
 623                 switch (hpd) {
 624                 case RADEON_HPD_1:
 625                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 626                         if (connected)
 627                                 tmp &= ~DC_HPDx_INT_POLARITY;
 628                         else
 629                                 tmp |= DC_HPDx_INT_POLARITY;
 630                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 631                         break;
 632                 case RADEON_HPD_2:
 633                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 634                         if (connected)
 635                                 tmp &= ~DC_HPDx_INT_POLARITY;
 636                         else
 637                                 tmp |= DC_HPDx_INT_POLARITY;
 638                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 639                         break;
 640                 case RADEON_HPD_3:
 641                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 642                         if (connected)
 643                                 tmp &= ~DC_HPDx_INT_POLARITY;
 644                         else
 645                                 tmp |= DC_HPDx_INT_POLARITY;
 646                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 647                         break;
 648                 case RADEON_HPD_4:
 649                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 650                         if (connected)
 651                                 tmp &= ~DC_HPDx_INT_POLARITY;
 652                         else
 653                                 tmp |= DC_HPDx_INT_POLARITY;
 654                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 655                         break;
 656                 case RADEON_HPD_5:
 657                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 658                         if (connected)
 659                                 tmp &= ~DC_HPDx_INT_POLARITY;
 660                         else
 661                                 tmp |= DC_HPDx_INT_POLARITY;
 662                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 663                         break;
 664                         /* DCE 3.2 */
 665                 case RADEON_HPD_6:
 666                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 667                         if (connected)
 668                                 tmp &= ~DC_HPDx_INT_POLARITY;
 669                         else
 670                                 tmp |= DC_HPDx_INT_POLARITY;
 671                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 672                         break;
 673                 default:
 674                         break;
 675                 }
 676         } else {
 677                 switch (hpd) {
 678                 case RADEON_HPD_1:
 679                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 680                         if (connected)
 681                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 682                         else
 683                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 684                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 685                         break;
 686                 case RADEON_HPD_2:
 687                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 688                         if (connected)
 689                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 690                         else
 691                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 692                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 693                         break;
 694                 case RADEON_HPD_3:
 695                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 696                         if (connected)
 697                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 698                         else
 699                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 700                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 701                         break;
 702                 default:
 703                         break;
 704                 }
 705         }
 706 }
 707
 708 void r600_hpd_init(struct radeon_device *rdev)
 709 {
 710         struct drm_device *dev = rdev->ddev;
 711         struct drm_connector *connector;
 712
 713         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 714                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 715
 716                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 717                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 718                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 719                          * aux dp channel on imac and help (but not completely fix)
 720                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 721                          */
 722                         continue;
 723                 }
 724                 if (ASIC_IS_DCE3(rdev)) {
 725                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 726                         if (ASIC_IS_DCE32(rdev))
 727                                 tmp |= DC_HPDx_EN;
 728
 729                         switch (radeon_connector->hpd.hpd) {
 730                         case RADEON_HPD_1:
 731                                 WREG32(DC_HPD1_CONTROL, tmp);
 732                                 rdev->irq.hpd[0] = true;
 733                                 break;
 734                         case RADEON_HPD_2:
 735                                 WREG32(DC_HPD2_CONTROL, tmp);
 736                                 rdev->irq.hpd[1] = true;
 737                                 break;
 738                         case RADEON_HPD_3:
 739                                 WREG32(DC_HPD3_CONTROL, tmp);
 740                                 rdev->irq.hpd[2] = true;
 741                                 break;
 742                         case RADEON_HPD_4:
 743                                 WREG32(DC_HPD4_CONTROL, tmp);
 744                                 rdev->irq.hpd[3] = true;
 745                                 break;
 746                                 /* DCE 3.2 */
 747                         case RADEON_HPD_5:
 748                                 WREG32(DC_HPD5_CONTROL, tmp);
 749                                 rdev->irq.hpd[4] = true;
 750                                 break;
 751                         case RADEON_HPD_6:
 752                                 WREG32(DC_HPD6_CONTROL, tmp);
 753                                 rdev->irq.hpd[5] = true;
 754                                 break;
 755                         default:
 756                                 break;
 757                         }
 758                 } else {
 759                         switch (radeon_connector->hpd.hpd) {
 760                         case RADEON_HPD_1:
 761                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 762                                 rdev->irq.hpd[0] = true;
 763                                 break;
 764                         case RADEON_HPD_2:
 765                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 766                                 rdev->irq.hpd[1] = true;
 767                                 break;
 768                         case RADEON_HPD_3:
 769                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 770                                 rdev->irq.hpd[2] = true;
 771                                 break;
 772                         default:
 773                                 break;
 774                         }
 775                 }
 776                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 777         }
 778         if (rdev->irq.installed)
 779                 r600_irq_set(rdev);
 780 }
 781
 782 void r600_hpd_fini(struct radeon_device *rdev)
 783 {
 784         struct drm_device *dev = rdev->ddev;
 785         struct drm_connector *connector;
 786
 787         if (ASIC_IS_DCE3(rdev)) {
 788                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 789                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 790                         switch (radeon_connector->hpd.hpd) {
 791                         case RADEON_HPD_1:
 792                                 WREG32(DC_HPD1_CONTROL, 0);
 793                                 rdev->irq.hpd[0] = false;
 794                                 break;
 795                         case RADEON_HPD_2:
 796                                 WREG32(DC_HPD2_CONTROL, 0);
 797                                 rdev->irq.hpd[1] = false;
 798                                 break;
 799                         case RADEON_HPD_3:
 800                                 WREG32(DC_HPD3_CONTROL, 0);
 801                                 rdev->irq.hpd[2] = false;
 802                                 break;
 803                         case RADEON_HPD_4:
 804                                 WREG32(DC_HPD4_CONTROL, 0);
 805                                 rdev->irq.hpd[3] = false;
 806                                 break;
 807                                 /* DCE 3.2 */
 808                         case RADEON_HPD_5:
 809                                 WREG32(DC_HPD5_CONTROL, 0);
 810                                 rdev->irq.hpd[4] = false;
 811                                 break;
 812                         case RADEON_HPD_6:
 813                                 WREG32(DC_HPD6_CONTROL, 0);
 814                                 rdev->irq.hpd[5] = false;
 815                                 break;
 816                         default:
 817                                 break;
 818                         }
 819                 }
 820         } else {
 821                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 822                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 823                         switch (radeon_connector->hpd.hpd) {
 824                         case RADEON_HPD_1:
 825                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 826                                 rdev->irq.hpd[0] = false;
 827                                 break;
 828                         case RADEON_HPD_2:
 829                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 830                                 rdev->irq.hpd[1] = false;
 831                                 break;
 832                         case RADEON_HPD_3:
 833                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 834                                 rdev->irq.hpd[2] = false;
 835                                 break;
 836                         default:
 837                                 break;
 838                         }
 839                 }
 840         }
 841 }
 842
 843 /*
 844  * R600 PCIE GART
 845  */
 846 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 847 {
 848         unsigned i;
 849         u32 tmp;
 850
 851         /* flush hdp cache so updates hit vram */
 852         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 853             !(rdev->flags & RADEON_IS_AGP)) {
 854                 void __iomem *ptr = (void *)rdev->gart.ptr;
 855                 u32 tmp;
 856
 857                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 858                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 859                  * This seems to cause problems on some AGP cards. Just use the old
 860                  * method for them.
 861                  */
 862                 WREG32(HDP_DEBUG1, 0);
 863                 tmp = readl((void __iomem *)ptr);
 864         } else
 865                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 866
 867         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 868         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 869         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 870         for (i = 0; i < rdev->usec_timeout; i++) {
 871                 /* read MC_STATUS */
 872                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 873                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 874                 if (tmp == 2) {
 875                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 876                         return;
 877                 }
 878                 if (tmp) {
 879                         return;
 880                 }
 881                 udelay(1);
 882         }
 883 }
 884
 885 int r600_pcie_gart_init(struct radeon_device *rdev)
 886 {
 887         int r;
 888
 889         if (rdev->gart.robj) {
 890                 WARN(1, "R600 PCIE GART already initialized\n");
 891                 return 0;
 892         }
 893         /* Initialize common gart structure */
 894         r = radeon_gart_init(rdev);
 895         if (r)
 896                 return r;
 897         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 898         return radeon_gart_table_vram_alloc(rdev);
 899 }
 900
 901 int r600_pcie_gart_enable(struct radeon_device *rdev)
 902 {
 903         u32 tmp;
 904         int r, i;
 905
 906         if (rdev->gart.robj == NULL) {
 907                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 908                 return -EINVAL;
 909         }
 910         r = radeon_gart_table_vram_pin(rdev);
 911         if (r)
 912                 return r;
 913         radeon_gart_restore(rdev);
 914
 915         /* Setup L2 cache */
 916         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 917                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 918                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 919         WREG32(VM_L2_CNTL2, 0);
 920         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 921         /* Setup TLB control */
 922         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 923                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 924                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 925                 ENABLE_WAIT_L2_QUERY;
 926         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 927         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 928         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 929         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 930         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 931         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 932         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 933         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 934         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 935         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 936         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 937         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 938         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 939         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 940         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 941         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 942         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 943         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 944                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 945         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 946                         (u32)(rdev->dummy_page.addr >> 12));
 947         for (i = 1; i < 7; i++)
 948                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 949
 950         r600_pcie_gart_tlb_flush(rdev);
 951         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 952                  (unsigned)(rdev->mc.gtt_size >> 20),
 953                  (unsigned long long)rdev->gart.table_addr);
 954         rdev->gart.ready = true;
 955         return 0;
 956 }
 957
 958 void r600_pcie_gart_disable(struct radeon_device *rdev)
 959 {
 960         u32 tmp;
 961         int i;
 962
 963         /* Disable all tables */
 964         for (i = 0; i < 7; i++)
 965                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 966
 967         /* Disable L2 cache */
 968         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 969                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 970         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 971         /* Setup L1 TLB control */
 972         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 973                 ENABLE_WAIT_L2_QUERY;
 974         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 975         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 976         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 977         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 978         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 979         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 980         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 981         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 982         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 983         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 984         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 985         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 986         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 987         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 988         radeon_gart_table_vram_unpin(rdev);
 989 }
 990
 991 void r600_pcie_gart_fini(struct radeon_device *rdev)
 992 {
 993         radeon_gart_fini(rdev);
 994         r600_pcie_gart_disable(rdev);
 995         radeon_gart_table_vram_free(rdev);
 996 }
 997
 998 void r600_agp_enable(struct radeon_device *rdev)
 999 {
1000         u32 tmp;
1001         int i;
1002
1003         /* Setup L2 cache */
1004         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1005                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1006                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1007         WREG32(VM_L2_CNTL2, 0);
1008         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1009         /* Setup TLB control */
1010         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1011                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1012                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1013                 ENABLE_WAIT_L2_QUERY;
1014         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1015         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1016         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1017         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1018         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1019         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1020         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1021         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1022         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1023         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1024         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1025         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1026         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1027         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1028         for (i = 0; i < 7; i++)
1029                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1030 }
1031
1032 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1033 {
1034         unsigned i;
1035         u32 tmp;
1036
1037         for (i = 0; i < rdev->usec_timeout; i++) {
1038                 /* read MC_STATUS */
1039                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1040                 if (!tmp)
1041                         return 0;
1042                 udelay(1);
1043         }
1044         return -1;
1045 }
1046
1047 static void r600_mc_program(struct radeon_device *rdev)
1048 {
1049         struct rv515_mc_save save;
1050         u32 tmp;
1051         int i, j;
1052
1053         /* Initialize HDP */
1054         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1055                 WREG32((0x2c14 + j), 0x00000000);
1056                 WREG32((0x2c18 + j), 0x00000000);
1057                 WREG32((0x2c1c + j), 0x00000000);
1058                 WREG32((0x2c20 + j), 0x00000000);
1059                 WREG32((0x2c24 + j), 0x00000000);
1060         }
1061         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1062
1063         rv515_mc_stop(rdev, &save);
1064         if (r600_mc_wait_for_idle(rdev)) {
1065                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1066         }
1067         /* Lockout access through VGA aperture (doesn't exist before R600) */
1068         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1069         /* Update configuration */
1070         if (rdev->flags & RADEON_IS_AGP) {
1071                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1072                         /* VRAM before AGP */
1073                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1074                                 rdev->mc.vram_start >> 12);
1075                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1076                                 rdev->mc.gtt_end >> 12);
1077                 } else {
1078                         /* VRAM after AGP */
1079                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1080                                 rdev->mc.gtt_start >> 12);
1081                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1082                                 rdev->mc.vram_end >> 12);
1083                 }
1084         } else {
1085                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1086                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1087         }
1088         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1089         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1090         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1091         WREG32(MC_VM_FB_LOCATION, tmp);
1092         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1093         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1094         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1095         if (rdev->flags & RADEON_IS_AGP) {
1096                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1097                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1098                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1099         } else {
1100                 WREG32(MC_VM_AGP_BASE, 0);
1101                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1102                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1103         }
1104         if (r600_mc_wait_for_idle(rdev)) {
1105                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1106         }
1107         rv515_mc_resume(rdev, &save);
1108         /* we need to own VRAM, so turn off the VGA renderer here
1109          * to stop it overwriting our objects */
1110         rv515_vga_render_disable(rdev);
1111 }
1112
1113 /**
1114  * r600_vram_gtt_location - try to find VRAM & GTT location
1115  * @rdev: radeon device structure holding all necessary informations
1116  * @mc: memory controller structure holding memory informations
1117  *
1118  * Function will place try to place VRAM at same place as in CPU (PCI)
1119  * address space as some GPU seems to have issue when we reprogram at
1120  * different address space.
1121  *
1122  * If there is not enough space to fit the unvisible VRAM after the
1123  * aperture then we limit the VRAM size to the aperture.
1124  *
1125  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1126  * them to be in one from GPU point of view so that we can program GPU to
1127  * catch access outside them (weird GPU policy see ??).
1128  *
1129  * This function will never fails, worst case are limiting VRAM or GTT.
1130  *
1131  * Note: GTT start, end, size should be initialized before calling this
1132  * function on AGP platform.
1133  */
1134 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1135 {
1136         u64 size_bf, size_af;
1137
1138         if (mc->mc_vram_size > 0xE0000000) {
1139                 /* leave room for at least 512M GTT */
1140                 dev_warn(rdev->dev, "limiting VRAM\n");
1141                 mc->real_vram_size = 0xE0000000;
1142                 mc->mc_vram_size = 0xE0000000;
1143         }
1144         if (rdev->flags & RADEON_IS_AGP) {
1145                 size_bf = mc->gtt_start;
1146                 size_af = 0xFFFFFFFF - mc->gtt_end;
1147                 if (size_bf > size_af) {
1148                         if (mc->mc_vram_size > size_bf) {
1149                                 dev_warn(rdev->dev, "limiting VRAM\n");
1150                                 mc->real_vram_size = size_bf;
1151                                 mc->mc_vram_size = size_bf;
1152                         }
1153                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1154                 } else {
1155                         if (mc->mc_vram_size > size_af) {
1156                                 dev_warn(rdev->dev, "limiting VRAM\n");
1157                                 mc->real_vram_size = size_af;
1158                                 mc->mc_vram_size = size_af;
1159                         }
1160                         mc->vram_start = mc->gtt_end + 1;
1161                 }
1162                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1163                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1164                                 mc->mc_vram_size >> 20, mc->vram_start,
1165                                 mc->vram_end, mc->real_vram_size >> 20);
1166         } else {
1167                 u64 base = 0;
1168                 if (rdev->flags & RADEON_IS_IGP) {
1169                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1170                         base <<= 24;
1171                 }
1172                 radeon_vram_location(rdev, &rdev->mc, base);
1173                 rdev->mc.gtt_base_align = 0;
1174                 radeon_gtt_location(rdev, mc);
1175         }
1176 }
1177
1178 int r600_mc_init(struct radeon_device *rdev)
1179 {
1180         u32 tmp;
1181         int chansize, numchan;
1182
1183         /* Get VRAM informations */
1184         rdev->mc.vram_is_ddr = true;
1185         tmp = RREG32(RAMCFG);
1186         if (tmp & CHANSIZE_OVERRIDE) {
1187                 chansize = 16;
1188         } else if (tmp & CHANSIZE_MASK) {
1189                 chansize = 64;
1190         } else {
1191                 chansize = 32;
1192         }
1193         tmp = RREG32(CHMAP);
1194         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1195         case 0:
1196         default:
1197                 numchan = 1;
1198                 break;
1199         case 1:
1200                 numchan = 2;
1201                 break;
1202         case 2:
1203                 numchan = 4;
1204                 break;
1205         case 3:
1206                 numchan = 8;
1207                 break;
1208         }
1209         rdev->mc.vram_width = numchan * chansize;
1210         /* Could aper size report 0 ? */
1211         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1212         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1213         /* Setup GPU memory space */
1214         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1215         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1216         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1217         r600_vram_gtt_location(rdev, &rdev->mc);
1218
1219         if (rdev->flags & RADEON_IS_IGP) {
1220                 rs690_pm_info(rdev);
1221                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1222         }
1223         radeon_update_bandwidth_info(rdev);
1224         return 0;
1225 }
1226
1227 int r600_vram_scratch_init(struct radeon_device *rdev)
1228 {
1229         int r;
1230
1231         if (rdev->vram_scratch.robj == NULL) {
1232                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1233                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1234                                      NULL, &rdev->vram_scratch.robj);
1235                 if (r) {
1236                         return r;
1237                 }
1238         }
1239
1240         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1241         if (unlikely(r != 0))
1242                 return r;
1243         r = radeon_bo_pin(rdev->vram_scratch.robj,
1244                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1245         if (r) {
1246                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1247                 return r;
1248         }
1249         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1250                                 (void **)&rdev->vram_scratch.ptr);
1251         if (r)
1252                 radeon_bo_unpin(rdev->vram_scratch.robj);
1253         radeon_bo_unreserve(rdev->vram_scratch.robj);
1254
1255         return r;
1256 }
1257
1258 void r600_vram_scratch_fini(struct radeon_device *rdev)
1259 {
1260         int r;
1261
1262         if (rdev->vram_scratch.robj == NULL) {
1263                 return;
1264         }
1265         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1266         if (likely(r == 0)) {
1267                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1268                 radeon_bo_unpin(rdev->vram_scratch.robj);
1269                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1270         }
1271         radeon_bo_unref(&rdev->vram_scratch.robj);
1272 }
1273
1274 /* We doesn't check that the GPU really needs a reset we simply do the
1275  * reset, it's up to the caller to determine if the GPU needs one. We
1276  * might add an helper function to check that.
1277  */
1278 int r600_gpu_soft_reset(struct radeon_device *rdev)
1279 {
1280         struct rv515_mc_save save;
1281         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1282                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1283                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1284                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1285                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1286                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1287                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1288                                 S_008010_GUI_ACTIVE(1);
1289         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1290                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1291                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1292                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1293                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1294                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1295                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1296                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1297         u32 tmp;
1298
1299         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1300                 return 0;
1301
1302         dev_info(rdev->dev, "GPU softreset \n");
1303         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1304                 RREG32(R_008010_GRBM_STATUS));
1305         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1306                 RREG32(R_008014_GRBM_STATUS2));
1307         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1308                 RREG32(R_000E50_SRBM_STATUS));
1309         rv515_mc_stop(rdev, &save);
1310         if (r600_mc_wait_for_idle(rdev)) {
1311                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1312         }
1313         /* Disable CP parsing/prefetching */
1314         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1315         /* Check if any of the rendering block is busy and reset it */
1316         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1317             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1318                 tmp = S_008020_SOFT_RESET_CR(1) |
1319                         S_008020_SOFT_RESET_DB(1) |
1320                         S_008020_SOFT_RESET_CB(1) |
1321                         S_008020_SOFT_RESET_PA(1) |
1322                         S_008020_SOFT_RESET_SC(1) |
1323                         S_008020_SOFT_RESET_SMX(1) |
1324                         S_008020_SOFT_RESET_SPI(1) |
1325                         S_008020_SOFT_RESET_SX(1) |
1326                         S_008020_SOFT_RESET_SH(1) |
1327                         S_008020_SOFT_RESET_TC(1) |
1328                         S_008020_SOFT_RESET_TA(1) |
1329                         S_008020_SOFT_RESET_VC(1) |
1330                         S_008020_SOFT_RESET_VGT(1);
1331                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1332                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1333                 RREG32(R_008020_GRBM_SOFT_RESET);
1334                 mdelay(15);
1335                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1336         }
1337         /* Reset CP (we always reset CP) */
1338         tmp = S_008020_SOFT_RESET_CP(1);
1339         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1340         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1341         RREG32(R_008020_GRBM_SOFT_RESET);
1342         mdelay(15);
1343         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1344         /* Wait a little for things to settle down */
1345         mdelay(1);
1346         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1347                 RREG32(R_008010_GRBM_STATUS));
1348         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1349                 RREG32(R_008014_GRBM_STATUS2));
1350         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1351                 RREG32(R_000E50_SRBM_STATUS));
1352         rv515_mc_resume(rdev, &save);
1353         return 0;
1354 }
1355
1356 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1357 {
1358         u32 srbm_status;
1359         u32 grbm_status;
1360         u32 grbm_status2;
1361
1362         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1363         grbm_status = RREG32(R_008010_GRBM_STATUS);
1364         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1365         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1366                 radeon_ring_lockup_update(ring);
1367                 return false;
1368         }
1369         /* force CP activities */
1370         radeon_ring_force_activity(rdev, ring);
1371         return radeon_ring_test_lockup(rdev, ring);
1372 }
1373
1374 int r600_asic_reset(struct radeon_device *rdev)
1375 {
1376         return r600_gpu_soft_reset(rdev);
1377 }
1378
1379 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1380                               u32 tiling_pipe_num,
1381                               u32 max_rb_num,
1382                               u32 total_max_rb_num,
1383                               u32 disabled_rb_mask)
1384 {
1385         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1386         u32 pipe_rb_ratio, pipe_rb_remain;
1387         u32 data = 0, mask = 1 << (max_rb_num - 1);
1388         unsigned i, j;
1389
1390         /* mask out the RBs that don't exist on that asic */
1391         disabled_rb_mask |= (0xff << max_rb_num) & 0xff;
1392
1393         rendering_pipe_num = 1 << tiling_pipe_num;
1394         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1395         BUG_ON(rendering_pipe_num < req_rb_num);
1396
1397         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1398         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1399
1400         if (rdev->family <= CHIP_RV740) {
1401                 /* r6xx/r7xx */
1402                 rb_num_width = 2;
1403         } else {
1404                 /* eg+ */
1405                 rb_num_width = 4;
1406         }
1407
1408         for (i = 0; i < max_rb_num; i++) {
1409                 if (!(mask & disabled_rb_mask)) {
1410                         for (j = 0; j < pipe_rb_ratio; j++) {
1411                                 data <<= rb_num_width;
1412                                 data |= max_rb_num - i - 1;
1413                         }
1414                         if (pipe_rb_remain) {
1415                                 data <<= rb_num_width;
1416                                 data |= max_rb_num - i - 1;
1417                                 pipe_rb_remain--;
1418                         }
1419                 }
1420                 mask >>= 1;
1421         }
1422
1423         return data;
1424 }
1425
1426 int r600_count_pipe_bits(uint32_t val)
1427 {
1428         int i, ret = 0;
1429
1430         for (i = 0; i < 32; i++) {
1431                 ret += val & 1;
1432                 val >>= 1;
1433         }
1434         return ret;
1435 }
1436
1437 void r600_gpu_init(struct radeon_device *rdev)
1438 {
1439         u32 tiling_config;
1440         u32 ramcfg;
1441         u32 cc_rb_backend_disable;
1442         u32 cc_gc_shader_pipe_config;
1443         u32 tmp;
1444         int i, j;
1445         u32 sq_config;
1446         u32 sq_gpr_resource_mgmt_1 = 0;
1447         u32 sq_gpr_resource_mgmt_2 = 0;
1448         u32 sq_thread_resource_mgmt = 0;
1449         u32 sq_stack_resource_mgmt_1 = 0;
1450         u32 sq_stack_resource_mgmt_2 = 0;
1451         u32 disabled_rb_mask;
1452
1453         rdev->config.r600.tiling_group_size = 256;
1454         switch (rdev->family) {
1455         case CHIP_R600:
1456                 rdev->config.r600.max_pipes = 4;
1457                 rdev->config.r600.max_tile_pipes = 8;
1458                 rdev->config.r600.max_simds = 4;
1459                 rdev->config.r600.max_backends = 4;
1460                 rdev->config.r600.max_gprs = 256;
1461                 rdev->config.r600.max_threads = 192;
1462                 rdev->config.r600.max_stack_entries = 256;
1463                 rdev->config.r600.max_hw_contexts = 8;
1464                 rdev->config.r600.max_gs_threads = 16;
1465                 rdev->config.r600.sx_max_export_size = 128;
1466                 rdev->config.r600.sx_max_export_pos_size = 16;
1467                 rdev->config.r600.sx_max_export_smx_size = 128;
1468                 rdev->config.r600.sq_num_cf_insts = 2;
1469                 break;
1470         case CHIP_RV630:
1471         case CHIP_RV635:
1472                 rdev->config.r600.max_pipes = 2;
1473                 rdev->config.r600.max_tile_pipes = 2;
1474                 rdev->config.r600.max_simds = 3;
1475                 rdev->config.r600.max_backends = 1;
1476                 rdev->config.r600.max_gprs = 128;
1477                 rdev->config.r600.max_threads = 192;
1478                 rdev->config.r600.max_stack_entries = 128;
1479                 rdev->config.r600.max_hw_contexts = 8;
1480                 rdev->config.r600.max_gs_threads = 4;
1481                 rdev->config.r600.sx_max_export_size = 128;
1482                 rdev->config.r600.sx_max_export_pos_size = 16;
1483                 rdev->config.r600.sx_max_export_smx_size = 128;
1484                 rdev->config.r600.sq_num_cf_insts = 2;
1485                 break;
1486         case CHIP_RV610:
1487         case CHIP_RV620:
1488         case CHIP_RS780:
1489         case CHIP_RS880:
1490                 rdev->config.r600.max_pipes = 1;
1491                 rdev->config.r600.max_tile_pipes = 1;
1492                 rdev->config.r600.max_simds = 2;
1493                 rdev->config.r600.max_backends = 1;
1494                 rdev->config.r600.max_gprs = 128;
1495                 rdev->config.r600.max_threads = 192;
1496                 rdev->config.r600.max_stack_entries = 128;
1497                 rdev->config.r600.max_hw_contexts = 4;
1498                 rdev->config.r600.max_gs_threads = 4;
1499                 rdev->config.r600.sx_max_export_size = 128;
1500                 rdev->config.r600.sx_max_export_pos_size = 16;
1501                 rdev->config.r600.sx_max_export_smx_size = 128;
1502                 rdev->config.r600.sq_num_cf_insts = 1;
1503                 break;
1504         case CHIP_RV670:
1505                 rdev->config.r600.max_pipes = 4;
1506                 rdev->config.r600.max_tile_pipes = 4;
1507                 rdev->config.r600.max_simds = 4;
1508                 rdev->config.r600.max_backends = 4;
1509                 rdev->config.r600.max_gprs = 192;
1510                 rdev->config.r600.max_threads = 192;
1511                 rdev->config.r600.max_stack_entries = 256;
1512                 rdev->config.r600.max_hw_contexts = 8;
1513                 rdev->config.r600.max_gs_threads = 16;
1514                 rdev->config.r600.sx_max_export_size = 128;
1515                 rdev->config.r600.sx_max_export_pos_size = 16;
1516                 rdev->config.r600.sx_max_export_smx_size = 128;
1517                 rdev->config.r600.sq_num_cf_insts = 2;
1518                 break;
1519         default:
1520                 break;
1521         }
1522
1523         /* Initialize HDP */
1524         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1525                 WREG32((0x2c14 + j), 0x00000000);
1526                 WREG32((0x2c18 + j), 0x00000000);
1527                 WREG32((0x2c1c + j), 0x00000000);
1528                 WREG32((0x2c20 + j), 0x00000000);
1529                 WREG32((0x2c24 + j), 0x00000000);
1530         }
1531
1532         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1533
1534         /* Setup tiling */
1535         tiling_config = 0;
1536         ramcfg = RREG32(RAMCFG);
1537         switch (rdev->config.r600.max_tile_pipes) {
1538         case 1:
1539                 tiling_config |= PIPE_TILING(0);
1540                 break;
1541         case 2:
1542                 tiling_config |= PIPE_TILING(1);
1543                 break;
1544         case 4:
1545                 tiling_config |= PIPE_TILING(2);
1546                 break;
1547         case 8:
1548                 tiling_config |= PIPE_TILING(3);
1549                 break;
1550         default:
1551                 break;
1552         }
1553         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1554         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1555         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1556         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1557
1558         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1559         if (tmp > 3) {
1560                 tiling_config |= ROW_TILING(3);
1561                 tiling_config |= SAMPLE_SPLIT(3);
1562         } else {
1563                 tiling_config |= ROW_TILING(tmp);
1564                 tiling_config |= SAMPLE_SPLIT(tmp);
1565         }
1566         tiling_config |= BANK_SWAPS(1);
1567
1568         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1569         tmp = R6XX_MAX_BACKENDS -
1570                 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1571         if (tmp < rdev->config.r600.max_backends) {
1572                 rdev->config.r600.max_backends = tmp;
1573         }
1574
1575         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1576         tmp = R6XX_MAX_PIPES -
1577                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1578         if (tmp < rdev->config.r600.max_pipes) {
1579                 rdev->config.r600.max_pipes = tmp;
1580         }
1581         tmp = R6XX_MAX_SIMDS -
1582                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1583         if (tmp < rdev->config.r600.max_simds) {
1584                 rdev->config.r600.max_simds = tmp;
1585         }
1586
1587         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1588         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1589         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1590                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
1591         tiling_config |= tmp << 16;
1592         rdev->config.r600.backend_map = tmp;
1593
1594         rdev->config.r600.tile_config = tiling_config;
1595         WREG32(GB_TILING_CONFIG, tiling_config);
1596         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1597         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1598
1599         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1600         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1601         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1602
1603         /* Setup some CP states */
1604         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1605         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1606
1607         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1608                              SYNC_WALKER | SYNC_ALIGNER));
1609         /* Setup various GPU states */
1610         if (rdev->family == CHIP_RV670)
1611                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1612
1613         tmp = RREG32(SX_DEBUG_1);
1614         tmp |= SMX_EVENT_RELEASE;
1615         if ((rdev->family > CHIP_R600))
1616                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1617         WREG32(SX_DEBUG_1, tmp);
1618
1619         if (((rdev->family) == CHIP_R600) ||
1620             ((rdev->family) == CHIP_RV630) ||
1621             ((rdev->family) == CHIP_RV610) ||
1622             ((rdev->family) == CHIP_RV620) ||
1623             ((rdev->family) == CHIP_RS780) ||
1624             ((rdev->family) == CHIP_RS880)) {
1625                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1626         } else {
1627                 WREG32(DB_DEBUG, 0);
1628         }
1629         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1630                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1631
1632         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1633         WREG32(VGT_NUM_INSTANCES, 0);
1634
1635         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1636         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1637
1638         tmp = RREG32(SQ_MS_FIFO_SIZES);
1639         if (((rdev->family) == CHIP_RV610) ||
1640             ((rdev->family) == CHIP_RV620) ||
1641             ((rdev->family) == CHIP_RS780) ||
1642             ((rdev->family) == CHIP_RS880)) {
1643                 tmp = (CACHE_FIFO_SIZE(0xa) |
1644                        FETCH_FIFO_HIWATER(0xa) |
1645                        DONE_FIFO_HIWATER(0xe0) |
1646                        ALU_UPDATE_FIFO_HIWATER(0x8));
1647         } else if (((rdev->family) == CHIP_R600) ||
1648                    ((rdev->family) == CHIP_RV630)) {
1649                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1650                 tmp |= DONE_FIFO_HIWATER(0x4);
1651         }
1652         WREG32(SQ_MS_FIFO_SIZES, tmp);
1653
1654         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1655          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1656          */
1657         sq_config = RREG32(SQ_CONFIG);
1658         sq_config &= ~(PS_PRIO(3) |
1659                        VS_PRIO(3) |
1660                        GS_PRIO(3) |
1661                        ES_PRIO(3));
1662         sq_config |= (DX9_CONSTS |
1663                       VC_ENABLE |
1664                       PS_PRIO(0) |
1665                       VS_PRIO(1) |
1666                       GS_PRIO(2) |
1667                       ES_PRIO(3));
1668
1669         if ((rdev->family) == CHIP_R600) {
1670                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1671                                           NUM_VS_GPRS(124) |
1672                                           NUM_CLAUSE_TEMP_GPRS(4));
1673                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1674                                           NUM_ES_GPRS(0));
1675                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1676                                            NUM_VS_THREADS(48) |
1677                                            NUM_GS_THREADS(4) |
1678                                            NUM_ES_THREADS(4));
1679                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1680                                             NUM_VS_STACK_ENTRIES(128));
1681                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1682                                             NUM_ES_STACK_ENTRIES(0));
1683         } else if (((rdev->family) == CHIP_RV610) ||
1684                    ((rdev->family) == CHIP_RV620) ||
1685                    ((rdev->family) == CHIP_RS780) ||
1686                    ((rdev->family) == CHIP_RS880)) {
1687                 /* no vertex cache */
1688                 sq_config &= ~VC_ENABLE;
1689
1690                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1691                                           NUM_VS_GPRS(44) |
1692                                           NUM_CLAUSE_TEMP_GPRS(2));
1693                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1694                                           NUM_ES_GPRS(17));
1695                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1696                                            NUM_VS_THREADS(78) |
1697                                            NUM_GS_THREADS(4) |
1698                                            NUM_ES_THREADS(31));
1699                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1700                                             NUM_VS_STACK_ENTRIES(40));
1701                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1702                                             NUM_ES_STACK_ENTRIES(16));
1703         } else if (((rdev->family) == CHIP_RV630) ||
1704                    ((rdev->family) == CHIP_RV635)) {
1705                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1706                                           NUM_VS_GPRS(44) |
1707                                           NUM_CLAUSE_TEMP_GPRS(2));
1708                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1709                                           NUM_ES_GPRS(18));
1710                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1711                                            NUM_VS_THREADS(78) |
1712                                            NUM_GS_THREADS(4) |
1713                                            NUM_ES_THREADS(31));
1714                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1715                                             NUM_VS_STACK_ENTRIES(40));
1716                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1717                                             NUM_ES_STACK_ENTRIES(16));
1718         } else if ((rdev->family) == CHIP_RV670) {
1719                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1720                                           NUM_VS_GPRS(44) |
1721                                           NUM_CLAUSE_TEMP_GPRS(2));
1722                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1723                                           NUM_ES_GPRS(17));
1724                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1725                                            NUM_VS_THREADS(78) |
1726                                            NUM_GS_THREADS(4) |
1727                                            NUM_ES_THREADS(31));
1728                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1729                                             NUM_VS_STACK_ENTRIES(64));
1730                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1731                                             NUM_ES_STACK_ENTRIES(64));
1732         }
1733
1734         WREG32(SQ_CONFIG, sq_config);
1735         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1736         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1737         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1738         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1739         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1740
1741         if (((rdev->family) == CHIP_RV610) ||
1742             ((rdev->family) == CHIP_RV620) ||
1743             ((rdev->family) == CHIP_RS780) ||
1744             ((rdev->family) == CHIP_RS880)) {
1745                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1746         } else {
1747                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1748         }
1749
1750         /* More default values. 2D/3D driver should adjust as needed */
1751         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1752                                          S1_X(0x4) | S1_Y(0xc)));
1753         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1754                                          S1_X(0x2) | S1_Y(0x2) |
1755                                          S2_X(0xa) | S2_Y(0x6) |
1756                                          S3_X(0x6) | S3_Y(0xa)));
1757         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1758                                              S1_X(0x4) | S1_Y(0xc) |
1759                                              S2_X(0x1) | S2_Y(0x6) |
1760                                              S3_X(0xa) | S3_Y(0xe)));
1761         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1762                                              S5_X(0x0) | S5_Y(0x0) |
1763                                              S6_X(0xb) | S6_Y(0x4) |
1764                                              S7_X(0x7) | S7_Y(0x8)));
1765
1766         WREG32(VGT_STRMOUT_EN, 0);
1767         tmp = rdev->config.r600.max_pipes * 16;
1768         switch (rdev->family) {
1769         case CHIP_RV610:
1770         case CHIP_RV620:
1771         case CHIP_RS780:
1772         case CHIP_RS880:
1773                 tmp += 32;
1774                 break;
1775         case CHIP_RV670:
1776                 tmp += 128;
1777                 break;
1778         default:
1779                 break;
1780         }
1781         if (tmp > 256) {
1782                 tmp = 256;
1783         }
1784         WREG32(VGT_ES_PER_GS, 128);
1785         WREG32(VGT_GS_PER_ES, tmp);
1786         WREG32(VGT_GS_PER_VS, 2);
1787         WREG32(VGT_GS_VERTEX_REUSE, 16);
1788
1789         /* more default values. 2D/3D driver should adjust as needed */
1790         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1791         WREG32(VGT_STRMOUT_EN, 0);
1792         WREG32(SX_MISC, 0);
1793         WREG32(PA_SC_MODE_CNTL, 0);
1794         WREG32(PA_SC_AA_CONFIG, 0);
1795         WREG32(PA_SC_LINE_STIPPLE, 0);
1796         WREG32(SPI_INPUT_Z, 0);
1797         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1798         WREG32(CB_COLOR7_FRAG, 0);
1799
1800         /* Clear render buffer base addresses */
1801         WREG32(CB_COLOR0_BASE, 0);
1802         WREG32(CB_COLOR1_BASE, 0);
1803         WREG32(CB_COLOR2_BASE, 0);
1804         WREG32(CB_COLOR3_BASE, 0);
1805         WREG32(CB_COLOR4_BASE, 0);
1806         WREG32(CB_COLOR5_BASE, 0);
1807         WREG32(CB_COLOR6_BASE, 0);
1808         WREG32(CB_COLOR7_BASE, 0);
1809         WREG32(CB_COLOR7_FRAG, 0);
1810
1811         switch (rdev->family) {
1812         case CHIP_RV610:
1813         case CHIP_RV620:
1814         case CHIP_RS780:
1815         case CHIP_RS880:
1816                 tmp = TC_L2_SIZE(8);
1817                 break;
1818         case CHIP_RV630:
1819         case CHIP_RV635:
1820                 tmp = TC_L2_SIZE(4);
1821                 break;
1822         case CHIP_R600:
1823                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1824                 break;
1825         default:
1826                 tmp = TC_L2_SIZE(0);
1827                 break;
1828         }
1829         WREG32(TC_CNTL, tmp);
1830
1831         tmp = RREG32(HDP_HOST_PATH_CNTL);
1832         WREG32(HDP_HOST_PATH_CNTL, tmp);
1833
1834         tmp = RREG32(ARB_POP);
1835         tmp |= ENABLE_TC128;
1836         WREG32(ARB_POP, tmp);
1837
1838         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1839         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1840                                NUM_CLIP_SEQ(3)));
1841         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1842 }
1843
1844
1845 /*
1846  * Indirect registers accessor
1847  */
1848 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1849 {
1850         u32 r;
1851
1852         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1853         (void)RREG32(PCIE_PORT_INDEX);
1854         r = RREG32(PCIE_PORT_DATA);
1855         return r;
1856 }
1857
1858 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1859 {
1860         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1861         (void)RREG32(PCIE_PORT_INDEX);
1862         WREG32(PCIE_PORT_DATA, (v));
1863         (void)RREG32(PCIE_PORT_DATA);
1864 }
1865
1866 /*
1867  * CP & Ring
1868  */
1869 void r600_cp_stop(struct radeon_device *rdev)
1870 {
1871         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1872         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1873         WREG32(SCRATCH_UMSK, 0);
1874 }
1875
1876 int r600_init_microcode(struct radeon_device *rdev)
1877 {
1878         struct platform_device *pdev;
1879         const char *chip_name;
1880         const char *rlc_chip_name;
1881         size_t pfp_req_size, me_req_size, rlc_req_size;
1882         char fw_name[30];
1883         int err;
1884
1885         DRM_DEBUG("\n");
1886
1887         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1888         err = IS_ERR(pdev);
1889         if (err) {
1890                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1891                 return -EINVAL;
1892         }
1893
1894         switch (rdev->family) {
1895         case CHIP_R600:
1896                 chip_name = "R600";
1897                 rlc_chip_name = "R600";
1898                 break;
1899         case CHIP_RV610:
1900                 chip_name = "RV610";
1901                 rlc_chip_name = "R600";
1902                 break;
1903         case CHIP_RV630:
1904                 chip_name = "RV630";
1905                 rlc_chip_name = "R600";
1906                 break;
1907         case CHIP_RV620:
1908                 chip_name = "RV620";
1909                 rlc_chip_name = "R600";
1910                 break;
1911         case CHIP_RV635:
1912                 chip_name = "RV635";
1913                 rlc_chip_name = "R600";
1914                 break;
1915         case CHIP_RV670:
1916                 chip_name = "RV670";
1917                 rlc_chip_name = "R600";
1918                 break;
1919         case CHIP_RS780:
1920         case CHIP_RS880:
1921                 chip_name = "RS780";
1922                 rlc_chip_name = "R600";
1923                 break;
1924         case CHIP_RV770:
1925                 chip_name = "RV770";
1926                 rlc_chip_name = "R700";
1927                 break;
1928         case CHIP_RV730:
1929         case CHIP_RV740:
1930                 chip_name = "RV730";
1931                 rlc_chip_name = "R700";
1932                 break;
1933         case CHIP_RV710:
1934                 chip_name = "RV710";
1935                 rlc_chip_name = "R700";
1936                 break;
1937         case CHIP_CEDAR:
1938                 chip_name = "CEDAR";
1939                 rlc_chip_name = "CEDAR";
1940                 break;
1941         case CHIP_REDWOOD:
1942                 chip_name = "REDWOOD";
1943                 rlc_chip_name = "REDWOOD";
1944                 break;
1945         case CHIP_JUNIPER:
1946                 chip_name = "JUNIPER";
1947                 rlc_chip_name = "JUNIPER";
1948                 break;
1949         case CHIP_CYPRESS:
1950         case CHIP_HEMLOCK:
1951                 chip_name = "CYPRESS";
1952                 rlc_chip_name = "CYPRESS";
1953                 break;
1954         case CHIP_PALM:
1955                 chip_name = "PALM";
1956                 rlc_chip_name = "SUMO";
1957                 break;
1958         case CHIP_SUMO:
1959                 chip_name = "SUMO";
1960                 rlc_chip_name = "SUMO";
1961                 break;
1962         case CHIP_SUMO2:
1963                 chip_name = "SUMO2";
1964                 rlc_chip_name = "SUMO";
1965                 break;
1966         default: BUG();
1967         }
1968
1969         if (rdev->family >= CHIP_CEDAR) {
1970                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1971                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1972                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1973         } else if (rdev->family >= CHIP_RV770) {
1974                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1975                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1976                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1977         } else {
1978                 pfp_req_size = PFP_UCODE_SIZE * 4;
1979                 me_req_size = PM4_UCODE_SIZE * 12;
1980                 rlc_req_size = RLC_UCODE_SIZE * 4;
1981         }
1982
1983         DRM_INFO("Loading %s Microcode\n", chip_name);
1984
1985         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1986         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1987         if (err)
1988                 goto out;
1989         if (rdev->pfp_fw->size != pfp_req_size) {
1990                 printk(KERN_ERR
1991                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1992                        rdev->pfp_fw->size, fw_name);
1993                 err = -EINVAL;
1994                 goto out;
1995         }
1996
1997         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1998         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1999         if (err)
2000                 goto out;
2001         if (rdev->me_fw->size != me_req_size) {
2002                 printk(KERN_ERR
2003                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2004                        rdev->me_fw->size, fw_name);
2005                 err = -EINVAL;
2006         }
2007
2008         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2009         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2010         if (err)
2011                 goto out;
2012         if (rdev->rlc_fw->size != rlc_req_size) {
2013                 printk(KERN_ERR
2014                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2015                        rdev->rlc_fw->size, fw_name);
2016                 err = -EINVAL;
2017         }
2018
2019 out:
2020         platform_device_unregister(pdev);
2021
2022         if (err) {
2023                 if (err != -EINVAL)
2024                         printk(KERN_ERR
2025                                "r600_cp: Failed to load firmware \"%s\"\n",
2026                                fw_name);
2027                 release_firmware(rdev->pfp_fw);
2028                 rdev->pfp_fw = NULL;
2029                 release_firmware(rdev->me_fw);
2030                 rdev->me_fw = NULL;
2031                 release_firmware(rdev->rlc_fw);
2032                 rdev->rlc_fw = NULL;
2033         }
2034         return err;
2035 }
2036
2037 static int r600_cp_load_microcode(struct radeon_device *rdev)
2038 {
2039         const __be32 *fw_data;
2040         int i;
2041
2042         if (!rdev->me_fw || !rdev->pfp_fw)
2043                 return -EINVAL;
2044
2045         r600_cp_stop(rdev);
2046
2047         WREG32(CP_RB_CNTL,
2048 #ifdef __BIG_ENDIAN
2049                BUF_SWAP_32BIT |
2050 #endif
2051                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2052
2053         /* Reset cp */
2054         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2055         RREG32(GRBM_SOFT_RESET);
2056         mdelay(15);
2057         WREG32(GRBM_SOFT_RESET, 0);
2058
2059         WREG32(CP_ME_RAM_WADDR, 0);
2060
2061         fw_data = (const __be32 *)rdev->me_fw->data;
2062         WREG32(CP_ME_RAM_WADDR, 0);
2063         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2064                 WREG32(CP_ME_RAM_DATA,
2065                        be32_to_cpup(fw_data++));
2066
2067         fw_data = (const __be32 *)rdev->pfp_fw->data;
2068         WREG32(CP_PFP_UCODE_ADDR, 0);
2069         for (i = 0; i < PFP_UCODE_SIZE; i++)
2070                 WREG32(CP_PFP_UCODE_DATA,
2071                        be32_to_cpup(fw_data++));
2072
2073         WREG32(CP_PFP_UCODE_ADDR, 0);
2074         WREG32(CP_ME_RAM_WADDR, 0);
2075         WREG32(CP_ME_RAM_RADDR, 0);
2076         return 0;
2077 }
2078
2079 int r600_cp_start(struct radeon_device *rdev)
2080 {
2081         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2082         int r;
2083         uint32_t cp_me;
2084
2085         r = radeon_ring_lock(rdev, ring, 7);
2086         if (r) {
2087                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2088                 return r;
2089         }
2090         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2091         radeon_ring_write(ring, 0x1);
2092         if (rdev->family >= CHIP_RV770) {
2093                 radeon_ring_write(ring, 0x0);
2094                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2095         } else {
2096                 radeon_ring_write(ring, 0x3);
2097                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2098         }
2099         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2100         radeon_ring_write(ring, 0);
2101         radeon_ring_write(ring, 0);
2102         radeon_ring_unlock_commit(rdev, ring);
2103
2104         cp_me = 0xff;
2105         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2106         return 0;
2107 }
2108
2109 int r600_cp_resume(struct radeon_device *rdev)
2110 {
2111         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2112         u32 tmp;
2113         u32 rb_bufsz;
2114         int r;
2115
2116         /* Reset cp */
2117         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2118         RREG32(GRBM_SOFT_RESET);
2119         mdelay(15);
2120         WREG32(GRBM_SOFT_RESET, 0);
2121
2122         /* Set ring buffer size */
2123         rb_bufsz = drm_order(ring->ring_size / 8);
2124         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2125 #ifdef __BIG_ENDIAN
2126         tmp |= BUF_SWAP_32BIT;
2127 #endif
2128         WREG32(CP_RB_CNTL, tmp);
2129         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2130
2131         /* Set the write pointer delay */
2132         WREG32(CP_RB_WPTR_DELAY, 0);
2133
2134         /* Initialize the ring buffer's read and write pointers */
2135         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2136         WREG32(CP_RB_RPTR_WR, 0);
2137         ring->wptr = 0;
2138         WREG32(CP_RB_WPTR, ring->wptr);
2139
2140         /* set the wb address whether it's enabled or not */
2141         WREG32(CP_RB_RPTR_ADDR,
2142                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2143         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2144         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2145
2146         if (rdev->wb.enabled)
2147                 WREG32(SCRATCH_UMSK, 0xff);
2148         else {
2149                 tmp |= RB_NO_UPDATE;
2150                 WREG32(SCRATCH_UMSK, 0);
2151         }
2152
2153         mdelay(1);
2154         WREG32(CP_RB_CNTL, tmp);
2155
2156         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2157         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2158
2159         ring->rptr = RREG32(CP_RB_RPTR);
2160
2161         r600_cp_start(rdev);
2162         ring->ready = true;
2163         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2164         if (r) {
2165                 ring->ready = false;
2166                 return r;
2167         }
2168         return 0;
2169 }
2170
2171 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2172 {
2173         u32 rb_bufsz;
2174
2175         /* Align ring size */
2176         rb_bufsz = drm_order(ring_size / 8);
2177         ring_size = (1 << (rb_bufsz + 1)) * 4;
2178         ring->ring_size = ring_size;
2179         ring->align_mask = 16 - 1;
2180 }
2181
2182 void r600_cp_fini(struct radeon_device *rdev)
2183 {
2184         r600_cp_stop(rdev);
2185         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2186 }
2187
2188
2189 /*
2190  * GPU scratch registers helpers function.
2191  */
2192 void r600_scratch_init(struct radeon_device *rdev)
2193 {
2194         int i;
2195
2196         rdev->scratch.num_reg = 7;
2197         rdev->scratch.reg_base = SCRATCH_REG0;
2198         for (i = 0; i < rdev->scratch.num_reg; i++) {
2199                 rdev->scratch.free[i] = true;
2200                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2201         }
2202 }
2203
2204 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2205 {
2206         uint32_t scratch;
2207         uint32_t tmp = 0;
2208         unsigned i, ridx = radeon_ring_index(rdev, ring);
2209         int r;
2210
2211         r = radeon_scratch_get(rdev, &scratch);
2212         if (r) {
2213                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2214                 return r;
2215         }
2216         WREG32(scratch, 0xCAFEDEAD);
2217         r = radeon_ring_lock(rdev, ring, 3);
2218         if (r) {
2219                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ridx, r);
2220                 radeon_scratch_free(rdev, scratch);
2221                 return r;
2222         }
2223         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2224         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2225         radeon_ring_write(ring, 0xDEADBEEF);
2226         radeon_ring_unlock_commit(rdev, ring);
2227         for (i = 0; i < rdev->usec_timeout; i++) {
2228                 tmp = RREG32(scratch);
2229                 if (tmp == 0xDEADBEEF)
2230                         break;
2231                 DRM_UDELAY(1);
2232         }
2233         if (i < rdev->usec_timeout) {
2234                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ridx, i);
2235         } else {
2236                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2237                           ridx, scratch, tmp);
2238                 r = -EINVAL;
2239         }
2240         radeon_scratch_free(rdev, scratch);
2241         return r;
2242 }
2243
2244 void r600_fence_ring_emit(struct radeon_device *rdev,
2245                           struct radeon_fence *fence)
2246 {
2247         struct radeon_ring *ring = &rdev->ring[fence->ring];
2248
2249         if (rdev->wb.use_event) {
2250                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2251                 /* flush read cache over gart */
2252                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2253                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2254                                         PACKET3_VC_ACTION_ENA |
2255                                         PACKET3_SH_ACTION_ENA);
2256                 radeon_ring_write(ring, 0xFFFFFFFF);
2257                 radeon_ring_write(ring, 0);
2258                 radeon_ring_write(ring, 10); /* poll interval */
2259                 /* EVENT_WRITE_EOP - flush caches, send int */
2260                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2261                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2262                 radeon_ring_write(ring, addr & 0xffffffff);
2263                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2264                 radeon_ring_write(ring, fence->seq);
2265                 radeon_ring_write(ring, 0);
2266         } else {
2267                 /* flush read cache over gart */
2268                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2269                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2270                                         PACKET3_VC_ACTION_ENA |
2271                                         PACKET3_SH_ACTION_ENA);
2272                 radeon_ring_write(ring, 0xFFFFFFFF);
2273                 radeon_ring_write(ring, 0);
2274                 radeon_ring_write(ring, 10); /* poll interval */
2275                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2276                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2277                 /* wait for 3D idle clean */
2278                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2279                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2280                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2281                 /* Emit fence sequence & fire IRQ */
2282                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2283                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2284                 radeon_ring_write(ring, fence->seq);
2285                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2286                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2287                 radeon_ring_write(ring, RB_INT_STAT);
2288         }
2289 }
2290
2291 void r600_semaphore_ring_emit(struct radeon_device *rdev,
2292                               struct radeon_ring *ring,
2293                               struct radeon_semaphore *semaphore,
2294                               bool emit_wait)
2295 {
2296         uint64_t addr = semaphore->gpu_addr;
2297         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2298
2299         if (rdev->family < CHIP_CAYMAN)
2300                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2301
2302         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2303         radeon_ring_write(ring, addr & 0xffffffff);
2304         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2305 }
2306
2307 int r600_copy_blit(struct radeon_device *rdev,
2308                    uint64_t src_offset,
2309                    uint64_t dst_offset,
2310                    unsigned num_gpu_pages,
2311                    struct radeon_fence *fence)
2312 {
2313         struct radeon_sa_bo *vb = NULL;
2314         int r;
2315
2316         r = r600_blit_prepare_copy(rdev, num_gpu_pages, &vb);
2317         if (r) {
2318                 return r;
2319         }
2320         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
2321         r600_blit_done_copy(rdev, fence, vb);
2322         return 0;
2323 }
2324
2325 void r600_blit_suspend(struct radeon_device *rdev)
2326 {
2327         int r;
2328
2329         /* unpin shaders bo */
2330         if (rdev->r600_blit.shader_obj) {
2331                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2332                 if (!r) {
2333                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2334                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2335                 }
2336         }
2337 }
2338
2339 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2340                          uint32_t tiling_flags, uint32_t pitch,
2341                          uint32_t offset, uint32_t obj_size)
2342 {
2343         /* FIXME: implement */
2344         return 0;
2345 }
2346
2347 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2348 {
2349         /* FIXME: implement */
2350 }
2351
2352 int r600_startup(struct radeon_device *rdev)
2353 {
2354         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2355         int r;
2356
2357         /* enable pcie gen2 link */
2358         r600_pcie_gen2_enable(rdev);
2359
2360         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2361                 r = r600_init_microcode(rdev);
2362                 if (r) {
2363                         DRM_ERROR("Failed to load firmware!\n");
2364                         return r;
2365                 }
2366         }
2367
2368         r = r600_vram_scratch_init(rdev);
2369         if (r)
2370                 return r;
2371
2372         r600_mc_program(rdev);
2373         if (rdev->flags & RADEON_IS_AGP) {
2374                 r600_agp_enable(rdev);
2375         } else {
2376                 r = r600_pcie_gart_enable(rdev);
2377                 if (r)
2378                         return r;
2379         }
2380         r600_gpu_init(rdev);
2381         r = r600_blit_init(rdev);
2382         if (r) {
2383                 r600_blit_fini(rdev);
2384                 rdev->asic->copy.copy = NULL;
2385                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2386         }
2387
2388         /* allocate wb buffer */
2389         r = radeon_wb_init(rdev);
2390         if (r)
2391                 return r;
2392
2393         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2394         if (r) {
2395                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2396                 return r;
2397         }
2398
2399         /* Enable IRQ */
2400         r = r600_irq_init(rdev);
2401         if (r) {
2402                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2403                 radeon_irq_kms_fini(rdev);
2404                 return r;
2405         }
2406         r600_irq_set(rdev);
2407
2408         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2409                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2410                              0, 0xfffff, RADEON_CP_PACKET2);
2411
2412         if (r)
2413                 return r;
2414         r = r600_cp_load_microcode(rdev);
2415         if (r)
2416                 return r;
2417         r = r600_cp_resume(rdev);
2418         if (r)
2419                 return r;
2420
2421         r = radeon_ib_pool_start(rdev);
2422         if (r)
2423                 return r;
2424
2425         r = radeon_ib_ring_tests(rdev);
2426         if (r)
2427                 return r;
2428
2429         r = r600_audio_init(rdev);
2430         if (r) {
2431                 DRM_ERROR("radeon: audio init failed\n");
2432                 return r;
2433         }
2434
2435         return 0;
2436 }
2437
2438 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2439 {
2440         uint32_t temp;
2441
2442         temp = RREG32(CONFIG_CNTL);
2443         if (state == false) {
2444                 temp &= ~(1<<0);
2445                 temp |= (1<<1);
2446         } else {
2447                 temp &= ~(1<<1);
2448         }
2449         WREG32(CONFIG_CNTL, temp);
2450 }
2451
2452 int r600_resume(struct radeon_device *rdev)
2453 {
2454         int r;
2455
2456         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2457          * posting will perform necessary task to bring back GPU into good
2458          * shape.
2459          */
2460         /* post card */
2461         atom_asic_init(rdev->mode_info.atom_context);
2462
2463         rdev->accel_working = true;
2464         r = r600_startup(rdev);
2465         if (r) {
2466                 DRM_ERROR("r600 startup failed on resume\n");
2467                 rdev->accel_working = false;
2468                 return r;
2469         }
2470
2471         return r;
2472 }
2473
2474 int r600_suspend(struct radeon_device *rdev)
2475 {
2476         r600_audio_fini(rdev);
2477         radeon_ib_pool_suspend(rdev);
2478         r600_blit_suspend(rdev);
2479         /* FIXME: we should wait for ring to be empty */
2480         r600_cp_stop(rdev);
2481         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2482         r600_irq_suspend(rdev);
2483         radeon_wb_disable(rdev);
2484         r600_pcie_gart_disable(rdev);
2485
2486         return 0;
2487 }
2488
2489 /* Plan is to move initialization in that function and use
2490  * helper function so that radeon_device_init pretty much
2491  * do nothing more than calling asic specific function. This
2492  * should also allow to remove a bunch of callback function
2493  * like vram_info.
2494  */
2495 int r600_init(struct radeon_device *rdev)
2496 {
2497         int r;
2498
2499         if (r600_debugfs_mc_info_init(rdev)) {
2500                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2501         }
2502         /* Read BIOS */
2503         if (!radeon_get_bios(rdev)) {
2504                 if (ASIC_IS_AVIVO(rdev))
2505                         return -EINVAL;
2506         }
2507         /* Must be an ATOMBIOS */
2508         if (!rdev->is_atom_bios) {
2509                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2510                 return -EINVAL;
2511         }
2512         r = radeon_atombios_init(rdev);
2513         if (r)
2514                 return r;
2515         /* Post card if necessary */
2516         if (!radeon_card_posted(rdev)) {
2517                 if (!rdev->bios) {
2518                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2519                         return -EINVAL;
2520                 }
2521                 DRM_INFO("GPU not posted. posting now...\n");
2522                 atom_asic_init(rdev->mode_info.atom_context);
2523         }
2524         /* Initialize scratch registers */
2525         r600_scratch_init(rdev);
2526         /* Initialize surface registers */
2527         radeon_surface_init(rdev);
2528         /* Initialize clocks */
2529         radeon_get_clock_info(rdev->ddev);
2530         /* Fence driver */
2531         r = radeon_fence_driver_init(rdev);
2532         if (r)
2533                 return r;
2534         if (rdev->flags & RADEON_IS_AGP) {
2535                 r = radeon_agp_init(rdev);
2536                 if (r)
2537                         radeon_agp_disable(rdev);
2538         }
2539         r = r600_mc_init(rdev);
2540         if (r)
2541                 return r;
2542         /* Memory manager */
2543         r = radeon_bo_init(rdev);
2544         if (r)
2545                 return r;
2546
2547         r = radeon_irq_kms_init(rdev);
2548         if (r)
2549                 return r;
2550
2551         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2552         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2553
2554         rdev->ih.ring_obj = NULL;
2555         r600_ih_ring_init(rdev, 64 * 1024);
2556
2557         r = r600_pcie_gart_init(rdev);
2558         if (r)
2559                 return r;
2560
2561         r = radeon_ib_pool_init(rdev);
2562         rdev->accel_working = true;
2563         if (r) {
2564                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2565                 rdev->accel_working = false;
2566         }
2567
2568         r = r600_startup(rdev);
2569         if (r) {
2570                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2571                 r600_cp_fini(rdev);
2572                 r600_irq_fini(rdev);
2573                 radeon_wb_fini(rdev);
2574                 r100_ib_fini(rdev);
2575                 radeon_irq_kms_fini(rdev);
2576                 r600_pcie_gart_fini(rdev);
2577                 rdev->accel_working = false;
2578         }
2579
2580         return 0;
2581 }
2582
2583 void r600_fini(struct radeon_device *rdev)
2584 {
2585         r600_audio_fini(rdev);
2586         r600_blit_fini(rdev);
2587         r600_cp_fini(rdev);
2588         r600_irq_fini(rdev);
2589         radeon_wb_fini(rdev);
2590         r100_ib_fini(rdev);
2591         radeon_irq_kms_fini(rdev);
2592         r600_pcie_gart_fini(rdev);
2593         r600_vram_scratch_fini(rdev);
2594         radeon_agp_fini(rdev);
2595         radeon_gem_fini(rdev);
2596         radeon_fence_driver_fini(rdev);
2597         radeon_bo_fini(rdev);
2598         radeon_atombios_fini(rdev);
2599         kfree(rdev->bios);
2600         rdev->bios = NULL;
2601 }
2602
2603
2604 /*
2605  * CS stuff
2606  */
2607 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2608 {
2609         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
2610
2611         /* FIXME: implement */
2612         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2613         radeon_ring_write(ring,
2614 #ifdef __BIG_ENDIAN
2615                           (2 << 0) |
2616 #endif
2617                           (ib->gpu_addr & 0xFFFFFFFC));
2618         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
2619         radeon_ring_write(ring, ib->length_dw);
2620 }
2621
2622 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
2623 {
2624         struct radeon_ib ib;
2625         uint32_t scratch;
2626         uint32_t tmp = 0;
2627         unsigned i;
2628         int r;
2629         int ring_index = radeon_ring_index(rdev, ring);
2630
2631         r = radeon_scratch_get(rdev, &scratch);
2632         if (r) {
2633                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2634                 return r;
2635         }
2636         WREG32(scratch, 0xCAFEDEAD);
2637         r = radeon_ib_get(rdev, ring_index, &ib, 256);
2638         if (r) {
2639                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2640                 return r;
2641         }
2642         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2643         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2644         ib.ptr[2] = 0xDEADBEEF;
2645         ib.length_dw = 3;
2646         r = radeon_ib_schedule(rdev, &ib);
2647         if (r) {
2648                 radeon_scratch_free(rdev, scratch);
2649                 radeon_ib_free(rdev, &ib);
2650                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2651                 return r;
2652         }
2653         r = radeon_fence_wait(ib.fence, false);
2654         if (r) {
2655                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2656                 return r;
2657         }
2658         for (i = 0; i < rdev->usec_timeout; i++) {
2659                 tmp = RREG32(scratch);
2660                 if (tmp == 0xDEADBEEF)
2661                         break;
2662                 DRM_UDELAY(1);
2663         }
2664         if (i < rdev->usec_timeout) {
2665                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
2666         } else {
2667                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2668                           scratch, tmp);
2669                 r = -EINVAL;
2670         }
2671         radeon_scratch_free(rdev, scratch);
2672         radeon_ib_free(rdev, &ib);
2673         return r;
2674 }
2675
2676 /*
2677  * Interrupts
2678  *
2679  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2680  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2681  * writing to the ring and the GPU consuming, the GPU writes to the ring
2682  * and host consumes.  As the host irq handler processes interrupts, it
2683  * increments the rptr.  When the rptr catches up with the wptr, all the
2684  * current interrupts have been processed.
2685  */
2686
2687 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2688 {
2689         u32 rb_bufsz;
2690
2691         /* Align ring size */
2692         rb_bufsz = drm_order(ring_size / 4);
2693         ring_size = (1 << rb_bufsz) * 4;
2694         rdev->ih.ring_size = ring_size;
2695         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2696         rdev->ih.rptr = 0;
2697 }
2698
2699 int r600_ih_ring_alloc(struct radeon_device *rdev)
2700 {
2701         int r;
2702
2703         /* Allocate ring buffer */
2704         if (rdev->ih.ring_obj == NULL) {
2705                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
2706                                      PAGE_SIZE, true,
2707                                      RADEON_GEM_DOMAIN_GTT,
2708                                      NULL, &rdev->ih.ring_obj);
2709                 if (r) {
2710                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2711                         return r;
2712                 }
2713                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2714                 if (unlikely(r != 0))
2715                         return r;
2716                 r = radeon_bo_pin(rdev->ih.ring_obj,
2717                                   RADEON_GEM_DOMAIN_GTT,
2718                                   &rdev->ih.gpu_addr);
2719                 if (r) {
2720                         radeon_bo_unreserve(rdev->ih.ring_obj);
2721                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2722                         return r;
2723                 }
2724                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2725                                    (void **)&rdev->ih.ring);
2726                 radeon_bo_unreserve(rdev->ih.ring_obj);
2727                 if (r) {
2728                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2729                         return r;
2730                 }
2731         }
2732         return 0;
2733 }
2734
2735 void r600_ih_ring_fini(struct radeon_device *rdev)
2736 {
2737         int r;
2738         if (rdev->ih.ring_obj) {
2739                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2740                 if (likely(r == 0)) {
2741                         radeon_bo_kunmap(rdev->ih.ring_obj);
2742                         radeon_bo_unpin(rdev->ih.ring_obj);
2743                         radeon_bo_unreserve(rdev->ih.ring_obj);
2744                 }
2745                 radeon_bo_unref(&rdev->ih.ring_obj);
2746                 rdev->ih.ring = NULL;
2747                 rdev->ih.ring_obj = NULL;
2748         }
2749 }
2750
2751 void r600_rlc_stop(struct radeon_device *rdev)
2752 {
2753
2754         if ((rdev->family >= CHIP_RV770) &&
2755             (rdev->family <= CHIP_RV740)) {
2756                 /* r7xx asics need to soft reset RLC before halting */
2757                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2758                 RREG32(SRBM_SOFT_RESET);
2759                 mdelay(15);
2760                 WREG32(SRBM_SOFT_RESET, 0);
2761                 RREG32(SRBM_SOFT_RESET);
2762         }
2763
2764         WREG32(RLC_CNTL, 0);
2765 }
2766
2767 static void r600_rlc_start(struct radeon_device *rdev)
2768 {
2769         WREG32(RLC_CNTL, RLC_ENABLE);
2770 }
2771
2772 static int r600_rlc_init(struct radeon_device *rdev)
2773 {
2774         u32 i;
2775         const __be32 *fw_data;
2776
2777         if (!rdev->rlc_fw)
2778                 return -EINVAL;
2779
2780         r600_rlc_stop(rdev);
2781
2782         WREG32(RLC_HB_CNTL, 0);
2783
2784         if (rdev->family == CHIP_ARUBA) {
2785                 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
2786                 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
2787         }
2788         if (rdev->family <= CHIP_CAYMAN) {
2789                 WREG32(RLC_HB_BASE, 0);
2790                 WREG32(RLC_HB_RPTR, 0);
2791                 WREG32(RLC_HB_WPTR, 0);
2792         }
2793         if (rdev->family <= CHIP_CAICOS) {
2794                 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2795                 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2796         }
2797         WREG32(RLC_MC_CNTL, 0);
2798         WREG32(RLC_UCODE_CNTL, 0);
2799
2800         fw_data = (const __be32 *)rdev->rlc_fw->data;
2801         if (rdev->family >= CHIP_ARUBA) {
2802                 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
2803                         WREG32(RLC_UCODE_ADDR, i);
2804                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2805                 }
2806         } else if (rdev->family >= CHIP_CAYMAN) {
2807                 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2808                         WREG32(RLC_UCODE_ADDR, i);
2809                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2810                 }
2811         } else if (rdev->family >= CHIP_CEDAR) {
2812                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2813                         WREG32(RLC_UCODE_ADDR, i);
2814                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2815                 }
2816         } else if (rdev->family >= CHIP_RV770) {
2817                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2818                         WREG32(RLC_UCODE_ADDR, i);
2819                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2820                 }
2821         } else {
2822                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2823                         WREG32(RLC_UCODE_ADDR, i);
2824                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2825                 }
2826         }
2827         WREG32(RLC_UCODE_ADDR, 0);
2828
2829         r600_rlc_start(rdev);
2830
2831         return 0;
2832 }
2833
2834 static void r600_enable_interrupts(struct radeon_device *rdev)
2835 {
2836         u32 ih_cntl = RREG32(IH_CNTL);
2837         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2838
2839         ih_cntl |= ENABLE_INTR;
2840         ih_rb_cntl |= IH_RB_ENABLE;
2841         WREG32(IH_CNTL, ih_cntl);
2842         WREG32(IH_RB_CNTL, ih_rb_cntl);
2843         rdev->ih.enabled = true;
2844 }
2845
2846 void r600_disable_interrupts(struct radeon_device *rdev)
2847 {
2848         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2849         u32 ih_cntl = RREG32(IH_CNTL);
2850
2851         ih_rb_cntl &= ~IH_RB_ENABLE;
2852         ih_cntl &= ~ENABLE_INTR;
2853         WREG32(IH_RB_CNTL, ih_rb_cntl);
2854         WREG32(IH_CNTL, ih_cntl);
2855         /* set rptr, wptr to 0 */
2856         WREG32(IH_RB_RPTR, 0);
2857         WREG32(IH_RB_WPTR, 0);
2858         rdev->ih.enabled = false;
2859         rdev->ih.wptr = 0;
2860         rdev->ih.rptr = 0;
2861 }
2862
2863 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2864 {
2865         u32 tmp;
2866
2867         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2868         WREG32(GRBM_INT_CNTL, 0);
2869         WREG32(DxMODE_INT_MASK, 0);
2870         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2871         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2872         if (ASIC_IS_DCE3(rdev)) {
2873                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2874                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2875                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2876                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2877                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2878                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2879                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2880                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2881                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2882                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2883                 if (ASIC_IS_DCE32(rdev)) {
2884                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2885                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2886                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2887                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2888                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2889                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
2890                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2891                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
2892                 } else {
2893                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2894                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
2895                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2896                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
2897                 }
2898         } else {
2899                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2900                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2901                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2902                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2903                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2904                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2905                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2906                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2907                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2908                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
2909                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2910                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
2911         }
2912 }
2913
2914 int r600_irq_init(struct radeon_device *rdev)
2915 {
2916         int ret = 0;
2917         int rb_bufsz;
2918         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2919
2920         /* allocate ring */
2921         ret = r600_ih_ring_alloc(rdev);
2922         if (ret)
2923                 return ret;
2924
2925         /* disable irqs */
2926         r600_disable_interrupts(rdev);
2927
2928         /* init rlc */
2929         ret = r600_rlc_init(rdev);
2930         if (ret) {
2931                 r600_ih_ring_fini(rdev);
2932                 return ret;
2933         }
2934
2935         /* setup interrupt control */
2936         /* set dummy read address to ring address */
2937         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2938         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2939         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2940          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2941          */
2942         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2943         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2944         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2945         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2946
2947         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2948         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2949
2950         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2951                       IH_WPTR_OVERFLOW_CLEAR |
2952                       (rb_bufsz << 1));
2953
2954         if (rdev->wb.enabled)
2955                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2956
2957         /* set the writeback address whether it's enabled or not */
2958         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2959         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2960
2961         WREG32(IH_RB_CNTL, ih_rb_cntl);
2962
2963         /* set rptr, wptr to 0 */
2964         WREG32(IH_RB_RPTR, 0);
2965         WREG32(IH_RB_WPTR, 0);
2966
2967         /* Default settings for IH_CNTL (disabled at first) */
2968         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2969         /* RPTR_REARM only works if msi's are enabled */
2970         if (rdev->msi_enabled)
2971                 ih_cntl |= RPTR_REARM;
2972         WREG32(IH_CNTL, ih_cntl);
2973
2974         /* force the active interrupt state to all disabled */
2975         if (rdev->family >= CHIP_CEDAR)
2976                 evergreen_disable_interrupt_state(rdev);
2977         else
2978                 r600_disable_interrupt_state(rdev);
2979
2980         /* at this point everything should be setup correctly to enable master */
2981         pci_set_master(rdev->pdev);
2982
2983         /* enable irqs */
2984         r600_enable_interrupts(rdev);
2985
2986         return ret;
2987 }
2988
2989 void r600_irq_suspend(struct radeon_device *rdev)
2990 {
2991         r600_irq_disable(rdev);
2992         r600_rlc_stop(rdev);
2993 }
2994
2995 void r600_irq_fini(struct radeon_device *rdev)
2996 {
2997         r600_irq_suspend(rdev);
2998         r600_ih_ring_fini(rdev);
2999 }
3000
3001 int r600_irq_set(struct radeon_device *rdev)
3002 {
3003         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3004         u32 mode_int = 0;
3005         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3006         u32 grbm_int_cntl = 0;
3007         u32 hdmi0, hdmi1;
3008         u32 d1grph = 0, d2grph = 0;
3009
3010         if (!rdev->irq.installed) {
3011                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3012                 return -EINVAL;
3013         }
3014         /* don't enable anything if the ih is disabled */
3015         if (!rdev->ih.enabled) {
3016                 r600_disable_interrupts(rdev);
3017                 /* force the active interrupt state to all disabled */
3018                 r600_disable_interrupt_state(rdev);
3019                 return 0;
3020         }
3021
3022         if (ASIC_IS_DCE3(rdev)) {
3023                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3024                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3025                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3026                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3027                 if (ASIC_IS_DCE32(rdev)) {
3028                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3029                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3030                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3031                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3032                 } else {
3033                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3034                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3035                 }
3036         } else {
3037                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3038                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3039                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3040                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3041                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3042         }
3043
3044         if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
3045                 DRM_DEBUG("r600_irq_set: sw int\n");
3046                 cp_int_cntl |= RB_INT_ENABLE;
3047                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3048         }
3049         if (rdev->irq.crtc_vblank_int[0] ||
3050             rdev->irq.pflip[0]) {
3051                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3052                 mode_int |= D1MODE_VBLANK_INT_MASK;
3053         }
3054         if (rdev->irq.crtc_vblank_int[1] ||
3055             rdev->irq.pflip[1]) {
3056                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3057                 mode_int |= D2MODE_VBLANK_INT_MASK;
3058         }
3059         if (rdev->irq.hpd[0]) {
3060                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3061                 hpd1 |= DC_HPDx_INT_EN;
3062         }
3063         if (rdev->irq.hpd[1]) {
3064                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3065                 hpd2 |= DC_HPDx_INT_EN;
3066         }
3067         if (rdev->irq.hpd[2]) {
3068                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3069                 hpd3 |= DC_HPDx_INT_EN;
3070         }
3071         if (rdev->irq.hpd[3]) {
3072                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3073                 hpd4 |= DC_HPDx_INT_EN;
3074         }
3075         if (rdev->irq.hpd[4]) {
3076                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3077                 hpd5 |= DC_HPDx_INT_EN;
3078         }
3079         if (rdev->irq.hpd[5]) {
3080                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3081                 hpd6 |= DC_HPDx_INT_EN;
3082         }
3083         if (rdev->irq.afmt[0]) {
3084                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3085                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3086         }
3087         if (rdev->irq.afmt[1]) {
3088                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3089                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3090         }
3091         if (rdev->irq.gui_idle) {
3092                 DRM_DEBUG("gui idle\n");
3093                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3094         }
3095
3096         WREG32(CP_INT_CNTL, cp_int_cntl);
3097         WREG32(DxMODE_INT_MASK, mode_int);
3098         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3099         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3100         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3101         if (ASIC_IS_DCE3(rdev)) {
3102                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3103                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3104                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3105                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3106                 if (ASIC_IS_DCE32(rdev)) {
3107                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3108                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3109                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3110                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3111                 } else {
3112                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3113                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3114                 }
3115         } else {
3116                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3117                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3118                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3119                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3120                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3121         }
3122
3123         return 0;
3124 }
3125
3126 static void r600_irq_ack(struct radeon_device *rdev)
3127 {
3128         u32 tmp;
3129
3130         if (ASIC_IS_DCE3(rdev)) {
3131                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3132                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3133                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3134                 if (ASIC_IS_DCE32(rdev)) {
3135                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3136                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3137                 } else {
3138                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3139                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3140                 }
3141         } else {
3142                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3143                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3144                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3145                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3146                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3147         }
3148         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3149         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3150
3151         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3152                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3153         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3154                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3155         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3156                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3157         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3158                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3159         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3160                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3161         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3162                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3163         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3164                 if (ASIC_IS_DCE3(rdev)) {
3165                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3166                         tmp |= DC_HPDx_INT_ACK;
3167                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3168                 } else {
3169                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3170                         tmp |= DC_HPDx_INT_ACK;
3171                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3172                 }
3173         }
3174         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3175                 if (ASIC_IS_DCE3(rdev)) {
3176                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3177                         tmp |= DC_HPDx_INT_ACK;
3178                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3179                 } else {
3180                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3181                         tmp |= DC_HPDx_INT_ACK;
3182                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3183                 }
3184         }
3185         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3186                 if (ASIC_IS_DCE3(rdev)) {
3187                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3188                         tmp |= DC_HPDx_INT_ACK;
3189                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3190                 } else {
3191                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3192                         tmp |= DC_HPDx_INT_ACK;
3193                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3194                 }
3195         }
3196         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3197                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3198                 tmp |= DC_HPDx_INT_ACK;
3199                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3200         }
3201         if (ASIC_IS_DCE32(rdev)) {
3202                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3203                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3204                         tmp |= DC_HPDx_INT_ACK;
3205                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3206                 }
3207                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3208                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3209                         tmp |= DC_HPDx_INT_ACK;
3210                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3211                 }
3212                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3213                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3214                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3215                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3216                 }
3217                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3218                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3219                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3220                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3221                 }
3222         } else {
3223                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3224                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3225                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3226                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3227                 }
3228                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3229                         if (ASIC_IS_DCE3(rdev)) {
3230                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3231                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3232                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3233                         } else {
3234                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3235                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3236                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3237                         }
3238                 }
3239         }
3240 }
3241
3242 void r600_irq_disable(struct radeon_device *rdev)
3243 {
3244         r600_disable_interrupts(rdev);
3245         /* Wait and acknowledge irq */
3246         mdelay(1);
3247         r600_irq_ack(rdev);
3248         r600_disable_interrupt_state(rdev);
3249 }
3250
3251 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3252 {
3253         u32 wptr, tmp;
3254
3255         if (rdev->wb.enabled)
3256                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3257         else
3258                 wptr = RREG32(IH_RB_WPTR);
3259
3260         if (wptr & RB_OVERFLOW) {
3261                 /* When a ring buffer overflow happen start parsing interrupt
3262                  * from the last not overwritten vector (wptr + 16). Hopefully
3263                  * this should allow us to catchup.
3264                  */
3265                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3266                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3267                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3268                 tmp = RREG32(IH_RB_CNTL);
3269                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3270                 WREG32(IH_RB_CNTL, tmp);
3271         }
3272         return (wptr & rdev->ih.ptr_mask);
3273 }
3274
3275 /*        r600 IV Ring
3276  * Each IV ring entry is 128 bits:
3277  * [7:0]    - interrupt source id
3278  * [31:8]   - reserved
3279  * [59:32]  - interrupt source data
3280  * [127:60]  - reserved
3281  *
3282  * The basic interrupt vector entries
3283  * are decoded as follows:
3284  * src_id  src_data  description
3285  *      1         0  D1 Vblank
3286  *      1         1  D1 Vline
3287  *      5         0  D2 Vblank
3288  *      5         1  D2 Vline
3289  *     19         0  FP Hot plug detection A
3290  *     19         1  FP Hot plug detection B
3291  *     19         2  DAC A auto-detection
3292  *     19         3  DAC B auto-detection
3293  *     21         4  HDMI block A
3294  *     21         5  HDMI block B
3295  *    176         -  CP_INT RB
3296  *    177         -  CP_INT IB1
3297  *    178         -  CP_INT IB2
3298  *    181         -  EOP Interrupt
3299  *    233         -  GUI Idle
3300  *
3301  * Note, these are based on r600 and may need to be
3302  * adjusted or added to on newer asics
3303  */
3304
3305 int r600_irq_process(struct radeon_device *rdev)
3306 {
3307         u32 wptr;
3308         u32 rptr;
3309         u32 src_id, src_data;
3310         u32 ring_index;
3311         unsigned long flags;
3312         bool queue_hotplug = false;
3313         bool queue_hdmi = false;
3314
3315         if (!rdev->ih.enabled || rdev->shutdown)
3316                 return IRQ_NONE;
3317
3318         /* No MSIs, need a dummy read to flush PCI DMAs */
3319         if (!rdev->msi_enabled)
3320                 RREG32(IH_RB_WPTR);
3321
3322         wptr = r600_get_ih_wptr(rdev);
3323         rptr = rdev->ih.rptr;
3324         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3325
3326         spin_lock_irqsave(&rdev->ih.lock, flags);
3327
3328         if (rptr == wptr) {
3329                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3330                 return IRQ_NONE;
3331         }
3332
3333 restart_ih:
3334         /* Order reading of wptr vs. reading of IH ring data */
3335         rmb();
3336
3337         /* display interrupts */
3338         r600_irq_ack(rdev);
3339
3340         rdev->ih.wptr = wptr;
3341         while (rptr != wptr) {
3342                 /* wptr/rptr are in bytes! */
3343                 ring_index = rptr / 4;
3344                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3345                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3346
3347                 switch (src_id) {
3348                 case 1: /* D1 vblank/vline */
3349                         switch (src_data) {
3350                         case 0: /* D1 vblank */
3351                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3352                                         if (rdev->irq.crtc_vblank_int[0]) {
3353                                                 drm_handle_vblank(rdev->ddev, 0);
3354                                                 rdev->pm.vblank_sync = true;
3355                                                 wake_up(&rdev->irq.vblank_queue);
3356                                         }
3357                                         if (rdev->irq.pflip[0])
3358                                                 radeon_crtc_handle_flip(rdev, 0);
3359                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3360                                         DRM_DEBUG("IH: D1 vblank\n");
3361                                 }
3362                                 break;
3363                         case 1: /* D1 vline */
3364                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3365                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3366                                         DRM_DEBUG("IH: D1 vline\n");
3367                                 }
3368                                 break;
3369                         default:
3370                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3371                                 break;
3372                         }
3373                         break;
3374                 case 5: /* D2 vblank/vline */
3375                         switch (src_data) {
3376                         case 0: /* D2 vblank */
3377                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3378                                         if (rdev->irq.crtc_vblank_int[1]) {
3379                                                 drm_handle_vblank(rdev->ddev, 1);
3380                                                 rdev->pm.vblank_sync = true;
3381                                                 wake_up(&rdev->irq.vblank_queue);
3382                                         }
3383                                         if (rdev->irq.pflip[1])
3384                                                 radeon_crtc_handle_flip(rdev, 1);
3385                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3386                                         DRM_DEBUG("IH: D2 vblank\n");
3387                                 }
3388                                 break;
3389                         case 1: /* D1 vline */
3390                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3391                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3392                                         DRM_DEBUG("IH: D2 vline\n");
3393                                 }
3394                                 break;
3395                         default:
3396                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3397                                 break;
3398                         }
3399                         break;
3400                 case 19: /* HPD/DAC hotplug */
3401                         switch (src_data) {
3402                         case 0:
3403                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3404                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3405                                         queue_hotplug = true;
3406                                         DRM_DEBUG("IH: HPD1\n");
3407                                 }
3408                                 break;
3409                         case 1:
3410                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3411                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3412                                         queue_hotplug = true;
3413                                         DRM_DEBUG("IH: HPD2\n");
3414                                 }
3415                                 break;
3416                         case 4:
3417                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3418                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3419                                         queue_hotplug = true;
3420                                         DRM_DEBUG("IH: HPD3\n");
3421                                 }
3422                                 break;
3423                         case 5:
3424                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3425                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3426                                         queue_hotplug = true;
3427                                         DRM_DEBUG("IH: HPD4\n");
3428                                 }
3429                                 break;
3430                         case 10:
3431                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3432                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3433                                         queue_hotplug = true;
3434                                         DRM_DEBUG("IH: HPD5\n");
3435                                 }
3436                                 break;
3437                         case 12:
3438                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3439                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3440                                         queue_hotplug = true;
3441                                         DRM_DEBUG("IH: HPD6\n");
3442                                 }
3443                                 break;
3444                         default:
3445                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3446                                 break;
3447                         }
3448                         break;
3449                 case 21: /* hdmi */
3450                         switch (src_data) {
3451                         case 4:
3452                                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3453                                         rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3454                                         queue_hdmi = true;
3455                                         DRM_DEBUG("IH: HDMI0\n");
3456                                 }
3457                                 break;
3458                         case 5:
3459                                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3460                                         rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3461                                         queue_hdmi = true;
3462                                         DRM_DEBUG("IH: HDMI1\n");
3463                                 }
3464                                 break;
3465                         default:
3466                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3467                                 break;
3468                         }
3469                         break;
3470                 case 176: /* CP_INT in ring buffer */
3471                 case 177: /* CP_INT in IB1 */
3472                 case 178: /* CP_INT in IB2 */
3473                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3474                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3475                         break;
3476                 case 181: /* CP EOP event */
3477                         DRM_DEBUG("IH: CP EOP\n");
3478                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3479                         break;
3480                 case 233: /* GUI IDLE */
3481                         DRM_DEBUG("IH: GUI idle\n");
3482                         rdev->pm.gui_idle = true;
3483                         wake_up(&rdev->irq.idle_queue);
3484                         break;
3485                 default:
3486                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3487                         break;
3488                 }
3489
3490                 /* wptr/rptr are in bytes! */
3491                 rptr += 16;
3492                 rptr &= rdev->ih.ptr_mask;
3493         }
3494         /* make sure wptr hasn't changed while processing */
3495         wptr = r600_get_ih_wptr(rdev);
3496         if (wptr != rdev->ih.wptr)
3497                 goto restart_ih;
3498         if (queue_hotplug)
3499                 schedule_work(&rdev->hotplug_work);
3500         if (queue_hdmi)
3501                 schedule_work(&rdev->audio_work);
3502         rdev->ih.rptr = rptr;
3503         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3504         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3505         return IRQ_HANDLED;
3506 }
3507
3508 /*
3509  * Debugfs info
3510  */
3511 #if defined(CONFIG_DEBUG_FS)
3512
3513 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3514 {
3515         struct drm_info_node *node = (struct drm_info_node *) m->private;
3516         struct drm_device *dev = node->minor->dev;
3517         struct radeon_device *rdev = dev->dev_private;
3518
3519         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3520         DREG32_SYS(m, rdev, VM_L2_STATUS);
3521         return 0;
3522 }
3523
3524 static struct drm_info_list r600_mc_info_list[] = {
3525         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3526 };
3527 #endif
3528
3529 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3530 {
3531 #if defined(CONFIG_DEBUG_FS)
3532         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3533 #else
3534         return 0;
3535 #endif
3536 }
3537
3538 /**
3539  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3540  * rdev: radeon device structure
3541  * bo: buffer object struct which userspace is waiting for idle
3542  *
3543  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3544  * through ring buffer, this leads to corruption in rendering, see
3545  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3546  * directly perform HDP flush by writing register through MMIO.
3547  */
3548 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3549 {
3550         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3551          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3552          * This seems to cause problems on some AGP cards. Just use the old
3553          * method for them.
3554          */
3555         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3556             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3557                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3558                 u32 tmp;
3559
3560                 WREG32(HDP_DEBUG1, 0);
3561                 tmp = readl((void __iomem *)ptr);
3562         } else
3563                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3564 }
3565
3566 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3567 {
3568         u32 link_width_cntl, mask, target_reg;
3569
3570         if (rdev->flags & RADEON_IS_IGP)
3571                 return;
3572
3573         if (!(rdev->flags & RADEON_IS_PCIE))
3574                 return;
3575
3576         /* x2 cards have a special sequence */
3577         if (ASIC_IS_X2(rdev))
3578                 return;
3579
3580         /* FIXME wait for idle */
3581
3582         switch (lanes) {
3583         case 0:
3584                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3585                 break;
3586         case 1:
3587                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3588                 break;
3589         case 2:
3590                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3591                 break;
3592         case 4:
3593                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3594                 break;
3595         case 8:
3596                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3597                 break;
3598         case 12:
3599                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3600                 break;
3601         case 16:
3602         default:
3603                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3604                 break;
3605         }
3606
3607         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3608
3609         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3610             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3611                 return;
3612
3613         if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3614                 return;
3615
3616         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3617                              RADEON_PCIE_LC_RECONFIG_NOW |
3618                              R600_PCIE_LC_RENEGOTIATE_EN |
3619                              R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3620         link_width_cntl |= mask;
3621
3622         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3623
3624         /* some northbridges can renegotiate the link rather than requiring
3625          * a complete re-config.
3626          * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3627          */
3628         if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3629                 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3630         else
3631                 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3632
3633         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3634                                                        RADEON_PCIE_LC_RECONFIG_NOW));
3635
3636         if (rdev->family >= CHIP_RV770)
3637                 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3638         else
3639                 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3640
3641         /* wait for lane set to complete */
3642         link_width_cntl = RREG32(target_reg);
3643         while (link_width_cntl == 0xffffffff)
3644                 link_width_cntl = RREG32(target_reg);
3645
3646 }
3647
3648 int r600_get_pcie_lanes(struct radeon_device *rdev)
3649 {
3650         u32 link_width_cntl;
3651
3652         if (rdev->flags & RADEON_IS_IGP)
3653                 return 0;
3654
3655         if (!(rdev->flags & RADEON_IS_PCIE))
3656                 return 0;
3657
3658         /* x2 cards have a special sequence */
3659         if (ASIC_IS_X2(rdev))
3660                 return 0;
3661
3662         /* FIXME wait for idle */
3663
3664         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3665
3666         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3667         case RADEON_PCIE_LC_LINK_WIDTH_X0:
3668                 return 0;
3669         case RADEON_PCIE_LC_LINK_WIDTH_X1:
3670                 return 1;
3671         case RADEON_PCIE_LC_LINK_WIDTH_X2:
3672                 return 2;
3673         case RADEON_PCIE_LC_LINK_WIDTH_X4:
3674                 return 4;
3675         case RADEON_PCIE_LC_LINK_WIDTH_X8:
3676                 return 8;
3677         case RADEON_PCIE_LC_LINK_WIDTH_X16:
3678         default:
3679                 return 16;
3680         }
3681 }
3682
3683 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3684 {
3685         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3686         u16 link_cntl2;
3687
3688         if (radeon_pcie_gen2 == 0)
3689                 return;
3690
3691         if (rdev->flags & RADEON_IS_IGP)
3692                 return;
3693
3694         if (!(rdev->flags & RADEON_IS_PCIE))
3695                 return;
3696
3697         /* x2 cards have a special sequence */
3698         if (ASIC_IS_X2(rdev))
3699                 return;
3700
3701         /* only RV6xx+ chips are supported */
3702         if (rdev->family <= CHIP_R600)
3703                 return;
3704
3705         /* 55 nm r6xx asics */
3706         if ((rdev->family == CHIP_RV670) ||
3707             (rdev->family == CHIP_RV620) ||
3708             (rdev->family == CHIP_RV635)) {
3709                 /* advertise upconfig capability */
3710                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3711                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3712                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3713                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3714                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3715                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3716                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3717                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
3718                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3719                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3720                 } else {
3721                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3722                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3723                 }
3724         }
3725
3726         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3727         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3728             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3729
3730                 /* 55 nm r6xx asics */
3731                 if ((rdev->family == CHIP_RV670) ||
3732                     (rdev->family == CHIP_RV620) ||
3733                     (rdev->family == CHIP_RV635)) {
3734                         WREG32(MM_CFGREGS_CNTL, 0x8);
3735                         link_cntl2 = RREG32(0x4088);
3736                         WREG32(MM_CFGREGS_CNTL, 0);
3737                         /* not supported yet */
3738                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3739                                 return;
3740                 }
3741
3742                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3743                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3744                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3745                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3746                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3747                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3748
3749                 tmp = RREG32(0x541c);
3750                 WREG32(0x541c, tmp | 0x8);
3751                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3752                 link_cntl2 = RREG16(0x4088);
3753                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3754                 link_cntl2 |= 0x2;
3755                 WREG16(0x4088, link_cntl2);
3756                 WREG32(MM_CFGREGS_CNTL, 0);
3757
3758                 if ((rdev->family == CHIP_RV670) ||
3759                     (rdev->family == CHIP_RV620) ||
3760                     (rdev->family == CHIP_RV635)) {
3761                         training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3762                         training_cntl &= ~LC_POINT_7_PLUS_EN;
3763                         WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3764                 } else {
3765                         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3766                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3767                         WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3768                 }
3769
3770                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3771                 speed_cntl |= LC_GEN2_EN_STRAP;
3772                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3773
3774         } else {
3775                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3776                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3777                 if (1)
3778                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3779                 else
3780                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3781                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3782         }
3783 }