2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
33 #include "radeon_drm.h"
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
41 #define PFP_UCODE_SIZE 576
42 #define PM4_UCODE_SIZE 1792
43 #define RLC_UCODE_SIZE 768
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
46 #define R700_RLC_UCODE_SIZE 1024
47 #define EVERGREEN_PFP_UCODE_SIZE 1120
48 #define EVERGREEN_PM4_UCODE_SIZE 1376
49 #define EVERGREEN_RLC_UCODE_SIZE 768
52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
53 MODULE_FIRMWARE("radeon/R600_me.bin");
54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55 MODULE_FIRMWARE("radeon/RV610_me.bin");
56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57 MODULE_FIRMWARE("radeon/RV630_me.bin");
58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59 MODULE_FIRMWARE("radeon/RV620_me.bin");
60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61 MODULE_FIRMWARE("radeon/RV635_me.bin");
62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63 MODULE_FIRMWARE("radeon/RV670_me.bin");
64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65 MODULE_FIRMWARE("radeon/RS780_me.bin");
66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67 MODULE_FIRMWARE("radeon/RV770_me.bin");
68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69 MODULE_FIRMWARE("radeon/RV730_me.bin");
70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71 MODULE_FIRMWARE("radeon/RV710_me.bin");
72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
89 /* r600,rv610,rv630,rv620,rv635,rv670 */
90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
91 void r600_gpu_init(struct radeon_device *rdev);
92 void r600_fini(struct radeon_device *rdev);
93 void r600_irq_disable(struct radeon_device *rdev);
95 /* get temperature in millidegrees */
96 u32 rv6xx_get_temp(struct radeon_device *rdev)
98 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
104 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
108 rdev->pm.dynpm_can_upclock = true;
109 rdev->pm.dynpm_can_downclock = true;
111 /* power state array is low to high, default is first */
112 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
113 int min_power_state_index = 0;
115 if (rdev->pm.num_power_states > 2)
116 min_power_state_index = 1;
118 switch (rdev->pm.dynpm_planned_action) {
119 case DYNPM_ACTION_MINIMUM:
120 rdev->pm.requested_power_state_index = min_power_state_index;
121 rdev->pm.requested_clock_mode_index = 0;
122 rdev->pm.dynpm_can_downclock = false;
124 case DYNPM_ACTION_DOWNCLOCK:
125 if (rdev->pm.current_power_state_index == min_power_state_index) {
126 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
127 rdev->pm.dynpm_can_downclock = false;
129 if (rdev->pm.active_crtc_count > 1) {
130 for (i = 0; i < rdev->pm.num_power_states; i++) {
131 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
133 else if (i >= rdev->pm.current_power_state_index) {
134 rdev->pm.requested_power_state_index =
135 rdev->pm.current_power_state_index;
138 rdev->pm.requested_power_state_index = i;
143 if (rdev->pm.current_power_state_index == 0)
144 rdev->pm.requested_power_state_index =
145 rdev->pm.num_power_states - 1;
147 rdev->pm.requested_power_state_index =
148 rdev->pm.current_power_state_index - 1;
151 rdev->pm.requested_clock_mode_index = 0;
152 /* don't use the power state if crtcs are active and no display flag is set */
153 if ((rdev->pm.active_crtc_count > 0) &&
154 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
155 clock_info[rdev->pm.requested_clock_mode_index].flags &
156 RADEON_PM_MODE_NO_DISPLAY)) {
157 rdev->pm.requested_power_state_index++;
160 case DYNPM_ACTION_UPCLOCK:
161 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
162 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
163 rdev->pm.dynpm_can_upclock = false;
165 if (rdev->pm.active_crtc_count > 1) {
166 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
167 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
169 else if (i <= rdev->pm.current_power_state_index) {
170 rdev->pm.requested_power_state_index =
171 rdev->pm.current_power_state_index;
174 rdev->pm.requested_power_state_index = i;
179 rdev->pm.requested_power_state_index =
180 rdev->pm.current_power_state_index + 1;
182 rdev->pm.requested_clock_mode_index = 0;
184 case DYNPM_ACTION_DEFAULT:
185 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
186 rdev->pm.requested_clock_mode_index = 0;
187 rdev->pm.dynpm_can_upclock = false;
189 case DYNPM_ACTION_NONE:
191 DRM_ERROR("Requested mode for not defined action\n");
195 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
196 /* for now just select the first power state and switch between clock modes */
197 /* power state array is low to high, default is first (0) */
198 if (rdev->pm.active_crtc_count > 1) {
199 rdev->pm.requested_power_state_index = -1;
200 /* start at 1 as we don't want the default mode */
201 for (i = 1; i < rdev->pm.num_power_states; i++) {
202 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
204 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
205 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
206 rdev->pm.requested_power_state_index = i;
210 /* if nothing selected, grab the default state. */
211 if (rdev->pm.requested_power_state_index == -1)
212 rdev->pm.requested_power_state_index = 0;
214 rdev->pm.requested_power_state_index = 1;
216 switch (rdev->pm.dynpm_planned_action) {
217 case DYNPM_ACTION_MINIMUM:
218 rdev->pm.requested_clock_mode_index = 0;
219 rdev->pm.dynpm_can_downclock = false;
221 case DYNPM_ACTION_DOWNCLOCK:
222 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
223 if (rdev->pm.current_clock_mode_index == 0) {
224 rdev->pm.requested_clock_mode_index = 0;
225 rdev->pm.dynpm_can_downclock = false;
227 rdev->pm.requested_clock_mode_index =
228 rdev->pm.current_clock_mode_index - 1;
230 rdev->pm.requested_clock_mode_index = 0;
231 rdev->pm.dynpm_can_downclock = false;
233 /* don't use the power state if crtcs are active and no display flag is set */
234 if ((rdev->pm.active_crtc_count > 0) &&
235 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
236 clock_info[rdev->pm.requested_clock_mode_index].flags &
237 RADEON_PM_MODE_NO_DISPLAY)) {
238 rdev->pm.requested_clock_mode_index++;
241 case DYNPM_ACTION_UPCLOCK:
242 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
243 if (rdev->pm.current_clock_mode_index ==
244 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
245 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
246 rdev->pm.dynpm_can_upclock = false;
248 rdev->pm.requested_clock_mode_index =
249 rdev->pm.current_clock_mode_index + 1;
251 rdev->pm.requested_clock_mode_index =
252 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
253 rdev->pm.dynpm_can_upclock = false;
256 case DYNPM_ACTION_DEFAULT:
257 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
258 rdev->pm.requested_clock_mode_index = 0;
259 rdev->pm.dynpm_can_upclock = false;
261 case DYNPM_ACTION_NONE:
263 DRM_ERROR("Requested mode for not defined action\n");
268 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
269 rdev->pm.power_state[rdev->pm.requested_power_state_index].
270 clock_info[rdev->pm.requested_clock_mode_index].sclk,
271 rdev->pm.power_state[rdev->pm.requested_power_state_index].
272 clock_info[rdev->pm.requested_clock_mode_index].mclk,
273 rdev->pm.power_state[rdev->pm.requested_power_state_index].
277 static int r600_pm_get_type_index(struct radeon_device *rdev,
278 enum radeon_pm_state_type ps_type,
282 int found_instance = -1;
284 for (i = 0; i < rdev->pm.num_power_states; i++) {
285 if (rdev->pm.power_state[i].type == ps_type) {
287 if (found_instance == instance)
291 /* return default if no match */
292 return rdev->pm.default_power_state_index;
295 void rs780_pm_init_profile(struct radeon_device *rdev)
297 if (rdev->pm.num_power_states == 2) {
299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
300 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
305 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
333 } else if (rdev->pm.num_power_states == 3) {
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
336 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
337 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
341 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
342 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
346 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
351 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
352 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
353 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
356 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
357 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
358 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
361 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
362 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
363 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
366 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
367 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
368 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
372 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
373 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
374 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
377 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
378 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
379 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
382 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
384 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
387 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
388 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
389 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
392 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
393 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
394 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
397 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
398 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
399 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
402 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
403 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
404 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
408 void r600_pm_init_profile(struct radeon_device *rdev)
410 if (rdev->family == CHIP_R600) {
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
415 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
416 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
420 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
421 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
425 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
426 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
430 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
431 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
435 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
436 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
440 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
441 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
445 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
446 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
448 if (rdev->pm.num_power_states < 4) {
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
452 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
453 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
457 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
458 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
462 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
463 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
467 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
468 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
473 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
477 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
478 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
482 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
483 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
489 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
491 if (rdev->flags & RADEON_IS_MOBILITY) {
492 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
493 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
495 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
497 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
499 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
500 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
501 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
502 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
503 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
504 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
507 if (rdev->flags & RADEON_IS_MOBILITY) {
508 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
509 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
510 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
511 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
512 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
513 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
515 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
516 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
517 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
518 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
519 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
520 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
523 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
524 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
525 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
526 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
527 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
530 if (rdev->flags & RADEON_IS_MOBILITY) {
531 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
532 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
533 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
534 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
535 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
536 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
538 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
539 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
540 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
541 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
542 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
543 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
546 if (rdev->flags & RADEON_IS_MOBILITY) {
547 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
548 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
549 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
550 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
551 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
552 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
554 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
555 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
556 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
557 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
558 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
559 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
562 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
563 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
564 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
565 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
566 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
567 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
572 void r600_pm_misc(struct radeon_device *rdev)
574 int req_ps_idx = rdev->pm.requested_power_state_index;
575 int req_cm_idx = rdev->pm.requested_clock_mode_index;
576 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
577 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
579 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
580 if (voltage->voltage != rdev->pm.current_vddc) {
581 radeon_atom_set_voltage(rdev, voltage->voltage);
582 rdev->pm.current_vddc = voltage->voltage;
583 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
588 bool r600_gui_idle(struct radeon_device *rdev)
590 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
596 /* hpd for digital panel detect/disconnect */
597 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
599 bool connected = false;
601 if (ASIC_IS_DCE3(rdev)) {
604 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
608 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
612 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
616 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
621 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
625 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
634 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
638 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
642 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
652 void r600_hpd_set_polarity(struct radeon_device *rdev,
653 enum radeon_hpd_id hpd)
656 bool connected = r600_hpd_sense(rdev, hpd);
658 if (ASIC_IS_DCE3(rdev)) {
661 tmp = RREG32(DC_HPD1_INT_CONTROL);
663 tmp &= ~DC_HPDx_INT_POLARITY;
665 tmp |= DC_HPDx_INT_POLARITY;
666 WREG32(DC_HPD1_INT_CONTROL, tmp);
669 tmp = RREG32(DC_HPD2_INT_CONTROL);
671 tmp &= ~DC_HPDx_INT_POLARITY;
673 tmp |= DC_HPDx_INT_POLARITY;
674 WREG32(DC_HPD2_INT_CONTROL, tmp);
677 tmp = RREG32(DC_HPD3_INT_CONTROL);
679 tmp &= ~DC_HPDx_INT_POLARITY;
681 tmp |= DC_HPDx_INT_POLARITY;
682 WREG32(DC_HPD3_INT_CONTROL, tmp);
685 tmp = RREG32(DC_HPD4_INT_CONTROL);
687 tmp &= ~DC_HPDx_INT_POLARITY;
689 tmp |= DC_HPDx_INT_POLARITY;
690 WREG32(DC_HPD4_INT_CONTROL, tmp);
693 tmp = RREG32(DC_HPD5_INT_CONTROL);
695 tmp &= ~DC_HPDx_INT_POLARITY;
697 tmp |= DC_HPDx_INT_POLARITY;
698 WREG32(DC_HPD5_INT_CONTROL, tmp);
702 tmp = RREG32(DC_HPD6_INT_CONTROL);
704 tmp &= ~DC_HPDx_INT_POLARITY;
706 tmp |= DC_HPDx_INT_POLARITY;
707 WREG32(DC_HPD6_INT_CONTROL, tmp);
715 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
717 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
719 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
720 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
723 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
725 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
727 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
728 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
731 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
733 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
735 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
736 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
744 void r600_hpd_init(struct radeon_device *rdev)
746 struct drm_device *dev = rdev->ddev;
747 struct drm_connector *connector;
749 if (ASIC_IS_DCE3(rdev)) {
750 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
751 if (ASIC_IS_DCE32(rdev))
754 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
755 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
756 switch (radeon_connector->hpd.hpd) {
758 WREG32(DC_HPD1_CONTROL, tmp);
759 rdev->irq.hpd[0] = true;
762 WREG32(DC_HPD2_CONTROL, tmp);
763 rdev->irq.hpd[1] = true;
766 WREG32(DC_HPD3_CONTROL, tmp);
767 rdev->irq.hpd[2] = true;
770 WREG32(DC_HPD4_CONTROL, tmp);
771 rdev->irq.hpd[3] = true;
775 WREG32(DC_HPD5_CONTROL, tmp);
776 rdev->irq.hpd[4] = true;
779 WREG32(DC_HPD6_CONTROL, tmp);
780 rdev->irq.hpd[5] = true;
787 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
788 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
789 switch (radeon_connector->hpd.hpd) {
791 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
792 rdev->irq.hpd[0] = true;
795 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
796 rdev->irq.hpd[1] = true;
799 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
800 rdev->irq.hpd[2] = true;
807 if (rdev->irq.installed)
811 void r600_hpd_fini(struct radeon_device *rdev)
813 struct drm_device *dev = rdev->ddev;
814 struct drm_connector *connector;
816 if (ASIC_IS_DCE3(rdev)) {
817 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
818 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
819 switch (radeon_connector->hpd.hpd) {
821 WREG32(DC_HPD1_CONTROL, 0);
822 rdev->irq.hpd[0] = false;
825 WREG32(DC_HPD2_CONTROL, 0);
826 rdev->irq.hpd[1] = false;
829 WREG32(DC_HPD3_CONTROL, 0);
830 rdev->irq.hpd[2] = false;
833 WREG32(DC_HPD4_CONTROL, 0);
834 rdev->irq.hpd[3] = false;
838 WREG32(DC_HPD5_CONTROL, 0);
839 rdev->irq.hpd[4] = false;
842 WREG32(DC_HPD6_CONTROL, 0);
843 rdev->irq.hpd[5] = false;
850 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
851 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
852 switch (radeon_connector->hpd.hpd) {
854 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
855 rdev->irq.hpd[0] = false;
858 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
859 rdev->irq.hpd[1] = false;
862 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
863 rdev->irq.hpd[2] = false;
875 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
880 /* flush hdp cache so updates hit vram */
881 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
882 !(rdev->flags & RADEON_IS_AGP)) {
883 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
886 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
887 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
888 * This seems to cause problems on some AGP cards. Just use the old
891 WREG32(HDP_DEBUG1, 0);
892 tmp = readl((void __iomem *)ptr);
894 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
896 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
897 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
898 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
899 for (i = 0; i < rdev->usec_timeout; i++) {
901 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
902 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
904 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
914 int r600_pcie_gart_init(struct radeon_device *rdev)
918 if (rdev->gart.table.vram.robj) {
919 WARN(1, "R600 PCIE GART already initialized\n");
922 /* Initialize common gart structure */
923 r = radeon_gart_init(rdev);
926 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
927 return radeon_gart_table_vram_alloc(rdev);
930 int r600_pcie_gart_enable(struct radeon_device *rdev)
935 if (rdev->gart.table.vram.robj == NULL) {
936 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
939 r = radeon_gart_table_vram_pin(rdev);
942 radeon_gart_restore(rdev);
945 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
946 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
947 EFFECTIVE_L2_QUEUE_SIZE(7));
948 WREG32(VM_L2_CNTL2, 0);
949 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
950 /* Setup TLB control */
951 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
952 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
953 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
954 ENABLE_WAIT_L2_QUERY;
955 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
956 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
957 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
958 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
959 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
960 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
961 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
962 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
963 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
964 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
965 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
968 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
969 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
970 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
971 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
972 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
973 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
974 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
975 (u32)(rdev->dummy_page.addr >> 12));
976 for (i = 1; i < 7; i++)
977 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
979 r600_pcie_gart_tlb_flush(rdev);
980 rdev->gart.ready = true;
984 void r600_pcie_gart_disable(struct radeon_device *rdev)
989 /* Disable all tables */
990 for (i = 0; i < 7; i++)
991 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
993 /* Disable L2 cache */
994 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
995 EFFECTIVE_L2_QUEUE_SIZE(7));
996 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
997 /* Setup L1 TLB control */
998 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
999 ENABLE_WAIT_L2_QUERY;
1000 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1001 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1002 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1003 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1004 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1010 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1011 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1012 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1013 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1014 if (rdev->gart.table.vram.robj) {
1015 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1016 if (likely(r == 0)) {
1017 radeon_bo_kunmap(rdev->gart.table.vram.robj);
1018 radeon_bo_unpin(rdev->gart.table.vram.robj);
1019 radeon_bo_unreserve(rdev->gart.table.vram.robj);
1024 void r600_pcie_gart_fini(struct radeon_device *rdev)
1026 radeon_gart_fini(rdev);
1027 r600_pcie_gart_disable(rdev);
1028 radeon_gart_table_vram_free(rdev);
1031 void r600_agp_enable(struct radeon_device *rdev)
1036 /* Setup L2 cache */
1037 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1038 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1039 EFFECTIVE_L2_QUEUE_SIZE(7));
1040 WREG32(VM_L2_CNTL2, 0);
1041 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1042 /* Setup TLB control */
1043 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1044 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1045 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1046 ENABLE_WAIT_L2_QUERY;
1047 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1048 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1049 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1050 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1051 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1052 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1053 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1054 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1055 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1056 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1057 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1058 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1059 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1060 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1061 for (i = 0; i < 7; i++)
1062 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1065 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1070 for (i = 0; i < rdev->usec_timeout; i++) {
1071 /* read MC_STATUS */
1072 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1080 static void r600_mc_program(struct radeon_device *rdev)
1082 struct rv515_mc_save save;
1086 /* Initialize HDP */
1087 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1088 WREG32((0x2c14 + j), 0x00000000);
1089 WREG32((0x2c18 + j), 0x00000000);
1090 WREG32((0x2c1c + j), 0x00000000);
1091 WREG32((0x2c20 + j), 0x00000000);
1092 WREG32((0x2c24 + j), 0x00000000);
1094 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1096 rv515_mc_stop(rdev, &save);
1097 if (r600_mc_wait_for_idle(rdev)) {
1098 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1100 /* Lockout access through VGA aperture (doesn't exist before R600) */
1101 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1102 /* Update configuration */
1103 if (rdev->flags & RADEON_IS_AGP) {
1104 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1105 /* VRAM before AGP */
1106 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1107 rdev->mc.vram_start >> 12);
1108 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1109 rdev->mc.gtt_end >> 12);
1111 /* VRAM after AGP */
1112 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1113 rdev->mc.gtt_start >> 12);
1114 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1115 rdev->mc.vram_end >> 12);
1118 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1119 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1121 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1122 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1123 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1124 WREG32(MC_VM_FB_LOCATION, tmp);
1125 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1126 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1127 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1128 if (rdev->flags & RADEON_IS_AGP) {
1129 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1130 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1131 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1133 WREG32(MC_VM_AGP_BASE, 0);
1134 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1135 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1137 if (r600_mc_wait_for_idle(rdev)) {
1138 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1140 rv515_mc_resume(rdev, &save);
1141 /* we need to own VRAM, so turn off the VGA renderer here
1142 * to stop it overwriting our objects */
1143 rv515_vga_render_disable(rdev);
1147 * r600_vram_gtt_location - try to find VRAM & GTT location
1148 * @rdev: radeon device structure holding all necessary informations
1149 * @mc: memory controller structure holding memory informations
1151 * Function will place try to place VRAM at same place as in CPU (PCI)
1152 * address space as some GPU seems to have issue when we reprogram at
1153 * different address space.
1155 * If there is not enough space to fit the unvisible VRAM after the
1156 * aperture then we limit the VRAM size to the aperture.
1158 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1159 * them to be in one from GPU point of view so that we can program GPU to
1160 * catch access outside them (weird GPU policy see ??).
1162 * This function will never fails, worst case are limiting VRAM or GTT.
1164 * Note: GTT start, end, size should be initialized before calling this
1165 * function on AGP platform.
1167 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1169 u64 size_bf, size_af;
1171 if (mc->mc_vram_size > 0xE0000000) {
1172 /* leave room for at least 512M GTT */
1173 dev_warn(rdev->dev, "limiting VRAM\n");
1174 mc->real_vram_size = 0xE0000000;
1175 mc->mc_vram_size = 0xE0000000;
1177 if (rdev->flags & RADEON_IS_AGP) {
1178 size_bf = mc->gtt_start;
1179 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1180 if (size_bf > size_af) {
1181 if (mc->mc_vram_size > size_bf) {
1182 dev_warn(rdev->dev, "limiting VRAM\n");
1183 mc->real_vram_size = size_bf;
1184 mc->mc_vram_size = size_bf;
1186 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1188 if (mc->mc_vram_size > size_af) {
1189 dev_warn(rdev->dev, "limiting VRAM\n");
1190 mc->real_vram_size = size_af;
1191 mc->mc_vram_size = size_af;
1193 mc->vram_start = mc->gtt_end;
1195 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1196 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1197 mc->mc_vram_size >> 20, mc->vram_start,
1198 mc->vram_end, mc->real_vram_size >> 20);
1201 if (rdev->flags & RADEON_IS_IGP) {
1202 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1205 radeon_vram_location(rdev, &rdev->mc, base);
1206 rdev->mc.gtt_base_align = 0;
1207 radeon_gtt_location(rdev, mc);
1211 int r600_mc_init(struct radeon_device *rdev)
1214 int chansize, numchan;
1216 /* Get VRAM informations */
1217 rdev->mc.vram_is_ddr = true;
1218 tmp = RREG32(RAMCFG);
1219 if (tmp & CHANSIZE_OVERRIDE) {
1221 } else if (tmp & CHANSIZE_MASK) {
1226 tmp = RREG32(CHMAP);
1227 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1242 rdev->mc.vram_width = numchan * chansize;
1243 /* Could aper size report 0 ? */
1244 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1245 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1246 /* Setup GPU memory space */
1247 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1248 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1249 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1250 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1251 r600_vram_gtt_location(rdev, &rdev->mc);
1253 if (rdev->flags & RADEON_IS_IGP) {
1254 rs690_pm_info(rdev);
1255 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1257 radeon_update_bandwidth_info(rdev);
1261 /* We doesn't check that the GPU really needs a reset we simply do the
1262 * reset, it's up to the caller to determine if the GPU needs one. We
1263 * might add an helper function to check that.
1265 int r600_gpu_soft_reset(struct radeon_device *rdev)
1267 struct rv515_mc_save save;
1268 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1269 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1270 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1271 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1272 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1273 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1274 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1275 S_008010_GUI_ACTIVE(1);
1276 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1277 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1278 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1279 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1280 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1281 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1282 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1283 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1286 dev_info(rdev->dev, "GPU softreset \n");
1287 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1288 RREG32(R_008010_GRBM_STATUS));
1289 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1290 RREG32(R_008014_GRBM_STATUS2));
1291 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1292 RREG32(R_000E50_SRBM_STATUS));
1293 rv515_mc_stop(rdev, &save);
1294 if (r600_mc_wait_for_idle(rdev)) {
1295 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1297 /* Disable CP parsing/prefetching */
1298 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1299 /* Check if any of the rendering block is busy and reset it */
1300 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1301 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1302 tmp = S_008020_SOFT_RESET_CR(1) |
1303 S_008020_SOFT_RESET_DB(1) |
1304 S_008020_SOFT_RESET_CB(1) |
1305 S_008020_SOFT_RESET_PA(1) |
1306 S_008020_SOFT_RESET_SC(1) |
1307 S_008020_SOFT_RESET_SMX(1) |
1308 S_008020_SOFT_RESET_SPI(1) |
1309 S_008020_SOFT_RESET_SX(1) |
1310 S_008020_SOFT_RESET_SH(1) |
1311 S_008020_SOFT_RESET_TC(1) |
1312 S_008020_SOFT_RESET_TA(1) |
1313 S_008020_SOFT_RESET_VC(1) |
1314 S_008020_SOFT_RESET_VGT(1);
1315 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1316 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1317 RREG32(R_008020_GRBM_SOFT_RESET);
1319 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1321 /* Reset CP (we always reset CP) */
1322 tmp = S_008020_SOFT_RESET_CP(1);
1323 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1324 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1325 RREG32(R_008020_GRBM_SOFT_RESET);
1327 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1328 /* Wait a little for things to settle down */
1330 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1331 RREG32(R_008010_GRBM_STATUS));
1332 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1333 RREG32(R_008014_GRBM_STATUS2));
1334 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1335 RREG32(R_000E50_SRBM_STATUS));
1336 rv515_mc_resume(rdev, &save);
1340 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1345 struct r100_gpu_lockup *lockup;
1348 if (rdev->family >= CHIP_RV770)
1349 lockup = &rdev->config.rv770.lockup;
1351 lockup = &rdev->config.r600.lockup;
1353 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1354 grbm_status = RREG32(R_008010_GRBM_STATUS);
1355 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1356 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1357 r100_gpu_lockup_update(lockup, &rdev->cp);
1360 /* force CP activities */
1361 r = radeon_ring_lock(rdev, 2);
1364 radeon_ring_write(rdev, 0x80000000);
1365 radeon_ring_write(rdev, 0x80000000);
1366 radeon_ring_unlock_commit(rdev);
1368 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1369 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1372 int r600_asic_reset(struct radeon_device *rdev)
1374 return r600_gpu_soft_reset(rdev);
1377 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1379 u32 backend_disable_mask)
1381 u32 backend_map = 0;
1382 u32 enabled_backends_mask;
1383 u32 enabled_backends_count;
1385 u32 swizzle_pipe[R6XX_MAX_PIPES];
1389 if (num_tile_pipes > R6XX_MAX_PIPES)
1390 num_tile_pipes = R6XX_MAX_PIPES;
1391 if (num_tile_pipes < 1)
1393 if (num_backends > R6XX_MAX_BACKENDS)
1394 num_backends = R6XX_MAX_BACKENDS;
1395 if (num_backends < 1)
1398 enabled_backends_mask = 0;
1399 enabled_backends_count = 0;
1400 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1401 if (((backend_disable_mask >> i) & 1) == 0) {
1402 enabled_backends_mask |= (1 << i);
1403 ++enabled_backends_count;
1405 if (enabled_backends_count == num_backends)
1409 if (enabled_backends_count == 0) {
1410 enabled_backends_mask = 1;
1411 enabled_backends_count = 1;
1414 if (enabled_backends_count != num_backends)
1415 num_backends = enabled_backends_count;
1417 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1418 switch (num_tile_pipes) {
1420 swizzle_pipe[0] = 0;
1423 swizzle_pipe[0] = 0;
1424 swizzle_pipe[1] = 1;
1427 swizzle_pipe[0] = 0;
1428 swizzle_pipe[1] = 1;
1429 swizzle_pipe[2] = 2;
1432 swizzle_pipe[0] = 0;
1433 swizzle_pipe[1] = 1;
1434 swizzle_pipe[2] = 2;
1435 swizzle_pipe[3] = 3;
1438 swizzle_pipe[0] = 0;
1439 swizzle_pipe[1] = 1;
1440 swizzle_pipe[2] = 2;
1441 swizzle_pipe[3] = 3;
1442 swizzle_pipe[4] = 4;
1445 swizzle_pipe[0] = 0;
1446 swizzle_pipe[1] = 2;
1447 swizzle_pipe[2] = 4;
1448 swizzle_pipe[3] = 5;
1449 swizzle_pipe[4] = 1;
1450 swizzle_pipe[5] = 3;
1453 swizzle_pipe[0] = 0;
1454 swizzle_pipe[1] = 2;
1455 swizzle_pipe[2] = 4;
1456 swizzle_pipe[3] = 6;
1457 swizzle_pipe[4] = 1;
1458 swizzle_pipe[5] = 3;
1459 swizzle_pipe[6] = 5;
1462 swizzle_pipe[0] = 0;
1463 swizzle_pipe[1] = 2;
1464 swizzle_pipe[2] = 4;
1465 swizzle_pipe[3] = 6;
1466 swizzle_pipe[4] = 1;
1467 swizzle_pipe[5] = 3;
1468 swizzle_pipe[6] = 5;
1469 swizzle_pipe[7] = 7;
1474 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1475 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1476 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1478 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1480 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1486 int r600_count_pipe_bits(uint32_t val)
1490 for (i = 0; i < 32; i++) {
1497 void r600_gpu_init(struct radeon_device *rdev)
1502 u32 cc_rb_backend_disable;
1503 u32 cc_gc_shader_pipe_config;
1507 u32 sq_gpr_resource_mgmt_1 = 0;
1508 u32 sq_gpr_resource_mgmt_2 = 0;
1509 u32 sq_thread_resource_mgmt = 0;
1510 u32 sq_stack_resource_mgmt_1 = 0;
1511 u32 sq_stack_resource_mgmt_2 = 0;
1513 /* FIXME: implement */
1514 switch (rdev->family) {
1516 rdev->config.r600.max_pipes = 4;
1517 rdev->config.r600.max_tile_pipes = 8;
1518 rdev->config.r600.max_simds = 4;
1519 rdev->config.r600.max_backends = 4;
1520 rdev->config.r600.max_gprs = 256;
1521 rdev->config.r600.max_threads = 192;
1522 rdev->config.r600.max_stack_entries = 256;
1523 rdev->config.r600.max_hw_contexts = 8;
1524 rdev->config.r600.max_gs_threads = 16;
1525 rdev->config.r600.sx_max_export_size = 128;
1526 rdev->config.r600.sx_max_export_pos_size = 16;
1527 rdev->config.r600.sx_max_export_smx_size = 128;
1528 rdev->config.r600.sq_num_cf_insts = 2;
1532 rdev->config.r600.max_pipes = 2;
1533 rdev->config.r600.max_tile_pipes = 2;
1534 rdev->config.r600.max_simds = 3;
1535 rdev->config.r600.max_backends = 1;
1536 rdev->config.r600.max_gprs = 128;
1537 rdev->config.r600.max_threads = 192;
1538 rdev->config.r600.max_stack_entries = 128;
1539 rdev->config.r600.max_hw_contexts = 8;
1540 rdev->config.r600.max_gs_threads = 4;
1541 rdev->config.r600.sx_max_export_size = 128;
1542 rdev->config.r600.sx_max_export_pos_size = 16;
1543 rdev->config.r600.sx_max_export_smx_size = 128;
1544 rdev->config.r600.sq_num_cf_insts = 2;
1550 rdev->config.r600.max_pipes = 1;
1551 rdev->config.r600.max_tile_pipes = 1;
1552 rdev->config.r600.max_simds = 2;
1553 rdev->config.r600.max_backends = 1;
1554 rdev->config.r600.max_gprs = 128;
1555 rdev->config.r600.max_threads = 192;
1556 rdev->config.r600.max_stack_entries = 128;
1557 rdev->config.r600.max_hw_contexts = 4;
1558 rdev->config.r600.max_gs_threads = 4;
1559 rdev->config.r600.sx_max_export_size = 128;
1560 rdev->config.r600.sx_max_export_pos_size = 16;
1561 rdev->config.r600.sx_max_export_smx_size = 128;
1562 rdev->config.r600.sq_num_cf_insts = 1;
1565 rdev->config.r600.max_pipes = 4;
1566 rdev->config.r600.max_tile_pipes = 4;
1567 rdev->config.r600.max_simds = 4;
1568 rdev->config.r600.max_backends = 4;
1569 rdev->config.r600.max_gprs = 192;
1570 rdev->config.r600.max_threads = 192;
1571 rdev->config.r600.max_stack_entries = 256;
1572 rdev->config.r600.max_hw_contexts = 8;
1573 rdev->config.r600.max_gs_threads = 16;
1574 rdev->config.r600.sx_max_export_size = 128;
1575 rdev->config.r600.sx_max_export_pos_size = 16;
1576 rdev->config.r600.sx_max_export_smx_size = 128;
1577 rdev->config.r600.sq_num_cf_insts = 2;
1583 /* Initialize HDP */
1584 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1585 WREG32((0x2c14 + j), 0x00000000);
1586 WREG32((0x2c18 + j), 0x00000000);
1587 WREG32((0x2c1c + j), 0x00000000);
1588 WREG32((0x2c20 + j), 0x00000000);
1589 WREG32((0x2c24 + j), 0x00000000);
1592 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1596 ramcfg = RREG32(RAMCFG);
1597 switch (rdev->config.r600.max_tile_pipes) {
1599 tiling_config |= PIPE_TILING(0);
1602 tiling_config |= PIPE_TILING(1);
1605 tiling_config |= PIPE_TILING(2);
1608 tiling_config |= PIPE_TILING(3);
1613 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1614 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1615 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1616 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1617 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1618 rdev->config.r600.tiling_group_size = 512;
1620 rdev->config.r600.tiling_group_size = 256;
1621 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1623 tiling_config |= ROW_TILING(3);
1624 tiling_config |= SAMPLE_SPLIT(3);
1626 tiling_config |= ROW_TILING(tmp);
1627 tiling_config |= SAMPLE_SPLIT(tmp);
1629 tiling_config |= BANK_SWAPS(1);
1631 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1632 cc_rb_backend_disable |=
1633 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1635 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1636 cc_gc_shader_pipe_config |=
1637 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1638 cc_gc_shader_pipe_config |=
1639 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1641 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1642 (R6XX_MAX_BACKENDS -
1643 r600_count_pipe_bits((cc_rb_backend_disable &
1644 R6XX_MAX_BACKENDS_MASK) >> 16)),
1645 (cc_rb_backend_disable >> 16));
1646 rdev->config.r600.tile_config = tiling_config;
1647 tiling_config |= BACKEND_MAP(backend_map);
1648 WREG32(GB_TILING_CONFIG, tiling_config);
1649 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1650 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1653 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1654 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1655 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1657 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1658 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1659 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1661 /* Setup some CP states */
1662 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1663 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1665 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1666 SYNC_WALKER | SYNC_ALIGNER));
1667 /* Setup various GPU states */
1668 if (rdev->family == CHIP_RV670)
1669 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1671 tmp = RREG32(SX_DEBUG_1);
1672 tmp |= SMX_EVENT_RELEASE;
1673 if ((rdev->family > CHIP_R600))
1674 tmp |= ENABLE_NEW_SMX_ADDRESS;
1675 WREG32(SX_DEBUG_1, tmp);
1677 if (((rdev->family) == CHIP_R600) ||
1678 ((rdev->family) == CHIP_RV630) ||
1679 ((rdev->family) == CHIP_RV610) ||
1680 ((rdev->family) == CHIP_RV620) ||
1681 ((rdev->family) == CHIP_RS780) ||
1682 ((rdev->family) == CHIP_RS880)) {
1683 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1685 WREG32(DB_DEBUG, 0);
1687 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1688 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1690 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1691 WREG32(VGT_NUM_INSTANCES, 0);
1693 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1694 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1696 tmp = RREG32(SQ_MS_FIFO_SIZES);
1697 if (((rdev->family) == CHIP_RV610) ||
1698 ((rdev->family) == CHIP_RV620) ||
1699 ((rdev->family) == CHIP_RS780) ||
1700 ((rdev->family) == CHIP_RS880)) {
1701 tmp = (CACHE_FIFO_SIZE(0xa) |
1702 FETCH_FIFO_HIWATER(0xa) |
1703 DONE_FIFO_HIWATER(0xe0) |
1704 ALU_UPDATE_FIFO_HIWATER(0x8));
1705 } else if (((rdev->family) == CHIP_R600) ||
1706 ((rdev->family) == CHIP_RV630)) {
1707 tmp &= ~DONE_FIFO_HIWATER(0xff);
1708 tmp |= DONE_FIFO_HIWATER(0x4);
1710 WREG32(SQ_MS_FIFO_SIZES, tmp);
1712 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1713 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1715 sq_config = RREG32(SQ_CONFIG);
1716 sq_config &= ~(PS_PRIO(3) |
1720 sq_config |= (DX9_CONSTS |
1727 if ((rdev->family) == CHIP_R600) {
1728 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1730 NUM_CLAUSE_TEMP_GPRS(4));
1731 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1733 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1734 NUM_VS_THREADS(48) |
1737 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1738 NUM_VS_STACK_ENTRIES(128));
1739 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1740 NUM_ES_STACK_ENTRIES(0));
1741 } else if (((rdev->family) == CHIP_RV610) ||
1742 ((rdev->family) == CHIP_RV620) ||
1743 ((rdev->family) == CHIP_RS780) ||
1744 ((rdev->family) == CHIP_RS880)) {
1745 /* no vertex cache */
1746 sq_config &= ~VC_ENABLE;
1748 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1750 NUM_CLAUSE_TEMP_GPRS(2));
1751 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1753 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1754 NUM_VS_THREADS(78) |
1756 NUM_ES_THREADS(31));
1757 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1758 NUM_VS_STACK_ENTRIES(40));
1759 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1760 NUM_ES_STACK_ENTRIES(16));
1761 } else if (((rdev->family) == CHIP_RV630) ||
1762 ((rdev->family) == CHIP_RV635)) {
1763 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1765 NUM_CLAUSE_TEMP_GPRS(2));
1766 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1768 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1769 NUM_VS_THREADS(78) |
1771 NUM_ES_THREADS(31));
1772 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1773 NUM_VS_STACK_ENTRIES(40));
1774 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1775 NUM_ES_STACK_ENTRIES(16));
1776 } else if ((rdev->family) == CHIP_RV670) {
1777 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1779 NUM_CLAUSE_TEMP_GPRS(2));
1780 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1782 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1783 NUM_VS_THREADS(78) |
1785 NUM_ES_THREADS(31));
1786 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1787 NUM_VS_STACK_ENTRIES(64));
1788 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1789 NUM_ES_STACK_ENTRIES(64));
1792 WREG32(SQ_CONFIG, sq_config);
1793 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1794 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1795 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1796 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1797 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1799 if (((rdev->family) == CHIP_RV610) ||
1800 ((rdev->family) == CHIP_RV620) ||
1801 ((rdev->family) == CHIP_RS780) ||
1802 ((rdev->family) == CHIP_RS880)) {
1803 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1805 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1808 /* More default values. 2D/3D driver should adjust as needed */
1809 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1810 S1_X(0x4) | S1_Y(0xc)));
1811 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1812 S1_X(0x2) | S1_Y(0x2) |
1813 S2_X(0xa) | S2_Y(0x6) |
1814 S3_X(0x6) | S3_Y(0xa)));
1815 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1816 S1_X(0x4) | S1_Y(0xc) |
1817 S2_X(0x1) | S2_Y(0x6) |
1818 S3_X(0xa) | S3_Y(0xe)));
1819 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1820 S5_X(0x0) | S5_Y(0x0) |
1821 S6_X(0xb) | S6_Y(0x4) |
1822 S7_X(0x7) | S7_Y(0x8)));
1824 WREG32(VGT_STRMOUT_EN, 0);
1825 tmp = rdev->config.r600.max_pipes * 16;
1826 switch (rdev->family) {
1842 WREG32(VGT_ES_PER_GS, 128);
1843 WREG32(VGT_GS_PER_ES, tmp);
1844 WREG32(VGT_GS_PER_VS, 2);
1845 WREG32(VGT_GS_VERTEX_REUSE, 16);
1847 /* more default values. 2D/3D driver should adjust as needed */
1848 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1849 WREG32(VGT_STRMOUT_EN, 0);
1851 WREG32(PA_SC_MODE_CNTL, 0);
1852 WREG32(PA_SC_AA_CONFIG, 0);
1853 WREG32(PA_SC_LINE_STIPPLE, 0);
1854 WREG32(SPI_INPUT_Z, 0);
1855 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1856 WREG32(CB_COLOR7_FRAG, 0);
1858 /* Clear render buffer base addresses */
1859 WREG32(CB_COLOR0_BASE, 0);
1860 WREG32(CB_COLOR1_BASE, 0);
1861 WREG32(CB_COLOR2_BASE, 0);
1862 WREG32(CB_COLOR3_BASE, 0);
1863 WREG32(CB_COLOR4_BASE, 0);
1864 WREG32(CB_COLOR5_BASE, 0);
1865 WREG32(CB_COLOR6_BASE, 0);
1866 WREG32(CB_COLOR7_BASE, 0);
1867 WREG32(CB_COLOR7_FRAG, 0);
1869 switch (rdev->family) {
1874 tmp = TC_L2_SIZE(8);
1878 tmp = TC_L2_SIZE(4);
1881 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1884 tmp = TC_L2_SIZE(0);
1887 WREG32(TC_CNTL, tmp);
1889 tmp = RREG32(HDP_HOST_PATH_CNTL);
1890 WREG32(HDP_HOST_PATH_CNTL, tmp);
1892 tmp = RREG32(ARB_POP);
1893 tmp |= ENABLE_TC128;
1894 WREG32(ARB_POP, tmp);
1896 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1897 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1899 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1904 * Indirect registers accessor
1906 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1910 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1911 (void)RREG32(PCIE_PORT_INDEX);
1912 r = RREG32(PCIE_PORT_DATA);
1916 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1918 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1919 (void)RREG32(PCIE_PORT_INDEX);
1920 WREG32(PCIE_PORT_DATA, (v));
1921 (void)RREG32(PCIE_PORT_DATA);
1927 void r600_cp_stop(struct radeon_device *rdev)
1929 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1930 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1931 WREG32(SCRATCH_UMSK, 0);
1934 int r600_init_microcode(struct radeon_device *rdev)
1936 struct platform_device *pdev;
1937 const char *chip_name;
1938 const char *rlc_chip_name;
1939 size_t pfp_req_size, me_req_size, rlc_req_size;
1945 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1948 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1952 switch (rdev->family) {
1955 rlc_chip_name = "R600";
1958 chip_name = "RV610";
1959 rlc_chip_name = "R600";
1962 chip_name = "RV630";
1963 rlc_chip_name = "R600";
1966 chip_name = "RV620";
1967 rlc_chip_name = "R600";
1970 chip_name = "RV635";
1971 rlc_chip_name = "R600";
1974 chip_name = "RV670";
1975 rlc_chip_name = "R600";
1979 chip_name = "RS780";
1980 rlc_chip_name = "R600";
1983 chip_name = "RV770";
1984 rlc_chip_name = "R700";
1988 chip_name = "RV730";
1989 rlc_chip_name = "R700";
1992 chip_name = "RV710";
1993 rlc_chip_name = "R700";
1996 chip_name = "CEDAR";
1997 rlc_chip_name = "CEDAR";
2000 chip_name = "REDWOOD";
2001 rlc_chip_name = "REDWOOD";
2004 chip_name = "JUNIPER";
2005 rlc_chip_name = "JUNIPER";
2009 chip_name = "CYPRESS";
2010 rlc_chip_name = "CYPRESS";
2015 if (rdev->family >= CHIP_CEDAR) {
2016 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2017 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2018 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2019 } else if (rdev->family >= CHIP_RV770) {
2020 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2021 me_req_size = R700_PM4_UCODE_SIZE * 4;
2022 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2024 pfp_req_size = PFP_UCODE_SIZE * 4;
2025 me_req_size = PM4_UCODE_SIZE * 12;
2026 rlc_req_size = RLC_UCODE_SIZE * 4;
2029 DRM_INFO("Loading %s Microcode\n", chip_name);
2031 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2032 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2035 if (rdev->pfp_fw->size != pfp_req_size) {
2037 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2038 rdev->pfp_fw->size, fw_name);
2043 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2044 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2047 if (rdev->me_fw->size != me_req_size) {
2049 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2050 rdev->me_fw->size, fw_name);
2054 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2055 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2058 if (rdev->rlc_fw->size != rlc_req_size) {
2060 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2061 rdev->rlc_fw->size, fw_name);
2066 platform_device_unregister(pdev);
2071 "r600_cp: Failed to load firmware \"%s\"\n",
2073 release_firmware(rdev->pfp_fw);
2074 rdev->pfp_fw = NULL;
2075 release_firmware(rdev->me_fw);
2077 release_firmware(rdev->rlc_fw);
2078 rdev->rlc_fw = NULL;
2083 static int r600_cp_load_microcode(struct radeon_device *rdev)
2085 const __be32 *fw_data;
2088 if (!rdev->me_fw || !rdev->pfp_fw)
2093 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2096 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2097 RREG32(GRBM_SOFT_RESET);
2099 WREG32(GRBM_SOFT_RESET, 0);
2101 WREG32(CP_ME_RAM_WADDR, 0);
2103 fw_data = (const __be32 *)rdev->me_fw->data;
2104 WREG32(CP_ME_RAM_WADDR, 0);
2105 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2106 WREG32(CP_ME_RAM_DATA,
2107 be32_to_cpup(fw_data++));
2109 fw_data = (const __be32 *)rdev->pfp_fw->data;
2110 WREG32(CP_PFP_UCODE_ADDR, 0);
2111 for (i = 0; i < PFP_UCODE_SIZE; i++)
2112 WREG32(CP_PFP_UCODE_DATA,
2113 be32_to_cpup(fw_data++));
2115 WREG32(CP_PFP_UCODE_ADDR, 0);
2116 WREG32(CP_ME_RAM_WADDR, 0);
2117 WREG32(CP_ME_RAM_RADDR, 0);
2121 int r600_cp_start(struct radeon_device *rdev)
2126 r = radeon_ring_lock(rdev, 7);
2128 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2131 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2132 radeon_ring_write(rdev, 0x1);
2133 if (rdev->family >= CHIP_RV770) {
2134 radeon_ring_write(rdev, 0x0);
2135 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2137 radeon_ring_write(rdev, 0x3);
2138 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2140 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2141 radeon_ring_write(rdev, 0);
2142 radeon_ring_write(rdev, 0);
2143 radeon_ring_unlock_commit(rdev);
2146 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2150 int r600_cp_resume(struct radeon_device *rdev)
2157 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2158 RREG32(GRBM_SOFT_RESET);
2160 WREG32(GRBM_SOFT_RESET, 0);
2162 /* Set ring buffer size */
2163 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2164 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2166 tmp |= BUF_SWAP_32BIT;
2168 WREG32(CP_RB_CNTL, tmp);
2169 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2171 /* Set the write pointer delay */
2172 WREG32(CP_RB_WPTR_DELAY, 0);
2174 /* Initialize the ring buffer's read and write pointers */
2175 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2176 WREG32(CP_RB_RPTR_WR, 0);
2177 WREG32(CP_RB_WPTR, 0);
2179 /* set the wb address whether it's enabled or not */
2180 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2181 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2182 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2184 if (rdev->wb.enabled)
2185 WREG32(SCRATCH_UMSK, 0xff);
2187 tmp |= RB_NO_UPDATE;
2188 WREG32(SCRATCH_UMSK, 0);
2192 WREG32(CP_RB_CNTL, tmp);
2194 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2195 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2197 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2198 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2200 r600_cp_start(rdev);
2201 rdev->cp.ready = true;
2202 r = radeon_ring_test(rdev);
2204 rdev->cp.ready = false;
2210 void r600_cp_commit(struct radeon_device *rdev)
2212 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2213 (void)RREG32(CP_RB_WPTR);
2216 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2220 /* Align ring size */
2221 rb_bufsz = drm_order(ring_size / 8);
2222 ring_size = (1 << (rb_bufsz + 1)) * 4;
2223 rdev->cp.ring_size = ring_size;
2224 rdev->cp.align_mask = 16 - 1;
2227 void r600_cp_fini(struct radeon_device *rdev)
2230 radeon_ring_fini(rdev);
2235 * GPU scratch registers helpers function.
2237 void r600_scratch_init(struct radeon_device *rdev)
2241 rdev->scratch.num_reg = 7;
2242 rdev->scratch.reg_base = SCRATCH_REG0;
2243 for (i = 0; i < rdev->scratch.num_reg; i++) {
2244 rdev->scratch.free[i] = true;
2245 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2249 int r600_ring_test(struct radeon_device *rdev)
2256 r = radeon_scratch_get(rdev, &scratch);
2258 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2261 WREG32(scratch, 0xCAFEDEAD);
2262 r = radeon_ring_lock(rdev, 3);
2264 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2265 radeon_scratch_free(rdev, scratch);
2268 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2269 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2270 radeon_ring_write(rdev, 0xDEADBEEF);
2271 radeon_ring_unlock_commit(rdev);
2272 for (i = 0; i < rdev->usec_timeout; i++) {
2273 tmp = RREG32(scratch);
2274 if (tmp == 0xDEADBEEF)
2278 if (i < rdev->usec_timeout) {
2279 DRM_INFO("ring test succeeded in %d usecs\n", i);
2281 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2285 radeon_scratch_free(rdev, scratch);
2289 void r600_fence_ring_emit(struct radeon_device *rdev,
2290 struct radeon_fence *fence)
2292 if (rdev->wb.use_event) {
2293 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2294 (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2295 /* EVENT_WRITE_EOP - flush caches, send int */
2296 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2297 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2298 radeon_ring_write(rdev, addr & 0xffffffff);
2299 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2300 radeon_ring_write(rdev, fence->seq);
2301 radeon_ring_write(rdev, 0);
2303 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2304 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2305 /* wait for 3D idle clean */
2306 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2307 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2308 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2309 /* Emit fence sequence & fire IRQ */
2310 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2311 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2312 radeon_ring_write(rdev, fence->seq);
2313 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2314 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2315 radeon_ring_write(rdev, RB_INT_STAT);
2319 int r600_copy_blit(struct radeon_device *rdev,
2320 uint64_t src_offset, uint64_t dst_offset,
2321 unsigned num_pages, struct radeon_fence *fence)
2325 mutex_lock(&rdev->r600_blit.mutex);
2326 rdev->r600_blit.vb_ib = NULL;
2327 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2329 if (rdev->r600_blit.vb_ib)
2330 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2331 mutex_unlock(&rdev->r600_blit.mutex);
2334 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2335 r600_blit_done_copy(rdev, fence);
2336 mutex_unlock(&rdev->r600_blit.mutex);
2340 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2341 uint32_t tiling_flags, uint32_t pitch,
2342 uint32_t offset, uint32_t obj_size)
2344 /* FIXME: implement */
2348 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2350 /* FIXME: implement */
2354 bool r600_card_posted(struct radeon_device *rdev)
2358 /* first check CRTCs */
2359 reg = RREG32(D1CRTC_CONTROL) |
2360 RREG32(D2CRTC_CONTROL);
2364 /* then check MEM_SIZE, in case the crtcs are off */
2365 if (RREG32(CONFIG_MEMSIZE))
2371 int r600_startup(struct radeon_device *rdev)
2375 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2376 r = r600_init_microcode(rdev);
2378 DRM_ERROR("Failed to load firmware!\n");
2383 r600_mc_program(rdev);
2384 if (rdev->flags & RADEON_IS_AGP) {
2385 r600_agp_enable(rdev);
2387 r = r600_pcie_gart_enable(rdev);
2391 r600_gpu_init(rdev);
2392 r = r600_blit_init(rdev);
2394 r600_blit_fini(rdev);
2395 rdev->asic->copy = NULL;
2396 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2399 /* allocate wb buffer */
2400 r = radeon_wb_init(rdev);
2405 r = r600_irq_init(rdev);
2407 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2408 radeon_irq_kms_fini(rdev);
2413 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2416 r = r600_cp_load_microcode(rdev);
2419 r = r600_cp_resume(rdev);
2426 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2430 temp = RREG32(CONFIG_CNTL);
2431 if (state == false) {
2437 WREG32(CONFIG_CNTL, temp);
2440 int r600_resume(struct radeon_device *rdev)
2444 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2445 * posting will perform necessary task to bring back GPU into good
2449 atom_asic_init(rdev->mode_info.atom_context);
2451 r = r600_startup(rdev);
2453 DRM_ERROR("r600 startup failed on resume\n");
2457 r = r600_ib_test(rdev);
2459 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2463 r = r600_audio_init(rdev);
2465 DRM_ERROR("radeon: audio resume failed\n");
2472 int r600_suspend(struct radeon_device *rdev)
2476 r600_audio_fini(rdev);
2477 /* FIXME: we should wait for ring to be empty */
2479 rdev->cp.ready = false;
2480 r600_irq_suspend(rdev);
2481 radeon_wb_disable(rdev);
2482 r600_pcie_gart_disable(rdev);
2483 /* unpin shaders bo */
2484 if (rdev->r600_blit.shader_obj) {
2485 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2487 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2488 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2494 /* Plan is to move initialization in that function and use
2495 * helper function so that radeon_device_init pretty much
2496 * do nothing more than calling asic specific function. This
2497 * should also allow to remove a bunch of callback function
2500 int r600_init(struct radeon_device *rdev)
2504 r = radeon_dummy_page_init(rdev);
2507 if (r600_debugfs_mc_info_init(rdev)) {
2508 DRM_ERROR("Failed to register debugfs file for mc !\n");
2510 /* This don't do much */
2511 r = radeon_gem_init(rdev);
2515 if (!radeon_get_bios(rdev)) {
2516 if (ASIC_IS_AVIVO(rdev))
2519 /* Must be an ATOMBIOS */
2520 if (!rdev->is_atom_bios) {
2521 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2524 r = radeon_atombios_init(rdev);
2527 /* Post card if necessary */
2528 if (!r600_card_posted(rdev)) {
2530 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2533 DRM_INFO("GPU not posted. posting now...\n");
2534 atom_asic_init(rdev->mode_info.atom_context);
2536 /* Initialize scratch registers */
2537 r600_scratch_init(rdev);
2538 /* Initialize surface registers */
2539 radeon_surface_init(rdev);
2540 /* Initialize clocks */
2541 radeon_get_clock_info(rdev->ddev);
2543 r = radeon_fence_driver_init(rdev);
2546 if (rdev->flags & RADEON_IS_AGP) {
2547 r = radeon_agp_init(rdev);
2549 radeon_agp_disable(rdev);
2551 r = r600_mc_init(rdev);
2554 /* Memory manager */
2555 r = radeon_bo_init(rdev);
2559 r = radeon_irq_kms_init(rdev);
2563 rdev->cp.ring_obj = NULL;
2564 r600_ring_init(rdev, 1024 * 1024);
2566 rdev->ih.ring_obj = NULL;
2567 r600_ih_ring_init(rdev, 64 * 1024);
2569 r = r600_pcie_gart_init(rdev);
2573 rdev->accel_working = true;
2574 r = r600_startup(rdev);
2576 dev_err(rdev->dev, "disabling GPU acceleration\n");
2578 r600_irq_fini(rdev);
2579 radeon_wb_fini(rdev);
2580 radeon_irq_kms_fini(rdev);
2581 r600_pcie_gart_fini(rdev);
2582 rdev->accel_working = false;
2584 if (rdev->accel_working) {
2585 r = radeon_ib_pool_init(rdev);
2587 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2588 rdev->accel_working = false;
2590 r = r600_ib_test(rdev);
2592 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2593 rdev->accel_working = false;
2598 r = r600_audio_init(rdev);
2600 return r; /* TODO error handling */
2604 void r600_fini(struct radeon_device *rdev)
2606 r600_audio_fini(rdev);
2607 r600_blit_fini(rdev);
2609 r600_irq_fini(rdev);
2610 radeon_wb_fini(rdev);
2611 radeon_irq_kms_fini(rdev);
2612 r600_pcie_gart_fini(rdev);
2613 radeon_agp_fini(rdev);
2614 radeon_gem_fini(rdev);
2615 radeon_fence_driver_fini(rdev);
2616 radeon_bo_fini(rdev);
2617 radeon_atombios_fini(rdev);
2620 radeon_dummy_page_fini(rdev);
2627 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2629 /* FIXME: implement */
2630 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2631 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2632 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2633 radeon_ring_write(rdev, ib->length_dw);
2636 int r600_ib_test(struct radeon_device *rdev)
2638 struct radeon_ib *ib;
2644 r = radeon_scratch_get(rdev, &scratch);
2646 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2649 WREG32(scratch, 0xCAFEDEAD);
2650 r = radeon_ib_get(rdev, &ib);
2652 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2655 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2656 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2657 ib->ptr[2] = 0xDEADBEEF;
2658 ib->ptr[3] = PACKET2(0);
2659 ib->ptr[4] = PACKET2(0);
2660 ib->ptr[5] = PACKET2(0);
2661 ib->ptr[6] = PACKET2(0);
2662 ib->ptr[7] = PACKET2(0);
2663 ib->ptr[8] = PACKET2(0);
2664 ib->ptr[9] = PACKET2(0);
2665 ib->ptr[10] = PACKET2(0);
2666 ib->ptr[11] = PACKET2(0);
2667 ib->ptr[12] = PACKET2(0);
2668 ib->ptr[13] = PACKET2(0);
2669 ib->ptr[14] = PACKET2(0);
2670 ib->ptr[15] = PACKET2(0);
2672 r = radeon_ib_schedule(rdev, ib);
2674 radeon_scratch_free(rdev, scratch);
2675 radeon_ib_free(rdev, &ib);
2676 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2679 r = radeon_fence_wait(ib->fence, false);
2681 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2684 for (i = 0; i < rdev->usec_timeout; i++) {
2685 tmp = RREG32(scratch);
2686 if (tmp == 0xDEADBEEF)
2690 if (i < rdev->usec_timeout) {
2691 DRM_INFO("ib test succeeded in %u usecs\n", i);
2693 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2697 radeon_scratch_free(rdev, scratch);
2698 radeon_ib_free(rdev, &ib);
2705 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2706 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2707 * writing to the ring and the GPU consuming, the GPU writes to the ring
2708 * and host consumes. As the host irq handler processes interrupts, it
2709 * increments the rptr. When the rptr catches up with the wptr, all the
2710 * current interrupts have been processed.
2713 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2717 /* Align ring size */
2718 rb_bufsz = drm_order(ring_size / 4);
2719 ring_size = (1 << rb_bufsz) * 4;
2720 rdev->ih.ring_size = ring_size;
2721 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2725 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2729 /* Allocate ring buffer */
2730 if (rdev->ih.ring_obj == NULL) {
2731 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2733 RADEON_GEM_DOMAIN_GTT,
2734 &rdev->ih.ring_obj);
2736 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2739 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2740 if (unlikely(r != 0))
2742 r = radeon_bo_pin(rdev->ih.ring_obj,
2743 RADEON_GEM_DOMAIN_GTT,
2744 &rdev->ih.gpu_addr);
2746 radeon_bo_unreserve(rdev->ih.ring_obj);
2747 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2750 r = radeon_bo_kmap(rdev->ih.ring_obj,
2751 (void **)&rdev->ih.ring);
2752 radeon_bo_unreserve(rdev->ih.ring_obj);
2754 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2761 static void r600_ih_ring_fini(struct radeon_device *rdev)
2764 if (rdev->ih.ring_obj) {
2765 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2766 if (likely(r == 0)) {
2767 radeon_bo_kunmap(rdev->ih.ring_obj);
2768 radeon_bo_unpin(rdev->ih.ring_obj);
2769 radeon_bo_unreserve(rdev->ih.ring_obj);
2771 radeon_bo_unref(&rdev->ih.ring_obj);
2772 rdev->ih.ring = NULL;
2773 rdev->ih.ring_obj = NULL;
2777 void r600_rlc_stop(struct radeon_device *rdev)
2780 if ((rdev->family >= CHIP_RV770) &&
2781 (rdev->family <= CHIP_RV740)) {
2782 /* r7xx asics need to soft reset RLC before halting */
2783 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2784 RREG32(SRBM_SOFT_RESET);
2786 WREG32(SRBM_SOFT_RESET, 0);
2787 RREG32(SRBM_SOFT_RESET);
2790 WREG32(RLC_CNTL, 0);
2793 static void r600_rlc_start(struct radeon_device *rdev)
2795 WREG32(RLC_CNTL, RLC_ENABLE);
2798 static int r600_rlc_init(struct radeon_device *rdev)
2801 const __be32 *fw_data;
2806 r600_rlc_stop(rdev);
2808 WREG32(RLC_HB_BASE, 0);
2809 WREG32(RLC_HB_CNTL, 0);
2810 WREG32(RLC_HB_RPTR, 0);
2811 WREG32(RLC_HB_WPTR, 0);
2812 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2813 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2814 WREG32(RLC_MC_CNTL, 0);
2815 WREG32(RLC_UCODE_CNTL, 0);
2817 fw_data = (const __be32 *)rdev->rlc_fw->data;
2818 if (rdev->family >= CHIP_CEDAR) {
2819 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2820 WREG32(RLC_UCODE_ADDR, i);
2821 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2823 } else if (rdev->family >= CHIP_RV770) {
2824 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2825 WREG32(RLC_UCODE_ADDR, i);
2826 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2829 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2830 WREG32(RLC_UCODE_ADDR, i);
2831 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2834 WREG32(RLC_UCODE_ADDR, 0);
2836 r600_rlc_start(rdev);
2841 static void r600_enable_interrupts(struct radeon_device *rdev)
2843 u32 ih_cntl = RREG32(IH_CNTL);
2844 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2846 ih_cntl |= ENABLE_INTR;
2847 ih_rb_cntl |= IH_RB_ENABLE;
2848 WREG32(IH_CNTL, ih_cntl);
2849 WREG32(IH_RB_CNTL, ih_rb_cntl);
2850 rdev->ih.enabled = true;
2853 void r600_disable_interrupts(struct radeon_device *rdev)
2855 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2856 u32 ih_cntl = RREG32(IH_CNTL);
2858 ih_rb_cntl &= ~IH_RB_ENABLE;
2859 ih_cntl &= ~ENABLE_INTR;
2860 WREG32(IH_RB_CNTL, ih_rb_cntl);
2861 WREG32(IH_CNTL, ih_cntl);
2862 /* set rptr, wptr to 0 */
2863 WREG32(IH_RB_RPTR, 0);
2864 WREG32(IH_RB_WPTR, 0);
2865 rdev->ih.enabled = false;
2870 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2874 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2875 WREG32(GRBM_INT_CNTL, 0);
2876 WREG32(DxMODE_INT_MASK, 0);
2877 if (ASIC_IS_DCE3(rdev)) {
2878 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2879 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2880 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2881 WREG32(DC_HPD1_INT_CONTROL, tmp);
2882 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2883 WREG32(DC_HPD2_INT_CONTROL, tmp);
2884 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2885 WREG32(DC_HPD3_INT_CONTROL, tmp);
2886 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2887 WREG32(DC_HPD4_INT_CONTROL, tmp);
2888 if (ASIC_IS_DCE32(rdev)) {
2889 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2890 WREG32(DC_HPD5_INT_CONTROL, tmp);
2891 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2892 WREG32(DC_HPD6_INT_CONTROL, tmp);
2895 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2896 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2897 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2898 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2899 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2900 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2901 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2902 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2906 int r600_irq_init(struct radeon_device *rdev)
2910 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2913 ret = r600_ih_ring_alloc(rdev);
2918 r600_disable_interrupts(rdev);
2921 ret = r600_rlc_init(rdev);
2923 r600_ih_ring_fini(rdev);
2927 /* setup interrupt control */
2928 /* set dummy read address to ring address */
2929 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2930 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2931 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2932 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2934 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2935 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2936 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2937 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2939 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2940 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2942 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2943 IH_WPTR_OVERFLOW_CLEAR |
2946 if (rdev->wb.enabled)
2947 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2949 /* set the writeback address whether it's enabled or not */
2950 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2951 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2953 WREG32(IH_RB_CNTL, ih_rb_cntl);
2955 /* set rptr, wptr to 0 */
2956 WREG32(IH_RB_RPTR, 0);
2957 WREG32(IH_RB_WPTR, 0);
2959 /* Default settings for IH_CNTL (disabled at first) */
2960 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2961 /* RPTR_REARM only works if msi's are enabled */
2962 if (rdev->msi_enabled)
2963 ih_cntl |= RPTR_REARM;
2966 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2968 WREG32(IH_CNTL, ih_cntl);
2970 /* force the active interrupt state to all disabled */
2971 if (rdev->family >= CHIP_CEDAR)
2972 evergreen_disable_interrupt_state(rdev);
2974 r600_disable_interrupt_state(rdev);
2977 r600_enable_interrupts(rdev);
2982 void r600_irq_suspend(struct radeon_device *rdev)
2984 r600_irq_disable(rdev);
2985 r600_rlc_stop(rdev);
2988 void r600_irq_fini(struct radeon_device *rdev)
2990 r600_irq_suspend(rdev);
2991 r600_ih_ring_fini(rdev);
2994 int r600_irq_set(struct radeon_device *rdev)
2996 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2998 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2999 u32 grbm_int_cntl = 0;
3002 if (!rdev->irq.installed) {
3003 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3006 /* don't enable anything if the ih is disabled */
3007 if (!rdev->ih.enabled) {
3008 r600_disable_interrupts(rdev);
3009 /* force the active interrupt state to all disabled */
3010 r600_disable_interrupt_state(rdev);
3014 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3015 if (ASIC_IS_DCE3(rdev)) {
3016 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3017 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3018 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3019 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3020 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3021 if (ASIC_IS_DCE32(rdev)) {
3022 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3023 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3026 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3027 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3028 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3029 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3032 if (rdev->irq.sw_int) {
3033 DRM_DEBUG("r600_irq_set: sw int\n");
3034 cp_int_cntl |= RB_INT_ENABLE;
3035 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3037 if (rdev->irq.crtc_vblank_int[0]) {
3038 DRM_DEBUG("r600_irq_set: vblank 0\n");
3039 mode_int |= D1MODE_VBLANK_INT_MASK;
3041 if (rdev->irq.crtc_vblank_int[1]) {
3042 DRM_DEBUG("r600_irq_set: vblank 1\n");
3043 mode_int |= D2MODE_VBLANK_INT_MASK;
3045 if (rdev->irq.hpd[0]) {
3046 DRM_DEBUG("r600_irq_set: hpd 1\n");
3047 hpd1 |= DC_HPDx_INT_EN;
3049 if (rdev->irq.hpd[1]) {
3050 DRM_DEBUG("r600_irq_set: hpd 2\n");
3051 hpd2 |= DC_HPDx_INT_EN;
3053 if (rdev->irq.hpd[2]) {
3054 DRM_DEBUG("r600_irq_set: hpd 3\n");
3055 hpd3 |= DC_HPDx_INT_EN;
3057 if (rdev->irq.hpd[3]) {
3058 DRM_DEBUG("r600_irq_set: hpd 4\n");
3059 hpd4 |= DC_HPDx_INT_EN;
3061 if (rdev->irq.hpd[4]) {
3062 DRM_DEBUG("r600_irq_set: hpd 5\n");
3063 hpd5 |= DC_HPDx_INT_EN;
3065 if (rdev->irq.hpd[5]) {
3066 DRM_DEBUG("r600_irq_set: hpd 6\n");
3067 hpd6 |= DC_HPDx_INT_EN;
3069 if (rdev->irq.hdmi[0]) {
3070 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3071 hdmi1 |= R600_HDMI_INT_EN;
3073 if (rdev->irq.hdmi[1]) {
3074 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3075 hdmi2 |= R600_HDMI_INT_EN;
3077 if (rdev->irq.gui_idle) {
3078 DRM_DEBUG("gui idle\n");
3079 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3082 WREG32(CP_INT_CNTL, cp_int_cntl);
3083 WREG32(DxMODE_INT_MASK, mode_int);
3084 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3085 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3086 if (ASIC_IS_DCE3(rdev)) {
3087 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3088 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3089 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3090 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3091 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3092 if (ASIC_IS_DCE32(rdev)) {
3093 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3094 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3097 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3098 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3099 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3100 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3106 static inline void r600_irq_ack(struct radeon_device *rdev,
3109 u32 *disp_int_cont2)
3113 if (ASIC_IS_DCE3(rdev)) {
3114 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3115 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3116 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3118 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3119 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3120 *disp_int_cont2 = 0;
3123 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
3124 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3125 if (*disp_int & LB_D1_VLINE_INTERRUPT)
3126 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3127 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
3128 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3129 if (*disp_int & LB_D2_VLINE_INTERRUPT)
3130 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3131 if (*disp_int & DC_HPD1_INTERRUPT) {
3132 if (ASIC_IS_DCE3(rdev)) {
3133 tmp = RREG32(DC_HPD1_INT_CONTROL);
3134 tmp |= DC_HPDx_INT_ACK;
3135 WREG32(DC_HPD1_INT_CONTROL, tmp);
3137 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3138 tmp |= DC_HPDx_INT_ACK;
3139 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3142 if (*disp_int & DC_HPD2_INTERRUPT) {
3143 if (ASIC_IS_DCE3(rdev)) {
3144 tmp = RREG32(DC_HPD2_INT_CONTROL);
3145 tmp |= DC_HPDx_INT_ACK;
3146 WREG32(DC_HPD2_INT_CONTROL, tmp);
3148 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3149 tmp |= DC_HPDx_INT_ACK;
3150 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3153 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3154 if (ASIC_IS_DCE3(rdev)) {
3155 tmp = RREG32(DC_HPD3_INT_CONTROL);
3156 tmp |= DC_HPDx_INT_ACK;
3157 WREG32(DC_HPD3_INT_CONTROL, tmp);
3159 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3160 tmp |= DC_HPDx_INT_ACK;
3161 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3164 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3165 tmp = RREG32(DC_HPD4_INT_CONTROL);
3166 tmp |= DC_HPDx_INT_ACK;
3167 WREG32(DC_HPD4_INT_CONTROL, tmp);
3169 if (ASIC_IS_DCE32(rdev)) {
3170 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3171 tmp = RREG32(DC_HPD5_INT_CONTROL);
3172 tmp |= DC_HPDx_INT_ACK;
3173 WREG32(DC_HPD5_INT_CONTROL, tmp);
3175 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3176 tmp = RREG32(DC_HPD5_INT_CONTROL);
3177 tmp |= DC_HPDx_INT_ACK;
3178 WREG32(DC_HPD6_INT_CONTROL, tmp);
3181 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3182 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3184 if (ASIC_IS_DCE3(rdev)) {
3185 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3186 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3189 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3190 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3195 void r600_irq_disable(struct radeon_device *rdev)
3197 u32 disp_int, disp_int_cont, disp_int_cont2;
3199 r600_disable_interrupts(rdev);
3200 /* Wait and acknowledge irq */
3202 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3203 r600_disable_interrupt_state(rdev);
3206 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3210 if (rdev->wb.enabled)
3211 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3213 wptr = RREG32(IH_RB_WPTR);
3215 if (wptr & RB_OVERFLOW) {
3216 /* When a ring buffer overflow happen start parsing interrupt
3217 * from the last not overwritten vector (wptr + 16). Hopefully
3218 * this should allow us to catchup.
3220 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3221 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3222 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3223 tmp = RREG32(IH_RB_CNTL);
3224 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3225 WREG32(IH_RB_CNTL, tmp);
3227 return (wptr & rdev->ih.ptr_mask);
3231 * Each IV ring entry is 128 bits:
3232 * [7:0] - interrupt source id
3234 * [59:32] - interrupt source data
3235 * [127:60] - reserved
3237 * The basic interrupt vector entries
3238 * are decoded as follows:
3239 * src_id src_data description
3244 * 19 0 FP Hot plug detection A
3245 * 19 1 FP Hot plug detection B
3246 * 19 2 DAC A auto-detection
3247 * 19 3 DAC B auto-detection
3253 * 181 - EOP Interrupt
3256 * Note, these are based on r600 and may need to be
3257 * adjusted or added to on newer asics
3260 int r600_irq_process(struct radeon_device *rdev)
3262 u32 wptr = r600_get_ih_wptr(rdev);
3263 u32 rptr = rdev->ih.rptr;
3264 u32 src_id, src_data;
3265 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3266 unsigned long flags;
3267 bool queue_hotplug = false;
3269 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3270 if (!rdev->ih.enabled)
3273 spin_lock_irqsave(&rdev->ih.lock, flags);
3276 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3279 if (rdev->shutdown) {
3280 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3285 /* display interrupts */
3286 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3288 rdev->ih.wptr = wptr;
3289 while (rptr != wptr) {
3290 /* wptr/rptr are in bytes! */
3291 ring_index = rptr / 4;
3292 src_id = rdev->ih.ring[ring_index] & 0xff;
3293 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3296 case 1: /* D1 vblank/vline */
3298 case 0: /* D1 vblank */
3299 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3300 drm_handle_vblank(rdev->ddev, 0);
3301 rdev->pm.vblank_sync = true;
3302 wake_up(&rdev->irq.vblank_queue);
3303 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3304 DRM_DEBUG("IH: D1 vblank\n");
3307 case 1: /* D1 vline */
3308 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3309 disp_int &= ~LB_D1_VLINE_INTERRUPT;
3310 DRM_DEBUG("IH: D1 vline\n");
3314 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3318 case 5: /* D2 vblank/vline */
3320 case 0: /* D2 vblank */
3321 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3322 drm_handle_vblank(rdev->ddev, 1);
3323 rdev->pm.vblank_sync = true;
3324 wake_up(&rdev->irq.vblank_queue);
3325 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3326 DRM_DEBUG("IH: D2 vblank\n");
3329 case 1: /* D1 vline */
3330 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3331 disp_int &= ~LB_D2_VLINE_INTERRUPT;
3332 DRM_DEBUG("IH: D2 vline\n");
3336 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3340 case 19: /* HPD/DAC hotplug */
3343 if (disp_int & DC_HPD1_INTERRUPT) {
3344 disp_int &= ~DC_HPD1_INTERRUPT;
3345 queue_hotplug = true;
3346 DRM_DEBUG("IH: HPD1\n");
3350 if (disp_int & DC_HPD2_INTERRUPT) {
3351 disp_int &= ~DC_HPD2_INTERRUPT;
3352 queue_hotplug = true;
3353 DRM_DEBUG("IH: HPD2\n");
3357 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3358 disp_int_cont &= ~DC_HPD3_INTERRUPT;
3359 queue_hotplug = true;
3360 DRM_DEBUG("IH: HPD3\n");
3364 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3365 disp_int_cont &= ~DC_HPD4_INTERRUPT;
3366 queue_hotplug = true;
3367 DRM_DEBUG("IH: HPD4\n");
3371 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3372 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3373 queue_hotplug = true;
3374 DRM_DEBUG("IH: HPD5\n");
3378 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3379 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3380 queue_hotplug = true;
3381 DRM_DEBUG("IH: HPD6\n");
3385 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3390 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3391 r600_audio_schedule_polling(rdev);
3393 case 176: /* CP_INT in ring buffer */
3394 case 177: /* CP_INT in IB1 */
3395 case 178: /* CP_INT in IB2 */
3396 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3397 radeon_fence_process(rdev);
3399 case 181: /* CP EOP event */
3400 DRM_DEBUG("IH: CP EOP\n");
3401 radeon_fence_process(rdev);
3403 case 233: /* GUI IDLE */
3404 DRM_DEBUG("IH: CP EOP\n");
3405 rdev->pm.gui_idle = true;
3406 wake_up(&rdev->irq.idle_queue);
3409 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3413 /* wptr/rptr are in bytes! */
3415 rptr &= rdev->ih.ptr_mask;
3417 /* make sure wptr hasn't changed while processing */
3418 wptr = r600_get_ih_wptr(rdev);
3419 if (wptr != rdev->ih.wptr)
3422 queue_work(rdev->wq, &rdev->hotplug_work);
3423 rdev->ih.rptr = rptr;
3424 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3425 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3432 #if defined(CONFIG_DEBUG_FS)
3434 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3436 struct drm_info_node *node = (struct drm_info_node *) m->private;
3437 struct drm_device *dev = node->minor->dev;
3438 struct radeon_device *rdev = dev->dev_private;
3439 unsigned count, i, j;
3441 radeon_ring_free_size(rdev);
3442 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3443 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3444 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3445 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3446 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3447 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3448 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3449 seq_printf(m, "%u dwords in ring\n", count);
3451 for (j = 0; j <= count; j++) {
3452 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3453 i = (i + 1) & rdev->cp.ptr_mask;
3458 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3460 struct drm_info_node *node = (struct drm_info_node *) m->private;
3461 struct drm_device *dev = node->minor->dev;
3462 struct radeon_device *rdev = dev->dev_private;
3464 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3465 DREG32_SYS(m, rdev, VM_L2_STATUS);
3469 static struct drm_info_list r600_mc_info_list[] = {
3470 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3471 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3475 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3477 #if defined(CONFIG_DEBUG_FS)
3478 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3485 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3486 * rdev: radeon device structure
3487 * bo: buffer object struct which userspace is waiting for idle
3489 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3490 * through ring buffer, this leads to corruption in rendering, see
3491 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3492 * directly perform HDP flush by writing register through MMIO.
3494 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3496 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3497 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3498 * This seems to cause problems on some AGP cards. Just use the old
3501 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3502 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3503 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3506 WREG32(HDP_DEBUG1, 0);
3507 tmp = readl((void __iomem *)ptr);
3509 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);