drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/module.h>
  32 #include <drm/drmP.h>
  33 #include <drm/radeon_drm.h>
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_audio.h"
  37 #include "radeon_mode.h"
  38 #include "r600d.h"
  39 #include "atom.h"
  40 #include "avivod.h"
  41 #include "radeon_ucode.h"
  42
  43 /* Firmware Names */
  44 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  45 MODULE_FIRMWARE("radeon/R600_me.bin");
  46 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  47 MODULE_FIRMWARE("radeon/RV610_me.bin");
  48 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  49 MODULE_FIRMWARE("radeon/RV630_me.bin");
  50 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  51 MODULE_FIRMWARE("radeon/RV620_me.bin");
  52 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  53 MODULE_FIRMWARE("radeon/RV635_me.bin");
  54 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV670_me.bin");
  56 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RS780_me.bin");
  58 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV770_me.bin");
  60 MODULE_FIRMWARE("radeon/RV770_smc.bin");
  61 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV730_me.bin");
  63 MODULE_FIRMWARE("radeon/RV730_smc.bin");
  64 MODULE_FIRMWARE("radeon/RV740_smc.bin");
  65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RV710_me.bin");
  67 MODULE_FIRMWARE("radeon/RV710_smc.bin");
  68 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  69 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  70 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  71 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  72 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  73 MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
  74 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  75 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  76 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
  78 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  79 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
  82 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
  86 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  87 MODULE_FIRMWARE("radeon/PALM_me.bin");
  88 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  89 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  90 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  91 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  92 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  93
  94 static const u32 crtc_offsets[2] =
  95 {
  96         0,
  97         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  98 };
  99
 100 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
 101
 102 /* r600,rv610,rv630,rv620,rv635,rv670 */
 103 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 104 static void r600_gpu_init(struct radeon_device *rdev);
 105 void r600_fini(struct radeon_device *rdev);
 106 void r600_irq_disable(struct radeon_device *rdev);
 107 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 108 extern int evergreen_rlc_resume(struct radeon_device *rdev);
 109 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
 110
 111 /**
 112  * r600_get_xclk - get the xclk
 113  *
 114  * @rdev: radeon_device pointer
 115  *
 116  * Returns the reference clock used by the gfx engine
 117  * (r6xx, IGPs, APUs).
 118  */
 119 u32 r600_get_xclk(struct radeon_device *rdev)
 120 {
 121         return rdev->clock.spll.reference_freq;
 122 }
 123
 124 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
 125 {
 126         unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
 127         int r;
 128
 129         /* bypass vclk and dclk with bclk */
 130         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 131                  VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
 132                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 133
 134         /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */
 135         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
 136                  UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK));
 137
 138         if (rdev->family >= CHIP_RS780)
 139                 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,
 140                          ~UPLL_BYPASS_CNTL);
 141
 142         if (!vclk || !dclk) {
 143                 /* keep the Bypass mode, put PLL to sleep */
 144                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
 145                 return 0;
 146         }
 147
 148         if (rdev->clock.spll.reference_freq == 10000)
 149                 ref_div = 34;
 150         else
 151                 ref_div = 4;
 152
 153         r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
 154                                           ref_div + 1, 0xFFF, 2, 30, ~0,
 155                                           &fb_div, &vclk_div, &dclk_div);
 156         if (r)
 157                 return r;
 158
 159         if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
 160                 fb_div >>= 1;
 161         else
 162                 fb_div |= 1;
 163
 164         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 165         if (r)
 166                 return r;
 167
 168         /* assert PLL_RESET */
 169         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
 170
 171         /* For RS780 we have to choose ref clk */
 172         if (rdev->family >= CHIP_RS780)
 173                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
 174                          ~UPLL_REFCLK_SRC_SEL_MASK);
 175
 176         /* set the required fb, ref and post divder values */
 177         WREG32_P(CG_UPLL_FUNC_CNTL,
 178                  UPLL_FB_DIV(fb_div) |
 179                  UPLL_REF_DIV(ref_div),
 180                  ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK));
 181         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 182                  UPLL_SW_HILEN(vclk_div >> 1) |
 183                  UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
 184                  UPLL_SW_HILEN2(dclk_div >> 1) |
 185                  UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
 186                  UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK,
 187                  ~UPLL_SW_MASK);
 188
 189         /* give the PLL some time to settle */
 190         mdelay(15);
 191
 192         /* deassert PLL_RESET */
 193         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 194
 195         mdelay(15);
 196
 197         /* deassert BYPASS EN */
 198         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
 199
 200         if (rdev->family >= CHIP_RS780)
 201                 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);
 202
 203         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 204         if (r)
 205                 return r;
 206
 207         /* switch VCLK and DCLK selection */
 208         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 209                  VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
 210                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 211
 212         mdelay(100);
 213
 214         return 0;
 215 }
 216
 217 void dce3_program_fmt(struct drm_encoder *encoder)
 218 {
 219         struct drm_device *dev = encoder->dev;
 220         struct radeon_device *rdev = dev->dev_private;
 221         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 222         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 223         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 224         int bpc = 0;
 225         u32 tmp = 0;
 226         enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
 227
 228         if (connector) {
 229                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 230                 bpc = radeon_get_monitor_bpc(connector);
 231                 dither = radeon_connector->dither;
 232         }
 233
 234         /* LVDS FMT is set up by atom */
 235         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 236                 return;
 237
 238         /* not needed for analog */
 239         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 240             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 241                 return;
 242
 243         if (bpc == 0)
 244                 return;
 245
 246         switch (bpc) {
 247         case 6:
 248                 if (dither == RADEON_FMT_DITHER_ENABLE)
 249                         /* XXX sort out optimal dither settings */
 250                         tmp |= FMT_SPATIAL_DITHER_EN;
 251                 else
 252                         tmp |= FMT_TRUNCATE_EN;
 253                 break;
 254         case 8:
 255                 if (dither == RADEON_FMT_DITHER_ENABLE)
 256                         /* XXX sort out optimal dither settings */
 257                         tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
 258                 else
 259                         tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
 260                 break;
 261         case 10:
 262         default:
 263                 /* not needed */
 264                 break;
 265         }
 266
 267         WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
 268 }
 269
 270 /* get temperature in millidegrees */
 271 int rv6xx_get_temp(struct radeon_device *rdev)
 272 {
 273         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 274                 ASIC_T_SHIFT;
 275         int actual_temp = temp & 0xff;
 276
 277         if (temp & 0x100)
 278                 actual_temp -= 256;
 279
 280         return actual_temp * 1000;
 281 }
 282
 283 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 284 {
 285         int i;
 286
 287         rdev->pm.dynpm_can_upclock = true;
 288         rdev->pm.dynpm_can_downclock = true;
 289
 290         /* power state array is low to high, default is first */
 291         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 292                 int min_power_state_index = 0;
 293
 294                 if (rdev->pm.num_power_states > 2)
 295                         min_power_state_index = 1;
 296
 297                 switch (rdev->pm.dynpm_planned_action) {
 298                 case DYNPM_ACTION_MINIMUM:
 299                         rdev->pm.requested_power_state_index = min_power_state_index;
 300                         rdev->pm.requested_clock_mode_index = 0;
 301                         rdev->pm.dynpm_can_downclock = false;
 302                         break;
 303                 case DYNPM_ACTION_DOWNCLOCK:
 304                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 305                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 306                                 rdev->pm.dynpm_can_downclock = false;
 307                         } else {
 308                                 if (rdev->pm.active_crtc_count > 1) {
 309                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 310                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 311                                                         continue;
 312                                                 else if (i >= rdev->pm.current_power_state_index) {
 313                                                         rdev->pm.requested_power_state_index =
 314                                                                 rdev->pm.current_power_state_index;
 315                                                         break;
 316                                                 } else {
 317                                                         rdev->pm.requested_power_state_index = i;
 318                                                         break;
 319                                                 }
 320                                         }
 321                                 } else {
 322                                         if (rdev->pm.current_power_state_index == 0)
 323                                                 rdev->pm.requested_power_state_index =
 324                                                         rdev->pm.num_power_states - 1;
 325                                         else
 326                                                 rdev->pm.requested_power_state_index =
 327                                                         rdev->pm.current_power_state_index - 1;
 328                                 }
 329                         }
 330                         rdev->pm.requested_clock_mode_index = 0;
 331                         /* don't use the power state if crtcs are active and no display flag is set */
 332                         if ((rdev->pm.active_crtc_count > 0) &&
 333                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 334                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 335                              RADEON_PM_MODE_NO_DISPLAY)) {
 336                                 rdev->pm.requested_power_state_index++;
 337                         }
 338                         break;
 339                 case DYNPM_ACTION_UPCLOCK:
 340                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 341                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 342                                 rdev->pm.dynpm_can_upclock = false;
 343                         } else {
 344                                 if (rdev->pm.active_crtc_count > 1) {
 345                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 346                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 347                                                         continue;
 348                                                 else if (i <= rdev->pm.current_power_state_index) {
 349                                                         rdev->pm.requested_power_state_index =
 350                                                                 rdev->pm.current_power_state_index;
 351                                                         break;
 352                                                 } else {
 353                                                         rdev->pm.requested_power_state_index = i;
 354                                                         break;
 355                                                 }
 356                                         }
 357                                 } else
 358                                         rdev->pm.requested_power_state_index =
 359                                                 rdev->pm.current_power_state_index + 1;
 360                         }
 361                         rdev->pm.requested_clock_mode_index = 0;
 362                         break;
 363                 case DYNPM_ACTION_DEFAULT:
 364                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 365                         rdev->pm.requested_clock_mode_index = 0;
 366                         rdev->pm.dynpm_can_upclock = false;
 367                         break;
 368                 case DYNPM_ACTION_NONE:
 369                 default:
 370                         DRM_ERROR("Requested mode for not defined action\n");
 371                         return;
 372                 }
 373         } else {
 374                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 375                 /* for now just select the first power state and switch between clock modes */
 376                 /* power state array is low to high, default is first (0) */
 377                 if (rdev->pm.active_crtc_count > 1) {
 378                         rdev->pm.requested_power_state_index = -1;
 379                         /* start at 1 as we don't want the default mode */
 380                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 381                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 382                                         continue;
 383                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 384                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 385                                         rdev->pm.requested_power_state_index = i;
 386                                         break;
 387                                 }
 388                         }
 389                         /* if nothing selected, grab the default state. */
 390                         if (rdev->pm.requested_power_state_index == -1)
 391                                 rdev->pm.requested_power_state_index = 0;
 392                 } else
 393                         rdev->pm.requested_power_state_index = 1;
 394
 395                 switch (rdev->pm.dynpm_planned_action) {
 396                 case DYNPM_ACTION_MINIMUM:
 397                         rdev->pm.requested_clock_mode_index = 0;
 398                         rdev->pm.dynpm_can_downclock = false;
 399                         break;
 400                 case DYNPM_ACTION_DOWNCLOCK:
 401                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 402                                 if (rdev->pm.current_clock_mode_index == 0) {
 403                                         rdev->pm.requested_clock_mode_index = 0;
 404                                         rdev->pm.dynpm_can_downclock = false;
 405                                 } else
 406                                         rdev->pm.requested_clock_mode_index =
 407                                                 rdev->pm.current_clock_mode_index - 1;
 408                         } else {
 409                                 rdev->pm.requested_clock_mode_index = 0;
 410                                 rdev->pm.dynpm_can_downclock = false;
 411                         }
 412                         /* don't use the power state if crtcs are active and no display flag is set */
 413                         if ((rdev->pm.active_crtc_count > 0) &&
 414                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 415                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 416                              RADEON_PM_MODE_NO_DISPLAY)) {
 417                                 rdev->pm.requested_clock_mode_index++;
 418                         }
 419                         break;
 420                 case DYNPM_ACTION_UPCLOCK:
 421                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 422                                 if (rdev->pm.current_clock_mode_index ==
 423                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 424                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 425                                         rdev->pm.dynpm_can_upclock = false;
 426                                 } else
 427                                         rdev->pm.requested_clock_mode_index =
 428                                                 rdev->pm.current_clock_mode_index + 1;
 429                         } else {
 430                                 rdev->pm.requested_clock_mode_index =
 431                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 432                                 rdev->pm.dynpm_can_upclock = false;
 433                         }
 434                         break;
 435                 case DYNPM_ACTION_DEFAULT:
 436                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 437                         rdev->pm.requested_clock_mode_index = 0;
 438                         rdev->pm.dynpm_can_upclock = false;
 439                         break;
 440                 case DYNPM_ACTION_NONE:
 441                 default:
 442                         DRM_ERROR("Requested mode for not defined action\n");
 443                         return;
 444                 }
 445         }
 446
 447         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 448                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 449                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 450                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 451                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 452                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 453                   pcie_lanes);
 454 }
 455
 456 void rs780_pm_init_profile(struct radeon_device *rdev)
 457 {
 458         if (rdev->pm.num_power_states == 2) {
 459                 /* default */
 460                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 461                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 462                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 463                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 464                 /* low sh */
 465                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 466                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 467                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 468                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 469                 /* mid sh */
 470                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 471                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 472                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 473                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 474                 /* high sh */
 475                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 476                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 477                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 478                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 479                 /* low mh */
 480                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 481                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 482                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 483                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 484                 /* mid mh */
 485                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 486                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 487                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 488                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 489                 /* high mh */
 490                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 491                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 492                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 493                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 494         } else if (rdev->pm.num_power_states == 3) {
 495                 /* default */
 496                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 497                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 498                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 499                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 500                 /* low sh */
 501                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 502                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 503                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 504                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 505                 /* mid sh */
 506                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 507                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 508                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 509                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 510                 /* high sh */
 511                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 512                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 513                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 514                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 515                 /* low mh */
 516                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 517                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 518                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 519                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 520                 /* mid mh */
 521                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 522                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 523                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 524                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 525                 /* high mh */
 526                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 527                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 528                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 529                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 530         } else {
 531                 /* default */
 532                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 533                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 534                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 535                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 536                 /* low sh */
 537                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 538                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 539                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 540                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 541                 /* mid sh */
 542                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 543                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 544                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 545                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 546                 /* high sh */
 547                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 548                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 549                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 550                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 551                 /* low mh */
 552                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 553                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 554                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 555                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 556                 /* mid mh */
 557                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 558                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 559                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 560                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 561                 /* high mh */
 562                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 563                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 564                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 565                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 566         }
 567 }
 568
 569 void r600_pm_init_profile(struct radeon_device *rdev)
 570 {
 571         int idx;
 572
 573         if (rdev->family == CHIP_R600) {
 574                 /* XXX */
 575                 /* default */
 576                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 577                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 578                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 579                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 580                 /* low sh */
 581                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 582                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 583                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 584                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 585                 /* mid sh */
 586                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 587                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 588                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 589                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 590                 /* high sh */
 591                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 592                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 593                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 594                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 595                 /* low mh */
 596                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 597                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 598                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 599                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 600                 /* mid mh */
 601                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 602                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 603                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 604                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 605                 /* high mh */
 606                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 607                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 608                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 609                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 610         } else {
 611                 if (rdev->pm.num_power_states < 4) {
 612                         /* default */
 613                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 614                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 615                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 616                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 617                         /* low sh */
 618                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 619                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 620                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 621                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 622                         /* mid sh */
 623                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 624                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 625                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 626                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 627                         /* high sh */
 628                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 629                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 630                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 631                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 632                         /* low mh */
 633                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 634                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 635                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 636                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 637                         /* low mh */
 638                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 639                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 640                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 641                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 642                         /* high mh */
 643                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 644                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 645                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 646                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 647                 } else {
 648                         /* default */
 649                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 650                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 651                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 652                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 653                         /* low sh */
 654                         if (rdev->flags & RADEON_IS_MOBILITY)
 655                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 656                         else
 657                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 658                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 659                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 660                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 661                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 662                         /* mid sh */
 663                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 664                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 665                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 666                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 667                         /* high sh */
 668                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 669                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 670                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 671                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 672                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 673                         /* low mh */
 674                         if (rdev->flags & RADEON_IS_MOBILITY)
 675                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 676                         else
 677                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 678                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 679                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 680                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 681                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 682                         /* mid mh */
 683                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 684                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 685                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 686                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 687                         /* high mh */
 688                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 689                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 690                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 691                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 692                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 693                 }
 694         }
 695 }
 696
 697 void r600_pm_misc(struct radeon_device *rdev)
 698 {
 699         int req_ps_idx = rdev->pm.requested_power_state_index;
 700         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 701         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 702         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 703
 704         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 705                 /* 0xff01 is a flag rather then an actual voltage */
 706                 if (voltage->voltage == 0xff01)
 707                         return;
 708                 if (voltage->voltage != rdev->pm.current_vddc) {
 709                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 710                         rdev->pm.current_vddc = voltage->voltage;
 711                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 712                 }
 713         }
 714 }
 715
 716 bool r600_gui_idle(struct radeon_device *rdev)
 717 {
 718         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 719                 return false;
 720         else
 721                 return true;
 722 }
 723
 724 /* hpd for digital panel detect/disconnect */
 725 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 726 {
 727         bool connected = false;
 728
 729         if (ASIC_IS_DCE3(rdev)) {
 730                 switch (hpd) {
 731                 case RADEON_HPD_1:
 732                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 733                                 connected = true;
 734                         break;
 735                 case RADEON_HPD_2:
 736                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 737                                 connected = true;
 738                         break;
 739                 case RADEON_HPD_3:
 740                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 741                                 connected = true;
 742                         break;
 743                 case RADEON_HPD_4:
 744                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 745                                 connected = true;
 746                         break;
 747                         /* DCE 3.2 */
 748                 case RADEON_HPD_5:
 749                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 750                                 connected = true;
 751                         break;
 752                 case RADEON_HPD_6:
 753                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 754                                 connected = true;
 755                         break;
 756                 default:
 757                         break;
 758                 }
 759         } else {
 760                 switch (hpd) {
 761                 case RADEON_HPD_1:
 762                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 763                                 connected = true;
 764                         break;
 765                 case RADEON_HPD_2:
 766                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 767                                 connected = true;
 768                         break;
 769                 case RADEON_HPD_3:
 770                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 771                                 connected = true;
 772                         break;
 773                 default:
 774                         break;
 775                 }
 776         }
 777         return connected;
 778 }
 779
 780 void r600_hpd_set_polarity(struct radeon_device *rdev,
 781                            enum radeon_hpd_id hpd)
 782 {
 783         u32 tmp;
 784         bool connected = r600_hpd_sense(rdev, hpd);
 785
 786         if (ASIC_IS_DCE3(rdev)) {
 787                 switch (hpd) {
 788                 case RADEON_HPD_1:
 789                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 790                         if (connected)
 791                                 tmp &= ~DC_HPDx_INT_POLARITY;
 792                         else
 793                                 tmp |= DC_HPDx_INT_POLARITY;
 794                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 795                         break;
 796                 case RADEON_HPD_2:
 797                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 798                         if (connected)
 799                                 tmp &= ~DC_HPDx_INT_POLARITY;
 800                         else
 801                                 tmp |= DC_HPDx_INT_POLARITY;
 802                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 803                         break;
 804                 case RADEON_HPD_3:
 805                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 806                         if (connected)
 807                                 tmp &= ~DC_HPDx_INT_POLARITY;
 808                         else
 809                                 tmp |= DC_HPDx_INT_POLARITY;
 810                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 811                         break;
 812                 case RADEON_HPD_4:
 813                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 814                         if (connected)
 815                                 tmp &= ~DC_HPDx_INT_POLARITY;
 816                         else
 817                                 tmp |= DC_HPDx_INT_POLARITY;
 818                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 819                         break;
 820                 case RADEON_HPD_5:
 821                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 822                         if (connected)
 823                                 tmp &= ~DC_HPDx_INT_POLARITY;
 824                         else
 825                                 tmp |= DC_HPDx_INT_POLARITY;
 826                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 827                         break;
 828                         /* DCE 3.2 */
 829                 case RADEON_HPD_6:
 830                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 831                         if (connected)
 832                                 tmp &= ~DC_HPDx_INT_POLARITY;
 833                         else
 834                                 tmp |= DC_HPDx_INT_POLARITY;
 835                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 836                         break;
 837                 default:
 838                         break;
 839                 }
 840         } else {
 841                 switch (hpd) {
 842                 case RADEON_HPD_1:
 843                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 844                         if (connected)
 845                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 846                         else
 847                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 848                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 849                         break;
 850                 case RADEON_HPD_2:
 851                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 852                         if (connected)
 853                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 854                         else
 855                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 856                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 857                         break;
 858                 case RADEON_HPD_3:
 859                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 860                         if (connected)
 861                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 862                         else
 863                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 864                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 865                         break;
 866                 default:
 867                         break;
 868                 }
 869         }
 870 }
 871
 872 void r600_hpd_init(struct radeon_device *rdev)
 873 {
 874         struct drm_device *dev = rdev->ddev;
 875         struct drm_connector *connector;
 876         unsigned enable = 0;
 877
 878         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 879                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 880
 881                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 882                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 883                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 884                          * aux dp channel on imac and help (but not completely fix)
 885                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 886                          */
 887                         continue;
 888                 }
 889                 if (ASIC_IS_DCE3(rdev)) {
 890                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 891                         if (ASIC_IS_DCE32(rdev))
 892                                 tmp |= DC_HPDx_EN;
 893
 894                         switch (radeon_connector->hpd.hpd) {
 895                         case RADEON_HPD_1:
 896                                 WREG32(DC_HPD1_CONTROL, tmp);
 897                                 break;
 898                         case RADEON_HPD_2:
 899                                 WREG32(DC_HPD2_CONTROL, tmp);
 900                                 break;
 901                         case RADEON_HPD_3:
 902                                 WREG32(DC_HPD3_CONTROL, tmp);
 903                                 break;
 904                         case RADEON_HPD_4:
 905                                 WREG32(DC_HPD4_CONTROL, tmp);
 906                                 break;
 907                                 /* DCE 3.2 */
 908                         case RADEON_HPD_5:
 909                                 WREG32(DC_HPD5_CONTROL, tmp);
 910                                 break;
 911                         case RADEON_HPD_6:
 912                                 WREG32(DC_HPD6_CONTROL, tmp);
 913                                 break;
 914                         default:
 915                                 break;
 916                         }
 917                 } else {
 918                         switch (radeon_connector->hpd.hpd) {
 919                         case RADEON_HPD_1:
 920                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 921                                 break;
 922                         case RADEON_HPD_2:
 923                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 924                                 break;
 925                         case RADEON_HPD_3:
 926                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 927                                 break;
 928                         default:
 929                                 break;
 930                         }
 931                 }
 932                 enable |= 1 << radeon_connector->hpd.hpd;
 933                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 934         }
 935         radeon_irq_kms_enable_hpd(rdev, enable);
 936 }
 937
 938 void r600_hpd_fini(struct radeon_device *rdev)
 939 {
 940         struct drm_device *dev = rdev->ddev;
 941         struct drm_connector *connector;
 942         unsigned disable = 0;
 943
 944         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 945                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 946                 if (ASIC_IS_DCE3(rdev)) {
 947                         switch (radeon_connector->hpd.hpd) {
 948                         case RADEON_HPD_1:
 949                                 WREG32(DC_HPD1_CONTROL, 0);
 950                                 break;
 951                         case RADEON_HPD_2:
 952                                 WREG32(DC_HPD2_CONTROL, 0);
 953                                 break;
 954                         case RADEON_HPD_3:
 955                                 WREG32(DC_HPD3_CONTROL, 0);
 956                                 break;
 957                         case RADEON_HPD_4:
 958                                 WREG32(DC_HPD4_CONTROL, 0);
 959                                 break;
 960                                 /* DCE 3.2 */
 961                         case RADEON_HPD_5:
 962                                 WREG32(DC_HPD5_CONTROL, 0);
 963                                 break;
 964                         case RADEON_HPD_6:
 965                                 WREG32(DC_HPD6_CONTROL, 0);
 966                                 break;
 967                         default:
 968                                 break;
 969                         }
 970                 } else {
 971                         switch (radeon_connector->hpd.hpd) {
 972                         case RADEON_HPD_1:
 973                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 974                                 break;
 975                         case RADEON_HPD_2:
 976                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 977                                 break;
 978                         case RADEON_HPD_3:
 979                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 980                                 break;
 981                         default:
 982                                 break;
 983                         }
 984                 }
 985                 disable |= 1 << radeon_connector->hpd.hpd;
 986         }
 987         radeon_irq_kms_disable_hpd(rdev, disable);
 988 }
 989
 990 /*
 991  * R600 PCIE GART
 992  */
 993 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 994 {
 995         unsigned i;
 996         u32 tmp;
 997
 998         /* flush hdp cache so updates hit vram */
 999         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
1000             !(rdev->flags & RADEON_IS_AGP)) {
1001                 void __iomem *ptr = (void *)rdev->gart.ptr;
1002                 u32 tmp;
1003
1004                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
1005                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
1006                  * This seems to cause problems on some AGP cards. Just use the old
1007                  * method for them.
1008                  */
1009                 WREG32(HDP_DEBUG1, 0);
1010                 tmp = readl((void __iomem *)ptr);
1011         } else
1012                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1013
1014         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1015         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1016         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1017         for (i = 0; i < rdev->usec_timeout; i++) {
1018                 /* read MC_STATUS */
1019                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1020                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1021                 if (tmp == 2) {
1022                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1023                         return;
1024                 }
1025                 if (tmp) {
1026                         return;
1027                 }
1028                 udelay(1);
1029         }
1030 }
1031
1032 int r600_pcie_gart_init(struct radeon_device *rdev)
1033 {
1034         int r;
1035
1036         if (rdev->gart.robj) {
1037                 WARN(1, "R600 PCIE GART already initialized\n");
1038                 return 0;
1039         }
1040         /* Initialize common gart structure */
1041         r = radeon_gart_init(rdev);
1042         if (r)
1043                 return r;
1044         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1045         return radeon_gart_table_vram_alloc(rdev);
1046 }
1047
1048 static int r600_pcie_gart_enable(struct radeon_device *rdev)
1049 {
1050         u32 tmp;
1051         int r, i;
1052
1053         if (rdev->gart.robj == NULL) {
1054                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1055                 return -EINVAL;
1056         }
1057         r = radeon_gart_table_vram_pin(rdev);
1058         if (r)
1059                 return r;
1060
1061         /* Setup L2 cache */
1062         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1063                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1064                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1065         WREG32(VM_L2_CNTL2, 0);
1066         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1067         /* Setup TLB control */
1068         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1069                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1070                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1071                 ENABLE_WAIT_L2_QUERY;
1072         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1073         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1074         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1075         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1076         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1077         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1078         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1079         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1080         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1081         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1082         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1083         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1084         WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1085         WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1086         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1087         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1088         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1089         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1090         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1091         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1092                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1093         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1094                         (u32)(rdev->dummy_page.addr >> 12));
1095         for (i = 1; i < 7; i++)
1096                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1097
1098         r600_pcie_gart_tlb_flush(rdev);
1099         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1100                  (unsigned)(rdev->mc.gtt_size >> 20),
1101                  (unsigned long long)rdev->gart.table_addr);
1102         rdev->gart.ready = true;
1103         return 0;
1104 }
1105
1106 static void r600_pcie_gart_disable(struct radeon_device *rdev)
1107 {
1108         u32 tmp;
1109         int i;
1110
1111         /* Disable all tables */
1112         for (i = 0; i < 7; i++)
1113                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1114
1115         /* Disable L2 cache */
1116         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1117                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1118         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1119         /* Setup L1 TLB control */
1120         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1121                 ENABLE_WAIT_L2_QUERY;
1122         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1123         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1124         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1125         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1126         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1127         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1128         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1129         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1130         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1131         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1132         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1133         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1134         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1135         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1136         WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1137         WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1138         radeon_gart_table_vram_unpin(rdev);
1139 }
1140
1141 static void r600_pcie_gart_fini(struct radeon_device *rdev)
1142 {
1143         radeon_gart_fini(rdev);
1144         r600_pcie_gart_disable(rdev);
1145         radeon_gart_table_vram_free(rdev);
1146 }
1147
1148 static void r600_agp_enable(struct radeon_device *rdev)
1149 {
1150         u32 tmp;
1151         int i;
1152
1153         /* Setup L2 cache */
1154         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1155                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1156                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1157         WREG32(VM_L2_CNTL2, 0);
1158         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1159         /* Setup TLB control */
1160         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1161                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1162                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1163                 ENABLE_WAIT_L2_QUERY;
1164         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1165         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1166         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1167         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1168         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1169         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1170         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1171         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1172         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1173         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1174         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1175         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1176         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1177         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1178         for (i = 0; i < 7; i++)
1179                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1180 }
1181
1182 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1183 {
1184         unsigned i;
1185         u32 tmp;
1186
1187         for (i = 0; i < rdev->usec_timeout; i++) {
1188                 /* read MC_STATUS */
1189                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1190                 if (!tmp)
1191                         return 0;
1192                 udelay(1);
1193         }
1194         return -1;
1195 }
1196
1197 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1198 {
1199         unsigned long flags;
1200         uint32_t r;
1201
1202         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1203         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1204         r = RREG32(R_0028FC_MC_DATA);
1205         WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1206         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1207         return r;
1208 }
1209
1210 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1211 {
1212         unsigned long flags;
1213
1214         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1215         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1216                 S_0028F8_MC_IND_WR_EN(1));
1217         WREG32(R_0028FC_MC_DATA, v);
1218         WREG32(R_0028F8_MC_INDEX, 0x7F);
1219         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1220 }
1221
1222 static void r600_mc_program(struct radeon_device *rdev)
1223 {
1224         struct rv515_mc_save save;
1225         u32 tmp;
1226         int i, j;
1227
1228         /* Initialize HDP */
1229         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1230                 WREG32((0x2c14 + j), 0x00000000);
1231                 WREG32((0x2c18 + j), 0x00000000);
1232                 WREG32((0x2c1c + j), 0x00000000);
1233                 WREG32((0x2c20 + j), 0x00000000);
1234                 WREG32((0x2c24 + j), 0x00000000);
1235         }
1236         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1237
1238         rv515_mc_stop(rdev, &save);
1239         if (r600_mc_wait_for_idle(rdev)) {
1240                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1241         }
1242         /* Lockout access through VGA aperture (doesn't exist before R600) */
1243         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1244         /* Update configuration */
1245         if (rdev->flags & RADEON_IS_AGP) {
1246                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1247                         /* VRAM before AGP */
1248                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1249                                 rdev->mc.vram_start >> 12);
1250                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1251                                 rdev->mc.gtt_end >> 12);
1252                 } else {
1253                         /* VRAM after AGP */
1254                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1255                                 rdev->mc.gtt_start >> 12);
1256                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1257                                 rdev->mc.vram_end >> 12);
1258                 }
1259         } else {
1260                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1261                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1262         }
1263         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1264         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1265         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1266         WREG32(MC_VM_FB_LOCATION, tmp);
1267         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1268         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1269         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1270         if (rdev->flags & RADEON_IS_AGP) {
1271                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1272                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1273                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1274         } else {
1275                 WREG32(MC_VM_AGP_BASE, 0);
1276                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1277                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1278         }
1279         if (r600_mc_wait_for_idle(rdev)) {
1280                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1281         }
1282         rv515_mc_resume(rdev, &save);
1283         /* we need to own VRAM, so turn off the VGA renderer here
1284          * to stop it overwriting our objects */
1285         rv515_vga_render_disable(rdev);
1286 }
1287
1288 /**
1289  * r600_vram_gtt_location - try to find VRAM & GTT location
1290  * @rdev: radeon device structure holding all necessary informations
1291  * @mc: memory controller structure holding memory informations
1292  *
1293  * Function will place try to place VRAM at same place as in CPU (PCI)
1294  * address space as some GPU seems to have issue when we reprogram at
1295  * different address space.
1296  *
1297  * If there is not enough space to fit the unvisible VRAM after the
1298  * aperture then we limit the VRAM size to the aperture.
1299  *
1300  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1301  * them to be in one from GPU point of view so that we can program GPU to
1302  * catch access outside them (weird GPU policy see ??).
1303  *
1304  * This function will never fails, worst case are limiting VRAM or GTT.
1305  *
1306  * Note: GTT start, end, size should be initialized before calling this
1307  * function on AGP platform.
1308  */
1309 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1310 {
1311         u64 size_bf, size_af;
1312
1313         if (mc->mc_vram_size > 0xE0000000) {
1314                 /* leave room for at least 512M GTT */
1315                 dev_warn(rdev->dev, "limiting VRAM\n");
1316                 mc->real_vram_size = 0xE0000000;
1317                 mc->mc_vram_size = 0xE0000000;
1318         }
1319         if (rdev->flags & RADEON_IS_AGP) {
1320                 size_bf = mc->gtt_start;
1321                 size_af = mc->mc_mask - mc->gtt_end;
1322                 if (size_bf > size_af) {
1323                         if (mc->mc_vram_size > size_bf) {
1324                                 dev_warn(rdev->dev, "limiting VRAM\n");
1325                                 mc->real_vram_size = size_bf;
1326                                 mc->mc_vram_size = size_bf;
1327                         }
1328                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1329                 } else {
1330                         if (mc->mc_vram_size > size_af) {
1331                                 dev_warn(rdev->dev, "limiting VRAM\n");
1332                                 mc->real_vram_size = size_af;
1333                                 mc->mc_vram_size = size_af;
1334                         }
1335                         mc->vram_start = mc->gtt_end + 1;
1336                 }
1337                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1338                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1339                                 mc->mc_vram_size >> 20, mc->vram_start,
1340                                 mc->vram_end, mc->real_vram_size >> 20);
1341         } else {
1342                 u64 base = 0;
1343                 if (rdev->flags & RADEON_IS_IGP) {
1344                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1345                         base <<= 24;
1346                 }
1347                 radeon_vram_location(rdev, &rdev->mc, base);
1348                 rdev->mc.gtt_base_align = 0;
1349                 radeon_gtt_location(rdev, mc);
1350         }
1351 }
1352
1353 static int r600_mc_init(struct radeon_device *rdev)
1354 {
1355         u32 tmp;
1356         int chansize, numchan;
1357         uint32_t h_addr, l_addr;
1358         unsigned long long k8_addr;
1359
1360         /* Get VRAM informations */
1361         rdev->mc.vram_is_ddr = true;
1362         tmp = RREG32(RAMCFG);
1363         if (tmp & CHANSIZE_OVERRIDE) {
1364                 chansize = 16;
1365         } else if (tmp & CHANSIZE_MASK) {
1366                 chansize = 64;
1367         } else {
1368                 chansize = 32;
1369         }
1370         tmp = RREG32(CHMAP);
1371         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1372         case 0:
1373         default:
1374                 numchan = 1;
1375                 break;
1376         case 1:
1377                 numchan = 2;
1378                 break;
1379         case 2:
1380                 numchan = 4;
1381                 break;
1382         case 3:
1383                 numchan = 8;
1384                 break;
1385         }
1386         rdev->mc.vram_width = numchan * chansize;
1387         /* Could aper size report 0 ? */
1388         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1389         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1390         /* Setup GPU memory space */
1391         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1392         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1393         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1394         r600_vram_gtt_location(rdev, &rdev->mc);
1395
1396         if (rdev->flags & RADEON_IS_IGP) {
1397                 rs690_pm_info(rdev);
1398                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1399
1400                 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1401                         /* Use K8 direct mapping for fast fb access. */
1402                         rdev->fastfb_working = false;
1403                         h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1404                         l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1405                         k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1406 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1407                         if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1408 #endif
1409                         {
1410                                 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1411                                 * memory is present.
1412                                 */
1413                                 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1414                                         DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1415                                                 (unsigned long long)rdev->mc.aper_base, k8_addr);
1416                                         rdev->mc.aper_base = (resource_size_t)k8_addr;
1417                                         rdev->fastfb_working = true;
1418                                 }
1419                         }
1420                 }
1421         }
1422
1423         radeon_update_bandwidth_info(rdev);
1424         return 0;
1425 }
1426
1427 int r600_vram_scratch_init(struct radeon_device *rdev)
1428 {
1429         int r;
1430
1431         if (rdev->vram_scratch.robj == NULL) {
1432                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1433                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1434                                      0, NULL, NULL, &rdev->vram_scratch.robj);
1435                 if (r) {
1436                         return r;
1437                 }
1438         }
1439
1440         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1441         if (unlikely(r != 0))
1442                 return r;
1443         r = radeon_bo_pin(rdev->vram_scratch.robj,
1444                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1445         if (r) {
1446                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1447                 return r;
1448         }
1449         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1450                                 (void **)&rdev->vram_scratch.ptr);
1451         if (r)
1452                 radeon_bo_unpin(rdev->vram_scratch.robj);
1453         radeon_bo_unreserve(rdev->vram_scratch.robj);
1454
1455         return r;
1456 }
1457
1458 void r600_vram_scratch_fini(struct radeon_device *rdev)
1459 {
1460         int r;
1461
1462         if (rdev->vram_scratch.robj == NULL) {
1463                 return;
1464         }
1465         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1466         if (likely(r == 0)) {
1467                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1468                 radeon_bo_unpin(rdev->vram_scratch.robj);
1469                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1470         }
1471         radeon_bo_unref(&rdev->vram_scratch.robj);
1472 }
1473
1474 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1475 {
1476         u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1477
1478         if (hung)
1479                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1480         else
1481                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1482
1483         WREG32(R600_BIOS_3_SCRATCH, tmp);
1484 }
1485
1486 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1487 {
1488         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1489                  RREG32(R_008010_GRBM_STATUS));
1490         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1491                  RREG32(R_008014_GRBM_STATUS2));
1492         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1493                  RREG32(R_000E50_SRBM_STATUS));
1494         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1495                  RREG32(CP_STALLED_STAT1));
1496         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1497                  RREG32(CP_STALLED_STAT2));
1498         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1499                  RREG32(CP_BUSY_STAT));
1500         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1501                  RREG32(CP_STAT));
1502         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1503                 RREG32(DMA_STATUS_REG));
1504 }
1505
1506 static bool r600_is_display_hung(struct radeon_device *rdev)
1507 {
1508         u32 crtc_hung = 0;
1509         u32 crtc_status[2];
1510         u32 i, j, tmp;
1511
1512         for (i = 0; i < rdev->num_crtc; i++) {
1513                 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1514                         crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1515                         crtc_hung |= (1 << i);
1516                 }
1517         }
1518
1519         for (j = 0; j < 10; j++) {
1520                 for (i = 0; i < rdev->num_crtc; i++) {
1521                         if (crtc_hung & (1 << i)) {
1522                                 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1523                                 if (tmp != crtc_status[i])
1524                                         crtc_hung &= ~(1 << i);
1525                         }
1526                 }
1527                 if (crtc_hung == 0)
1528                         return false;
1529                 udelay(100);
1530         }
1531
1532         return true;
1533 }
1534
1535 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1536 {
1537         u32 reset_mask = 0;
1538         u32 tmp;
1539
1540         /* GRBM_STATUS */
1541         tmp = RREG32(R_008010_GRBM_STATUS);
1542         if (rdev->family >= CHIP_RV770) {
1543                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1544                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1545                     G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1546                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1547                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1548                         reset_mask |= RADEON_RESET_GFX;
1549         } else {
1550                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1551                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1552                     G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1553                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1554                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1555                         reset_mask |= RADEON_RESET_GFX;
1556         }
1557
1558         if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1559             G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1560                 reset_mask |= RADEON_RESET_CP;
1561
1562         if (G_008010_GRBM_EE_BUSY(tmp))
1563                 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1564
1565         /* DMA_STATUS_REG */
1566         tmp = RREG32(DMA_STATUS_REG);
1567         if (!(tmp & DMA_IDLE))
1568                 reset_mask |= RADEON_RESET_DMA;
1569
1570         /* SRBM_STATUS */
1571         tmp = RREG32(R_000E50_SRBM_STATUS);
1572         if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1573                 reset_mask |= RADEON_RESET_RLC;
1574
1575         if (G_000E50_IH_BUSY(tmp))
1576                 reset_mask |= RADEON_RESET_IH;
1577
1578         if (G_000E50_SEM_BUSY(tmp))
1579                 reset_mask |= RADEON_RESET_SEM;
1580
1581         if (G_000E50_GRBM_RQ_PENDING(tmp))
1582                 reset_mask |= RADEON_RESET_GRBM;
1583
1584         if (G_000E50_VMC_BUSY(tmp))
1585                 reset_mask |= RADEON_RESET_VMC;
1586
1587         if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1588             G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1589             G_000E50_MCDW_BUSY(tmp))
1590                 reset_mask |= RADEON_RESET_MC;
1591
1592         if (r600_is_display_hung(rdev))
1593                 reset_mask |= RADEON_RESET_DISPLAY;
1594
1595         /* Skip MC reset as it's mostly likely not hung, just busy */
1596         if (reset_mask & RADEON_RESET_MC) {
1597                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1598                 reset_mask &= ~RADEON_RESET_MC;
1599         }
1600
1601         return reset_mask;
1602 }
1603
1604 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1605 {
1606         struct rv515_mc_save save;
1607         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1608         u32 tmp;
1609
1610         if (reset_mask == 0)
1611                 return;
1612
1613         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1614
1615         r600_print_gpu_status_regs(rdev);
1616
1617         /* Disable CP parsing/prefetching */
1618         if (rdev->family >= CHIP_RV770)
1619                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1620         else
1621                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1622
1623         /* disable the RLC */
1624         WREG32(RLC_CNTL, 0);
1625
1626         if (reset_mask & RADEON_RESET_DMA) {
1627                 /* Disable DMA */
1628                 tmp = RREG32(DMA_RB_CNTL);
1629                 tmp &= ~DMA_RB_ENABLE;
1630                 WREG32(DMA_RB_CNTL, tmp);
1631         }
1632
1633         mdelay(50);
1634
1635         rv515_mc_stop(rdev, &save);
1636         if (r600_mc_wait_for_idle(rdev)) {
1637                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1638         }
1639
1640         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1641                 if (rdev->family >= CHIP_RV770)
1642                         grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1643                                 S_008020_SOFT_RESET_CB(1) |
1644                                 S_008020_SOFT_RESET_PA(1) |
1645                                 S_008020_SOFT_RESET_SC(1) |
1646                                 S_008020_SOFT_RESET_SPI(1) |
1647                                 S_008020_SOFT_RESET_SX(1) |
1648                                 S_008020_SOFT_RESET_SH(1) |
1649                                 S_008020_SOFT_RESET_TC(1) |
1650                                 S_008020_SOFT_RESET_TA(1) |
1651                                 S_008020_SOFT_RESET_VC(1) |
1652                                 S_008020_SOFT_RESET_VGT(1);
1653                 else
1654                         grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1655                                 S_008020_SOFT_RESET_DB(1) |
1656                                 S_008020_SOFT_RESET_CB(1) |
1657                                 S_008020_SOFT_RESET_PA(1) |
1658                                 S_008020_SOFT_RESET_SC(1) |
1659                                 S_008020_SOFT_RESET_SMX(1) |
1660                                 S_008020_SOFT_RESET_SPI(1) |
1661                                 S_008020_SOFT_RESET_SX(1) |
1662                                 S_008020_SOFT_RESET_SH(1) |
1663                                 S_008020_SOFT_RESET_TC(1) |
1664                                 S_008020_SOFT_RESET_TA(1) |
1665                                 S_008020_SOFT_RESET_VC(1) |
1666                                 S_008020_SOFT_RESET_VGT(1);
1667         }
1668
1669         if (reset_mask & RADEON_RESET_CP) {
1670                 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1671                         S_008020_SOFT_RESET_VGT(1);
1672
1673                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1674         }
1675
1676         if (reset_mask & RADEON_RESET_DMA) {
1677                 if (rdev->family >= CHIP_RV770)
1678                         srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1679                 else
1680                         srbm_soft_reset |= SOFT_RESET_DMA;
1681         }
1682
1683         if (reset_mask & RADEON_RESET_RLC)
1684                 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1685
1686         if (reset_mask & RADEON_RESET_SEM)
1687                 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1688
1689         if (reset_mask & RADEON_RESET_IH)
1690                 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1691
1692         if (reset_mask & RADEON_RESET_GRBM)
1693                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1694
1695         if (!(rdev->flags & RADEON_IS_IGP)) {
1696                 if (reset_mask & RADEON_RESET_MC)
1697                         srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1698         }
1699
1700         if (reset_mask & RADEON_RESET_VMC)
1701                 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1702
1703         if (grbm_soft_reset) {
1704                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1705                 tmp |= grbm_soft_reset;
1706                 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1707                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1708                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1709
1710                 udelay(50);
1711
1712                 tmp &= ~grbm_soft_reset;
1713                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1714                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1715         }
1716
1717         if (srbm_soft_reset) {
1718                 tmp = RREG32(SRBM_SOFT_RESET);
1719                 tmp |= srbm_soft_reset;
1720                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1721                 WREG32(SRBM_SOFT_RESET, tmp);
1722                 tmp = RREG32(SRBM_SOFT_RESET);
1723
1724                 udelay(50);
1725
1726                 tmp &= ~srbm_soft_reset;
1727                 WREG32(SRBM_SOFT_RESET, tmp);
1728                 tmp = RREG32(SRBM_SOFT_RESET);
1729         }
1730
1731         /* Wait a little for things to settle down */
1732         mdelay(1);
1733
1734         rv515_mc_resume(rdev, &save);
1735         udelay(50);
1736
1737         r600_print_gpu_status_regs(rdev);
1738 }
1739
1740 static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1741 {
1742         struct rv515_mc_save save;
1743         u32 tmp, i;
1744
1745         dev_info(rdev->dev, "GPU pci config reset\n");
1746
1747         /* disable dpm? */
1748
1749         /* Disable CP parsing/prefetching */
1750         if (rdev->family >= CHIP_RV770)
1751                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1752         else
1753                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1754
1755         /* disable the RLC */
1756         WREG32(RLC_CNTL, 0);
1757
1758         /* Disable DMA */
1759         tmp = RREG32(DMA_RB_CNTL);
1760         tmp &= ~DMA_RB_ENABLE;
1761         WREG32(DMA_RB_CNTL, tmp);
1762
1763         mdelay(50);
1764
1765         /* set mclk/sclk to bypass */
1766         if (rdev->family >= CHIP_RV770)
1767                 rv770_set_clk_bypass_mode(rdev);
1768         /* disable BM */
1769         pci_clear_master(rdev->pdev);
1770         /* disable mem access */
1771         rv515_mc_stop(rdev, &save);
1772         if (r600_mc_wait_for_idle(rdev)) {
1773                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1774         }
1775
1776         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1777         tmp = RREG32(BUS_CNTL);
1778         tmp |= VGA_COHE_SPEC_TIMER_DIS;
1779         WREG32(BUS_CNTL, tmp);
1780
1781         tmp = RREG32(BIF_SCRATCH0);
1782
1783         /* reset */
1784         radeon_pci_config_reset(rdev);
1785         mdelay(1);
1786
1787         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1788         tmp = SOFT_RESET_BIF;
1789         WREG32(SRBM_SOFT_RESET, tmp);
1790         mdelay(1);
1791         WREG32(SRBM_SOFT_RESET, 0);
1792
1793         /* wait for asic to come out of reset */
1794         for (i = 0; i < rdev->usec_timeout; i++) {
1795                 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1796                         break;
1797                 udelay(1);
1798         }
1799 }
1800
1801 int r600_asic_reset(struct radeon_device *rdev)
1802 {
1803         u32 reset_mask;
1804
1805         reset_mask = r600_gpu_check_soft_reset(rdev);
1806
1807         if (reset_mask)
1808                 r600_set_bios_scratch_engine_hung(rdev, true);
1809
1810         /* try soft reset */
1811         r600_gpu_soft_reset(rdev, reset_mask);
1812
1813         reset_mask = r600_gpu_check_soft_reset(rdev);
1814
1815         /* try pci config reset */
1816         if (reset_mask && radeon_hard_reset)
1817                 r600_gpu_pci_config_reset(rdev);
1818
1819         reset_mask = r600_gpu_check_soft_reset(rdev);
1820
1821         if (!reset_mask)
1822                 r600_set_bios_scratch_engine_hung(rdev, false);
1823
1824         return 0;
1825 }
1826
1827 /**
1828  * r600_gfx_is_lockup - Check if the GFX engine is locked up
1829  *
1830  * @rdev: radeon_device pointer
1831  * @ring: radeon_ring structure holding ring information
1832  *
1833  * Check if the GFX engine is locked up.
1834  * Returns true if the engine appears to be locked up, false if not.
1835  */
1836 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1837 {
1838         u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1839
1840         if (!(reset_mask & (RADEON_RESET_GFX |
1841                             RADEON_RESET_COMPUTE |
1842                             RADEON_RESET_CP))) {
1843                 radeon_ring_lockup_update(rdev, ring);
1844                 return false;
1845         }
1846         return radeon_ring_test_lockup(rdev, ring);
1847 }
1848
1849 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1850                               u32 tiling_pipe_num,
1851                               u32 max_rb_num,
1852                               u32 total_max_rb_num,
1853                               u32 disabled_rb_mask)
1854 {
1855         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1856         u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1857         u32 data = 0, mask = 1 << (max_rb_num - 1);
1858         unsigned i, j;
1859
1860         /* mask out the RBs that don't exist on that asic */
1861         tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1862         /* make sure at least one RB is available */
1863         if ((tmp & 0xff) != 0xff)
1864                 disabled_rb_mask = tmp;
1865
1866         rendering_pipe_num = 1 << tiling_pipe_num;
1867         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1868         BUG_ON(rendering_pipe_num < req_rb_num);
1869
1870         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1871         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1872
1873         if (rdev->family <= CHIP_RV740) {
1874                 /* r6xx/r7xx */
1875                 rb_num_width = 2;
1876         } else {
1877                 /* eg+ */
1878                 rb_num_width = 4;
1879         }
1880
1881         for (i = 0; i < max_rb_num; i++) {
1882                 if (!(mask & disabled_rb_mask)) {
1883                         for (j = 0; j < pipe_rb_ratio; j++) {
1884                                 data <<= rb_num_width;
1885                                 data |= max_rb_num - i - 1;
1886                         }
1887                         if (pipe_rb_remain) {
1888                                 data <<= rb_num_width;
1889                                 data |= max_rb_num - i - 1;
1890                                 pipe_rb_remain--;
1891                         }
1892                 }
1893                 mask >>= 1;
1894         }
1895
1896         return data;
1897 }
1898
1899 int r600_count_pipe_bits(uint32_t val)
1900 {
1901         return hweight32(val);
1902 }
1903
1904 static void r600_gpu_init(struct radeon_device *rdev)
1905 {
1906         u32 tiling_config;
1907         u32 ramcfg;
1908         u32 cc_gc_shader_pipe_config;
1909         u32 tmp;
1910         int i, j;
1911         u32 sq_config;
1912         u32 sq_gpr_resource_mgmt_1 = 0;
1913         u32 sq_gpr_resource_mgmt_2 = 0;
1914         u32 sq_thread_resource_mgmt = 0;
1915         u32 sq_stack_resource_mgmt_1 = 0;
1916         u32 sq_stack_resource_mgmt_2 = 0;
1917         u32 disabled_rb_mask;
1918
1919         rdev->config.r600.tiling_group_size = 256;
1920         switch (rdev->family) {
1921         case CHIP_R600:
1922                 rdev->config.r600.max_pipes = 4;
1923                 rdev->config.r600.max_tile_pipes = 8;
1924                 rdev->config.r600.max_simds = 4;
1925                 rdev->config.r600.max_backends = 4;
1926                 rdev->config.r600.max_gprs = 256;
1927                 rdev->config.r600.max_threads = 192;
1928                 rdev->config.r600.max_stack_entries = 256;
1929                 rdev->config.r600.max_hw_contexts = 8;
1930                 rdev->config.r600.max_gs_threads = 16;
1931                 rdev->config.r600.sx_max_export_size = 128;
1932                 rdev->config.r600.sx_max_export_pos_size = 16;
1933                 rdev->config.r600.sx_max_export_smx_size = 128;
1934                 rdev->config.r600.sq_num_cf_insts = 2;
1935                 break;
1936         case CHIP_RV630:
1937         case CHIP_RV635:
1938                 rdev->config.r600.max_pipes = 2;
1939                 rdev->config.r600.max_tile_pipes = 2;
1940                 rdev->config.r600.max_simds = 3;
1941                 rdev->config.r600.max_backends = 1;
1942                 rdev->config.r600.max_gprs = 128;
1943                 rdev->config.r600.max_threads = 192;
1944                 rdev->config.r600.max_stack_entries = 128;
1945                 rdev->config.r600.max_hw_contexts = 8;
1946                 rdev->config.r600.max_gs_threads = 4;
1947                 rdev->config.r600.sx_max_export_size = 128;
1948                 rdev->config.r600.sx_max_export_pos_size = 16;
1949                 rdev->config.r600.sx_max_export_smx_size = 128;
1950                 rdev->config.r600.sq_num_cf_insts = 2;
1951                 break;
1952         case CHIP_RV610:
1953         case CHIP_RV620:
1954         case CHIP_RS780:
1955         case CHIP_RS880:
1956                 rdev->config.r600.max_pipes = 1;
1957                 rdev->config.r600.max_tile_pipes = 1;
1958                 rdev->config.r600.max_simds = 2;
1959                 rdev->config.r600.max_backends = 1;
1960                 rdev->config.r600.max_gprs = 128;
1961                 rdev->config.r600.max_threads = 192;
1962                 rdev->config.r600.max_stack_entries = 128;
1963                 rdev->config.r600.max_hw_contexts = 4;
1964                 rdev->config.r600.max_gs_threads = 4;
1965                 rdev->config.r600.sx_max_export_size = 128;
1966                 rdev->config.r600.sx_max_export_pos_size = 16;
1967                 rdev->config.r600.sx_max_export_smx_size = 128;
1968                 rdev->config.r600.sq_num_cf_insts = 1;
1969                 break;
1970         case CHIP_RV670:
1971                 rdev->config.r600.max_pipes = 4;
1972                 rdev->config.r600.max_tile_pipes = 4;
1973                 rdev->config.r600.max_simds = 4;
1974                 rdev->config.r600.max_backends = 4;
1975                 rdev->config.r600.max_gprs = 192;
1976                 rdev->config.r600.max_threads = 192;
1977                 rdev->config.r600.max_stack_entries = 256;
1978                 rdev->config.r600.max_hw_contexts = 8;
1979                 rdev->config.r600.max_gs_threads = 16;
1980                 rdev->config.r600.sx_max_export_size = 128;
1981                 rdev->config.r600.sx_max_export_pos_size = 16;
1982                 rdev->config.r600.sx_max_export_smx_size = 128;
1983                 rdev->config.r600.sq_num_cf_insts = 2;
1984                 break;
1985         default:
1986                 break;
1987         }
1988
1989         /* Initialize HDP */
1990         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1991                 WREG32((0x2c14 + j), 0x00000000);
1992                 WREG32((0x2c18 + j), 0x00000000);
1993                 WREG32((0x2c1c + j), 0x00000000);
1994                 WREG32((0x2c20 + j), 0x00000000);
1995                 WREG32((0x2c24 + j), 0x00000000);
1996         }
1997
1998         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1999
2000         /* Setup tiling */
2001         tiling_config = 0;
2002         ramcfg = RREG32(RAMCFG);
2003         switch (rdev->config.r600.max_tile_pipes) {
2004         case 1:
2005                 tiling_config |= PIPE_TILING(0);
2006                 break;
2007         case 2:
2008                 tiling_config |= PIPE_TILING(1);
2009                 break;
2010         case 4:
2011                 tiling_config |= PIPE_TILING(2);
2012                 break;
2013         case 8:
2014                 tiling_config |= PIPE_TILING(3);
2015                 break;
2016         default:
2017                 break;
2018         }
2019         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2020         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2021         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2022         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
2023
2024         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
2025         if (tmp > 3) {
2026                 tiling_config |= ROW_TILING(3);
2027                 tiling_config |= SAMPLE_SPLIT(3);
2028         } else {
2029                 tiling_config |= ROW_TILING(tmp);
2030                 tiling_config |= SAMPLE_SPLIT(tmp);
2031         }
2032         tiling_config |= BANK_SWAPS(1);
2033
2034         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
2035         tmp = rdev->config.r600.max_simds -
2036                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
2037         rdev->config.r600.active_simds = tmp;
2038
2039         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
2040         tmp = 0;
2041         for (i = 0; i < rdev->config.r600.max_backends; i++)
2042                 tmp |= (1 << i);
2043         /* if all the backends are disabled, fix it up here */
2044         if ((disabled_rb_mask & tmp) == tmp) {
2045                 for (i = 0; i < rdev->config.r600.max_backends; i++)
2046                         disabled_rb_mask &= ~(1 << i);
2047         }
2048         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
2049         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2050                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
2051         tiling_config |= tmp << 16;
2052         rdev->config.r600.backend_map = tmp;
2053
2054         rdev->config.r600.tile_config = tiling_config;
2055         WREG32(GB_TILING_CONFIG, tiling_config);
2056         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
2057         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
2058         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
2059
2060         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
2061         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
2062         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
2063
2064         /* Setup some CP states */
2065         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
2066         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
2067
2068         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
2069                              SYNC_WALKER | SYNC_ALIGNER));
2070         /* Setup various GPU states */
2071         if (rdev->family == CHIP_RV670)
2072                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
2073
2074         tmp = RREG32(SX_DEBUG_1);
2075         tmp |= SMX_EVENT_RELEASE;
2076         if ((rdev->family > CHIP_R600))
2077                 tmp |= ENABLE_NEW_SMX_ADDRESS;
2078         WREG32(SX_DEBUG_1, tmp);
2079
2080         if (((rdev->family) == CHIP_R600) ||
2081             ((rdev->family) == CHIP_RV630) ||
2082             ((rdev->family) == CHIP_RV610) ||
2083             ((rdev->family) == CHIP_RV620) ||
2084             ((rdev->family) == CHIP_RS780) ||
2085             ((rdev->family) == CHIP_RS880)) {
2086                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2087         } else {
2088                 WREG32(DB_DEBUG, 0);
2089         }
2090         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2091                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
2092
2093         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2094         WREG32(VGT_NUM_INSTANCES, 0);
2095
2096         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2097         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2098
2099         tmp = RREG32(SQ_MS_FIFO_SIZES);
2100         if (((rdev->family) == CHIP_RV610) ||
2101             ((rdev->family) == CHIP_RV620) ||
2102             ((rdev->family) == CHIP_RS780) ||
2103             ((rdev->family) == CHIP_RS880)) {
2104                 tmp = (CACHE_FIFO_SIZE(0xa) |
2105                        FETCH_FIFO_HIWATER(0xa) |
2106                        DONE_FIFO_HIWATER(0xe0) |
2107                        ALU_UPDATE_FIFO_HIWATER(0x8));
2108         } else if (((rdev->family) == CHIP_R600) ||
2109                    ((rdev->family) == CHIP_RV630)) {
2110                 tmp &= ~DONE_FIFO_HIWATER(0xff);
2111                 tmp |= DONE_FIFO_HIWATER(0x4);
2112         }
2113         WREG32(SQ_MS_FIFO_SIZES, tmp);
2114
2115         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2116          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
2117          */
2118         sq_config = RREG32(SQ_CONFIG);
2119         sq_config &= ~(PS_PRIO(3) |
2120                        VS_PRIO(3) |
2121                        GS_PRIO(3) |
2122                        ES_PRIO(3));
2123         sq_config |= (DX9_CONSTS |
2124                       VC_ENABLE |
2125                       PS_PRIO(0) |
2126                       VS_PRIO(1) |
2127                       GS_PRIO(2) |
2128                       ES_PRIO(3));
2129
2130         if ((rdev->family) == CHIP_R600) {
2131                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
2132                                           NUM_VS_GPRS(124) |
2133                                           NUM_CLAUSE_TEMP_GPRS(4));
2134                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
2135                                           NUM_ES_GPRS(0));
2136                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
2137                                            NUM_VS_THREADS(48) |
2138                                            NUM_GS_THREADS(4) |
2139                                            NUM_ES_THREADS(4));
2140                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
2141                                             NUM_VS_STACK_ENTRIES(128));
2142                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
2143                                             NUM_ES_STACK_ENTRIES(0));
2144         } else if (((rdev->family) == CHIP_RV610) ||
2145                    ((rdev->family) == CHIP_RV620) ||
2146                    ((rdev->family) == CHIP_RS780) ||
2147                    ((rdev->family) == CHIP_RS880)) {
2148                 /* no vertex cache */
2149                 sq_config &= ~VC_ENABLE;
2150
2151                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2152                                           NUM_VS_GPRS(44) |
2153                                           NUM_CLAUSE_TEMP_GPRS(2));
2154                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2155                                           NUM_ES_GPRS(17));
2156                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2157                                            NUM_VS_THREADS(78) |
2158                                            NUM_GS_THREADS(4) |
2159                                            NUM_ES_THREADS(31));
2160                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2161                                             NUM_VS_STACK_ENTRIES(40));
2162                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2163                                             NUM_ES_STACK_ENTRIES(16));
2164         } else if (((rdev->family) == CHIP_RV630) ||
2165                    ((rdev->family) == CHIP_RV635)) {
2166                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2167                                           NUM_VS_GPRS(44) |
2168                                           NUM_CLAUSE_TEMP_GPRS(2));
2169                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2170                                           NUM_ES_GPRS(18));
2171                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2172                                            NUM_VS_THREADS(78) |
2173                                            NUM_GS_THREADS(4) |
2174                                            NUM_ES_THREADS(31));
2175                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2176                                             NUM_VS_STACK_ENTRIES(40));
2177                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2178                                             NUM_ES_STACK_ENTRIES(16));
2179         } else if ((rdev->family) == CHIP_RV670) {
2180                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2181                                           NUM_VS_GPRS(44) |
2182                                           NUM_CLAUSE_TEMP_GPRS(2));
2183                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2184                                           NUM_ES_GPRS(17));
2185                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2186                                            NUM_VS_THREADS(78) |
2187                                            NUM_GS_THREADS(4) |
2188                                            NUM_ES_THREADS(31));
2189                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2190                                             NUM_VS_STACK_ENTRIES(64));
2191                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2192                                             NUM_ES_STACK_ENTRIES(64));
2193         }
2194
2195         WREG32(SQ_CONFIG, sq_config);
2196         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
2197         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
2198         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2199         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2200         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2201
2202         if (((rdev->family) == CHIP_RV610) ||
2203             ((rdev->family) == CHIP_RV620) ||
2204             ((rdev->family) == CHIP_RS780) ||
2205             ((rdev->family) == CHIP_RS880)) {
2206                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2207         } else {
2208                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2209         }
2210
2211         /* More default values. 2D/3D driver should adjust as needed */
2212         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2213                                          S1_X(0x4) | S1_Y(0xc)));
2214         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2215                                          S1_X(0x2) | S1_Y(0x2) |
2216                                          S2_X(0xa) | S2_Y(0x6) |
2217                                          S3_X(0x6) | S3_Y(0xa)));
2218         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2219                                              S1_X(0x4) | S1_Y(0xc) |
2220                                              S2_X(0x1) | S2_Y(0x6) |
2221                                              S3_X(0xa) | S3_Y(0xe)));
2222         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2223                                              S5_X(0x0) | S5_Y(0x0) |
2224                                              S6_X(0xb) | S6_Y(0x4) |
2225                                              S7_X(0x7) | S7_Y(0x8)));
2226
2227         WREG32(VGT_STRMOUT_EN, 0);
2228         tmp = rdev->config.r600.max_pipes * 16;
2229         switch (rdev->family) {
2230         case CHIP_RV610:
2231         case CHIP_RV620:
2232         case CHIP_RS780:
2233         case CHIP_RS880:
2234                 tmp += 32;
2235                 break;
2236         case CHIP_RV670:
2237                 tmp += 128;
2238                 break;
2239         default:
2240                 break;
2241         }
2242         if (tmp > 256) {
2243                 tmp = 256;
2244         }
2245         WREG32(VGT_ES_PER_GS, 128);
2246         WREG32(VGT_GS_PER_ES, tmp);
2247         WREG32(VGT_GS_PER_VS, 2);
2248         WREG32(VGT_GS_VERTEX_REUSE, 16);
2249
2250         /* more default values. 2D/3D driver should adjust as needed */
2251         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2252         WREG32(VGT_STRMOUT_EN, 0);
2253         WREG32(SX_MISC, 0);
2254         WREG32(PA_SC_MODE_CNTL, 0);
2255         WREG32(PA_SC_AA_CONFIG, 0);
2256         WREG32(PA_SC_LINE_STIPPLE, 0);
2257         WREG32(SPI_INPUT_Z, 0);
2258         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2259         WREG32(CB_COLOR7_FRAG, 0);
2260
2261         /* Clear render buffer base addresses */
2262         WREG32(CB_COLOR0_BASE, 0);
2263         WREG32(CB_COLOR1_BASE, 0);
2264         WREG32(CB_COLOR2_BASE, 0);
2265         WREG32(CB_COLOR3_BASE, 0);
2266         WREG32(CB_COLOR4_BASE, 0);
2267         WREG32(CB_COLOR5_BASE, 0);
2268         WREG32(CB_COLOR6_BASE, 0);
2269         WREG32(CB_COLOR7_BASE, 0);
2270         WREG32(CB_COLOR7_FRAG, 0);
2271
2272         switch (rdev->family) {
2273         case CHIP_RV610:
2274         case CHIP_RV620:
2275         case CHIP_RS780:
2276         case CHIP_RS880:
2277                 tmp = TC_L2_SIZE(8);
2278                 break;
2279         case CHIP_RV630:
2280         case CHIP_RV635:
2281                 tmp = TC_L2_SIZE(4);
2282                 break;
2283         case CHIP_R600:
2284                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2285                 break;
2286         default:
2287                 tmp = TC_L2_SIZE(0);
2288                 break;
2289         }
2290         WREG32(TC_CNTL, tmp);
2291
2292         tmp = RREG32(HDP_HOST_PATH_CNTL);
2293         WREG32(HDP_HOST_PATH_CNTL, tmp);
2294
2295         tmp = RREG32(ARB_POP);
2296         tmp |= ENABLE_TC128;
2297         WREG32(ARB_POP, tmp);
2298
2299         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2300         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2301                                NUM_CLIP_SEQ(3)));
2302         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2303         WREG32(VC_ENHANCE, 0);
2304 }
2305
2306
2307 /*
2308  * Indirect registers accessor
2309  */
2310 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2311 {
2312         unsigned long flags;
2313         u32 r;
2314
2315         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2316         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2317         (void)RREG32(PCIE_PORT_INDEX);
2318         r = RREG32(PCIE_PORT_DATA);
2319         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2320         return r;
2321 }
2322
2323 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2324 {
2325         unsigned long flags;
2326
2327         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2328         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2329         (void)RREG32(PCIE_PORT_INDEX);
2330         WREG32(PCIE_PORT_DATA, (v));
2331         (void)RREG32(PCIE_PORT_DATA);
2332         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2333 }
2334
2335 /*
2336  * CP & Ring
2337  */
2338 void r600_cp_stop(struct radeon_device *rdev)
2339 {
2340         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2341                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2342         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2343         WREG32(SCRATCH_UMSK, 0);
2344         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2345 }
2346
2347 int r600_init_microcode(struct radeon_device *rdev)
2348 {
2349         const char *chip_name;
2350         const char *rlc_chip_name;
2351         const char *smc_chip_name = "RV770";
2352         size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
2353         char fw_name[30];
2354         int err;
2355
2356         DRM_DEBUG("\n");
2357
2358         switch (rdev->family) {
2359         case CHIP_R600:
2360                 chip_name = "R600";
2361                 rlc_chip_name = "R600";
2362                 break;
2363         case CHIP_RV610:
2364                 chip_name = "RV610";
2365                 rlc_chip_name = "R600";
2366                 break;
2367         case CHIP_RV630:
2368                 chip_name = "RV630";
2369                 rlc_chip_name = "R600";
2370                 break;
2371         case CHIP_RV620:
2372                 chip_name = "RV620";
2373                 rlc_chip_name = "R600";
2374                 break;
2375         case CHIP_RV635:
2376                 chip_name = "RV635";
2377                 rlc_chip_name = "R600";
2378                 break;
2379         case CHIP_RV670:
2380                 chip_name = "RV670";
2381                 rlc_chip_name = "R600";
2382                 break;
2383         case CHIP_RS780:
2384         case CHIP_RS880:
2385                 chip_name = "RS780";
2386                 rlc_chip_name = "R600";
2387                 break;
2388         case CHIP_RV770:
2389                 chip_name = "RV770";
2390                 rlc_chip_name = "R700";
2391                 smc_chip_name = "RV770";
2392                 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
2393                 break;
2394         case CHIP_RV730:
2395                 chip_name = "RV730";
2396                 rlc_chip_name = "R700";
2397                 smc_chip_name = "RV730";
2398                 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
2399                 break;
2400         case CHIP_RV710:
2401                 chip_name = "RV710";
2402                 rlc_chip_name = "R700";
2403                 smc_chip_name = "RV710";
2404                 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2405                 break;
2406         case CHIP_RV740:
2407                 chip_name = "RV730";
2408                 rlc_chip_name = "R700";
2409                 smc_chip_name = "RV740";
2410                 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
2411                 break;
2412         case CHIP_CEDAR:
2413                 chip_name = "CEDAR";
2414                 rlc_chip_name = "CEDAR";
2415                 smc_chip_name = "CEDAR";
2416                 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
2417                 break;
2418         case CHIP_REDWOOD:
2419                 chip_name = "REDWOOD";
2420                 rlc_chip_name = "REDWOOD";
2421                 smc_chip_name = "REDWOOD";
2422                 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
2423                 break;
2424         case CHIP_JUNIPER:
2425                 chip_name = "JUNIPER";
2426                 rlc_chip_name = "JUNIPER";
2427                 smc_chip_name = "JUNIPER";
2428                 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
2429                 break;
2430         case CHIP_CYPRESS:
2431         case CHIP_HEMLOCK:
2432                 chip_name = "CYPRESS";
2433                 rlc_chip_name = "CYPRESS";
2434                 smc_chip_name = "CYPRESS";
2435                 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
2436                 break;
2437         case CHIP_PALM:
2438                 chip_name = "PALM";
2439                 rlc_chip_name = "SUMO";
2440                 break;
2441         case CHIP_SUMO:
2442                 chip_name = "SUMO";
2443                 rlc_chip_name = "SUMO";
2444                 break;
2445         case CHIP_SUMO2:
2446                 chip_name = "SUMO2";
2447                 rlc_chip_name = "SUMO";
2448                 break;
2449         default: BUG();
2450         }
2451
2452         if (rdev->family >= CHIP_CEDAR) {
2453                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2454                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2455                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2456         } else if (rdev->family >= CHIP_RV770) {
2457                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2458                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2459                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2460         } else {
2461                 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2462                 me_req_size = R600_PM4_UCODE_SIZE * 12;
2463                 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
2464         }
2465
2466         DRM_INFO("Loading %s Microcode\n", chip_name);
2467
2468         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2469         err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2470         if (err)
2471                 goto out;
2472         if (rdev->pfp_fw->size != pfp_req_size) {
2473                 printk(KERN_ERR
2474                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2475                        rdev->pfp_fw->size, fw_name);
2476                 err = -EINVAL;
2477                 goto out;
2478         }
2479
2480         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2481         err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2482         if (err)
2483                 goto out;
2484         if (rdev->me_fw->size != me_req_size) {
2485                 printk(KERN_ERR
2486                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2487                        rdev->me_fw->size, fw_name);
2488                 err = -EINVAL;
2489         }
2490
2491         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2492         err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2493         if (err)
2494                 goto out;
2495         if (rdev->rlc_fw->size != rlc_req_size) {
2496                 printk(KERN_ERR
2497                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2498                        rdev->rlc_fw->size, fw_name);
2499                 err = -EINVAL;
2500         }
2501
2502         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2503                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name);
2504                 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2505                 if (err) {
2506                         printk(KERN_ERR
2507                                "smc: error loading firmware \"%s\"\n",
2508                                fw_name);
2509                         release_firmware(rdev->smc_fw);
2510                         rdev->smc_fw = NULL;
2511                         err = 0;
2512                 } else if (rdev->smc_fw->size != smc_req_size) {
2513                         printk(KERN_ERR
2514                                "smc: Bogus length %zu in firmware \"%s\"\n",
2515                                rdev->smc_fw->size, fw_name);
2516                         err = -EINVAL;
2517                 }
2518         }
2519
2520 out:
2521         if (err) {
2522                 if (err != -EINVAL)
2523                         printk(KERN_ERR
2524                                "r600_cp: Failed to load firmware \"%s\"\n",
2525                                fw_name);
2526                 release_firmware(rdev->pfp_fw);
2527                 rdev->pfp_fw = NULL;
2528                 release_firmware(rdev->me_fw);
2529                 rdev->me_fw = NULL;
2530                 release_firmware(rdev->rlc_fw);
2531                 rdev->rlc_fw = NULL;
2532                 release_firmware(rdev->smc_fw);
2533                 rdev->smc_fw = NULL;
2534         }
2535         return err;
2536 }
2537
2538 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2539                       struct radeon_ring *ring)
2540 {
2541         u32 rptr;
2542
2543         if (rdev->wb.enabled)
2544                 rptr = rdev->wb.wb[ring->rptr_offs/4];
2545         else
2546                 rptr = RREG32(R600_CP_RB_RPTR);
2547
2548         return rptr;
2549 }
2550
2551 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2552                       struct radeon_ring *ring)
2553 {
2554         u32 wptr;
2555
2556         wptr = RREG32(R600_CP_RB_WPTR);
2557
2558         return wptr;
2559 }
2560
2561 void r600_gfx_set_wptr(struct radeon_device *rdev,
2562                        struct radeon_ring *ring)
2563 {
2564         WREG32(R600_CP_RB_WPTR, ring->wptr);
2565         (void)RREG32(R600_CP_RB_WPTR);
2566 }
2567
2568 static int r600_cp_load_microcode(struct radeon_device *rdev)
2569 {
2570         const __be32 *fw_data;
2571         int i;
2572
2573         if (!rdev->me_fw || !rdev->pfp_fw)
2574                 return -EINVAL;
2575
2576         r600_cp_stop(rdev);
2577
2578         WREG32(CP_RB_CNTL,
2579 #ifdef __BIG_ENDIAN
2580                BUF_SWAP_32BIT |
2581 #endif
2582                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2583
2584         /* Reset cp */
2585         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2586         RREG32(GRBM_SOFT_RESET);
2587         mdelay(15);
2588         WREG32(GRBM_SOFT_RESET, 0);
2589
2590         WREG32(CP_ME_RAM_WADDR, 0);
2591
2592         fw_data = (const __be32 *)rdev->me_fw->data;
2593         WREG32(CP_ME_RAM_WADDR, 0);
2594         for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
2595                 WREG32(CP_ME_RAM_DATA,
2596                        be32_to_cpup(fw_data++));
2597
2598         fw_data = (const __be32 *)rdev->pfp_fw->data;
2599         WREG32(CP_PFP_UCODE_ADDR, 0);
2600         for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
2601                 WREG32(CP_PFP_UCODE_DATA,
2602                        be32_to_cpup(fw_data++));
2603
2604         WREG32(CP_PFP_UCODE_ADDR, 0);
2605         WREG32(CP_ME_RAM_WADDR, 0);
2606         WREG32(CP_ME_RAM_RADDR, 0);
2607         return 0;
2608 }
2609
2610 int r600_cp_start(struct radeon_device *rdev)
2611 {
2612         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2613         int r;
2614         uint32_t cp_me;
2615
2616         r = radeon_ring_lock(rdev, ring, 7);
2617         if (r) {
2618                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2619                 return r;
2620         }
2621         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2622         radeon_ring_write(ring, 0x1);
2623         if (rdev->family >= CHIP_RV770) {
2624                 radeon_ring_write(ring, 0x0);
2625                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2626         } else {
2627                 radeon_ring_write(ring, 0x3);
2628                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2629         }
2630         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2631         radeon_ring_write(ring, 0);
2632         radeon_ring_write(ring, 0);
2633         radeon_ring_unlock_commit(rdev, ring, false);
2634
2635         cp_me = 0xff;
2636         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2637         return 0;
2638 }
2639
2640 int r600_cp_resume(struct radeon_device *rdev)
2641 {
2642         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2643         u32 tmp;
2644         u32 rb_bufsz;
2645         int r;
2646
2647         /* Reset cp */
2648         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2649         RREG32(GRBM_SOFT_RESET);
2650         mdelay(15);
2651         WREG32(GRBM_SOFT_RESET, 0);
2652
2653         /* Set ring buffer size */
2654         rb_bufsz = order_base_2(ring->ring_size / 8);
2655         tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2656 #ifdef __BIG_ENDIAN
2657         tmp |= BUF_SWAP_32BIT;
2658 #endif
2659         WREG32(CP_RB_CNTL, tmp);
2660         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2661
2662         /* Set the write pointer delay */
2663         WREG32(CP_RB_WPTR_DELAY, 0);
2664
2665         /* Initialize the ring buffer's read and write pointers */
2666         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2667         WREG32(CP_RB_RPTR_WR, 0);
2668         ring->wptr = 0;
2669         WREG32(CP_RB_WPTR, ring->wptr);
2670
2671         /* set the wb address whether it's enabled or not */
2672         WREG32(CP_RB_RPTR_ADDR,
2673                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2674         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2675         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2676
2677         if (rdev->wb.enabled)
2678                 WREG32(SCRATCH_UMSK, 0xff);
2679         else {
2680                 tmp |= RB_NO_UPDATE;
2681                 WREG32(SCRATCH_UMSK, 0);
2682         }
2683
2684         mdelay(1);
2685         WREG32(CP_RB_CNTL, tmp);
2686
2687         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2688         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2689
2690         r600_cp_start(rdev);
2691         ring->ready = true;
2692         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2693         if (r) {
2694                 ring->ready = false;
2695                 return r;
2696         }
2697
2698         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2699                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2700
2701         return 0;
2702 }
2703
2704 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2705 {
2706         u32 rb_bufsz;
2707         int r;
2708
2709         /* Align ring size */
2710         rb_bufsz = order_base_2(ring_size / 8);
2711         ring_size = (1 << (rb_bufsz + 1)) * 4;
2712         ring->ring_size = ring_size;
2713         ring->align_mask = 16 - 1;
2714
2715         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2716                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2717                 if (r) {
2718                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2719                         ring->rptr_save_reg = 0;
2720                 }
2721         }
2722 }
2723
2724 void r600_cp_fini(struct radeon_device *rdev)
2725 {
2726         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2727         r600_cp_stop(rdev);
2728         radeon_ring_fini(rdev, ring);
2729         radeon_scratch_free(rdev, ring->rptr_save_reg);
2730 }
2731
2732 /*
2733  * GPU scratch registers helpers function.
2734  */
2735 void r600_scratch_init(struct radeon_device *rdev)
2736 {
2737         int i;
2738
2739         rdev->scratch.num_reg = 7;
2740         rdev->scratch.reg_base = SCRATCH_REG0;
2741         for (i = 0; i < rdev->scratch.num_reg; i++) {
2742                 rdev->scratch.free[i] = true;
2743                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2744         }
2745 }
2746
2747 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2748 {
2749         uint32_t scratch;
2750         uint32_t tmp = 0;
2751         unsigned i;
2752         int r;
2753
2754         r = radeon_scratch_get(rdev, &scratch);
2755         if (r) {
2756                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2757                 return r;
2758         }
2759         WREG32(scratch, 0xCAFEDEAD);
2760         r = radeon_ring_lock(rdev, ring, 3);
2761         if (r) {
2762                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2763                 radeon_scratch_free(rdev, scratch);
2764                 return r;
2765         }
2766         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2767         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2768         radeon_ring_write(ring, 0xDEADBEEF);
2769         radeon_ring_unlock_commit(rdev, ring, false);
2770         for (i = 0; i < rdev->usec_timeout; i++) {
2771                 tmp = RREG32(scratch);
2772                 if (tmp == 0xDEADBEEF)
2773                         break;
2774                 DRM_UDELAY(1);
2775         }
2776         if (i < rdev->usec_timeout) {
2777                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2778         } else {
2779                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2780                           ring->idx, scratch, tmp);
2781                 r = -EINVAL;
2782         }
2783         radeon_scratch_free(rdev, scratch);
2784         return r;
2785 }
2786
2787 /*
2788  * CP fences/semaphores
2789  */
2790
2791 void r600_fence_ring_emit(struct radeon_device *rdev,
2792                           struct radeon_fence *fence)
2793 {
2794         struct radeon_ring *ring = &rdev->ring[fence->ring];
2795         u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
2796                 PACKET3_SH_ACTION_ENA;
2797
2798         if (rdev->family >= CHIP_RV770)
2799                 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
2800
2801         if (rdev->wb.use_event) {
2802                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2803                 /* flush read cache over gart */
2804                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2805                 radeon_ring_write(ring, cp_coher_cntl);
2806                 radeon_ring_write(ring, 0xFFFFFFFF);
2807                 radeon_ring_write(ring, 0);
2808                 radeon_ring_write(ring, 10); /* poll interval */
2809                 /* EVENT_WRITE_EOP - flush caches, send int */
2810                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2811                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2812                 radeon_ring_write(ring, lower_32_bits(addr));
2813                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2814                 radeon_ring_write(ring, fence->seq);
2815                 radeon_ring_write(ring, 0);
2816         } else {
2817                 /* flush read cache over gart */
2818                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2819                 radeon_ring_write(ring, cp_coher_cntl);
2820                 radeon_ring_write(ring, 0xFFFFFFFF);
2821                 radeon_ring_write(ring, 0);
2822                 radeon_ring_write(ring, 10); /* poll interval */
2823                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2824                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2825                 /* wait for 3D idle clean */
2826                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2827                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2828                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2829                 /* Emit fence sequence & fire IRQ */
2830                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2831                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2832                 radeon_ring_write(ring, fence->seq);
2833                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2834                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2835                 radeon_ring_write(ring, RB_INT_STAT);
2836         }
2837 }
2838
2839 /**
2840  * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2841  *
2842  * @rdev: radeon_device pointer
2843  * @ring: radeon ring buffer object
2844  * @semaphore: radeon semaphore object
2845  * @emit_wait: Is this a sempahore wait?
2846  *
2847  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2848  * from running ahead of semaphore waits.
2849  */
2850 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2851                               struct radeon_ring *ring,
2852                               struct radeon_semaphore *semaphore,
2853                               bool emit_wait)
2854 {
2855         uint64_t addr = semaphore->gpu_addr;
2856         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2857
2858         if (rdev->family < CHIP_CAYMAN)
2859                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2860
2861         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2862         radeon_ring_write(ring, lower_32_bits(addr));
2863         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2864
2865         /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
2866         if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
2867                 /* Prevent the PFP from running ahead of the semaphore wait */
2868                 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2869                 radeon_ring_write(ring, 0x0);
2870         }
2871
2872         return true;
2873 }
2874
2875 /**
2876  * r600_copy_cpdma - copy pages using the CP DMA engine
2877  *
2878  * @rdev: radeon_device pointer
2879  * @src_offset: src GPU address
2880  * @dst_offset: dst GPU address
2881  * @num_gpu_pages: number of GPU pages to xfer
2882  * @fence: radeon fence object
2883  *
2884  * Copy GPU paging using the CP DMA engine (r6xx+).
2885  * Used by the radeon ttm implementation to move pages if
2886  * registered as the asic copy callback.
2887  */
2888 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2889                                      uint64_t src_offset, uint64_t dst_offset,
2890                                      unsigned num_gpu_pages,
2891                                      struct reservation_object *resv)
2892 {
2893         struct radeon_fence *fence;
2894         struct radeon_sync sync;
2895         int ring_index = rdev->asic->copy.blit_ring_index;
2896         struct radeon_ring *ring = &rdev->ring[ring_index];
2897         u32 size_in_bytes, cur_size_in_bytes, tmp;
2898         int i, num_loops;
2899         int r = 0;
2900
2901         radeon_sync_create(&sync);
2902
2903         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2904         num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
2905         r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2906         if (r) {
2907                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2908                 radeon_sync_free(rdev, &sync, NULL);
2909                 return ERR_PTR(r);
2910         }
2911
2912         radeon_sync_resv(rdev, &sync, resv, false);
2913         radeon_sync_rings(rdev, &sync, ring->idx);
2914
2915         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2916         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2917         radeon_ring_write(ring, WAIT_3D_IDLE_bit);
2918         for (i = 0; i < num_loops; i++) {
2919                 cur_size_in_bytes = size_in_bytes;
2920                 if (cur_size_in_bytes > 0x1fffff)
2921                         cur_size_in_bytes = 0x1fffff;
2922                 size_in_bytes -= cur_size_in_bytes;
2923                 tmp = upper_32_bits(src_offset) & 0xff;
2924                 if (size_in_bytes == 0)
2925                         tmp |= PACKET3_CP_DMA_CP_SYNC;
2926                 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
2927                 radeon_ring_write(ring, lower_32_bits(src_offset));
2928                 radeon_ring_write(ring, tmp);
2929                 radeon_ring_write(ring, lower_32_bits(dst_offset));
2930                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2931                 radeon_ring_write(ring, cur_size_in_bytes);
2932                 src_offset += cur_size_in_bytes;
2933                 dst_offset += cur_size_in_bytes;
2934         }
2935         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2936         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2937         radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
2938
2939         r = radeon_fence_emit(rdev, &fence, ring->idx);
2940         if (r) {
2941                 radeon_ring_unlock_undo(rdev, ring);
2942                 radeon_sync_free(rdev, &sync, NULL);
2943                 return ERR_PTR(r);
2944         }
2945
2946         radeon_ring_unlock_commit(rdev, ring, false);
2947         radeon_sync_free(rdev, &sync, fence);
2948
2949         return fence;
2950 }
2951
2952 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2953                          uint32_t tiling_flags, uint32_t pitch,
2954                          uint32_t offset, uint32_t obj_size)
2955 {
2956         /* FIXME: implement */
2957         return 0;
2958 }
2959
2960 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2961 {
2962         /* FIXME: implement */
2963 }
2964
2965 static int r600_startup(struct radeon_device *rdev)
2966 {
2967         struct radeon_ring *ring;
2968         int r;
2969
2970         /* enable pcie gen2 link */
2971         r600_pcie_gen2_enable(rdev);
2972
2973         /* scratch needs to be initialized before MC */
2974         r = r600_vram_scratch_init(rdev);
2975         if (r)
2976                 return r;
2977
2978         r600_mc_program(rdev);
2979
2980         if (rdev->flags & RADEON_IS_AGP) {
2981                 r600_agp_enable(rdev);
2982         } else {
2983                 r = r600_pcie_gart_enable(rdev);
2984                 if (r)
2985                         return r;
2986         }
2987         r600_gpu_init(rdev);
2988
2989         /* allocate wb buffer */
2990         r = radeon_wb_init(rdev);
2991         if (r)
2992                 return r;
2993
2994         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2995         if (r) {
2996                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2997                 return r;
2998         }
2999
3000         if (rdev->has_uvd) {
3001                 r = uvd_v1_0_resume(rdev);
3002                 if (!r) {
3003                         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
3004                         if (r) {
3005                                 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
3006                         }
3007                 }
3008                 if (r)
3009                         rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3010         }
3011
3012         /* Enable IRQ */
3013         if (!rdev->irq.installed) {
3014                 r = radeon_irq_kms_init(rdev);
3015                 if (r)
3016                         return r;
3017         }
3018
3019         r = r600_irq_init(rdev);
3020         if (r) {
3021                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3022                 radeon_irq_kms_fini(rdev);
3023                 return r;
3024         }
3025         r600_irq_set(rdev);
3026
3027         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3028         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3029                              RADEON_CP_PACKET2);
3030         if (r)
3031                 return r;
3032
3033         r = r600_cp_load_microcode(rdev);
3034         if (r)
3035                 return r;
3036         r = r600_cp_resume(rdev);
3037         if (r)
3038                 return r;
3039
3040         if (rdev->has_uvd) {
3041                 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3042                 if (ring->ring_size) {
3043                         r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
3044                                              RADEON_CP_PACKET2);
3045                         if (!r)
3046                                 r = uvd_v1_0_init(rdev);
3047                         if (r)
3048                                 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
3049                 }
3050         }
3051
3052         r = radeon_ib_pool_init(rdev);
3053         if (r) {
3054                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3055                 return r;
3056         }
3057
3058         r = radeon_audio_init(rdev);
3059         if (r) {
3060                 DRM_ERROR("radeon: audio init failed\n");
3061                 return r;
3062         }
3063
3064         return 0;
3065 }
3066
3067 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3068 {
3069         uint32_t temp;
3070
3071         temp = RREG32(CONFIG_CNTL);
3072         if (state == false) {
3073                 temp &= ~(1<<0);
3074                 temp |= (1<<1);
3075         } else {
3076                 temp &= ~(1<<1);
3077         }
3078         WREG32(CONFIG_CNTL, temp);
3079 }
3080
3081 int r600_resume(struct radeon_device *rdev)
3082 {
3083         int r;
3084
3085         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3086          * posting will perform necessary task to bring back GPU into good
3087          * shape.
3088          */
3089         /* post card */
3090         atom_asic_init(rdev->mode_info.atom_context);
3091
3092         if (rdev->pm.pm_method == PM_METHOD_DPM)
3093                 radeon_pm_resume(rdev);
3094
3095         rdev->accel_working = true;
3096         r = r600_startup(rdev);
3097         if (r) {
3098                 DRM_ERROR("r600 startup failed on resume\n");
3099                 rdev->accel_working = false;
3100                 return r;
3101         }
3102
3103         return r;
3104 }
3105
3106 int r600_suspend(struct radeon_device *rdev)
3107 {
3108         radeon_pm_suspend(rdev);
3109         radeon_audio_fini(rdev);
3110         r600_cp_stop(rdev);
3111         if (rdev->has_uvd) {
3112                 uvd_v1_0_fini(rdev);
3113                 radeon_uvd_suspend(rdev);
3114         }
3115         r600_irq_suspend(rdev);
3116         radeon_wb_disable(rdev);
3117         r600_pcie_gart_disable(rdev);
3118
3119         return 0;
3120 }
3121
3122 /* Plan is to move initialization in that function and use
3123  * helper function so that radeon_device_init pretty much
3124  * do nothing more than calling asic specific function. This
3125  * should also allow to remove a bunch of callback function
3126  * like vram_info.
3127  */
3128 int r600_init(struct radeon_device *rdev)
3129 {
3130         int r;
3131
3132         if (r600_debugfs_mc_info_init(rdev)) {
3133                 DRM_ERROR("Failed to register debugfs file for mc !\n");
3134         }
3135         /* Read BIOS */
3136         if (!radeon_get_bios(rdev)) {
3137                 if (ASIC_IS_AVIVO(rdev))
3138                         return -EINVAL;
3139         }
3140         /* Must be an ATOMBIOS */
3141         if (!rdev->is_atom_bios) {
3142                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3143                 return -EINVAL;
3144         }
3145         r = radeon_atombios_init(rdev);
3146         if (r)
3147                 return r;
3148         /* Post card if necessary */
3149         if (!radeon_card_posted(rdev)) {
3150                 if (!rdev->bios) {
3151                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3152                         return -EINVAL;
3153                 }
3154                 DRM_INFO("GPU not posted. posting now...\n");
3155                 atom_asic_init(rdev->mode_info.atom_context);
3156         }
3157         /* Initialize scratch registers */
3158         r600_scratch_init(rdev);
3159         /* Initialize surface registers */
3160         radeon_surface_init(rdev);
3161         /* Initialize clocks */
3162         radeon_get_clock_info(rdev->ddev);
3163         /* Fence driver */
3164         r = radeon_fence_driver_init(rdev);
3165         if (r)
3166                 return r;
3167         if (rdev->flags & RADEON_IS_AGP) {
3168                 r = radeon_agp_init(rdev);
3169                 if (r)
3170                         radeon_agp_disable(rdev);
3171         }
3172         r = r600_mc_init(rdev);
3173         if (r)
3174                 return r;
3175         /* Memory manager */
3176         r = radeon_bo_init(rdev);
3177         if (r)
3178                 return r;
3179
3180         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3181                 r = r600_init_microcode(rdev);
3182                 if (r) {
3183                         DRM_ERROR("Failed to load firmware!\n");
3184                         return r;
3185                 }
3186         }
3187
3188         /* Initialize power management */
3189         radeon_pm_init(rdev);
3190
3191         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3192         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3193
3194         if (rdev->has_uvd) {
3195                 r = radeon_uvd_init(rdev);
3196                 if (!r) {
3197                         rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3198                         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
3199                 }
3200         }
3201
3202         rdev->ih.ring_obj = NULL;
3203         r600_ih_ring_init(rdev, 64 * 1024);
3204
3205         r = r600_pcie_gart_init(rdev);
3206         if (r)
3207                 return r;
3208
3209         rdev->accel_working = true;
3210         r = r600_startup(rdev);
3211         if (r) {
3212                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3213                 r600_cp_fini(rdev);
3214                 r600_irq_fini(rdev);
3215                 radeon_wb_fini(rdev);
3216                 radeon_ib_pool_fini(rdev);
3217                 radeon_irq_kms_fini(rdev);
3218                 r600_pcie_gart_fini(rdev);
3219                 rdev->accel_working = false;
3220         }
3221
3222         return 0;
3223 }
3224
3225 void r600_fini(struct radeon_device *rdev)
3226 {
3227         radeon_pm_fini(rdev);
3228         radeon_audio_fini(rdev);
3229         r600_cp_fini(rdev);
3230         r600_irq_fini(rdev);
3231         if (rdev->has_uvd) {
3232                 uvd_v1_0_fini(rdev);
3233                 radeon_uvd_fini(rdev);
3234         }
3235         radeon_wb_fini(rdev);
3236         radeon_ib_pool_fini(rdev);
3237         radeon_irq_kms_fini(rdev);
3238         r600_pcie_gart_fini(rdev);
3239         r600_vram_scratch_fini(rdev);
3240         radeon_agp_fini(rdev);
3241         radeon_gem_fini(rdev);
3242         radeon_fence_driver_fini(rdev);
3243         radeon_bo_fini(rdev);
3244         radeon_atombios_fini(rdev);
3245         kfree(rdev->bios);
3246         rdev->bios = NULL;
3247 }
3248
3249
3250 /*
3251  * CS stuff
3252  */
3253 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3254 {
3255         struct radeon_ring *ring = &rdev->ring[ib->ring];
3256         u32 next_rptr;
3257
3258         if (ring->rptr_save_reg) {
3259                 next_rptr = ring->wptr + 3 + 4;
3260                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3261                 radeon_ring_write(ring, ((ring->rptr_save_reg -
3262                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3263                 radeon_ring_write(ring, next_rptr);
3264         } else if (rdev->wb.enabled) {
3265                 next_rptr = ring->wptr + 5 + 4;
3266                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3267                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3268                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3269                 radeon_ring_write(ring, next_rptr);
3270                 radeon_ring_write(ring, 0);
3271         }
3272
3273         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3274         radeon_ring_write(ring,
3275 #ifdef __BIG_ENDIAN
3276                           (2 << 0) |
3277 #endif
3278                           (ib->gpu_addr & 0xFFFFFFFC));
3279         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3280         radeon_ring_write(ring, ib->length_dw);
3281 }
3282
3283 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3284 {
3285         struct radeon_ib ib;
3286         uint32_t scratch;
3287         uint32_t tmp = 0;
3288         unsigned i;
3289         int r;
3290
3291         r = radeon_scratch_get(rdev, &scratch);
3292         if (r) {
3293                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3294                 return r;
3295         }
3296         WREG32(scratch, 0xCAFEDEAD);
3297         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3298         if (r) {
3299                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3300                 goto free_scratch;
3301         }
3302         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3303         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3304         ib.ptr[2] = 0xDEADBEEF;
3305         ib.length_dw = 3;
3306         r = radeon_ib_schedule(rdev, &ib, NULL, false);
3307         if (r) {
3308                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3309                 goto free_ib;
3310         }
3311         r = radeon_fence_wait(ib.fence, false);
3312         if (r) {
3313                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3314                 goto free_ib;
3315         }
3316         for (i = 0; i < rdev->usec_timeout; i++) {
3317                 tmp = RREG32(scratch);
3318                 if (tmp == 0xDEADBEEF)
3319                         break;
3320                 DRM_UDELAY(1);
3321         }
3322         if (i < rdev->usec_timeout) {
3323                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3324         } else {
3325                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3326                           scratch, tmp);
3327                 r = -EINVAL;
3328         }
3329 free_ib:
3330         radeon_ib_free(rdev, &ib);
3331 free_scratch:
3332         radeon_scratch_free(rdev, scratch);
3333         return r;
3334 }
3335
3336 /*
3337  * Interrupts
3338  *
3339  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3340  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3341  * writing to the ring and the GPU consuming, the GPU writes to the ring
3342  * and host consumes.  As the host irq handler processes interrupts, it
3343  * increments the rptr.  When the rptr catches up with the wptr, all the
3344  * current interrupts have been processed.
3345  */
3346
3347 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3348 {
3349         u32 rb_bufsz;
3350
3351         /* Align ring size */
3352         rb_bufsz = order_base_2(ring_size / 4);
3353         ring_size = (1 << rb_bufsz) * 4;
3354         rdev->ih.ring_size = ring_size;
3355         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3356         rdev->ih.rptr = 0;
3357 }
3358
3359 int r600_ih_ring_alloc(struct radeon_device *rdev)
3360 {
3361         int r;
3362
3363         /* Allocate ring buffer */
3364         if (rdev->ih.ring_obj == NULL) {
3365                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3366                                      PAGE_SIZE, true,
3367                                      RADEON_GEM_DOMAIN_GTT, 0,
3368                                      NULL, NULL, &rdev->ih.ring_obj);
3369                 if (r) {
3370                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3371                         return r;
3372                 }
3373                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3374                 if (unlikely(r != 0))
3375                         return r;
3376                 r = radeon_bo_pin(rdev->ih.ring_obj,
3377                                   RADEON_GEM_DOMAIN_GTT,
3378                                   &rdev->ih.gpu_addr);
3379                 if (r) {
3380                         radeon_bo_unreserve(rdev->ih.ring_obj);
3381                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3382                         return r;
3383                 }
3384                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3385                                    (void **)&rdev->ih.ring);
3386                 radeon_bo_unreserve(rdev->ih.ring_obj);
3387                 if (r) {
3388                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3389                         return r;
3390                 }
3391         }
3392         return 0;
3393 }
3394
3395 void r600_ih_ring_fini(struct radeon_device *rdev)
3396 {
3397         int r;
3398         if (rdev->ih.ring_obj) {
3399                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3400                 if (likely(r == 0)) {
3401                         radeon_bo_kunmap(rdev->ih.ring_obj);
3402                         radeon_bo_unpin(rdev->ih.ring_obj);
3403                         radeon_bo_unreserve(rdev->ih.ring_obj);
3404                 }
3405                 radeon_bo_unref(&rdev->ih.ring_obj);
3406                 rdev->ih.ring = NULL;
3407                 rdev->ih.ring_obj = NULL;
3408         }
3409 }
3410
3411 void r600_rlc_stop(struct radeon_device *rdev)
3412 {
3413
3414         if ((rdev->family >= CHIP_RV770) &&
3415             (rdev->family <= CHIP_RV740)) {
3416                 /* r7xx asics need to soft reset RLC before halting */
3417                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3418                 RREG32(SRBM_SOFT_RESET);
3419                 mdelay(15);
3420                 WREG32(SRBM_SOFT_RESET, 0);
3421                 RREG32(SRBM_SOFT_RESET);
3422         }
3423
3424         WREG32(RLC_CNTL, 0);
3425 }
3426
3427 static void r600_rlc_start(struct radeon_device *rdev)
3428 {
3429         WREG32(RLC_CNTL, RLC_ENABLE);
3430 }
3431
3432 static int r600_rlc_resume(struct radeon_device *rdev)
3433 {
3434         u32 i;
3435         const __be32 *fw_data;
3436
3437         if (!rdev->rlc_fw)
3438                 return -EINVAL;
3439
3440         r600_rlc_stop(rdev);
3441
3442         WREG32(RLC_HB_CNTL, 0);
3443
3444         WREG32(RLC_HB_BASE, 0);
3445         WREG32(RLC_HB_RPTR, 0);
3446         WREG32(RLC_HB_WPTR, 0);
3447         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3448         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3449         WREG32(RLC_MC_CNTL, 0);
3450         WREG32(RLC_UCODE_CNTL, 0);
3451
3452         fw_data = (const __be32 *)rdev->rlc_fw->data;
3453         if (rdev->family >= CHIP_RV770) {
3454                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3455                         WREG32(RLC_UCODE_ADDR, i);
3456                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3457                 }
3458         } else {
3459                 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
3460                         WREG32(RLC_UCODE_ADDR, i);
3461                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3462                 }
3463         }
3464         WREG32(RLC_UCODE_ADDR, 0);
3465
3466         r600_rlc_start(rdev);
3467
3468         return 0;
3469 }
3470
3471 static void r600_enable_interrupts(struct radeon_device *rdev)
3472 {
3473         u32 ih_cntl = RREG32(IH_CNTL);
3474         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3475
3476         ih_cntl |= ENABLE_INTR;
3477         ih_rb_cntl |= IH_RB_ENABLE;
3478         WREG32(IH_CNTL, ih_cntl);
3479         WREG32(IH_RB_CNTL, ih_rb_cntl);
3480         rdev->ih.enabled = true;
3481 }
3482
3483 void r600_disable_interrupts(struct radeon_device *rdev)
3484 {
3485         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3486         u32 ih_cntl = RREG32(IH_CNTL);
3487
3488         ih_rb_cntl &= ~IH_RB_ENABLE;
3489         ih_cntl &= ~ENABLE_INTR;
3490         WREG32(IH_RB_CNTL, ih_rb_cntl);
3491         WREG32(IH_CNTL, ih_cntl);
3492         /* set rptr, wptr to 0 */
3493         WREG32(IH_RB_RPTR, 0);
3494         WREG32(IH_RB_WPTR, 0);
3495         rdev->ih.enabled = false;
3496         rdev->ih.rptr = 0;
3497 }
3498
3499 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3500 {
3501         u32 tmp;
3502
3503         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3504         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3505         WREG32(DMA_CNTL, tmp);
3506         WREG32(GRBM_INT_CNTL, 0);
3507         WREG32(DxMODE_INT_MASK, 0);
3508         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3509         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3510         if (ASIC_IS_DCE3(rdev)) {
3511                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3512                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3513                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3514                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3515                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3516                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3517                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3518                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3519                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3520                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3521                 if (ASIC_IS_DCE32(rdev)) {
3522                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3523                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3524                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3525                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3526                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3527                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3528                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3529                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3530                 } else {
3531                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3532                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3533                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3534                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3535                 }
3536         } else {
3537                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3538                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3539                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3540                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3541                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3542                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3543                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3544                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3545                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3546                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3547                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3548                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3549         }
3550 }
3551
3552 int r600_irq_init(struct radeon_device *rdev)
3553 {
3554         int ret = 0;
3555         int rb_bufsz;
3556         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3557
3558         /* allocate ring */
3559         ret = r600_ih_ring_alloc(rdev);
3560         if (ret)
3561                 return ret;
3562
3563         /* disable irqs */
3564         r600_disable_interrupts(rdev);
3565
3566         /* init rlc */
3567         if (rdev->family >= CHIP_CEDAR)
3568                 ret = evergreen_rlc_resume(rdev);
3569         else
3570                 ret = r600_rlc_resume(rdev);
3571         if (ret) {
3572                 r600_ih_ring_fini(rdev);
3573                 return ret;
3574         }
3575
3576         /* setup interrupt control */
3577         /* set dummy read address to ring address */
3578         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3579         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3580         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3581          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3582          */
3583         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3584         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3585         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3586         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3587
3588         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3589         rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3590
3591         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3592                       IH_WPTR_OVERFLOW_CLEAR |
3593                       (rb_bufsz << 1));
3594
3595         if (rdev->wb.enabled)
3596                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3597
3598         /* set the writeback address whether it's enabled or not */
3599         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3600         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3601
3602         WREG32(IH_RB_CNTL, ih_rb_cntl);
3603
3604         /* set rptr, wptr to 0 */
3605         WREG32(IH_RB_RPTR, 0);
3606         WREG32(IH_RB_WPTR, 0);
3607
3608         /* Default settings for IH_CNTL (disabled at first) */
3609         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3610         /* RPTR_REARM only works if msi's are enabled */
3611         if (rdev->msi_enabled)
3612                 ih_cntl |= RPTR_REARM;
3613         WREG32(IH_CNTL, ih_cntl);
3614
3615         /* force the active interrupt state to all disabled */
3616         if (rdev->family >= CHIP_CEDAR)
3617                 evergreen_disable_interrupt_state(rdev);
3618         else
3619                 r600_disable_interrupt_state(rdev);
3620
3621         /* at this point everything should be setup correctly to enable master */
3622         pci_set_master(rdev->pdev);
3623
3624         /* enable irqs */
3625         r600_enable_interrupts(rdev);
3626
3627         return ret;
3628 }
3629
3630 void r600_irq_suspend(struct radeon_device *rdev)
3631 {
3632         r600_irq_disable(rdev);
3633         r600_rlc_stop(rdev);
3634 }
3635
3636 void r600_irq_fini(struct radeon_device *rdev)
3637 {
3638         r600_irq_suspend(rdev);
3639         r600_ih_ring_fini(rdev);
3640 }
3641
3642 int r600_irq_set(struct radeon_device *rdev)
3643 {
3644         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3645         u32 mode_int = 0;
3646         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3647         u32 grbm_int_cntl = 0;
3648         u32 hdmi0, hdmi1;
3649         u32 dma_cntl;
3650         u32 thermal_int = 0;
3651
3652         if (!rdev->irq.installed) {
3653                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3654                 return -EINVAL;
3655         }
3656         /* don't enable anything if the ih is disabled */
3657         if (!rdev->ih.enabled) {
3658                 r600_disable_interrupts(rdev);
3659                 /* force the active interrupt state to all disabled */
3660                 r600_disable_interrupt_state(rdev);
3661                 return 0;
3662         }
3663
3664         if (ASIC_IS_DCE3(rdev)) {
3665                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3666                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3667                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3668                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3669                 if (ASIC_IS_DCE32(rdev)) {
3670                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3671                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3672                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3673                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3674                 } else {
3675                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3676                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3677                 }
3678         } else {
3679                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3680                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3681                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3682                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3683                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3684         }
3685
3686         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3687
3688         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3689                 thermal_int = RREG32(CG_THERMAL_INT) &
3690                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3691         } else if (rdev->family >= CHIP_RV770) {
3692                 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3693                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3694         }
3695         if (rdev->irq.dpm_thermal) {
3696                 DRM_DEBUG("dpm thermal\n");
3697                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
3698         }
3699
3700         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3701                 DRM_DEBUG("r600_irq_set: sw int\n");
3702                 cp_int_cntl |= RB_INT_ENABLE;
3703                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3704         }
3705
3706         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3707                 DRM_DEBUG("r600_irq_set: sw int dma\n");
3708                 dma_cntl |= TRAP_ENABLE;
3709         }
3710
3711         if (rdev->irq.crtc_vblank_int[0] ||
3712             atomic_read(&rdev->irq.pflip[0])) {
3713                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3714                 mode_int |= D1MODE_VBLANK_INT_MASK;
3715         }
3716         if (rdev->irq.crtc_vblank_int[1] ||
3717             atomic_read(&rdev->irq.pflip[1])) {
3718                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3719                 mode_int |= D2MODE_VBLANK_INT_MASK;
3720         }
3721         if (rdev->irq.hpd[0]) {
3722                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3723                 hpd1 |= DC_HPDx_INT_EN;
3724         }
3725         if (rdev->irq.hpd[1]) {
3726                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3727                 hpd2 |= DC_HPDx_INT_EN;
3728         }
3729         if (rdev->irq.hpd[2]) {
3730                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3731                 hpd3 |= DC_HPDx_INT_EN;
3732         }
3733         if (rdev->irq.hpd[3]) {
3734                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3735                 hpd4 |= DC_HPDx_INT_EN;
3736         }
3737         if (rdev->irq.hpd[4]) {
3738                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3739                 hpd5 |= DC_HPDx_INT_EN;
3740         }
3741         if (rdev->irq.hpd[5]) {
3742                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3743                 hpd6 |= DC_HPDx_INT_EN;
3744         }
3745         if (rdev->irq.afmt[0]) {
3746                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3747                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3748         }
3749         if (rdev->irq.afmt[1]) {
3750                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3751                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3752         }
3753
3754         WREG32(CP_INT_CNTL, cp_int_cntl);
3755         WREG32(DMA_CNTL, dma_cntl);
3756         WREG32(DxMODE_INT_MASK, mode_int);
3757         WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3758         WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3759         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3760         if (ASIC_IS_DCE3(rdev)) {
3761                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3762                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3763                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3764                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3765                 if (ASIC_IS_DCE32(rdev)) {
3766                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3767                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3768                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3769                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3770                 } else {
3771                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3772                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3773                 }
3774         } else {
3775                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3776                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3777                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3778                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3779                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3780         }
3781         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3782                 WREG32(CG_THERMAL_INT, thermal_int);
3783         } else if (rdev->family >= CHIP_RV770) {
3784                 WREG32(RV770_CG_THERMAL_INT, thermal_int);
3785         }
3786
3787         /* posting read */
3788         RREG32(R_000E50_SRBM_STATUS);
3789
3790         return 0;
3791 }
3792
3793 static void r600_irq_ack(struct radeon_device *rdev)
3794 {
3795         u32 tmp;
3796
3797         if (ASIC_IS_DCE3(rdev)) {
3798                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3799                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3800                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3801                 if (ASIC_IS_DCE32(rdev)) {
3802                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3803                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3804                 } else {
3805                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3806                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3807                 }
3808         } else {
3809                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3810                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3811                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3812                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3813                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3814         }
3815         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3816         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3817
3818         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3819                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3820         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3821                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3822         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3823                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3824         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3825                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3826         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3827                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3828         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3829                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3830         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3831                 if (ASIC_IS_DCE3(rdev)) {
3832                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3833                         tmp |= DC_HPDx_INT_ACK;
3834                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3835                 } else {
3836                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3837                         tmp |= DC_HPDx_INT_ACK;
3838                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3839                 }
3840         }
3841         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3842                 if (ASIC_IS_DCE3(rdev)) {
3843                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3844                         tmp |= DC_HPDx_INT_ACK;
3845                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3846                 } else {
3847                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3848                         tmp |= DC_HPDx_INT_ACK;
3849                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3850                 }
3851         }
3852         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3853                 if (ASIC_IS_DCE3(rdev)) {
3854                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3855                         tmp |= DC_HPDx_INT_ACK;
3856                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3857                 } else {
3858                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3859                         tmp |= DC_HPDx_INT_ACK;
3860                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3861                 }
3862         }
3863         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3864                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3865                 tmp |= DC_HPDx_INT_ACK;
3866                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3867         }
3868         if (ASIC_IS_DCE32(rdev)) {
3869                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3870                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3871                         tmp |= DC_HPDx_INT_ACK;
3872                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3873                 }
3874                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3875                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3876                         tmp |= DC_HPDx_INT_ACK;
3877                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3878                 }
3879                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3880                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3881                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3882                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3883                 }
3884                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3885                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3886                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3887                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3888                 }
3889         } else {
3890                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3891                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3892                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3893                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3894                 }
3895                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3896                         if (ASIC_IS_DCE3(rdev)) {
3897                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3898                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3899                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3900                         } else {
3901                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3902                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3903                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3904                         }
3905                 }
3906         }
3907 }
3908
3909 void r600_irq_disable(struct radeon_device *rdev)
3910 {
3911         r600_disable_interrupts(rdev);
3912         /* Wait and acknowledge irq */
3913         mdelay(1);
3914         r600_irq_ack(rdev);
3915         r600_disable_interrupt_state(rdev);
3916 }
3917
3918 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3919 {
3920         u32 wptr, tmp;
3921
3922         if (rdev->wb.enabled)
3923                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3924         else
3925                 wptr = RREG32(IH_RB_WPTR);
3926
3927         if (wptr & RB_OVERFLOW) {
3928                 wptr &= ~RB_OVERFLOW;
3929                 /* When a ring buffer overflow happen start parsing interrupt
3930                  * from the last not overwritten vector (wptr + 16). Hopefully
3931                  * this should allow us to catchup.
3932                  */
3933                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
3934                          wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
3935                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3936                 tmp = RREG32(IH_RB_CNTL);
3937                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3938                 WREG32(IH_RB_CNTL, tmp);
3939         }
3940         return (wptr & rdev->ih.ptr_mask);
3941 }
3942
3943 /*        r600 IV Ring
3944  * Each IV ring entry is 128 bits:
3945  * [7:0]    - interrupt source id
3946  * [31:8]   - reserved
3947  * [59:32]  - interrupt source data
3948  * [127:60]  - reserved
3949  *
3950  * The basic interrupt vector entries
3951  * are decoded as follows:
3952  * src_id  src_data  description
3953  *      1         0  D1 Vblank
3954  *      1         1  D1 Vline
3955  *      5         0  D2 Vblank
3956  *      5         1  D2 Vline
3957  *     19         0  FP Hot plug detection A
3958  *     19         1  FP Hot plug detection B
3959  *     19         2  DAC A auto-detection
3960  *     19         3  DAC B auto-detection
3961  *     21         4  HDMI block A
3962  *     21         5  HDMI block B
3963  *    176         -  CP_INT RB
3964  *    177         -  CP_INT IB1
3965  *    178         -  CP_INT IB2
3966  *    181         -  EOP Interrupt
3967  *    233         -  GUI Idle
3968  *
3969  * Note, these are based on r600 and may need to be
3970  * adjusted or added to on newer asics
3971  */
3972
3973 int r600_irq_process(struct radeon_device *rdev)
3974 {
3975         u32 wptr;
3976         u32 rptr;
3977         u32 src_id, src_data;
3978         u32 ring_index;
3979         bool queue_hotplug = false;
3980         bool queue_hdmi = false;
3981         bool queue_thermal = false;
3982
3983         if (!rdev->ih.enabled || rdev->shutdown)
3984                 return IRQ_NONE;
3985
3986         /* No MSIs, need a dummy read to flush PCI DMAs */
3987         if (!rdev->msi_enabled)
3988                 RREG32(IH_RB_WPTR);
3989
3990         wptr = r600_get_ih_wptr(rdev);
3991
3992 restart_ih:
3993         /* is somebody else already processing irqs? */
3994         if (atomic_xchg(&rdev->ih.lock, 1))
3995                 return IRQ_NONE;
3996
3997         rptr = rdev->ih.rptr;
3998         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3999
4000         /* Order reading of wptr vs. reading of IH ring data */
4001         rmb();
4002
4003         /* display interrupts */
4004         r600_irq_ack(rdev);
4005
4006         while (rptr != wptr) {
4007                 /* wptr/rptr are in bytes! */
4008                 ring_index = rptr / 4;
4009                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4010                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4011
4012                 switch (src_id) {
4013                 case 1: /* D1 vblank/vline */
4014                         switch (src_data) {
4015                         case 0: /* D1 vblank */
4016                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
4017                                         if (rdev->irq.crtc_vblank_int[0]) {
4018                                                 drm_handle_vblank(rdev->ddev, 0);
4019                                                 rdev->pm.vblank_sync = true;
4020                                                 wake_up(&rdev->irq.vblank_queue);
4021                                         }
4022                                         if (atomic_read(&rdev->irq.pflip[0]))
4023                                                 radeon_crtc_handle_vblank(rdev, 0);
4024                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4025                                         DRM_DEBUG("IH: D1 vblank\n");
4026                                 }
4027                                 break;
4028                         case 1: /* D1 vline */
4029                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
4030                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4031                                         DRM_DEBUG("IH: D1 vline\n");
4032                                 }
4033                                 break;
4034                         default:
4035                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4036                                 break;
4037                         }
4038                         break;
4039                 case 5: /* D2 vblank/vline */
4040                         switch (src_data) {
4041                         case 0: /* D2 vblank */
4042                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
4043                                         if (rdev->irq.crtc_vblank_int[1]) {
4044                                                 drm_handle_vblank(rdev->ddev, 1);
4045                                                 rdev->pm.vblank_sync = true;
4046                                                 wake_up(&rdev->irq.vblank_queue);
4047                                         }
4048                                         if (atomic_read(&rdev->irq.pflip[1]))
4049                                                 radeon_crtc_handle_vblank(rdev, 1);
4050                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4051                                         DRM_DEBUG("IH: D2 vblank\n");
4052                                 }
4053                                 break;
4054                         case 1: /* D1 vline */
4055                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
4056                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4057                                         DRM_DEBUG("IH: D2 vline\n");
4058                                 }
4059                                 break;
4060                         default:
4061                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4062                                 break;
4063                         }
4064                         break;
4065                 case 9: /* D1 pflip */
4066                         DRM_DEBUG("IH: D1 flip\n");
4067                         if (radeon_use_pflipirq > 0)
4068                                 radeon_crtc_handle_flip(rdev, 0);
4069                         break;
4070                 case 11: /* D2 pflip */
4071                         DRM_DEBUG("IH: D2 flip\n");
4072                         if (radeon_use_pflipirq > 0)
4073                                 radeon_crtc_handle_flip(rdev, 1);
4074                         break;
4075                 case 19: /* HPD/DAC hotplug */
4076                         switch (src_data) {
4077                         case 0:
4078                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
4079                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4080                                         queue_hotplug = true;
4081                                         DRM_DEBUG("IH: HPD1\n");
4082                                 }
4083                                 break;
4084                         case 1:
4085                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
4086                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4087                                         queue_hotplug = true;
4088                                         DRM_DEBUG("IH: HPD2\n");
4089                                 }
4090                                 break;
4091                         case 4:
4092                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
4093                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4094                                         queue_hotplug = true;
4095                                         DRM_DEBUG("IH: HPD3\n");
4096                                 }
4097                                 break;
4098                         case 5:
4099                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
4100                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4101                                         queue_hotplug = true;
4102                                         DRM_DEBUG("IH: HPD4\n");
4103                                 }
4104                                 break;
4105                         case 10:
4106                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4107                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4108                                         queue_hotplug = true;
4109                                         DRM_DEBUG("IH: HPD5\n");
4110                                 }
4111                                 break;
4112                         case 12:
4113                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4114                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4115                                         queue_hotplug = true;
4116                                         DRM_DEBUG("IH: HPD6\n");
4117                                 }
4118                                 break;
4119                         default:
4120                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4121                                 break;
4122                         }
4123                         break;
4124                 case 21: /* hdmi */
4125                         switch (src_data) {
4126                         case 4:
4127                                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4128                                         rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4129                                         queue_hdmi = true;
4130                                         DRM_DEBUG("IH: HDMI0\n");
4131                                 }
4132                                 break;
4133                         case 5:
4134                                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4135                                         rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4136                                         queue_hdmi = true;
4137                                         DRM_DEBUG("IH: HDMI1\n");
4138                                 }
4139                                 break;
4140                         default:
4141                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4142                                 break;
4143                         }
4144                         break;
4145                 case 124: /* UVD */
4146                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4147                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4148                         break;
4149                 case 176: /* CP_INT in ring buffer */
4150                 case 177: /* CP_INT in IB1 */
4151                 case 178: /* CP_INT in IB2 */
4152                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4153                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4154                         break;
4155                 case 181: /* CP EOP event */
4156                         DRM_DEBUG("IH: CP EOP\n");
4157                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4158                         break;
4159                 case 224: /* DMA trap event */
4160                         DRM_DEBUG("IH: DMA trap\n");
4161                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4162                         break;
4163                 case 230: /* thermal low to high */
4164                         DRM_DEBUG("IH: thermal low to high\n");
4165                         rdev->pm.dpm.thermal.high_to_low = false;
4166                         queue_thermal = true;
4167                         break;
4168                 case 231: /* thermal high to low */
4169                         DRM_DEBUG("IH: thermal high to low\n");
4170                         rdev->pm.dpm.thermal.high_to_low = true;
4171                         queue_thermal = true;
4172                         break;
4173                 case 233: /* GUI IDLE */
4174                         DRM_DEBUG("IH: GUI idle\n");
4175                         break;
4176                 default:
4177                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4178                         break;
4179                 }
4180
4181                 /* wptr/rptr are in bytes! */
4182                 rptr += 16;
4183                 rptr &= rdev->ih.ptr_mask;
4184                 WREG32(IH_RB_RPTR, rptr);
4185         }
4186         if (queue_hotplug)
4187                 schedule_work(&rdev->hotplug_work);
4188         if (queue_hdmi)
4189                 schedule_work(&rdev->audio_work);
4190         if (queue_thermal && rdev->pm.dpm_enabled)
4191                 schedule_work(&rdev->pm.dpm.thermal.work);
4192         rdev->ih.rptr = rptr;
4193         atomic_set(&rdev->ih.lock, 0);
4194
4195         /* make sure wptr hasn't changed while processing */
4196         wptr = r600_get_ih_wptr(rdev);
4197         if (wptr != rptr)
4198                 goto restart_ih;
4199
4200         return IRQ_HANDLED;
4201 }
4202
4203 /*
4204  * Debugfs info
4205  */
4206 #if defined(CONFIG_DEBUG_FS)
4207
4208 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4209 {
4210         struct drm_info_node *node = (struct drm_info_node *) m->private;
4211         struct drm_device *dev = node->minor->dev;
4212         struct radeon_device *rdev = dev->dev_private;
4213
4214         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4215         DREG32_SYS(m, rdev, VM_L2_STATUS);
4216         return 0;
4217 }
4218
4219 static struct drm_info_list r600_mc_info_list[] = {
4220         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4221 };
4222 #endif
4223
4224 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4225 {
4226 #if defined(CONFIG_DEBUG_FS)
4227         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4228 #else
4229         return 0;
4230 #endif
4231 }
4232
4233 /**
4234  * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
4235  * rdev: radeon device structure
4236  *
4237  * Some R6XX/R7XX don't seem to take into account HDP flushes performed
4238  * through the ring buffer. This leads to corruption in rendering, see
4239  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
4240  * directly perform the HDP flush by writing the register through MMIO.
4241  */
4242 void r600_mmio_hdp_flush(struct radeon_device *rdev)
4243 {
4244         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4245          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4246          * This seems to cause problems on some AGP cards. Just use the old
4247          * method for them.
4248          */
4249         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4250             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4251                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4252                 u32 tmp;
4253
4254                 WREG32(HDP_DEBUG1, 0);
4255                 tmp = readl((void __iomem *)ptr);
4256         } else
4257                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4258 }
4259
4260 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4261 {
4262         u32 link_width_cntl, mask;
4263
4264         if (rdev->flags & RADEON_IS_IGP)
4265                 return;
4266
4267         if (!(rdev->flags & RADEON_IS_PCIE))
4268                 return;
4269
4270         /* x2 cards have a special sequence */
4271         if (ASIC_IS_X2(rdev))
4272                 return;
4273
4274         radeon_gui_idle(rdev);
4275
4276         switch (lanes) {
4277         case 0:
4278                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4279                 break;
4280         case 1:
4281                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4282                 break;
4283         case 2:
4284                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4285                 break;
4286         case 4:
4287                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4288                 break;
4289         case 8:
4290                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4291                 break;
4292         case 12:
4293                 /* not actually supported */
4294                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4295                 break;
4296         case 16:
4297                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4298                 break;
4299         default:
4300                 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4301                 return;
4302         }
4303
4304         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4305         link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4306         link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4307         link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4308                             R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4309
4310         WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4311 }
4312
4313 int r600_get_pcie_lanes(struct radeon_device *rdev)
4314 {
4315         u32 link_width_cntl;
4316
4317         if (rdev->flags & RADEON_IS_IGP)
4318                 return 0;
4319
4320         if (!(rdev->flags & RADEON_IS_PCIE))
4321                 return 0;
4322
4323         /* x2 cards have a special sequence */
4324         if (ASIC_IS_X2(rdev))
4325                 return 0;
4326
4327         radeon_gui_idle(rdev);
4328
4329         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4330
4331         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4332         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4333                 return 1;
4334         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4335                 return 2;
4336         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4337                 return 4;
4338         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4339                 return 8;
4340         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4341                 /* not actually supported */
4342                 return 12;
4343         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4344         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4345         default:
4346                 return 16;
4347         }
4348 }
4349
4350 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4351 {
4352         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4353         u16 link_cntl2;
4354
4355         if (radeon_pcie_gen2 == 0)
4356                 return;
4357
4358         if (rdev->flags & RADEON_IS_IGP)
4359                 return;
4360
4361         if (!(rdev->flags & RADEON_IS_PCIE))
4362                 return;
4363
4364         /* x2 cards have a special sequence */
4365         if (ASIC_IS_X2(rdev))
4366                 return;
4367
4368         /* only RV6xx+ chips are supported */
4369         if (rdev->family <= CHIP_R600)
4370                 return;
4371
4372         if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4373                 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4374                 return;
4375
4376         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4377         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4378                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4379                 return;
4380         }
4381
4382         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4383
4384         /* 55 nm r6xx asics */
4385         if ((rdev->family == CHIP_RV670) ||
4386             (rdev->family == CHIP_RV620) ||
4387             (rdev->family == CHIP_RV635)) {
4388                 /* advertise upconfig capability */
4389                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4390                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4391                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4392                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4393                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4394                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4395                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4396                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4397                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4398                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4399                 } else {
4400                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4401                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4402                 }
4403         }
4404
4405         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4406         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4407             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4408
4409                 /* 55 nm r6xx asics */
4410                 if ((rdev->family == CHIP_RV670) ||
4411                     (rdev->family == CHIP_RV620) ||
4412                     (rdev->family == CHIP_RV635)) {
4413                         WREG32(MM_CFGREGS_CNTL, 0x8);
4414                         link_cntl2 = RREG32(0x4088);
4415                         WREG32(MM_CFGREGS_CNTL, 0);
4416                         /* not supported yet */
4417                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4418                                 return;
4419                 }
4420
4421                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4422                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4423                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4424                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4425                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4426                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4427
4428                 tmp = RREG32(0x541c);
4429                 WREG32(0x541c, tmp | 0x8);
4430                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4431                 link_cntl2 = RREG16(0x4088);
4432                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4433                 link_cntl2 |= 0x2;
4434                 WREG16(0x4088, link_cntl2);
4435                 WREG32(MM_CFGREGS_CNTL, 0);
4436
4437                 if ((rdev->family == CHIP_RV670) ||
4438                     (rdev->family == CHIP_RV620) ||
4439                     (rdev->family == CHIP_RV635)) {
4440                         training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4441                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4442                         WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4443                 } else {
4444                         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4445                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4446                         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4447                 }
4448
4449                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4450                 speed_cntl |= LC_GEN2_EN_STRAP;
4451                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4452
4453         } else {
4454                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4455                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4456                 if (1)
4457                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4458                 else
4459                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4460                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4461         }
4462 }
4463
4464 /**
4465  * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4466  *
4467  * @rdev: radeon_device pointer
4468  *
4469  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4470  * Returns the 64 bit clock counter snapshot.
4471  */
4472 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4473 {
4474         uint64_t clock;
4475
4476         mutex_lock(&rdev->gpu_clock_mutex);
4477         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4478         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4479                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4480         mutex_unlock(&rdev->gpu_clock_mutex);
4481         return clock;
4482 }