2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
31 #include <drm/radeon_drm.h>
32 #include "radeon_reg.h"
34 #include "radeon_asic.h"
41 #include <linux/firmware.h>
42 #include <linux/module.h>
44 #include "r100_reg_safe.h"
45 #include "rn50_reg_safe.h"
48 #define FIRMWARE_R100 "radeon/R100_cp.bin"
49 #define FIRMWARE_R200 "radeon/R200_cp.bin"
50 #define FIRMWARE_R300 "radeon/R300_cp.bin"
51 #define FIRMWARE_R420 "radeon/R420_cp.bin"
52 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
53 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
54 #define FIRMWARE_R520 "radeon/R520_cp.bin"
56 MODULE_FIRMWARE(FIRMWARE_R100);
57 MODULE_FIRMWARE(FIRMWARE_R200);
58 MODULE_FIRMWARE(FIRMWARE_R300);
59 MODULE_FIRMWARE(FIRMWARE_R420);
60 MODULE_FIRMWARE(FIRMWARE_RS690);
61 MODULE_FIRMWARE(FIRMWARE_RS600);
62 MODULE_FIRMWARE(FIRMWARE_R520);
64 #include "r100_track.h"
66 /* This files gather functions specifics to:
67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 * and others in some cases.
71 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
86 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
104 * r100_wait_for_vblank - vblank wait asic callback.
106 * @rdev: radeon_device pointer
107 * @crtc: crtc to wait for vblank on
109 * Wait for vblank on the requested crtc (r1xx-r4xx).
111 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
115 if (crtc >= rdev->num_crtc)
119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
126 /* depending on when we hit vblank, we may be close to active; if so,
127 * wait for another frame.
129 while (r100_is_in_vblank(rdev, crtc)) {
130 if (i++ % 100 == 0) {
131 if (!r100_is_counter_moving(rdev, crtc))
136 while (!r100_is_in_vblank(rdev, crtc)) {
137 if (i++ % 100 == 0) {
138 if (!r100_is_counter_moving(rdev, crtc))
145 * r100_pre_page_flip - pre-pageflip callback.
147 * @rdev: radeon_device pointer
148 * @crtc: crtc to prepare for pageflip on
150 * Pre-pageflip callback (r1xx-r4xx).
151 * Enables the pageflip irq (vblank irq).
153 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
155 /* enable the pflip int */
156 radeon_irq_kms_pflip_irq_get(rdev, crtc);
160 * r100_post_page_flip - pos-pageflip callback.
162 * @rdev: radeon_device pointer
163 * @crtc: crtc to cleanup pageflip on
165 * Post-pageflip callback (r1xx-r4xx).
166 * Disables the pageflip irq (vblank irq).
168 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
170 /* disable the pflip int */
171 radeon_irq_kms_pflip_irq_put(rdev, crtc);
175 * r100_page_flip - pageflip callback.
177 * @rdev: radeon_device pointer
178 * @crtc_id: crtc to cleanup pageflip on
179 * @crtc_base: new address of the crtc (GPU MC address)
181 * Does the actual pageflip (r1xx-r4xx).
182 * During vblank we take the crtc lock and wait for the update_pending
183 * bit to go high, when it does, we release the lock, and allow the
184 * double buffered update to take place.
185 * Returns the current update pending status.
187 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
189 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
190 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
193 /* Lock the graphics update lock */
194 /* update the scanout addresses */
195 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
197 /* Wait for update_pending to go high. */
198 for (i = 0; i < rdev->usec_timeout; i++) {
199 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
203 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
205 /* Unlock the lock, so double-buffering can take place inside vblank */
206 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
207 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
209 /* Return current update_pending status: */
210 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
214 * r100_pm_get_dynpm_state - look up dynpm power state callback.
216 * @rdev: radeon_device pointer
218 * Look up the optimal power state based on the
219 * current state of the GPU (r1xx-r5xx).
220 * Used for dynpm only.
222 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
225 rdev->pm.dynpm_can_upclock = true;
226 rdev->pm.dynpm_can_downclock = true;
228 switch (rdev->pm.dynpm_planned_action) {
229 case DYNPM_ACTION_MINIMUM:
230 rdev->pm.requested_power_state_index = 0;
231 rdev->pm.dynpm_can_downclock = false;
233 case DYNPM_ACTION_DOWNCLOCK:
234 if (rdev->pm.current_power_state_index == 0) {
235 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
236 rdev->pm.dynpm_can_downclock = false;
238 if (rdev->pm.active_crtc_count > 1) {
239 for (i = 0; i < rdev->pm.num_power_states; i++) {
240 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
242 else if (i >= rdev->pm.current_power_state_index) {
243 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
246 rdev->pm.requested_power_state_index = i;
251 rdev->pm.requested_power_state_index =
252 rdev->pm.current_power_state_index - 1;
254 /* don't use the power state if crtcs are active and no display flag is set */
255 if ((rdev->pm.active_crtc_count > 0) &&
256 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
257 RADEON_PM_MODE_NO_DISPLAY)) {
258 rdev->pm.requested_power_state_index++;
261 case DYNPM_ACTION_UPCLOCK:
262 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
263 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
264 rdev->pm.dynpm_can_upclock = false;
266 if (rdev->pm.active_crtc_count > 1) {
267 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
268 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
270 else if (i <= rdev->pm.current_power_state_index) {
271 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
274 rdev->pm.requested_power_state_index = i;
279 rdev->pm.requested_power_state_index =
280 rdev->pm.current_power_state_index + 1;
283 case DYNPM_ACTION_DEFAULT:
284 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
285 rdev->pm.dynpm_can_upclock = false;
287 case DYNPM_ACTION_NONE:
289 DRM_ERROR("Requested mode for not defined action\n");
292 /* only one clock mode per power state */
293 rdev->pm.requested_clock_mode_index = 0;
295 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
296 rdev->pm.power_state[rdev->pm.requested_power_state_index].
297 clock_info[rdev->pm.requested_clock_mode_index].sclk,
298 rdev->pm.power_state[rdev->pm.requested_power_state_index].
299 clock_info[rdev->pm.requested_clock_mode_index].mclk,
300 rdev->pm.power_state[rdev->pm.requested_power_state_index].
305 * r100_pm_init_profile - Initialize power profiles callback.
307 * @rdev: radeon_device pointer
309 * Initialize the power states used in profile mode
311 * Used for profile mode only.
313 void r100_pm_init_profile(struct radeon_device *rdev)
316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
353 * r100_pm_misc - set additional pm hw parameters callback.
355 * @rdev: radeon_device pointer
357 * Set non-clock parameters associated with a power state
358 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
360 void r100_pm_misc(struct radeon_device *rdev)
362 int requested_index = rdev->pm.requested_power_state_index;
363 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
364 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
365 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
367 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
368 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
369 tmp = RREG32(voltage->gpio.reg);
370 if (voltage->active_high)
371 tmp |= voltage->gpio.mask;
373 tmp &= ~(voltage->gpio.mask);
374 WREG32(voltage->gpio.reg, tmp);
376 udelay(voltage->delay);
378 tmp = RREG32(voltage->gpio.reg);
379 if (voltage->active_high)
380 tmp &= ~voltage->gpio.mask;
382 tmp |= voltage->gpio.mask;
383 WREG32(voltage->gpio.reg, tmp);
385 udelay(voltage->delay);
389 sclk_cntl = RREG32_PLL(SCLK_CNTL);
390 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
391 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
392 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
393 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
394 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
395 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
396 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
397 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
399 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
400 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
401 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
402 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
403 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
405 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
407 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
408 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
409 if (voltage->delay) {
410 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
411 switch (voltage->delay) {
413 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
416 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
419 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
422 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
426 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
428 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
430 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
431 sclk_cntl &= ~FORCE_HDP;
433 sclk_cntl |= FORCE_HDP;
435 WREG32_PLL(SCLK_CNTL, sclk_cntl);
436 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
437 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
440 if ((rdev->flags & RADEON_IS_PCIE) &&
441 !(rdev->flags & RADEON_IS_IGP) &&
442 rdev->asic->pm.set_pcie_lanes &&
444 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
445 radeon_set_pcie_lanes(rdev,
447 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
452 * r100_pm_prepare - pre-power state change callback.
454 * @rdev: radeon_device pointer
456 * Prepare for a power state change (r1xx-r4xx).
458 void r100_pm_prepare(struct radeon_device *rdev)
460 struct drm_device *ddev = rdev->ddev;
461 struct drm_crtc *crtc;
462 struct radeon_crtc *radeon_crtc;
465 /* disable any active CRTCs */
466 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
467 radeon_crtc = to_radeon_crtc(crtc);
468 if (radeon_crtc->enabled) {
469 if (radeon_crtc->crtc_id) {
470 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
471 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
472 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
474 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
475 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
476 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
483 * r100_pm_finish - post-power state change callback.
485 * @rdev: radeon_device pointer
487 * Clean up after a power state change (r1xx-r4xx).
489 void r100_pm_finish(struct radeon_device *rdev)
491 struct drm_device *ddev = rdev->ddev;
492 struct drm_crtc *crtc;
493 struct radeon_crtc *radeon_crtc;
496 /* enable any active CRTCs */
497 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
498 radeon_crtc = to_radeon_crtc(crtc);
499 if (radeon_crtc->enabled) {
500 if (radeon_crtc->crtc_id) {
501 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
502 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
503 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
505 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
506 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
507 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
514 * r100_gui_idle - gui idle callback.
516 * @rdev: radeon_device pointer
518 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
519 * Returns true if idle, false if not.
521 bool r100_gui_idle(struct radeon_device *rdev)
523 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
529 /* hpd for digital panel detect/disconnect */
531 * r100_hpd_sense - hpd sense callback.
533 * @rdev: radeon_device pointer
534 * @hpd: hpd (hotplug detect) pin
536 * Checks if a digital monitor is connected (r1xx-r4xx).
537 * Returns true if connected, false if not connected.
539 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
541 bool connected = false;
545 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
549 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
559 * r100_hpd_set_polarity - hpd set polarity callback.
561 * @rdev: radeon_device pointer
562 * @hpd: hpd (hotplug detect) pin
564 * Set the polarity of the hpd pin (r1xx-r4xx).
566 void r100_hpd_set_polarity(struct radeon_device *rdev,
567 enum radeon_hpd_id hpd)
570 bool connected = r100_hpd_sense(rdev, hpd);
574 tmp = RREG32(RADEON_FP_GEN_CNTL);
576 tmp &= ~RADEON_FP_DETECT_INT_POL;
578 tmp |= RADEON_FP_DETECT_INT_POL;
579 WREG32(RADEON_FP_GEN_CNTL, tmp);
582 tmp = RREG32(RADEON_FP2_GEN_CNTL);
584 tmp &= ~RADEON_FP2_DETECT_INT_POL;
586 tmp |= RADEON_FP2_DETECT_INT_POL;
587 WREG32(RADEON_FP2_GEN_CNTL, tmp);
595 * r100_hpd_init - hpd setup callback.
597 * @rdev: radeon_device pointer
599 * Setup the hpd pins used by the card (r1xx-r4xx).
600 * Set the polarity, and enable the hpd interrupts.
602 void r100_hpd_init(struct radeon_device *rdev)
604 struct drm_device *dev = rdev->ddev;
605 struct drm_connector *connector;
608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
609 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
610 enable |= 1 << radeon_connector->hpd.hpd;
611 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
613 radeon_irq_kms_enable_hpd(rdev, enable);
617 * r100_hpd_fini - hpd tear down callback.
619 * @rdev: radeon_device pointer
621 * Tear down the hpd pins used by the card (r1xx-r4xx).
622 * Disable the hpd interrupts.
624 void r100_hpd_fini(struct radeon_device *rdev)
626 struct drm_device *dev = rdev->ddev;
627 struct drm_connector *connector;
628 unsigned disable = 0;
630 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
631 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
632 disable |= 1 << radeon_connector->hpd.hpd;
634 radeon_irq_kms_disable_hpd(rdev, disable);
640 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
642 /* TODO: can we do somethings here ? */
643 /* It seems hw only cache one entry so we should discard this
644 * entry otherwise if first GPU GART read hit this entry it
645 * could end up in wrong address. */
648 int r100_pci_gart_init(struct radeon_device *rdev)
652 if (rdev->gart.ptr) {
653 WARN(1, "R100 PCI GART already initialized\n");
656 /* Initialize common gart structure */
657 r = radeon_gart_init(rdev);
660 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
661 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
662 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
663 return radeon_gart_table_ram_alloc(rdev);
666 int r100_pci_gart_enable(struct radeon_device *rdev)
670 radeon_gart_restore(rdev);
671 /* discard memory request outside of configured range */
672 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
673 WREG32(RADEON_AIC_CNTL, tmp);
674 /* set address range for PCI address translate */
675 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
676 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
677 /* set PCI GART page-table base address */
678 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
679 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
680 WREG32(RADEON_AIC_CNTL, tmp);
681 r100_pci_gart_tlb_flush(rdev);
682 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
683 (unsigned)(rdev->mc.gtt_size >> 20),
684 (unsigned long long)rdev->gart.table_addr);
685 rdev->gart.ready = true;
689 void r100_pci_gart_disable(struct radeon_device *rdev)
693 /* discard memory request outside of configured range */
694 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
695 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
696 WREG32(RADEON_AIC_LO_ADDR, 0);
697 WREG32(RADEON_AIC_HI_ADDR, 0);
700 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
702 u32 *gtt = rdev->gart.ptr;
704 if (i < 0 || i > rdev->gart.num_gpu_pages) {
707 gtt[i] = cpu_to_le32(lower_32_bits(addr));
711 void r100_pci_gart_fini(struct radeon_device *rdev)
713 radeon_gart_fini(rdev);
714 r100_pci_gart_disable(rdev);
715 radeon_gart_table_ram_free(rdev);
718 int r100_irq_set(struct radeon_device *rdev)
722 if (!rdev->irq.installed) {
723 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
724 WREG32(R_000040_GEN_INT_CNTL, 0);
727 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
728 tmp |= RADEON_SW_INT_ENABLE;
730 if (rdev->irq.crtc_vblank_int[0] ||
731 atomic_read(&rdev->irq.pflip[0])) {
732 tmp |= RADEON_CRTC_VBLANK_MASK;
734 if (rdev->irq.crtc_vblank_int[1] ||
735 atomic_read(&rdev->irq.pflip[1])) {
736 tmp |= RADEON_CRTC2_VBLANK_MASK;
738 if (rdev->irq.hpd[0]) {
739 tmp |= RADEON_FP_DETECT_MASK;
741 if (rdev->irq.hpd[1]) {
742 tmp |= RADEON_FP2_DETECT_MASK;
744 WREG32(RADEON_GEN_INT_CNTL, tmp);
748 void r100_irq_disable(struct radeon_device *rdev)
752 WREG32(R_000040_GEN_INT_CNTL, 0);
753 /* Wait and acknowledge irq */
755 tmp = RREG32(R_000044_GEN_INT_STATUS);
756 WREG32(R_000044_GEN_INT_STATUS, tmp);
759 static uint32_t r100_irq_ack(struct radeon_device *rdev)
761 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
762 uint32_t irq_mask = RADEON_SW_INT_TEST |
763 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
764 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
767 WREG32(RADEON_GEN_INT_STATUS, irqs);
769 return irqs & irq_mask;
772 int r100_irq_process(struct radeon_device *rdev)
774 uint32_t status, msi_rearm;
775 bool queue_hotplug = false;
777 status = r100_irq_ack(rdev);
781 if (rdev->shutdown) {
786 if (status & RADEON_SW_INT_TEST) {
787 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
789 /* Vertical blank interrupts */
790 if (status & RADEON_CRTC_VBLANK_STAT) {
791 if (rdev->irq.crtc_vblank_int[0]) {
792 drm_handle_vblank(rdev->ddev, 0);
793 rdev->pm.vblank_sync = true;
794 wake_up(&rdev->irq.vblank_queue);
796 if (atomic_read(&rdev->irq.pflip[0]))
797 radeon_crtc_handle_flip(rdev, 0);
799 if (status & RADEON_CRTC2_VBLANK_STAT) {
800 if (rdev->irq.crtc_vblank_int[1]) {
801 drm_handle_vblank(rdev->ddev, 1);
802 rdev->pm.vblank_sync = true;
803 wake_up(&rdev->irq.vblank_queue);
805 if (atomic_read(&rdev->irq.pflip[1]))
806 radeon_crtc_handle_flip(rdev, 1);
808 if (status & RADEON_FP_DETECT_STAT) {
809 queue_hotplug = true;
812 if (status & RADEON_FP2_DETECT_STAT) {
813 queue_hotplug = true;
816 status = r100_irq_ack(rdev);
819 schedule_work(&rdev->hotplug_work);
820 if (rdev->msi_enabled) {
821 switch (rdev->family) {
824 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
825 WREG32(RADEON_AIC_CNTL, msi_rearm);
826 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
829 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
836 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
839 return RREG32(RADEON_CRTC_CRNT_FRAME);
841 return RREG32(RADEON_CRTC2_CRNT_FRAME);
844 /* Who ever call radeon_fence_emit should call ring_lock and ask
845 * for enough space (today caller are ib schedule and buffer move) */
846 void r100_fence_ring_emit(struct radeon_device *rdev,
847 struct radeon_fence *fence)
849 struct radeon_ring *ring = &rdev->ring[fence->ring];
851 /* We have to make sure that caches are flushed before
852 * CPU might read something from VRAM. */
853 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
854 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
855 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
856 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
857 /* Wait until IDLE & CLEAN */
858 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
859 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
860 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
861 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
862 RADEON_HDP_READ_BUFFER_INVALIDATE);
863 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
864 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
865 /* Emit fence sequence & fire IRQ */
866 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
867 radeon_ring_write(ring, fence->seq);
868 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
869 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
872 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
873 struct radeon_ring *ring,
874 struct radeon_semaphore *semaphore,
877 /* Unused on older asics, since we don't have semaphores or multiple rings */
882 int r100_copy_blit(struct radeon_device *rdev,
885 unsigned num_gpu_pages,
886 struct radeon_fence **fence)
888 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
890 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
892 uint32_t stride_pixels;
897 /* radeon limited to 16k stride */
898 stride_bytes &= 0x3fff;
899 /* radeon pitch is /64 */
900 pitch = stride_bytes / 64;
901 stride_pixels = stride_bytes / 4;
902 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
904 /* Ask for enough room for blit + flush + fence */
905 ndw = 64 + (10 * num_loops);
906 r = radeon_ring_lock(rdev, ring, ndw);
908 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
911 while (num_gpu_pages > 0) {
912 cur_pages = num_gpu_pages;
913 if (cur_pages > 8191) {
916 num_gpu_pages -= cur_pages;
918 /* pages are in Y direction - height
919 page width in X direction - width */
920 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
921 radeon_ring_write(ring,
922 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
923 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
924 RADEON_GMC_SRC_CLIPPING |
925 RADEON_GMC_DST_CLIPPING |
926 RADEON_GMC_BRUSH_NONE |
927 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
928 RADEON_GMC_SRC_DATATYPE_COLOR |
930 RADEON_DP_SRC_SOURCE_MEMORY |
931 RADEON_GMC_CLR_CMP_CNTL_DIS |
932 RADEON_GMC_WR_MSK_DIS);
933 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
934 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
935 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
936 radeon_ring_write(ring, 0);
937 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
938 radeon_ring_write(ring, num_gpu_pages);
939 radeon_ring_write(ring, num_gpu_pages);
940 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
942 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
943 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
944 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
945 radeon_ring_write(ring,
946 RADEON_WAIT_2D_IDLECLEAN |
947 RADEON_WAIT_HOST_IDLECLEAN |
948 RADEON_WAIT_DMA_GUI_IDLE);
950 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
952 radeon_ring_unlock_commit(rdev, ring);
956 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
961 for (i = 0; i < rdev->usec_timeout; i++) {
962 tmp = RREG32(R_000E40_RBBM_STATUS);
963 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
971 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
975 r = radeon_ring_lock(rdev, ring, 2);
979 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
980 radeon_ring_write(ring,
981 RADEON_ISYNC_ANY2D_IDLE3D |
982 RADEON_ISYNC_ANY3D_IDLE2D |
983 RADEON_ISYNC_WAIT_IDLEGUI |
984 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
985 radeon_ring_unlock_commit(rdev, ring);
989 /* Load the microcode for the CP */
990 static int r100_cp_init_microcode(struct radeon_device *rdev)
992 const char *fw_name = NULL;
997 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
998 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
999 (rdev->family == CHIP_RS200)) {
1000 DRM_INFO("Loading R100 Microcode\n");
1001 fw_name = FIRMWARE_R100;
1002 } else if ((rdev->family == CHIP_R200) ||
1003 (rdev->family == CHIP_RV250) ||
1004 (rdev->family == CHIP_RV280) ||
1005 (rdev->family == CHIP_RS300)) {
1006 DRM_INFO("Loading R200 Microcode\n");
1007 fw_name = FIRMWARE_R200;
1008 } else if ((rdev->family == CHIP_R300) ||
1009 (rdev->family == CHIP_R350) ||
1010 (rdev->family == CHIP_RV350) ||
1011 (rdev->family == CHIP_RV380) ||
1012 (rdev->family == CHIP_RS400) ||
1013 (rdev->family == CHIP_RS480)) {
1014 DRM_INFO("Loading R300 Microcode\n");
1015 fw_name = FIRMWARE_R300;
1016 } else if ((rdev->family == CHIP_R420) ||
1017 (rdev->family == CHIP_R423) ||
1018 (rdev->family == CHIP_RV410)) {
1019 DRM_INFO("Loading R400 Microcode\n");
1020 fw_name = FIRMWARE_R420;
1021 } else if ((rdev->family == CHIP_RS690) ||
1022 (rdev->family == CHIP_RS740)) {
1023 DRM_INFO("Loading RS690/RS740 Microcode\n");
1024 fw_name = FIRMWARE_RS690;
1025 } else if (rdev->family == CHIP_RS600) {
1026 DRM_INFO("Loading RS600 Microcode\n");
1027 fw_name = FIRMWARE_RS600;
1028 } else if ((rdev->family == CHIP_RV515) ||
1029 (rdev->family == CHIP_R520) ||
1030 (rdev->family == CHIP_RV530) ||
1031 (rdev->family == CHIP_R580) ||
1032 (rdev->family == CHIP_RV560) ||
1033 (rdev->family == CHIP_RV570)) {
1034 DRM_INFO("Loading R500 Microcode\n");
1035 fw_name = FIRMWARE_R520;
1038 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1040 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1042 } else if (rdev->me_fw->size % 8) {
1044 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1045 rdev->me_fw->size, fw_name);
1047 release_firmware(rdev->me_fw);
1053 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1054 struct radeon_ring *ring)
1058 if (rdev->wb.enabled)
1059 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1061 rptr = RREG32(RADEON_CP_RB_RPTR);
1066 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1067 struct radeon_ring *ring)
1071 wptr = RREG32(RADEON_CP_RB_WPTR);
1076 void r100_gfx_set_wptr(struct radeon_device *rdev,
1077 struct radeon_ring *ring)
1079 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1080 (void)RREG32(RADEON_CP_RB_WPTR);
1083 static void r100_cp_load_microcode(struct radeon_device *rdev)
1085 const __be32 *fw_data;
1088 if (r100_gui_wait_for_idle(rdev)) {
1089 printk(KERN_WARNING "Failed to wait GUI idle while "
1090 "programming pipes. Bad things might happen.\n");
1094 size = rdev->me_fw->size / 4;
1095 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1096 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1097 for (i = 0; i < size; i += 2) {
1098 WREG32(RADEON_CP_ME_RAM_DATAH,
1099 be32_to_cpup(&fw_data[i]));
1100 WREG32(RADEON_CP_ME_RAM_DATAL,
1101 be32_to_cpup(&fw_data[i + 1]));
1106 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1108 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1112 unsigned pre_write_timer;
1113 unsigned pre_write_limit;
1114 unsigned indirect2_start;
1115 unsigned indirect1_start;
1119 if (r100_debugfs_cp_init(rdev)) {
1120 DRM_ERROR("Failed to register debugfs file for CP !\n");
1123 r = r100_cp_init_microcode(rdev);
1125 DRM_ERROR("Failed to load firmware!\n");
1130 /* Align ring size */
1131 rb_bufsz = order_base_2(ring_size / 8);
1132 ring_size = (1 << (rb_bufsz + 1)) * 4;
1133 r100_cp_load_microcode(rdev);
1134 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1139 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1140 * the rptr copy in system ram */
1142 /* cp will read 128bytes at a time (4 dwords) */
1144 ring->align_mask = 16 - 1;
1145 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1146 pre_write_timer = 64;
1147 /* Force CP_RB_WPTR write if written more than one time before the
1150 pre_write_limit = 0;
1151 /* Setup the cp cache like this (cache size is 96 dwords) :
1153 * INDIRECT1 16 to 79
1154 * INDIRECT2 80 to 95
1155 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1156 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1157 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1158 * Idea being that most of the gpu cmd will be through indirect1 buffer
1159 * so it gets the bigger cache.
1161 indirect2_start = 80;
1162 indirect1_start = 16;
1164 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1165 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1166 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1167 REG_SET(RADEON_MAX_FETCH, max_fetch));
1169 tmp |= RADEON_BUF_SWAP_32BIT;
1171 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1173 /* Set ring address */
1174 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1175 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1176 /* Force read & write ptr to 0 */
1177 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1178 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1180 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1182 /* set the wb address whether it's enabled or not */
1183 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1184 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1185 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1187 if (rdev->wb.enabled)
1188 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1190 tmp |= RADEON_RB_NO_UPDATE;
1191 WREG32(R_000770_SCRATCH_UMSK, 0);
1194 WREG32(RADEON_CP_RB_CNTL, tmp);
1196 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1197 /* Set cp mode to bus mastering & enable cp*/
1198 WREG32(RADEON_CP_CSQ_MODE,
1199 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1200 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1201 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1202 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1203 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1205 /* at this point everything should be setup correctly to enable master */
1206 pci_set_master(rdev->pdev);
1208 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1209 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1211 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1215 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1217 if (!ring->rptr_save_reg /* not resuming from suspend */
1218 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1219 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1221 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1222 ring->rptr_save_reg = 0;
1228 void r100_cp_fini(struct radeon_device *rdev)
1230 if (r100_cp_wait_for_idle(rdev)) {
1231 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1234 r100_cp_disable(rdev);
1235 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1236 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1237 DRM_INFO("radeon: cp finalized\n");
1240 void r100_cp_disable(struct radeon_device *rdev)
1243 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1244 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1245 WREG32(RADEON_CP_CSQ_MODE, 0);
1246 WREG32(RADEON_CP_CSQ_CNTL, 0);
1247 WREG32(R_000770_SCRATCH_UMSK, 0);
1248 if (r100_gui_wait_for_idle(rdev)) {
1249 printk(KERN_WARNING "Failed to wait GUI idle while "
1250 "programming pipes. Bad things might happen.\n");
1257 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1258 struct radeon_cs_packet *pkt,
1265 struct radeon_cs_reloc *reloc;
1268 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1270 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1272 radeon_cs_dump_packet(p, pkt);
1276 value = radeon_get_ib_value(p, idx);
1277 tmp = value & 0x003fffff;
1278 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1280 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1281 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1282 tile_flags |= RADEON_DST_TILE_MACRO;
1283 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1284 if (reg == RADEON_SRC_PITCH_OFFSET) {
1285 DRM_ERROR("Cannot src blit from microtiled surface\n");
1286 radeon_cs_dump_packet(p, pkt);
1289 tile_flags |= RADEON_DST_TILE_MICRO;
1293 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1295 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1299 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1300 struct radeon_cs_packet *pkt,
1304 struct radeon_cs_reloc *reloc;
1305 struct r100_cs_track *track;
1307 volatile uint32_t *ib;
1311 track = (struct r100_cs_track *)p->track;
1312 c = radeon_get_ib_value(p, idx++) & 0x1F;
1314 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1316 radeon_cs_dump_packet(p, pkt);
1319 track->num_arrays = c;
1320 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1321 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1323 DRM_ERROR("No reloc for packet3 %d\n",
1325 radeon_cs_dump_packet(p, pkt);
1328 idx_value = radeon_get_ib_value(p, idx);
1329 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1331 track->arrays[i + 0].esize = idx_value >> 8;
1332 track->arrays[i + 0].robj = reloc->robj;
1333 track->arrays[i + 0].esize &= 0x7F;
1334 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1336 DRM_ERROR("No reloc for packet3 %d\n",
1338 radeon_cs_dump_packet(p, pkt);
1341 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1342 track->arrays[i + 1].robj = reloc->robj;
1343 track->arrays[i + 1].esize = idx_value >> 24;
1344 track->arrays[i + 1].esize &= 0x7F;
1347 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1349 DRM_ERROR("No reloc for packet3 %d\n",
1351 radeon_cs_dump_packet(p, pkt);
1354 idx_value = radeon_get_ib_value(p, idx);
1355 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1356 track->arrays[i + 0].robj = reloc->robj;
1357 track->arrays[i + 0].esize = idx_value >> 8;
1358 track->arrays[i + 0].esize &= 0x7F;
1363 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1364 struct radeon_cs_packet *pkt,
1365 const unsigned *auth, unsigned n,
1366 radeon_packet0_check_t check)
1375 /* Check that register fall into register range
1376 * determined by the number of entry (n) in the
1377 * safe register bitmap.
1379 if (pkt->one_reg_wr) {
1380 if ((reg >> 7) > n) {
1384 if (((reg + (pkt->count << 2)) >> 7) > n) {
1388 for (i = 0; i <= pkt->count; i++, idx++) {
1390 m = 1 << ((reg >> 2) & 31);
1392 r = check(p, pkt, idx, reg);
1397 if (pkt->one_reg_wr) {
1398 if (!(auth[j] & m)) {
1409 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1410 * @parser: parser structure holding parsing context.
1412 * Userspace sends a special sequence for VLINE waits.
1413 * PACKET0 - VLINE_START_END + value
1414 * PACKET0 - WAIT_UNTIL +_value
1415 * RELOC (P3) - crtc_id in reloc.
1417 * This function parses this and relocates the VLINE START END
1418 * and WAIT UNTIL packets to the correct crtc.
1419 * It also detects a switched off crtc and nulls out the
1420 * wait in that case.
1422 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1424 struct drm_mode_object *obj;
1425 struct drm_crtc *crtc;
1426 struct radeon_crtc *radeon_crtc;
1427 struct radeon_cs_packet p3reloc, waitreloc;
1430 uint32_t header, h_idx, reg;
1431 volatile uint32_t *ib;
1435 /* parse the wait until */
1436 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1440 /* check its a wait until and only 1 count */
1441 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1442 waitreloc.count != 0) {
1443 DRM_ERROR("vline wait had illegal wait until segment\n");
1447 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1448 DRM_ERROR("vline wait had illegal wait until\n");
1452 /* jump over the NOP */
1453 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1458 p->idx += waitreloc.count + 2;
1459 p->idx += p3reloc.count + 2;
1461 header = radeon_get_ib_value(p, h_idx);
1462 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1463 reg = R100_CP_PACKET0_GET_REG(header);
1464 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1466 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1469 crtc = obj_to_crtc(obj);
1470 radeon_crtc = to_radeon_crtc(crtc);
1471 crtc_id = radeon_crtc->crtc_id;
1473 if (!crtc->enabled) {
1474 /* if the CRTC isn't enabled - we need to nop out the wait until */
1475 ib[h_idx + 2] = PACKET2(0);
1476 ib[h_idx + 3] = PACKET2(0);
1477 } else if (crtc_id == 1) {
1479 case AVIVO_D1MODE_VLINE_START_END:
1480 header &= ~R300_CP_PACKET0_REG_MASK;
1481 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1483 case RADEON_CRTC_GUI_TRIG_VLINE:
1484 header &= ~R300_CP_PACKET0_REG_MASK;
1485 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1488 DRM_ERROR("unknown crtc reloc\n");
1492 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1498 static int r100_get_vtx_size(uint32_t vtx_fmt)
1502 /* ordered according to bits in spec */
1503 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1505 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1507 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1509 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1511 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1513 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1515 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1517 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1519 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1521 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1523 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1525 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1527 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1529 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1531 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1534 if (vtx_fmt & (0x7 << 15))
1535 vtx_size += (vtx_fmt >> 15) & 0x7;
1536 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1538 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1540 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1542 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1544 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1546 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1551 static int r100_packet0_check(struct radeon_cs_parser *p,
1552 struct radeon_cs_packet *pkt,
1553 unsigned idx, unsigned reg)
1555 struct radeon_cs_reloc *reloc;
1556 struct r100_cs_track *track;
1557 volatile uint32_t *ib;
1565 track = (struct r100_cs_track *)p->track;
1567 idx_value = radeon_get_ib_value(p, idx);
1570 case RADEON_CRTC_GUI_TRIG_VLINE:
1571 r = r100_cs_packet_parse_vline(p);
1573 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1575 radeon_cs_dump_packet(p, pkt);
1579 /* FIXME: only allow PACKET3 blit? easier to check for out of
1581 case RADEON_DST_PITCH_OFFSET:
1582 case RADEON_SRC_PITCH_OFFSET:
1583 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1587 case RADEON_RB3D_DEPTHOFFSET:
1588 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1590 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1592 radeon_cs_dump_packet(p, pkt);
1595 track->zb.robj = reloc->robj;
1596 track->zb.offset = idx_value;
1597 track->zb_dirty = true;
1598 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1600 case RADEON_RB3D_COLOROFFSET:
1601 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1603 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1605 radeon_cs_dump_packet(p, pkt);
1608 track->cb[0].robj = reloc->robj;
1609 track->cb[0].offset = idx_value;
1610 track->cb_dirty = true;
1611 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1613 case RADEON_PP_TXOFFSET_0:
1614 case RADEON_PP_TXOFFSET_1:
1615 case RADEON_PP_TXOFFSET_2:
1616 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1617 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1619 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1621 radeon_cs_dump_packet(p, pkt);
1624 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1625 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1626 tile_flags |= RADEON_TXO_MACRO_TILE;
1627 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1628 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1630 tmp = idx_value & ~(0x7 << 2);
1632 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1634 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1635 track->textures[i].robj = reloc->robj;
1636 track->tex_dirty = true;
1638 case RADEON_PP_CUBIC_OFFSET_T0_0:
1639 case RADEON_PP_CUBIC_OFFSET_T0_1:
1640 case RADEON_PP_CUBIC_OFFSET_T0_2:
1641 case RADEON_PP_CUBIC_OFFSET_T0_3:
1642 case RADEON_PP_CUBIC_OFFSET_T0_4:
1643 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1644 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1646 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1648 radeon_cs_dump_packet(p, pkt);
1651 track->textures[0].cube_info[i].offset = idx_value;
1652 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1653 track->textures[0].cube_info[i].robj = reloc->robj;
1654 track->tex_dirty = true;
1656 case RADEON_PP_CUBIC_OFFSET_T1_0:
1657 case RADEON_PP_CUBIC_OFFSET_T1_1:
1658 case RADEON_PP_CUBIC_OFFSET_T1_2:
1659 case RADEON_PP_CUBIC_OFFSET_T1_3:
1660 case RADEON_PP_CUBIC_OFFSET_T1_4:
1661 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1662 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1664 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1666 radeon_cs_dump_packet(p, pkt);
1669 track->textures[1].cube_info[i].offset = idx_value;
1670 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1671 track->textures[1].cube_info[i].robj = reloc->robj;
1672 track->tex_dirty = true;
1674 case RADEON_PP_CUBIC_OFFSET_T2_0:
1675 case RADEON_PP_CUBIC_OFFSET_T2_1:
1676 case RADEON_PP_CUBIC_OFFSET_T2_2:
1677 case RADEON_PP_CUBIC_OFFSET_T2_3:
1678 case RADEON_PP_CUBIC_OFFSET_T2_4:
1679 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1680 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1682 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1684 radeon_cs_dump_packet(p, pkt);
1687 track->textures[2].cube_info[i].offset = idx_value;
1688 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1689 track->textures[2].cube_info[i].robj = reloc->robj;
1690 track->tex_dirty = true;
1692 case RADEON_RE_WIDTH_HEIGHT:
1693 track->maxy = ((idx_value >> 16) & 0x7FF);
1694 track->cb_dirty = true;
1695 track->zb_dirty = true;
1697 case RADEON_RB3D_COLORPITCH:
1698 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1700 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1702 radeon_cs_dump_packet(p, pkt);
1705 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1706 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1707 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1708 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1709 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1711 tmp = idx_value & ~(0x7 << 16);
1715 ib[idx] = idx_value;
1717 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1718 track->cb_dirty = true;
1720 case RADEON_RB3D_DEPTHPITCH:
1721 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1722 track->zb_dirty = true;
1724 case RADEON_RB3D_CNTL:
1725 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1731 track->cb[0].cpp = 1;
1736 track->cb[0].cpp = 2;
1739 track->cb[0].cpp = 4;
1742 DRM_ERROR("Invalid color buffer format (%d) !\n",
1743 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1746 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1747 track->cb_dirty = true;
1748 track->zb_dirty = true;
1750 case RADEON_RB3D_ZSTENCILCNTL:
1751 switch (idx_value & 0xf) {
1766 track->zb_dirty = true;
1768 case RADEON_RB3D_ZPASS_ADDR:
1769 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1771 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1773 radeon_cs_dump_packet(p, pkt);
1776 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1778 case RADEON_PP_CNTL:
1780 uint32_t temp = idx_value >> 4;
1781 for (i = 0; i < track->num_texture; i++)
1782 track->textures[i].enabled = !!(temp & (1 << i));
1783 track->tex_dirty = true;
1786 case RADEON_SE_VF_CNTL:
1787 track->vap_vf_cntl = idx_value;
1789 case RADEON_SE_VTX_FMT:
1790 track->vtx_size = r100_get_vtx_size(idx_value);
1792 case RADEON_PP_TEX_SIZE_0:
1793 case RADEON_PP_TEX_SIZE_1:
1794 case RADEON_PP_TEX_SIZE_2:
1795 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1796 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1797 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1798 track->tex_dirty = true;
1800 case RADEON_PP_TEX_PITCH_0:
1801 case RADEON_PP_TEX_PITCH_1:
1802 case RADEON_PP_TEX_PITCH_2:
1803 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1804 track->textures[i].pitch = idx_value + 32;
1805 track->tex_dirty = true;
1807 case RADEON_PP_TXFILTER_0:
1808 case RADEON_PP_TXFILTER_1:
1809 case RADEON_PP_TXFILTER_2:
1810 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1811 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1812 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1813 tmp = (idx_value >> 23) & 0x7;
1814 if (tmp == 2 || tmp == 6)
1815 track->textures[i].roundup_w = false;
1816 tmp = (idx_value >> 27) & 0x7;
1817 if (tmp == 2 || tmp == 6)
1818 track->textures[i].roundup_h = false;
1819 track->tex_dirty = true;
1821 case RADEON_PP_TXFORMAT_0:
1822 case RADEON_PP_TXFORMAT_1:
1823 case RADEON_PP_TXFORMAT_2:
1824 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1825 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1826 track->textures[i].use_pitch = 1;
1828 track->textures[i].use_pitch = 0;
1829 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1830 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1832 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1833 track->textures[i].tex_coord_type = 2;
1834 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1835 case RADEON_TXFORMAT_I8:
1836 case RADEON_TXFORMAT_RGB332:
1837 case RADEON_TXFORMAT_Y8:
1838 track->textures[i].cpp = 1;
1839 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1841 case RADEON_TXFORMAT_AI88:
1842 case RADEON_TXFORMAT_ARGB1555:
1843 case RADEON_TXFORMAT_RGB565:
1844 case RADEON_TXFORMAT_ARGB4444:
1845 case RADEON_TXFORMAT_VYUY422:
1846 case RADEON_TXFORMAT_YVYU422:
1847 case RADEON_TXFORMAT_SHADOW16:
1848 case RADEON_TXFORMAT_LDUDV655:
1849 case RADEON_TXFORMAT_DUDV88:
1850 track->textures[i].cpp = 2;
1851 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1853 case RADEON_TXFORMAT_ARGB8888:
1854 case RADEON_TXFORMAT_RGBA8888:
1855 case RADEON_TXFORMAT_SHADOW32:
1856 case RADEON_TXFORMAT_LDUDUV8888:
1857 track->textures[i].cpp = 4;
1858 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1860 case RADEON_TXFORMAT_DXT1:
1861 track->textures[i].cpp = 1;
1862 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1864 case RADEON_TXFORMAT_DXT23:
1865 case RADEON_TXFORMAT_DXT45:
1866 track->textures[i].cpp = 1;
1867 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1870 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1871 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1872 track->tex_dirty = true;
1874 case RADEON_PP_CUBIC_FACES_0:
1875 case RADEON_PP_CUBIC_FACES_1:
1876 case RADEON_PP_CUBIC_FACES_2:
1878 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1879 for (face = 0; face < 4; face++) {
1880 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1881 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1883 track->tex_dirty = true;
1886 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1893 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1894 struct radeon_cs_packet *pkt,
1895 struct radeon_bo *robj)
1900 value = radeon_get_ib_value(p, idx + 2);
1901 if ((value + 1) > radeon_bo_size(robj)) {
1902 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1903 "(need %u have %lu) !\n",
1905 radeon_bo_size(robj));
1911 static int r100_packet3_check(struct radeon_cs_parser *p,
1912 struct radeon_cs_packet *pkt)
1914 struct radeon_cs_reloc *reloc;
1915 struct r100_cs_track *track;
1917 volatile uint32_t *ib;
1922 track = (struct r100_cs_track *)p->track;
1923 switch (pkt->opcode) {
1924 case PACKET3_3D_LOAD_VBPNTR:
1925 r = r100_packet3_load_vbpntr(p, pkt, idx);
1929 case PACKET3_INDX_BUFFER:
1930 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1932 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1933 radeon_cs_dump_packet(p, pkt);
1936 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1937 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1943 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1944 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1946 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1947 radeon_cs_dump_packet(p, pkt);
1950 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1951 track->num_arrays = 1;
1952 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1954 track->arrays[0].robj = reloc->robj;
1955 track->arrays[0].esize = track->vtx_size;
1957 track->max_indx = radeon_get_ib_value(p, idx+1);
1959 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1960 track->immd_dwords = pkt->count - 1;
1961 r = r100_cs_track_check(p->rdev, track);
1965 case PACKET3_3D_DRAW_IMMD:
1966 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1967 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1970 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1971 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1972 track->immd_dwords = pkt->count - 1;
1973 r = r100_cs_track_check(p->rdev, track);
1977 /* triggers drawing using in-packet vertex data */
1978 case PACKET3_3D_DRAW_IMMD_2:
1979 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1980 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1983 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1984 track->immd_dwords = pkt->count;
1985 r = r100_cs_track_check(p->rdev, track);
1989 /* triggers drawing using in-packet vertex data */
1990 case PACKET3_3D_DRAW_VBUF_2:
1991 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1992 r = r100_cs_track_check(p->rdev, track);
1996 /* triggers drawing of vertex buffers setup elsewhere */
1997 case PACKET3_3D_DRAW_INDX_2:
1998 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1999 r = r100_cs_track_check(p->rdev, track);
2003 /* triggers drawing using indices to vertex buffer */
2004 case PACKET3_3D_DRAW_VBUF:
2005 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2006 r = r100_cs_track_check(p->rdev, track);
2010 /* triggers drawing of vertex buffers setup elsewhere */
2011 case PACKET3_3D_DRAW_INDX:
2012 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2013 r = r100_cs_track_check(p->rdev, track);
2017 /* triggers drawing using indices to vertex buffer */
2018 case PACKET3_3D_CLEAR_HIZ:
2019 case PACKET3_3D_CLEAR_ZMASK:
2020 if (p->rdev->hyperz_filp != p->filp)
2026 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2032 int r100_cs_parse(struct radeon_cs_parser *p)
2034 struct radeon_cs_packet pkt;
2035 struct r100_cs_track *track;
2038 track = kzalloc(sizeof(*track), GFP_KERNEL);
2041 r100_cs_track_clear(p->rdev, track);
2044 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2048 p->idx += pkt.count + 2;
2050 case RADEON_PACKET_TYPE0:
2051 if (p->rdev->family >= CHIP_R200)
2052 r = r100_cs_parse_packet0(p, &pkt,
2053 p->rdev->config.r100.reg_safe_bm,
2054 p->rdev->config.r100.reg_safe_bm_size,
2055 &r200_packet0_check);
2057 r = r100_cs_parse_packet0(p, &pkt,
2058 p->rdev->config.r100.reg_safe_bm,
2059 p->rdev->config.r100.reg_safe_bm_size,
2060 &r100_packet0_check);
2062 case RADEON_PACKET_TYPE2:
2064 case RADEON_PACKET_TYPE3:
2065 r = r100_packet3_check(p, &pkt);
2068 DRM_ERROR("Unknown packet type %d !\n",
2074 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2078 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2080 DRM_ERROR("pitch %d\n", t->pitch);
2081 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2082 DRM_ERROR("width %d\n", t->width);
2083 DRM_ERROR("width_11 %d\n", t->width_11);
2084 DRM_ERROR("height %d\n", t->height);
2085 DRM_ERROR("height_11 %d\n", t->height_11);
2086 DRM_ERROR("num levels %d\n", t->num_levels);
2087 DRM_ERROR("depth %d\n", t->txdepth);
2088 DRM_ERROR("bpp %d\n", t->cpp);
2089 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2090 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2091 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2092 DRM_ERROR("compress format %d\n", t->compress_format);
2095 static int r100_track_compress_size(int compress_format, int w, int h)
2097 int block_width, block_height, block_bytes;
2098 int wblocks, hblocks;
2105 switch (compress_format) {
2106 case R100_TRACK_COMP_DXT1:
2111 case R100_TRACK_COMP_DXT35:
2117 hblocks = (h + block_height - 1) / block_height;
2118 wblocks = (w + block_width - 1) / block_width;
2119 if (wblocks < min_wblocks)
2120 wblocks = min_wblocks;
2121 sz = wblocks * hblocks * block_bytes;
2125 static int r100_cs_track_cube(struct radeon_device *rdev,
2126 struct r100_cs_track *track, unsigned idx)
2128 unsigned face, w, h;
2129 struct radeon_bo *cube_robj;
2131 unsigned compress_format = track->textures[idx].compress_format;
2133 for (face = 0; face < 5; face++) {
2134 cube_robj = track->textures[idx].cube_info[face].robj;
2135 w = track->textures[idx].cube_info[face].width;
2136 h = track->textures[idx].cube_info[face].height;
2138 if (compress_format) {
2139 size = r100_track_compress_size(compress_format, w, h);
2142 size *= track->textures[idx].cpp;
2144 size += track->textures[idx].cube_info[face].offset;
2146 if (size > radeon_bo_size(cube_robj)) {
2147 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2148 size, radeon_bo_size(cube_robj));
2149 r100_cs_track_texture_print(&track->textures[idx]);
2156 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2157 struct r100_cs_track *track)
2159 struct radeon_bo *robj;
2161 unsigned u, i, w, h, d;
2164 for (u = 0; u < track->num_texture; u++) {
2165 if (!track->textures[u].enabled)
2167 if (track->textures[u].lookup_disable)
2169 robj = track->textures[u].robj;
2171 DRM_ERROR("No texture bound to unit %u\n", u);
2175 for (i = 0; i <= track->textures[u].num_levels; i++) {
2176 if (track->textures[u].use_pitch) {
2177 if (rdev->family < CHIP_R300)
2178 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2180 w = track->textures[u].pitch / (1 << i);
2182 w = track->textures[u].width;
2183 if (rdev->family >= CHIP_RV515)
2184 w |= track->textures[u].width_11;
2186 if (track->textures[u].roundup_w)
2187 w = roundup_pow_of_two(w);
2189 h = track->textures[u].height;
2190 if (rdev->family >= CHIP_RV515)
2191 h |= track->textures[u].height_11;
2193 if (track->textures[u].roundup_h)
2194 h = roundup_pow_of_two(h);
2195 if (track->textures[u].tex_coord_type == 1) {
2196 d = (1 << track->textures[u].txdepth) / (1 << i);
2202 if (track->textures[u].compress_format) {
2204 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2205 /* compressed textures are block based */
2209 size *= track->textures[u].cpp;
2211 switch (track->textures[u].tex_coord_type) {
2216 if (track->separate_cube) {
2217 ret = r100_cs_track_cube(rdev, track, u);
2224 DRM_ERROR("Invalid texture coordinate type %u for unit "
2225 "%u\n", track->textures[u].tex_coord_type, u);
2228 if (size > radeon_bo_size(robj)) {
2229 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2230 "%lu\n", u, size, radeon_bo_size(robj));
2231 r100_cs_track_texture_print(&track->textures[u]);
2238 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2244 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2246 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2247 !track->blend_read_enable)
2250 for (i = 0; i < num_cb; i++) {
2251 if (track->cb[i].robj == NULL) {
2252 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2255 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2256 size += track->cb[i].offset;
2257 if (size > radeon_bo_size(track->cb[i].robj)) {
2258 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2259 "(need %lu have %lu) !\n", i, size,
2260 radeon_bo_size(track->cb[i].robj));
2261 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2262 i, track->cb[i].pitch, track->cb[i].cpp,
2263 track->cb[i].offset, track->maxy);
2267 track->cb_dirty = false;
2269 if (track->zb_dirty && track->z_enabled) {
2270 if (track->zb.robj == NULL) {
2271 DRM_ERROR("[drm] No buffer for z buffer !\n");
2274 size = track->zb.pitch * track->zb.cpp * track->maxy;
2275 size += track->zb.offset;
2276 if (size > radeon_bo_size(track->zb.robj)) {
2277 DRM_ERROR("[drm] Buffer too small for z buffer "
2278 "(need %lu have %lu) !\n", size,
2279 radeon_bo_size(track->zb.robj));
2280 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2281 track->zb.pitch, track->zb.cpp,
2282 track->zb.offset, track->maxy);
2286 track->zb_dirty = false;
2288 if (track->aa_dirty && track->aaresolve) {
2289 if (track->aa.robj == NULL) {
2290 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2293 /* I believe the format comes from colorbuffer0. */
2294 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2295 size += track->aa.offset;
2296 if (size > radeon_bo_size(track->aa.robj)) {
2297 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2298 "(need %lu have %lu) !\n", i, size,
2299 radeon_bo_size(track->aa.robj));
2300 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2301 i, track->aa.pitch, track->cb[0].cpp,
2302 track->aa.offset, track->maxy);
2306 track->aa_dirty = false;
2308 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2309 if (track->vap_vf_cntl & (1 << 14)) {
2310 nverts = track->vap_alt_nverts;
2312 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2314 switch (prim_walk) {
2316 for (i = 0; i < track->num_arrays; i++) {
2317 size = track->arrays[i].esize * track->max_indx * 4;
2318 if (track->arrays[i].robj == NULL) {
2319 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2320 "bound\n", prim_walk, i);
2323 if (size > radeon_bo_size(track->arrays[i].robj)) {
2324 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2325 "need %lu dwords have %lu dwords\n",
2326 prim_walk, i, size >> 2,
2327 radeon_bo_size(track->arrays[i].robj)
2329 DRM_ERROR("Max indices %u\n", track->max_indx);
2335 for (i = 0; i < track->num_arrays; i++) {
2336 size = track->arrays[i].esize * (nverts - 1) * 4;
2337 if (track->arrays[i].robj == NULL) {
2338 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2339 "bound\n", prim_walk, i);
2342 if (size > radeon_bo_size(track->arrays[i].robj)) {
2343 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2344 "need %lu dwords have %lu dwords\n",
2345 prim_walk, i, size >> 2,
2346 radeon_bo_size(track->arrays[i].robj)
2353 size = track->vtx_size * nverts;
2354 if (size != track->immd_dwords) {
2355 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2356 track->immd_dwords, size);
2357 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2358 nverts, track->vtx_size);
2363 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2368 if (track->tex_dirty) {
2369 track->tex_dirty = false;
2370 return r100_cs_track_texture_check(rdev, track);
2375 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2379 track->cb_dirty = true;
2380 track->zb_dirty = true;
2381 track->tex_dirty = true;
2382 track->aa_dirty = true;
2384 if (rdev->family < CHIP_R300) {
2386 if (rdev->family <= CHIP_RS200)
2387 track->num_texture = 3;
2389 track->num_texture = 6;
2391 track->separate_cube = 1;
2394 track->num_texture = 16;
2396 track->separate_cube = 0;
2397 track->aaresolve = false;
2398 track->aa.robj = NULL;
2401 for (i = 0; i < track->num_cb; i++) {
2402 track->cb[i].robj = NULL;
2403 track->cb[i].pitch = 8192;
2404 track->cb[i].cpp = 16;
2405 track->cb[i].offset = 0;
2407 track->z_enabled = true;
2408 track->zb.robj = NULL;
2409 track->zb.pitch = 8192;
2411 track->zb.offset = 0;
2412 track->vtx_size = 0x7F;
2413 track->immd_dwords = 0xFFFFFFFFUL;
2414 track->num_arrays = 11;
2415 track->max_indx = 0x00FFFFFFUL;
2416 for (i = 0; i < track->num_arrays; i++) {
2417 track->arrays[i].robj = NULL;
2418 track->arrays[i].esize = 0x7F;
2420 for (i = 0; i < track->num_texture; i++) {
2421 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2422 track->textures[i].pitch = 16536;
2423 track->textures[i].width = 16536;
2424 track->textures[i].height = 16536;
2425 track->textures[i].width_11 = 1 << 11;
2426 track->textures[i].height_11 = 1 << 11;
2427 track->textures[i].num_levels = 12;
2428 if (rdev->family <= CHIP_RS200) {
2429 track->textures[i].tex_coord_type = 0;
2430 track->textures[i].txdepth = 0;
2432 track->textures[i].txdepth = 16;
2433 track->textures[i].tex_coord_type = 1;
2435 track->textures[i].cpp = 64;
2436 track->textures[i].robj = NULL;
2437 /* CS IB emission code makes sure texture unit are disabled */
2438 track->textures[i].enabled = false;
2439 track->textures[i].lookup_disable = false;
2440 track->textures[i].roundup_w = true;
2441 track->textures[i].roundup_h = true;
2442 if (track->separate_cube)
2443 for (face = 0; face < 5; face++) {
2444 track->textures[i].cube_info[face].robj = NULL;
2445 track->textures[i].cube_info[face].width = 16536;
2446 track->textures[i].cube_info[face].height = 16536;
2447 track->textures[i].cube_info[face].offset = 0;
2453 * Global GPU functions
2455 static void r100_errata(struct radeon_device *rdev)
2457 rdev->pll_errata = 0;
2459 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2460 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2463 if (rdev->family == CHIP_RV100 ||
2464 rdev->family == CHIP_RS100 ||
2465 rdev->family == CHIP_RS200) {
2466 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2470 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2475 for (i = 0; i < rdev->usec_timeout; i++) {
2476 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2485 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2490 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2491 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2492 " Bad things might happen.\n");
2494 for (i = 0; i < rdev->usec_timeout; i++) {
2495 tmp = RREG32(RADEON_RBBM_STATUS);
2496 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2504 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2509 for (i = 0; i < rdev->usec_timeout; i++) {
2510 /* read MC_STATUS */
2511 tmp = RREG32(RADEON_MC_STATUS);
2512 if (tmp & RADEON_MC_IDLE) {
2520 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2524 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2525 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2526 radeon_ring_lockup_update(ring);
2529 /* force CP activities */
2530 radeon_ring_force_activity(rdev, ring);
2531 return radeon_ring_test_lockup(rdev, ring);
2534 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2535 void r100_enable_bm(struct radeon_device *rdev)
2538 /* Enable bus mastering */
2539 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2540 WREG32(RADEON_BUS_CNTL, tmp);
2543 void r100_bm_disable(struct radeon_device *rdev)
2547 /* disable bus mastering */
2548 tmp = RREG32(R_000030_BUS_CNTL);
2549 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2551 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2553 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2554 tmp = RREG32(RADEON_BUS_CNTL);
2556 pci_clear_master(rdev->pdev);
2560 int r100_asic_reset(struct radeon_device *rdev)
2562 struct r100_mc_save save;
2566 status = RREG32(R_000E40_RBBM_STATUS);
2567 if (!G_000E40_GUI_ACTIVE(status)) {
2570 r100_mc_stop(rdev, &save);
2571 status = RREG32(R_000E40_RBBM_STATUS);
2572 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2574 WREG32(RADEON_CP_CSQ_CNTL, 0);
2575 tmp = RREG32(RADEON_CP_RB_CNTL);
2576 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2577 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2578 WREG32(RADEON_CP_RB_WPTR, 0);
2579 WREG32(RADEON_CP_RB_CNTL, tmp);
2580 /* save PCI state */
2581 pci_save_state(rdev->pdev);
2582 /* disable bus mastering */
2583 r100_bm_disable(rdev);
2584 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2585 S_0000F0_SOFT_RESET_RE(1) |
2586 S_0000F0_SOFT_RESET_PP(1) |
2587 S_0000F0_SOFT_RESET_RB(1));
2588 RREG32(R_0000F0_RBBM_SOFT_RESET);
2590 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2592 status = RREG32(R_000E40_RBBM_STATUS);
2593 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2595 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2596 RREG32(R_0000F0_RBBM_SOFT_RESET);
2598 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2600 status = RREG32(R_000E40_RBBM_STATUS);
2601 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2602 /* restore PCI & busmastering */
2603 pci_restore_state(rdev->pdev);
2604 r100_enable_bm(rdev);
2605 /* Check if GPU is idle */
2606 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2607 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2608 dev_err(rdev->dev, "failed to reset GPU\n");
2611 dev_info(rdev->dev, "GPU reset succeed\n");
2612 r100_mc_resume(rdev, &save);
2616 void r100_set_common_regs(struct radeon_device *rdev)
2618 struct drm_device *dev = rdev->ddev;
2619 bool force_dac2 = false;
2622 /* set these so they don't interfere with anything */
2623 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2624 WREG32(RADEON_SUBPIC_CNTL, 0);
2625 WREG32(RADEON_VIPH_CONTROL, 0);
2626 WREG32(RADEON_I2C_CNTL_1, 0);
2627 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2628 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2629 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2631 /* always set up dac2 on rn50 and some rv100 as lots
2632 * of servers seem to wire it up to a VGA port but
2633 * don't report it in the bios connector
2636 switch (dev->pdev->device) {
2645 /* DELL triple head servers */
2646 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2647 ((dev->pdev->subsystem_device == 0x016c) ||
2648 (dev->pdev->subsystem_device == 0x016d) ||
2649 (dev->pdev->subsystem_device == 0x016e) ||
2650 (dev->pdev->subsystem_device == 0x016f) ||
2651 (dev->pdev->subsystem_device == 0x0170) ||
2652 (dev->pdev->subsystem_device == 0x017d) ||
2653 (dev->pdev->subsystem_device == 0x017e) ||
2654 (dev->pdev->subsystem_device == 0x0183) ||
2655 (dev->pdev->subsystem_device == 0x018a) ||
2656 (dev->pdev->subsystem_device == 0x019a)))
2662 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2663 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2664 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2666 /* For CRT on DAC2, don't turn it on if BIOS didn't
2667 enable it, even it's detected.
2670 /* force it to crtc0 */
2671 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2672 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2673 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2675 /* set up the TV DAC */
2676 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2677 RADEON_TV_DAC_STD_MASK |
2678 RADEON_TV_DAC_RDACPD |
2679 RADEON_TV_DAC_GDACPD |
2680 RADEON_TV_DAC_BDACPD |
2681 RADEON_TV_DAC_BGADJ_MASK |
2682 RADEON_TV_DAC_DACADJ_MASK);
2683 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2684 RADEON_TV_DAC_NHOLD |
2685 RADEON_TV_DAC_STD_PS2 |
2688 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2689 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2690 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2693 /* switch PM block to ACPI mode */
2694 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2695 tmp &= ~RADEON_PM_MODE_SEL;
2696 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2703 static void r100_vram_get_type(struct radeon_device *rdev)
2707 rdev->mc.vram_is_ddr = false;
2708 if (rdev->flags & RADEON_IS_IGP)
2709 rdev->mc.vram_is_ddr = true;
2710 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2711 rdev->mc.vram_is_ddr = true;
2712 if ((rdev->family == CHIP_RV100) ||
2713 (rdev->family == CHIP_RS100) ||
2714 (rdev->family == CHIP_RS200)) {
2715 tmp = RREG32(RADEON_MEM_CNTL);
2716 if (tmp & RV100_HALF_MODE) {
2717 rdev->mc.vram_width = 32;
2719 rdev->mc.vram_width = 64;
2721 if (rdev->flags & RADEON_SINGLE_CRTC) {
2722 rdev->mc.vram_width /= 4;
2723 rdev->mc.vram_is_ddr = true;
2725 } else if (rdev->family <= CHIP_RV280) {
2726 tmp = RREG32(RADEON_MEM_CNTL);
2727 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2728 rdev->mc.vram_width = 128;
2730 rdev->mc.vram_width = 64;
2734 rdev->mc.vram_width = 128;
2738 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2743 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2745 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2746 * that is has the 2nd generation multifunction PCI interface
2748 if (rdev->family == CHIP_RV280 ||
2749 rdev->family >= CHIP_RV350) {
2750 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2751 ~RADEON_HDP_APER_CNTL);
2752 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2753 return aper_size * 2;
2756 /* Older cards have all sorts of funny issues to deal with. First
2757 * check if it's a multifunction card by reading the PCI config
2758 * header type... Limit those to one aperture size
2760 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2762 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2763 DRM_INFO("Limiting VRAM to one aperture\n");
2767 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2768 * have set it up. We don't write this as it's broken on some ASICs but
2769 * we expect the BIOS to have done the right thing (might be too optimistic...)
2771 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2772 return aper_size * 2;
2776 void r100_vram_init_sizes(struct radeon_device *rdev)
2778 u64 config_aper_size;
2780 /* work out accessible VRAM */
2781 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2782 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2783 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2784 /* FIXME we don't use the second aperture yet when we could use it */
2785 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2786 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2787 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2788 if (rdev->flags & RADEON_IS_IGP) {
2790 /* read NB_TOM to get the amount of ram stolen for the GPU */
2791 tom = RREG32(RADEON_NB_TOM);
2792 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2793 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2794 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2796 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2797 /* Some production boards of m6 will report 0
2800 if (rdev->mc.real_vram_size == 0) {
2801 rdev->mc.real_vram_size = 8192 * 1024;
2802 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2804 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2805 * Novell bug 204882 + along with lots of ubuntu ones
2807 if (rdev->mc.aper_size > config_aper_size)
2808 config_aper_size = rdev->mc.aper_size;
2810 if (config_aper_size > rdev->mc.real_vram_size)
2811 rdev->mc.mc_vram_size = config_aper_size;
2813 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2817 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2821 temp = RREG32(RADEON_CONFIG_CNTL);
2822 if (state == false) {
2823 temp &= ~RADEON_CFG_VGA_RAM_EN;
2824 temp |= RADEON_CFG_VGA_IO_DIS;
2826 temp &= ~RADEON_CFG_VGA_IO_DIS;
2828 WREG32(RADEON_CONFIG_CNTL, temp);
2831 static void r100_mc_init(struct radeon_device *rdev)
2835 r100_vram_get_type(rdev);
2836 r100_vram_init_sizes(rdev);
2837 base = rdev->mc.aper_base;
2838 if (rdev->flags & RADEON_IS_IGP)
2839 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2840 radeon_vram_location(rdev, &rdev->mc, base);
2841 rdev->mc.gtt_base_align = 0;
2842 if (!(rdev->flags & RADEON_IS_AGP))
2843 radeon_gtt_location(rdev, &rdev->mc);
2844 radeon_update_bandwidth_info(rdev);
2849 * Indirect registers accessor
2851 void r100_pll_errata_after_index(struct radeon_device *rdev)
2853 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2854 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2855 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2859 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2861 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2862 * or the chip could hang on a subsequent access
2864 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2868 /* This function is required to workaround a hardware bug in some (all?)
2869 * revisions of the R300. This workaround should be called after every
2870 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2871 * may not be correct.
2873 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2876 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2877 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2878 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2879 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2880 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2884 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2886 unsigned long flags;
2889 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2890 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2891 r100_pll_errata_after_index(rdev);
2892 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2893 r100_pll_errata_after_data(rdev);
2894 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2898 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2900 unsigned long flags;
2902 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2903 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2904 r100_pll_errata_after_index(rdev);
2905 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2906 r100_pll_errata_after_data(rdev);
2907 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2910 static void r100_set_safe_registers(struct radeon_device *rdev)
2912 if (ASIC_IS_RN50(rdev)) {
2913 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2914 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2915 } else if (rdev->family < CHIP_R200) {
2916 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2917 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2919 r200_set_safe_registers(rdev);
2926 #if defined(CONFIG_DEBUG_FS)
2927 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2929 struct drm_info_node *node = (struct drm_info_node *) m->private;
2930 struct drm_device *dev = node->minor->dev;
2931 struct radeon_device *rdev = dev->dev_private;
2932 uint32_t reg, value;
2935 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2936 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2937 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2938 for (i = 0; i < 64; i++) {
2939 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2940 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2941 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2942 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2943 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2948 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2950 struct drm_info_node *node = (struct drm_info_node *) m->private;
2951 struct drm_device *dev = node->minor->dev;
2952 struct radeon_device *rdev = dev->dev_private;
2953 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2955 unsigned count, i, j;
2957 radeon_ring_free_size(rdev, ring);
2958 rdp = RREG32(RADEON_CP_RB_RPTR);
2959 wdp = RREG32(RADEON_CP_RB_WPTR);
2960 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2961 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2962 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2963 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2964 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2965 seq_printf(m, "%u dwords in ring\n", count);
2967 for (j = 0; j <= count; j++) {
2968 i = (rdp + j) & ring->ptr_mask;
2969 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2976 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2978 struct drm_info_node *node = (struct drm_info_node *) m->private;
2979 struct drm_device *dev = node->minor->dev;
2980 struct radeon_device *rdev = dev->dev_private;
2981 uint32_t csq_stat, csq2_stat, tmp;
2982 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2985 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2986 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2987 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2988 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2989 r_rptr = (csq_stat >> 0) & 0x3ff;
2990 r_wptr = (csq_stat >> 10) & 0x3ff;
2991 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2992 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2993 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2994 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2995 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2996 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2997 seq_printf(m, "Ring rptr %u\n", r_rptr);
2998 seq_printf(m, "Ring wptr %u\n", r_wptr);
2999 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3000 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3001 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3002 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3003 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3004 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3005 seq_printf(m, "Ring fifo:\n");
3006 for (i = 0; i < 256; i++) {
3007 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3008 tmp = RREG32(RADEON_CP_CSQ_DATA);
3009 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3011 seq_printf(m, "Indirect1 fifo:\n");
3012 for (i = 256; i <= 512; i++) {
3013 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3014 tmp = RREG32(RADEON_CP_CSQ_DATA);
3015 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3017 seq_printf(m, "Indirect2 fifo:\n");
3018 for (i = 640; i < ib1_wptr; i++) {
3019 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3020 tmp = RREG32(RADEON_CP_CSQ_DATA);
3021 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3026 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3028 struct drm_info_node *node = (struct drm_info_node *) m->private;
3029 struct drm_device *dev = node->minor->dev;
3030 struct radeon_device *rdev = dev->dev_private;
3033 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3034 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3035 tmp = RREG32(RADEON_MC_FB_LOCATION);
3036 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3037 tmp = RREG32(RADEON_BUS_CNTL);
3038 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3039 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3040 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3041 tmp = RREG32(RADEON_AGP_BASE);
3042 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3043 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3044 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3045 tmp = RREG32(0x01D0);
3046 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3047 tmp = RREG32(RADEON_AIC_LO_ADDR);
3048 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3049 tmp = RREG32(RADEON_AIC_HI_ADDR);
3050 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3051 tmp = RREG32(0x01E4);
3052 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3056 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3057 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3060 static struct drm_info_list r100_debugfs_cp_list[] = {
3061 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3062 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3065 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3066 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3070 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3072 #if defined(CONFIG_DEBUG_FS)
3073 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3079 int r100_debugfs_cp_init(struct radeon_device *rdev)
3081 #if defined(CONFIG_DEBUG_FS)
3082 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3088 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3090 #if defined(CONFIG_DEBUG_FS)
3091 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3097 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3098 uint32_t tiling_flags, uint32_t pitch,
3099 uint32_t offset, uint32_t obj_size)
3101 int surf_index = reg * 16;
3104 if (rdev->family <= CHIP_RS200) {
3105 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3106 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3107 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3108 if (tiling_flags & RADEON_TILING_MACRO)
3109 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3110 /* setting pitch to 0 disables tiling */
3111 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3114 } else if (rdev->family <= CHIP_RV280) {
3115 if (tiling_flags & (RADEON_TILING_MACRO))
3116 flags |= R200_SURF_TILE_COLOR_MACRO;
3117 if (tiling_flags & RADEON_TILING_MICRO)
3118 flags |= R200_SURF_TILE_COLOR_MICRO;
3120 if (tiling_flags & RADEON_TILING_MACRO)
3121 flags |= R300_SURF_TILE_MACRO;
3122 if (tiling_flags & RADEON_TILING_MICRO)
3123 flags |= R300_SURF_TILE_MICRO;
3126 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3127 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3128 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3129 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3131 /* r100/r200 divide by 16 */
3132 if (rdev->family < CHIP_R300)
3133 flags |= pitch / 16;
3138 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3139 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3140 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3141 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3145 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3147 int surf_index = reg * 16;
3148 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3151 void r100_bandwidth_update(struct radeon_device *rdev)
3153 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3154 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3155 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3156 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3157 fixed20_12 memtcas_ff[8] = {
3162 dfixed_init_half(1),
3163 dfixed_init_half(2),
3166 fixed20_12 memtcas_rs480_ff[8] = {
3172 dfixed_init_half(1),
3173 dfixed_init_half(2),
3174 dfixed_init_half(3),
3176 fixed20_12 memtcas2_ff[8] = {
3186 fixed20_12 memtrbs[8] = {
3188 dfixed_init_half(1),
3190 dfixed_init_half(2),
3192 dfixed_init_half(3),
3196 fixed20_12 memtrbs_r4xx[8] = {
3206 fixed20_12 min_mem_eff;
3207 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3208 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3209 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3210 disp_drain_rate2, read_return_rate;
3211 fixed20_12 time_disp1_drop_priority;
3213 int cur_size = 16; /* in octawords */
3214 int critical_point = 0, critical_point2;
3215 /* uint32_t read_return_rate, time_disp1_drop_priority; */
3216 int stop_req, max_stop_req;
3217 struct drm_display_mode *mode1 = NULL;
3218 struct drm_display_mode *mode2 = NULL;
3219 uint32_t pixel_bytes1 = 0;
3220 uint32_t pixel_bytes2 = 0;
3222 radeon_update_display_priority(rdev);
3224 if (rdev->mode_info.crtcs[0]->base.enabled) {
3225 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3226 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3228 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3229 if (rdev->mode_info.crtcs[1]->base.enabled) {
3230 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3231 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3235 min_mem_eff.full = dfixed_const_8(0);
3237 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3238 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3239 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3240 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3241 /* check crtc enables */
3243 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3245 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3246 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3250 * determine is there is enough bw for current mode
3252 sclk_ff = rdev->pm.sclk;
3253 mclk_ff = rdev->pm.mclk;
3255 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3256 temp_ff.full = dfixed_const(temp);
3257 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3261 peak_disp_bw.full = 0;
3263 temp_ff.full = dfixed_const(1000);
3264 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3265 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3266 temp_ff.full = dfixed_const(pixel_bytes1);
3267 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3270 temp_ff.full = dfixed_const(1000);
3271 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3272 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3273 temp_ff.full = dfixed_const(pixel_bytes2);
3274 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3277 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3278 if (peak_disp_bw.full >= mem_bw.full) {
3279 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3280 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3283 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3284 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3285 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3286 mem_trcd = ((temp >> 2) & 0x3) + 1;
3287 mem_trp = ((temp & 0x3)) + 1;
3288 mem_tras = ((temp & 0x70) >> 4) + 1;
3289 } else if (rdev->family == CHIP_R300 ||
3290 rdev->family == CHIP_R350) { /* r300, r350 */
3291 mem_trcd = (temp & 0x7) + 1;
3292 mem_trp = ((temp >> 8) & 0x7) + 1;
3293 mem_tras = ((temp >> 11) & 0xf) + 4;
3294 } else if (rdev->family == CHIP_RV350 ||
3295 rdev->family <= CHIP_RV380) {
3297 mem_trcd = (temp & 0x7) + 3;
3298 mem_trp = ((temp >> 8) & 0x7) + 3;
3299 mem_tras = ((temp >> 11) & 0xf) + 6;
3300 } else if (rdev->family == CHIP_R420 ||
3301 rdev->family == CHIP_R423 ||
3302 rdev->family == CHIP_RV410) {
3304 mem_trcd = (temp & 0xf) + 3;
3307 mem_trp = ((temp >> 8) & 0xf) + 3;
3310 mem_tras = ((temp >> 12) & 0x1f) + 6;
3313 } else { /* RV200, R200 */
3314 mem_trcd = (temp & 0x7) + 1;
3315 mem_trp = ((temp >> 8) & 0x7) + 1;
3316 mem_tras = ((temp >> 12) & 0xf) + 4;
3319 trcd_ff.full = dfixed_const(mem_trcd);
3320 trp_ff.full = dfixed_const(mem_trp);
3321 tras_ff.full = dfixed_const(mem_tras);
3323 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3324 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3325 data = (temp & (7 << 20)) >> 20;
3326 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3327 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3328 tcas_ff = memtcas_rs480_ff[data];
3330 tcas_ff = memtcas_ff[data];
3332 tcas_ff = memtcas2_ff[data];
3334 if (rdev->family == CHIP_RS400 ||
3335 rdev->family == CHIP_RS480) {
3336 /* extra cas latency stored in bits 23-25 0-4 clocks */
3337 data = (temp >> 23) & 0x7;
3339 tcas_ff.full += dfixed_const(data);
3342 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3343 /* on the R300, Tcas is included in Trbs.
3345 temp = RREG32(RADEON_MEM_CNTL);
3346 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3348 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3349 temp = RREG32(R300_MC_IND_INDEX);
3350 temp &= ~R300_MC_IND_ADDR_MASK;
3351 temp |= R300_MC_READ_CNTL_CD_mcind;
3352 WREG32(R300_MC_IND_INDEX, temp);
3353 temp = RREG32(R300_MC_IND_DATA);
3354 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3356 temp = RREG32(R300_MC_READ_CNTL_AB);
3357 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3360 temp = RREG32(R300_MC_READ_CNTL_AB);
3361 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3363 if (rdev->family == CHIP_RV410 ||
3364 rdev->family == CHIP_R420 ||
3365 rdev->family == CHIP_R423)
3366 trbs_ff = memtrbs_r4xx[data];
3368 trbs_ff = memtrbs[data];
3369 tcas_ff.full += trbs_ff.full;
3372 sclk_eff_ff.full = sclk_ff.full;
3374 if (rdev->flags & RADEON_IS_AGP) {
3375 fixed20_12 agpmode_ff;
3376 agpmode_ff.full = dfixed_const(radeon_agpmode);
3377 temp_ff.full = dfixed_const_666(16);
3378 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3380 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3382 if (ASIC_IS_R300(rdev)) {
3383 sclk_delay_ff.full = dfixed_const(250);
3385 if ((rdev->family == CHIP_RV100) ||
3386 rdev->flags & RADEON_IS_IGP) {
3387 if (rdev->mc.vram_is_ddr)
3388 sclk_delay_ff.full = dfixed_const(41);
3390 sclk_delay_ff.full = dfixed_const(33);
3392 if (rdev->mc.vram_width == 128)
3393 sclk_delay_ff.full = dfixed_const(57);
3395 sclk_delay_ff.full = dfixed_const(41);
3399 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3401 if (rdev->mc.vram_is_ddr) {
3402 if (rdev->mc.vram_width == 32) {
3403 k1.full = dfixed_const(40);
3406 k1.full = dfixed_const(20);
3410 k1.full = dfixed_const(40);
3414 temp_ff.full = dfixed_const(2);
3415 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3416 temp_ff.full = dfixed_const(c);
3417 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3418 temp_ff.full = dfixed_const(4);
3419 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3420 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3421 mc_latency_mclk.full += k1.full;
3423 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3424 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3427 HW cursor time assuming worst case of full size colour cursor.
3429 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3430 temp_ff.full += trcd_ff.full;
3431 if (temp_ff.full < tras_ff.full)
3432 temp_ff.full = tras_ff.full;
3433 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3435 temp_ff.full = dfixed_const(cur_size);
3436 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3438 Find the total latency for the display data.
3440 disp_latency_overhead.full = dfixed_const(8);
3441 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3442 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3443 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3445 if (mc_latency_mclk.full > mc_latency_sclk.full)
3446 disp_latency.full = mc_latency_mclk.full;
3448 disp_latency.full = mc_latency_sclk.full;
3450 /* setup Max GRPH_STOP_REQ default value */
3451 if (ASIC_IS_RV100(rdev))
3452 max_stop_req = 0x5c;
3454 max_stop_req = 0x7c;
3458 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3459 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3461 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3463 if (stop_req > max_stop_req)
3464 stop_req = max_stop_req;
3467 Find the drain rate of the display buffer.
3469 temp_ff.full = dfixed_const((16/pixel_bytes1));
3470 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3473 Find the critical point of the display buffer.
3475 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3476 crit_point_ff.full += dfixed_const_half(0);
3478 critical_point = dfixed_trunc(crit_point_ff);
3480 if (rdev->disp_priority == 2) {
3485 The critical point should never be above max_stop_req-4. Setting
3486 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3488 if (max_stop_req - critical_point < 4)
3491 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3492 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3493 critical_point = 0x10;
3496 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3497 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3498 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3499 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3500 if ((rdev->family == CHIP_R350) &&
3501 (stop_req > 0x15)) {
3504 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3505 temp |= RADEON_GRPH_BUFFER_SIZE;
3506 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3507 RADEON_GRPH_CRITICAL_AT_SOF |
3508 RADEON_GRPH_STOP_CNTL);
3510 Write the result into the register.
3512 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3513 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3516 if ((rdev->family == CHIP_RS400) ||
3517 (rdev->family == CHIP_RS480)) {
3518 /* attempt to program RS400 disp regs correctly ??? */
3519 temp = RREG32(RS400_DISP1_REG_CNTL);
3520 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3521 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3522 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3523 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3524 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3525 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3526 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3527 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3528 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3529 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3530 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3534 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3535 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3536 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3541 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3543 if (stop_req > max_stop_req)
3544 stop_req = max_stop_req;
3547 Find the drain rate of the display buffer.
3549 temp_ff.full = dfixed_const((16/pixel_bytes2));
3550 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3552 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3553 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3554 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3555 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3556 if ((rdev->family == CHIP_R350) &&
3557 (stop_req > 0x15)) {
3560 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3561 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3562 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3563 RADEON_GRPH_CRITICAL_AT_SOF |
3564 RADEON_GRPH_STOP_CNTL);
3566 if ((rdev->family == CHIP_RS100) ||
3567 (rdev->family == CHIP_RS200))
3568 critical_point2 = 0;
3570 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3571 temp_ff.full = dfixed_const(temp);
3572 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3573 if (sclk_ff.full < temp_ff.full)
3574 temp_ff.full = sclk_ff.full;
3576 read_return_rate.full = temp_ff.full;
3579 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3580 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3582 time_disp1_drop_priority.full = 0;
3584 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3585 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3586 crit_point_ff.full += dfixed_const_half(0);
3588 critical_point2 = dfixed_trunc(crit_point_ff);
3590 if (rdev->disp_priority == 2) {
3591 critical_point2 = 0;
3594 if (max_stop_req - critical_point2 < 4)
3595 critical_point2 = 0;
3599 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3600 /* some R300 cards have problem with this set to 0 */
3601 critical_point2 = 0x10;
3604 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3605 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3607 if ((rdev->family == CHIP_RS400) ||
3608 (rdev->family == CHIP_RS480)) {
3610 /* attempt to program RS400 disp2 regs correctly ??? */
3611 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3612 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3613 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3614 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3615 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3616 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3617 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3618 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3619 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3620 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3621 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3622 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3624 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3625 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3626 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3627 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3630 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3631 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3635 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3642 r = radeon_scratch_get(rdev, &scratch);
3644 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3647 WREG32(scratch, 0xCAFEDEAD);
3648 r = radeon_ring_lock(rdev, ring, 2);
3650 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3651 radeon_scratch_free(rdev, scratch);
3654 radeon_ring_write(ring, PACKET0(scratch, 0));
3655 radeon_ring_write(ring, 0xDEADBEEF);
3656 radeon_ring_unlock_commit(rdev, ring);
3657 for (i = 0; i < rdev->usec_timeout; i++) {
3658 tmp = RREG32(scratch);
3659 if (tmp == 0xDEADBEEF) {
3664 if (i < rdev->usec_timeout) {
3665 DRM_INFO("ring test succeeded in %d usecs\n", i);
3667 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3671 radeon_scratch_free(rdev, scratch);
3675 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3677 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3679 if (ring->rptr_save_reg) {
3680 u32 next_rptr = ring->wptr + 2 + 3;
3681 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3682 radeon_ring_write(ring, next_rptr);
3685 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3686 radeon_ring_write(ring, ib->gpu_addr);
3687 radeon_ring_write(ring, ib->length_dw);
3690 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3692 struct radeon_ib ib;
3698 r = radeon_scratch_get(rdev, &scratch);
3700 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3703 WREG32(scratch, 0xCAFEDEAD);
3704 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3706 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3709 ib.ptr[0] = PACKET0(scratch, 0);
3710 ib.ptr[1] = 0xDEADBEEF;
3711 ib.ptr[2] = PACKET2(0);
3712 ib.ptr[3] = PACKET2(0);
3713 ib.ptr[4] = PACKET2(0);
3714 ib.ptr[5] = PACKET2(0);
3715 ib.ptr[6] = PACKET2(0);
3716 ib.ptr[7] = PACKET2(0);
3718 r = radeon_ib_schedule(rdev, &ib, NULL);
3720 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3723 r = radeon_fence_wait(ib.fence, false);
3725 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3728 for (i = 0; i < rdev->usec_timeout; i++) {
3729 tmp = RREG32(scratch);
3730 if (tmp == 0xDEADBEEF) {
3735 if (i < rdev->usec_timeout) {
3736 DRM_INFO("ib test succeeded in %u usecs\n", i);
3738 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3743 radeon_ib_free(rdev, &ib);
3745 radeon_scratch_free(rdev, scratch);
3749 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3751 /* Shutdown CP we shouldn't need to do that but better be safe than
3754 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3755 WREG32(R_000740_CP_CSQ_CNTL, 0);
3757 /* Save few CRTC registers */
3758 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3759 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3760 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3761 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3762 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3763 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3764 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3767 /* Disable VGA aperture access */
3768 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3769 /* Disable cursor, overlay, crtc */
3770 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3771 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3772 S_000054_CRTC_DISPLAY_DIS(1));
3773 WREG32(R_000050_CRTC_GEN_CNTL,
3774 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3775 S_000050_CRTC_DISP_REQ_EN_B(1));
3776 WREG32(R_000420_OV0_SCALE_CNTL,
3777 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3778 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3779 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3780 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3781 S_000360_CUR2_LOCK(1));
3782 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3783 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3784 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3785 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3786 WREG32(R_000360_CUR2_OFFSET,
3787 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3791 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3793 /* Update base address for crtc */
3794 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3795 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3796 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3798 /* Restore CRTC registers */
3799 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3800 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3801 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3802 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3803 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3807 void r100_vga_render_disable(struct radeon_device *rdev)
3811 tmp = RREG8(R_0003C2_GENMO_WT);
3812 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3815 static void r100_debugfs(struct radeon_device *rdev)
3819 r = r100_debugfs_mc_info_init(rdev);
3821 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3824 static void r100_mc_program(struct radeon_device *rdev)
3826 struct r100_mc_save save;
3828 /* Stops all mc clients */
3829 r100_mc_stop(rdev, &save);
3830 if (rdev->flags & RADEON_IS_AGP) {
3831 WREG32(R_00014C_MC_AGP_LOCATION,
3832 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3833 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3834 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3835 if (rdev->family > CHIP_RV200)
3836 WREG32(R_00015C_AGP_BASE_2,
3837 upper_32_bits(rdev->mc.agp_base) & 0xff);
3839 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3840 WREG32(R_000170_AGP_BASE, 0);
3841 if (rdev->family > CHIP_RV200)
3842 WREG32(R_00015C_AGP_BASE_2, 0);
3844 /* Wait for mc idle */
3845 if (r100_mc_wait_for_idle(rdev))
3846 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3847 /* Program MC, should be a 32bits limited address space */
3848 WREG32(R_000148_MC_FB_LOCATION,
3849 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3850 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3851 r100_mc_resume(rdev, &save);
3854 static void r100_clock_startup(struct radeon_device *rdev)
3858 if (radeon_dynclks != -1 && radeon_dynclks)
3859 radeon_legacy_set_clock_gating(rdev, 1);
3860 /* We need to force on some of the block */
3861 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3862 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3863 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3864 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3865 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3868 static int r100_startup(struct radeon_device *rdev)
3872 /* set common regs */
3873 r100_set_common_regs(rdev);
3875 r100_mc_program(rdev);
3877 r100_clock_startup(rdev);
3878 /* Initialize GART (initialize after TTM so we can allocate
3879 * memory through TTM but finalize after TTM) */
3880 r100_enable_bm(rdev);
3881 if (rdev->flags & RADEON_IS_PCI) {
3882 r = r100_pci_gart_enable(rdev);
3887 /* allocate wb buffer */
3888 r = radeon_wb_init(rdev);
3892 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3894 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3899 if (!rdev->irq.installed) {
3900 r = radeon_irq_kms_init(rdev);
3906 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3907 /* 1M ring buffer */
3908 r = r100_cp_init(rdev, 1024 * 1024);
3910 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3914 r = radeon_ib_pool_init(rdev);
3916 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3923 int r100_resume(struct radeon_device *rdev)
3927 /* Make sur GART are not working */
3928 if (rdev->flags & RADEON_IS_PCI)
3929 r100_pci_gart_disable(rdev);
3930 /* Resume clock before doing reset */
3931 r100_clock_startup(rdev);
3932 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3933 if (radeon_asic_reset(rdev)) {
3934 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3935 RREG32(R_000E40_RBBM_STATUS),
3936 RREG32(R_0007C0_CP_STAT));
3939 radeon_combios_asic_init(rdev->ddev);
3940 /* Resume clock after posting */
3941 r100_clock_startup(rdev);
3942 /* Initialize surface registers */
3943 radeon_surface_init(rdev);
3945 rdev->accel_working = true;
3946 r = r100_startup(rdev);
3948 rdev->accel_working = false;
3953 int r100_suspend(struct radeon_device *rdev)
3955 radeon_pm_suspend(rdev);
3956 r100_cp_disable(rdev);
3957 radeon_wb_disable(rdev);
3958 r100_irq_disable(rdev);
3959 if (rdev->flags & RADEON_IS_PCI)
3960 r100_pci_gart_disable(rdev);
3964 void r100_fini(struct radeon_device *rdev)
3966 radeon_pm_fini(rdev);
3968 radeon_wb_fini(rdev);
3969 radeon_ib_pool_fini(rdev);
3970 radeon_gem_fini(rdev);
3971 if (rdev->flags & RADEON_IS_PCI)
3972 r100_pci_gart_fini(rdev);
3973 radeon_agp_fini(rdev);
3974 radeon_irq_kms_fini(rdev);
3975 radeon_fence_driver_fini(rdev);
3976 radeon_bo_fini(rdev);
3977 radeon_atombios_fini(rdev);
3983 * Due to how kexec works, it can leave the hw fully initialised when it
3984 * boots the new kernel. However doing our init sequence with the CP and
3985 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3986 * do some quick sanity checks and restore sane values to avoid this
3989 void r100_restore_sanity(struct radeon_device *rdev)
3993 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3995 WREG32(RADEON_CP_CSQ_CNTL, 0);
3997 tmp = RREG32(RADEON_CP_RB_CNTL);
3999 WREG32(RADEON_CP_RB_CNTL, 0);
4001 tmp = RREG32(RADEON_SCRATCH_UMSK);
4003 WREG32(RADEON_SCRATCH_UMSK, 0);
4007 int r100_init(struct radeon_device *rdev)
4011 /* Register debugfs file specific to this group of asics */
4014 r100_vga_render_disable(rdev);
4015 /* Initialize scratch registers */
4016 radeon_scratch_init(rdev);
4017 /* Initialize surface registers */
4018 radeon_surface_init(rdev);
4019 /* sanity check some register to avoid hangs like after kexec */
4020 r100_restore_sanity(rdev);
4021 /* TODO: disable VGA need to use VGA request */
4023 if (!radeon_get_bios(rdev)) {
4024 if (ASIC_IS_AVIVO(rdev))
4027 if (rdev->is_atom_bios) {
4028 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4031 r = radeon_combios_init(rdev);
4035 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4036 if (radeon_asic_reset(rdev)) {
4038 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4039 RREG32(R_000E40_RBBM_STATUS),
4040 RREG32(R_0007C0_CP_STAT));
4042 /* check if cards are posted or not */
4043 if (radeon_boot_test_post_card(rdev) == false)
4045 /* Set asic errata */
4047 /* Initialize clocks */
4048 radeon_get_clock_info(rdev->ddev);
4049 /* initialize AGP */
4050 if (rdev->flags & RADEON_IS_AGP) {
4051 r = radeon_agp_init(rdev);
4053 radeon_agp_disable(rdev);
4056 /* initialize VRAM */
4059 r = radeon_fence_driver_init(rdev);
4062 /* Memory manager */
4063 r = radeon_bo_init(rdev);
4066 if (rdev->flags & RADEON_IS_PCI) {
4067 r = r100_pci_gart_init(rdev);
4071 r100_set_safe_registers(rdev);
4073 /* Initialize power management */
4074 radeon_pm_init(rdev);
4076 rdev->accel_working = true;
4077 r = r100_startup(rdev);
4079 /* Somethings want wront with the accel init stop accel */
4080 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4082 radeon_wb_fini(rdev);
4083 radeon_ib_pool_fini(rdev);
4084 radeon_irq_kms_fini(rdev);
4085 if (rdev->flags & RADEON_IS_PCI)
4086 r100_pci_gart_fini(rdev);
4087 rdev->accel_working = false;
4092 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
4093 bool always_indirect)
4095 if (reg < rdev->rmmio_size && !always_indirect)
4096 return readl(((void __iomem *)rdev->rmmio) + reg);
4098 unsigned long flags;
4101 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4102 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4103 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4104 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4110 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
4111 bool always_indirect)
4113 if (reg < rdev->rmmio_size && !always_indirect)
4114 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4116 unsigned long flags;
4118 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4119 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4120 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4121 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4125 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4127 if (reg < rdev->rio_mem_size)
4128 return ioread32(rdev->rio_mem + reg);
4130 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4131 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4135 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4137 if (reg < rdev->rio_mem_size)
4138 iowrite32(v, rdev->rio_mem + reg);
4140 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4141 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);