2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
31 #include <drm/radeon_drm.h>
32 #include "radeon_reg.h"
34 #include "radeon_asic.h"
41 #include <linux/firmware.h>
42 #include <linux/module.h>
44 #include "r100_reg_safe.h"
45 #include "rn50_reg_safe.h"
48 #define FIRMWARE_R100 "radeon/R100_cp.bin"
49 #define FIRMWARE_R200 "radeon/R200_cp.bin"
50 #define FIRMWARE_R300 "radeon/R300_cp.bin"
51 #define FIRMWARE_R420 "radeon/R420_cp.bin"
52 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
53 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
54 #define FIRMWARE_R520 "radeon/R520_cp.bin"
56 MODULE_FIRMWARE(FIRMWARE_R100);
57 MODULE_FIRMWARE(FIRMWARE_R200);
58 MODULE_FIRMWARE(FIRMWARE_R300);
59 MODULE_FIRMWARE(FIRMWARE_R420);
60 MODULE_FIRMWARE(FIRMWARE_RS690);
61 MODULE_FIRMWARE(FIRMWARE_RS600);
62 MODULE_FIRMWARE(FIRMWARE_R520);
64 #include "r100_track.h"
66 /* This files gather functions specifics to:
67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 * and others in some cases.
71 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
86 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
104 * r100_wait_for_vblank - vblank wait asic callback.
106 * @rdev: radeon_device pointer
107 * @crtc: crtc to wait for vblank on
109 * Wait for vblank on the requested crtc (r1xx-r4xx).
111 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
115 if (crtc >= rdev->num_crtc)
119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
126 /* depending on when we hit vblank, we may be close to active; if so,
127 * wait for another frame.
129 while (r100_is_in_vblank(rdev, crtc)) {
130 if (i++ % 100 == 0) {
131 if (!r100_is_counter_moving(rdev, crtc))
136 while (!r100_is_in_vblank(rdev, crtc)) {
137 if (i++ % 100 == 0) {
138 if (!r100_is_counter_moving(rdev, crtc))
145 * r100_pre_page_flip - pre-pageflip callback.
147 * @rdev: radeon_device pointer
148 * @crtc: crtc to prepare for pageflip on
150 * Pre-pageflip callback (r1xx-r4xx).
151 * Enables the pageflip irq (vblank irq).
153 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
155 /* enable the pflip int */
156 radeon_irq_kms_pflip_irq_get(rdev, crtc);
160 * r100_post_page_flip - pos-pageflip callback.
162 * @rdev: radeon_device pointer
163 * @crtc: crtc to cleanup pageflip on
165 * Post-pageflip callback (r1xx-r4xx).
166 * Disables the pageflip irq (vblank irq).
168 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
170 /* disable the pflip int */
171 radeon_irq_kms_pflip_irq_put(rdev, crtc);
175 * r100_page_flip - pageflip callback.
177 * @rdev: radeon_device pointer
178 * @crtc_id: crtc to cleanup pageflip on
179 * @crtc_base: new address of the crtc (GPU MC address)
181 * Does the actual pageflip (r1xx-r4xx).
182 * During vblank we take the crtc lock and wait for the update_pending
183 * bit to go high, when it does, we release the lock, and allow the
184 * double buffered update to take place.
185 * Returns the current update pending status.
187 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
189 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
190 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
193 /* Lock the graphics update lock */
194 /* update the scanout addresses */
195 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
197 /* Wait for update_pending to go high. */
198 for (i = 0; i < rdev->usec_timeout; i++) {
199 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
203 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
205 /* Unlock the lock, so double-buffering can take place inside vblank */
206 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
207 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
209 /* Return current update_pending status: */
210 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
214 * r100_pm_get_dynpm_state - look up dynpm power state callback.
216 * @rdev: radeon_device pointer
218 * Look up the optimal power state based on the
219 * current state of the GPU (r1xx-r5xx).
220 * Used for dynpm only.
222 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
225 rdev->pm.dynpm_can_upclock = true;
226 rdev->pm.dynpm_can_downclock = true;
228 switch (rdev->pm.dynpm_planned_action) {
229 case DYNPM_ACTION_MINIMUM:
230 rdev->pm.requested_power_state_index = 0;
231 rdev->pm.dynpm_can_downclock = false;
233 case DYNPM_ACTION_DOWNCLOCK:
234 if (rdev->pm.current_power_state_index == 0) {
235 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
236 rdev->pm.dynpm_can_downclock = false;
238 if (rdev->pm.active_crtc_count > 1) {
239 for (i = 0; i < rdev->pm.num_power_states; i++) {
240 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
242 else if (i >= rdev->pm.current_power_state_index) {
243 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
246 rdev->pm.requested_power_state_index = i;
251 rdev->pm.requested_power_state_index =
252 rdev->pm.current_power_state_index - 1;
254 /* don't use the power state if crtcs are active and no display flag is set */
255 if ((rdev->pm.active_crtc_count > 0) &&
256 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
257 RADEON_PM_MODE_NO_DISPLAY)) {
258 rdev->pm.requested_power_state_index++;
261 case DYNPM_ACTION_UPCLOCK:
262 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
263 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
264 rdev->pm.dynpm_can_upclock = false;
266 if (rdev->pm.active_crtc_count > 1) {
267 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
268 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
270 else if (i <= rdev->pm.current_power_state_index) {
271 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
274 rdev->pm.requested_power_state_index = i;
279 rdev->pm.requested_power_state_index =
280 rdev->pm.current_power_state_index + 1;
283 case DYNPM_ACTION_DEFAULT:
284 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
285 rdev->pm.dynpm_can_upclock = false;
287 case DYNPM_ACTION_NONE:
289 DRM_ERROR("Requested mode for not defined action\n");
292 /* only one clock mode per power state */
293 rdev->pm.requested_clock_mode_index = 0;
295 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
296 rdev->pm.power_state[rdev->pm.requested_power_state_index].
297 clock_info[rdev->pm.requested_clock_mode_index].sclk,
298 rdev->pm.power_state[rdev->pm.requested_power_state_index].
299 clock_info[rdev->pm.requested_clock_mode_index].mclk,
300 rdev->pm.power_state[rdev->pm.requested_power_state_index].
305 * r100_pm_init_profile - Initialize power profiles callback.
307 * @rdev: radeon_device pointer
309 * Initialize the power states used in profile mode
311 * Used for profile mode only.
313 void r100_pm_init_profile(struct radeon_device *rdev)
316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
353 * r100_pm_misc - set additional pm hw parameters callback.
355 * @rdev: radeon_device pointer
357 * Set non-clock parameters associated with a power state
358 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
360 void r100_pm_misc(struct radeon_device *rdev)
362 int requested_index = rdev->pm.requested_power_state_index;
363 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
364 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
365 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
367 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
368 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
369 tmp = RREG32(voltage->gpio.reg);
370 if (voltage->active_high)
371 tmp |= voltage->gpio.mask;
373 tmp &= ~(voltage->gpio.mask);
374 WREG32(voltage->gpio.reg, tmp);
376 udelay(voltage->delay);
378 tmp = RREG32(voltage->gpio.reg);
379 if (voltage->active_high)
380 tmp &= ~voltage->gpio.mask;
382 tmp |= voltage->gpio.mask;
383 WREG32(voltage->gpio.reg, tmp);
385 udelay(voltage->delay);
389 sclk_cntl = RREG32_PLL(SCLK_CNTL);
390 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
391 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
392 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
393 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
394 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
395 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
396 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
397 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
399 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
400 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
401 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
402 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
403 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
405 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
407 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
408 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
409 if (voltage->delay) {
410 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
411 switch (voltage->delay) {
413 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
416 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
419 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
422 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
426 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
428 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
430 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
431 sclk_cntl &= ~FORCE_HDP;
433 sclk_cntl |= FORCE_HDP;
435 WREG32_PLL(SCLK_CNTL, sclk_cntl);
436 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
437 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
440 if ((rdev->flags & RADEON_IS_PCIE) &&
441 !(rdev->flags & RADEON_IS_IGP) &&
442 rdev->asic->pm.set_pcie_lanes &&
444 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
445 radeon_set_pcie_lanes(rdev,
447 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
452 * r100_pm_prepare - pre-power state change callback.
454 * @rdev: radeon_device pointer
456 * Prepare for a power state change (r1xx-r4xx).
458 void r100_pm_prepare(struct radeon_device *rdev)
460 struct drm_device *ddev = rdev->ddev;
461 struct drm_crtc *crtc;
462 struct radeon_crtc *radeon_crtc;
465 /* disable any active CRTCs */
466 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
467 radeon_crtc = to_radeon_crtc(crtc);
468 if (radeon_crtc->enabled) {
469 if (radeon_crtc->crtc_id) {
470 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
471 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
472 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
474 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
475 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
476 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
483 * r100_pm_finish - post-power state change callback.
485 * @rdev: radeon_device pointer
487 * Clean up after a power state change (r1xx-r4xx).
489 void r100_pm_finish(struct radeon_device *rdev)
491 struct drm_device *ddev = rdev->ddev;
492 struct drm_crtc *crtc;
493 struct radeon_crtc *radeon_crtc;
496 /* enable any active CRTCs */
497 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
498 radeon_crtc = to_radeon_crtc(crtc);
499 if (radeon_crtc->enabled) {
500 if (radeon_crtc->crtc_id) {
501 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
502 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
503 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
505 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
506 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
507 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
514 * r100_gui_idle - gui idle callback.
516 * @rdev: radeon_device pointer
518 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
519 * Returns true if idle, false if not.
521 bool r100_gui_idle(struct radeon_device *rdev)
523 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
529 /* hpd for digital panel detect/disconnect */
531 * r100_hpd_sense - hpd sense callback.
533 * @rdev: radeon_device pointer
534 * @hpd: hpd (hotplug detect) pin
536 * Checks if a digital monitor is connected (r1xx-r4xx).
537 * Returns true if connected, false if not connected.
539 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
541 bool connected = false;
545 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
549 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
559 * r100_hpd_set_polarity - hpd set polarity callback.
561 * @rdev: radeon_device pointer
562 * @hpd: hpd (hotplug detect) pin
564 * Set the polarity of the hpd pin (r1xx-r4xx).
566 void r100_hpd_set_polarity(struct radeon_device *rdev,
567 enum radeon_hpd_id hpd)
570 bool connected = r100_hpd_sense(rdev, hpd);
574 tmp = RREG32(RADEON_FP_GEN_CNTL);
576 tmp &= ~RADEON_FP_DETECT_INT_POL;
578 tmp |= RADEON_FP_DETECT_INT_POL;
579 WREG32(RADEON_FP_GEN_CNTL, tmp);
582 tmp = RREG32(RADEON_FP2_GEN_CNTL);
584 tmp &= ~RADEON_FP2_DETECT_INT_POL;
586 tmp |= RADEON_FP2_DETECT_INT_POL;
587 WREG32(RADEON_FP2_GEN_CNTL, tmp);
595 * r100_hpd_init - hpd setup callback.
597 * @rdev: radeon_device pointer
599 * Setup the hpd pins used by the card (r1xx-r4xx).
600 * Set the polarity, and enable the hpd interrupts.
602 void r100_hpd_init(struct radeon_device *rdev)
604 struct drm_device *dev = rdev->ddev;
605 struct drm_connector *connector;
608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
609 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
610 enable |= 1 << radeon_connector->hpd.hpd;
611 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
613 radeon_irq_kms_enable_hpd(rdev, enable);
617 * r100_hpd_fini - hpd tear down callback.
619 * @rdev: radeon_device pointer
621 * Tear down the hpd pins used by the card (r1xx-r4xx).
622 * Disable the hpd interrupts.
624 void r100_hpd_fini(struct radeon_device *rdev)
626 struct drm_device *dev = rdev->ddev;
627 struct drm_connector *connector;
628 unsigned disable = 0;
630 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
631 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
632 disable |= 1 << radeon_connector->hpd.hpd;
634 radeon_irq_kms_disable_hpd(rdev, disable);
640 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
642 /* TODO: can we do somethings here ? */
643 /* It seems hw only cache one entry so we should discard this
644 * entry otherwise if first GPU GART read hit this entry it
645 * could end up in wrong address. */
648 int r100_pci_gart_init(struct radeon_device *rdev)
652 if (rdev->gart.ptr) {
653 WARN(1, "R100 PCI GART already initialized\n");
656 /* Initialize common gart structure */
657 r = radeon_gart_init(rdev);
660 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
661 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
662 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
663 return radeon_gart_table_ram_alloc(rdev);
666 int r100_pci_gart_enable(struct radeon_device *rdev)
670 radeon_gart_restore(rdev);
671 /* discard memory request outside of configured range */
672 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
673 WREG32(RADEON_AIC_CNTL, tmp);
674 /* set address range for PCI address translate */
675 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
676 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
677 /* set PCI GART page-table base address */
678 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
679 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
680 WREG32(RADEON_AIC_CNTL, tmp);
681 r100_pci_gart_tlb_flush(rdev);
682 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
683 (unsigned)(rdev->mc.gtt_size >> 20),
684 (unsigned long long)rdev->gart.table_addr);
685 rdev->gart.ready = true;
689 void r100_pci_gart_disable(struct radeon_device *rdev)
693 /* discard memory request outside of configured range */
694 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
695 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
696 WREG32(RADEON_AIC_LO_ADDR, 0);
697 WREG32(RADEON_AIC_HI_ADDR, 0);
700 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
702 u32 *gtt = rdev->gart.ptr;
704 if (i < 0 || i > rdev->gart.num_gpu_pages) {
707 gtt[i] = cpu_to_le32(lower_32_bits(addr));
711 void r100_pci_gart_fini(struct radeon_device *rdev)
713 radeon_gart_fini(rdev);
714 r100_pci_gart_disable(rdev);
715 radeon_gart_table_ram_free(rdev);
718 int r100_irq_set(struct radeon_device *rdev)
722 if (!rdev->irq.installed) {
723 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
724 WREG32(R_000040_GEN_INT_CNTL, 0);
727 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
728 tmp |= RADEON_SW_INT_ENABLE;
730 if (rdev->irq.crtc_vblank_int[0] ||
731 atomic_read(&rdev->irq.pflip[0])) {
732 tmp |= RADEON_CRTC_VBLANK_MASK;
734 if (rdev->irq.crtc_vblank_int[1] ||
735 atomic_read(&rdev->irq.pflip[1])) {
736 tmp |= RADEON_CRTC2_VBLANK_MASK;
738 if (rdev->irq.hpd[0]) {
739 tmp |= RADEON_FP_DETECT_MASK;
741 if (rdev->irq.hpd[1]) {
742 tmp |= RADEON_FP2_DETECT_MASK;
744 WREG32(RADEON_GEN_INT_CNTL, tmp);
748 void r100_irq_disable(struct radeon_device *rdev)
752 WREG32(R_000040_GEN_INT_CNTL, 0);
753 /* Wait and acknowledge irq */
755 tmp = RREG32(R_000044_GEN_INT_STATUS);
756 WREG32(R_000044_GEN_INT_STATUS, tmp);
759 static uint32_t r100_irq_ack(struct radeon_device *rdev)
761 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
762 uint32_t irq_mask = RADEON_SW_INT_TEST |
763 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
764 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
767 WREG32(RADEON_GEN_INT_STATUS, irqs);
769 return irqs & irq_mask;
772 int r100_irq_process(struct radeon_device *rdev)
774 uint32_t status, msi_rearm;
775 bool queue_hotplug = false;
777 status = r100_irq_ack(rdev);
781 if (rdev->shutdown) {
786 if (status & RADEON_SW_INT_TEST) {
787 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
789 /* Vertical blank interrupts */
790 if (status & RADEON_CRTC_VBLANK_STAT) {
791 if (rdev->irq.crtc_vblank_int[0]) {
792 drm_handle_vblank(rdev->ddev, 0);
793 rdev->pm.vblank_sync = true;
794 wake_up(&rdev->irq.vblank_queue);
796 if (atomic_read(&rdev->irq.pflip[0]))
797 radeon_crtc_handle_flip(rdev, 0);
799 if (status & RADEON_CRTC2_VBLANK_STAT) {
800 if (rdev->irq.crtc_vblank_int[1]) {
801 drm_handle_vblank(rdev->ddev, 1);
802 rdev->pm.vblank_sync = true;
803 wake_up(&rdev->irq.vblank_queue);
805 if (atomic_read(&rdev->irq.pflip[1]))
806 radeon_crtc_handle_flip(rdev, 1);
808 if (status & RADEON_FP_DETECT_STAT) {
809 queue_hotplug = true;
812 if (status & RADEON_FP2_DETECT_STAT) {
813 queue_hotplug = true;
816 status = r100_irq_ack(rdev);
819 schedule_work(&rdev->hotplug_work);
820 if (rdev->msi_enabled) {
821 switch (rdev->family) {
824 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
825 WREG32(RADEON_AIC_CNTL, msi_rearm);
826 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
829 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
836 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
839 return RREG32(RADEON_CRTC_CRNT_FRAME);
841 return RREG32(RADEON_CRTC2_CRNT_FRAME);
844 /* Who ever call radeon_fence_emit should call ring_lock and ask
845 * for enough space (today caller are ib schedule and buffer move) */
846 void r100_fence_ring_emit(struct radeon_device *rdev,
847 struct radeon_fence *fence)
849 struct radeon_ring *ring = &rdev->ring[fence->ring];
851 /* We have to make sure that caches are flushed before
852 * CPU might read something from VRAM. */
853 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
854 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
855 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
856 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
857 /* Wait until IDLE & CLEAN */
858 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
859 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
860 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
861 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
862 RADEON_HDP_READ_BUFFER_INVALIDATE);
863 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
864 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
865 /* Emit fence sequence & fire IRQ */
866 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
867 radeon_ring_write(ring, fence->seq);
868 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
869 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
872 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
873 struct radeon_ring *ring,
874 struct radeon_semaphore *semaphore,
877 /* Unused on older asics, since we don't have semaphores or multiple rings */
882 int r100_copy_blit(struct radeon_device *rdev,
885 unsigned num_gpu_pages,
886 struct radeon_fence **fence)
888 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
890 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
892 uint32_t stride_pixels;
897 /* radeon limited to 16k stride */
898 stride_bytes &= 0x3fff;
899 /* radeon pitch is /64 */
900 pitch = stride_bytes / 64;
901 stride_pixels = stride_bytes / 4;
902 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
904 /* Ask for enough room for blit + flush + fence */
905 ndw = 64 + (10 * num_loops);
906 r = radeon_ring_lock(rdev, ring, ndw);
908 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
911 while (num_gpu_pages > 0) {
912 cur_pages = num_gpu_pages;
913 if (cur_pages > 8191) {
916 num_gpu_pages -= cur_pages;
918 /* pages are in Y direction - height
919 page width in X direction - width */
920 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
921 radeon_ring_write(ring,
922 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
923 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
924 RADEON_GMC_SRC_CLIPPING |
925 RADEON_GMC_DST_CLIPPING |
926 RADEON_GMC_BRUSH_NONE |
927 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
928 RADEON_GMC_SRC_DATATYPE_COLOR |
930 RADEON_DP_SRC_SOURCE_MEMORY |
931 RADEON_GMC_CLR_CMP_CNTL_DIS |
932 RADEON_GMC_WR_MSK_DIS);
933 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
934 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
935 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
936 radeon_ring_write(ring, 0);
937 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
938 radeon_ring_write(ring, num_gpu_pages);
939 radeon_ring_write(ring, num_gpu_pages);
940 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
942 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
943 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
944 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
945 radeon_ring_write(ring,
946 RADEON_WAIT_2D_IDLECLEAN |
947 RADEON_WAIT_HOST_IDLECLEAN |
948 RADEON_WAIT_DMA_GUI_IDLE);
950 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
952 radeon_ring_unlock_commit(rdev, ring);
956 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
961 for (i = 0; i < rdev->usec_timeout; i++) {
962 tmp = RREG32(R_000E40_RBBM_STATUS);
963 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
971 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
975 r = radeon_ring_lock(rdev, ring, 2);
979 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
980 radeon_ring_write(ring,
981 RADEON_ISYNC_ANY2D_IDLE3D |
982 RADEON_ISYNC_ANY3D_IDLE2D |
983 RADEON_ISYNC_WAIT_IDLEGUI |
984 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
985 radeon_ring_unlock_commit(rdev, ring);
989 /* Load the microcode for the CP */
990 static int r100_cp_init_microcode(struct radeon_device *rdev)
992 const char *fw_name = NULL;
997 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
998 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
999 (rdev->family == CHIP_RS200)) {
1000 DRM_INFO("Loading R100 Microcode\n");
1001 fw_name = FIRMWARE_R100;
1002 } else if ((rdev->family == CHIP_R200) ||
1003 (rdev->family == CHIP_RV250) ||
1004 (rdev->family == CHIP_RV280) ||
1005 (rdev->family == CHIP_RS300)) {
1006 DRM_INFO("Loading R200 Microcode\n");
1007 fw_name = FIRMWARE_R200;
1008 } else if ((rdev->family == CHIP_R300) ||
1009 (rdev->family == CHIP_R350) ||
1010 (rdev->family == CHIP_RV350) ||
1011 (rdev->family == CHIP_RV380) ||
1012 (rdev->family == CHIP_RS400) ||
1013 (rdev->family == CHIP_RS480)) {
1014 DRM_INFO("Loading R300 Microcode\n");
1015 fw_name = FIRMWARE_R300;
1016 } else if ((rdev->family == CHIP_R420) ||
1017 (rdev->family == CHIP_R423) ||
1018 (rdev->family == CHIP_RV410)) {
1019 DRM_INFO("Loading R400 Microcode\n");
1020 fw_name = FIRMWARE_R420;
1021 } else if ((rdev->family == CHIP_RS690) ||
1022 (rdev->family == CHIP_RS740)) {
1023 DRM_INFO("Loading RS690/RS740 Microcode\n");
1024 fw_name = FIRMWARE_RS690;
1025 } else if (rdev->family == CHIP_RS600) {
1026 DRM_INFO("Loading RS600 Microcode\n");
1027 fw_name = FIRMWARE_RS600;
1028 } else if ((rdev->family == CHIP_RV515) ||
1029 (rdev->family == CHIP_R520) ||
1030 (rdev->family == CHIP_RV530) ||
1031 (rdev->family == CHIP_R580) ||
1032 (rdev->family == CHIP_RV560) ||
1033 (rdev->family == CHIP_RV570)) {
1034 DRM_INFO("Loading R500 Microcode\n");
1035 fw_name = FIRMWARE_R520;
1038 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1040 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1042 } else if (rdev->me_fw->size % 8) {
1044 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1045 rdev->me_fw->size, fw_name);
1047 release_firmware(rdev->me_fw);
1053 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1054 struct radeon_ring *ring)
1058 if (rdev->wb.enabled)
1059 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1061 rptr = RREG32(RADEON_CP_RB_RPTR);
1066 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1067 struct radeon_ring *ring)
1071 wptr = RREG32(RADEON_CP_RB_WPTR);
1076 void r100_gfx_set_wptr(struct radeon_device *rdev,
1077 struct radeon_ring *ring)
1079 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1080 (void)RREG32(RADEON_CP_RB_WPTR);
1083 static void r100_cp_load_microcode(struct radeon_device *rdev)
1085 const __be32 *fw_data;
1088 if (r100_gui_wait_for_idle(rdev)) {
1089 printk(KERN_WARNING "Failed to wait GUI idle while "
1090 "programming pipes. Bad things might happen.\n");
1094 size = rdev->me_fw->size / 4;
1095 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1096 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1097 for (i = 0; i < size; i += 2) {
1098 WREG32(RADEON_CP_ME_RAM_DATAH,
1099 be32_to_cpup(&fw_data[i]));
1100 WREG32(RADEON_CP_ME_RAM_DATAL,
1101 be32_to_cpup(&fw_data[i + 1]));
1106 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1108 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1112 unsigned pre_write_timer;
1113 unsigned pre_write_limit;
1114 unsigned indirect2_start;
1115 unsigned indirect1_start;
1119 if (r100_debugfs_cp_init(rdev)) {
1120 DRM_ERROR("Failed to register debugfs file for CP !\n");
1123 r = r100_cp_init_microcode(rdev);
1125 DRM_ERROR("Failed to load firmware!\n");
1130 /* Align ring size */
1131 rb_bufsz = order_base_2(ring_size / 8);
1132 ring_size = (1 << (rb_bufsz + 1)) * 4;
1133 r100_cp_load_microcode(rdev);
1134 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1139 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1140 * the rptr copy in system ram */
1142 /* cp will read 128bytes at a time (4 dwords) */
1144 ring->align_mask = 16 - 1;
1145 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1146 pre_write_timer = 64;
1147 /* Force CP_RB_WPTR write if written more than one time before the
1150 pre_write_limit = 0;
1151 /* Setup the cp cache like this (cache size is 96 dwords) :
1153 * INDIRECT1 16 to 79
1154 * INDIRECT2 80 to 95
1155 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1156 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1157 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1158 * Idea being that most of the gpu cmd will be through indirect1 buffer
1159 * so it gets the bigger cache.
1161 indirect2_start = 80;
1162 indirect1_start = 16;
1164 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1165 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1166 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1167 REG_SET(RADEON_MAX_FETCH, max_fetch));
1169 tmp |= RADEON_BUF_SWAP_32BIT;
1171 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1173 /* Set ring address */
1174 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1175 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1176 /* Force read & write ptr to 0 */
1177 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1178 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1180 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1182 /* set the wb address whether it's enabled or not */
1183 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1184 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1185 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1187 if (rdev->wb.enabled)
1188 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1190 tmp |= RADEON_RB_NO_UPDATE;
1191 WREG32(R_000770_SCRATCH_UMSK, 0);
1194 WREG32(RADEON_CP_RB_CNTL, tmp);
1196 /* Set cp mode to bus mastering & enable cp*/
1197 WREG32(RADEON_CP_CSQ_MODE,
1198 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1199 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1200 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1201 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1202 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1204 /* at this point everything should be setup correctly to enable master */
1205 pci_set_master(rdev->pdev);
1207 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1208 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1210 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1214 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1216 if (!ring->rptr_save_reg /* not resuming from suspend */
1217 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1218 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1220 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1221 ring->rptr_save_reg = 0;
1227 void r100_cp_fini(struct radeon_device *rdev)
1229 if (r100_cp_wait_for_idle(rdev)) {
1230 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1233 r100_cp_disable(rdev);
1234 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1235 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1236 DRM_INFO("radeon: cp finalized\n");
1239 void r100_cp_disable(struct radeon_device *rdev)
1242 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1243 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1244 WREG32(RADEON_CP_CSQ_MODE, 0);
1245 WREG32(RADEON_CP_CSQ_CNTL, 0);
1246 WREG32(R_000770_SCRATCH_UMSK, 0);
1247 if (r100_gui_wait_for_idle(rdev)) {
1248 printk(KERN_WARNING "Failed to wait GUI idle while "
1249 "programming pipes. Bad things might happen.\n");
1256 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1257 struct radeon_cs_packet *pkt,
1264 struct radeon_cs_reloc *reloc;
1267 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1269 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1271 radeon_cs_dump_packet(p, pkt);
1275 value = radeon_get_ib_value(p, idx);
1276 tmp = value & 0x003fffff;
1277 tmp += (((u32)reloc->gpu_offset) >> 10);
1279 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1280 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1281 tile_flags |= RADEON_DST_TILE_MACRO;
1282 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1283 if (reg == RADEON_SRC_PITCH_OFFSET) {
1284 DRM_ERROR("Cannot src blit from microtiled surface\n");
1285 radeon_cs_dump_packet(p, pkt);
1288 tile_flags |= RADEON_DST_TILE_MICRO;
1292 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1294 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1298 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1299 struct radeon_cs_packet *pkt,
1303 struct radeon_cs_reloc *reloc;
1304 struct r100_cs_track *track;
1306 volatile uint32_t *ib;
1310 track = (struct r100_cs_track *)p->track;
1311 c = radeon_get_ib_value(p, idx++) & 0x1F;
1313 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1315 radeon_cs_dump_packet(p, pkt);
1318 track->num_arrays = c;
1319 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1320 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1322 DRM_ERROR("No reloc for packet3 %d\n",
1324 radeon_cs_dump_packet(p, pkt);
1327 idx_value = radeon_get_ib_value(p, idx);
1328 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1330 track->arrays[i + 0].esize = idx_value >> 8;
1331 track->arrays[i + 0].robj = reloc->robj;
1332 track->arrays[i + 0].esize &= 0x7F;
1333 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1335 DRM_ERROR("No reloc for packet3 %d\n",
1337 radeon_cs_dump_packet(p, pkt);
1340 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1341 track->arrays[i + 1].robj = reloc->robj;
1342 track->arrays[i + 1].esize = idx_value >> 24;
1343 track->arrays[i + 1].esize &= 0x7F;
1346 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1348 DRM_ERROR("No reloc for packet3 %d\n",
1350 radeon_cs_dump_packet(p, pkt);
1353 idx_value = radeon_get_ib_value(p, idx);
1354 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1355 track->arrays[i + 0].robj = reloc->robj;
1356 track->arrays[i + 0].esize = idx_value >> 8;
1357 track->arrays[i + 0].esize &= 0x7F;
1362 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1363 struct radeon_cs_packet *pkt,
1364 const unsigned *auth, unsigned n,
1365 radeon_packet0_check_t check)
1374 /* Check that register fall into register range
1375 * determined by the number of entry (n) in the
1376 * safe register bitmap.
1378 if (pkt->one_reg_wr) {
1379 if ((reg >> 7) > n) {
1383 if (((reg + (pkt->count << 2)) >> 7) > n) {
1387 for (i = 0; i <= pkt->count; i++, idx++) {
1389 m = 1 << ((reg >> 2) & 31);
1391 r = check(p, pkt, idx, reg);
1396 if (pkt->one_reg_wr) {
1397 if (!(auth[j] & m)) {
1408 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1409 * @parser: parser structure holding parsing context.
1411 * Userspace sends a special sequence for VLINE waits.
1412 * PACKET0 - VLINE_START_END + value
1413 * PACKET0 - WAIT_UNTIL +_value
1414 * RELOC (P3) - crtc_id in reloc.
1416 * This function parses this and relocates the VLINE START END
1417 * and WAIT UNTIL packets to the correct crtc.
1418 * It also detects a switched off crtc and nulls out the
1419 * wait in that case.
1421 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1423 struct drm_mode_object *obj;
1424 struct drm_crtc *crtc;
1425 struct radeon_crtc *radeon_crtc;
1426 struct radeon_cs_packet p3reloc, waitreloc;
1429 uint32_t header, h_idx, reg;
1430 volatile uint32_t *ib;
1434 /* parse the wait until */
1435 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1439 /* check its a wait until and only 1 count */
1440 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1441 waitreloc.count != 0) {
1442 DRM_ERROR("vline wait had illegal wait until segment\n");
1446 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1447 DRM_ERROR("vline wait had illegal wait until\n");
1451 /* jump over the NOP */
1452 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1457 p->idx += waitreloc.count + 2;
1458 p->idx += p3reloc.count + 2;
1460 header = radeon_get_ib_value(p, h_idx);
1461 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1462 reg = R100_CP_PACKET0_GET_REG(header);
1463 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1465 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1468 crtc = obj_to_crtc(obj);
1469 radeon_crtc = to_radeon_crtc(crtc);
1470 crtc_id = radeon_crtc->crtc_id;
1472 if (!crtc->enabled) {
1473 /* if the CRTC isn't enabled - we need to nop out the wait until */
1474 ib[h_idx + 2] = PACKET2(0);
1475 ib[h_idx + 3] = PACKET2(0);
1476 } else if (crtc_id == 1) {
1478 case AVIVO_D1MODE_VLINE_START_END:
1479 header &= ~R300_CP_PACKET0_REG_MASK;
1480 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1482 case RADEON_CRTC_GUI_TRIG_VLINE:
1483 header &= ~R300_CP_PACKET0_REG_MASK;
1484 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1487 DRM_ERROR("unknown crtc reloc\n");
1491 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1497 static int r100_get_vtx_size(uint32_t vtx_fmt)
1501 /* ordered according to bits in spec */
1502 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1504 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1506 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1508 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1510 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1512 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1514 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1516 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1518 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1520 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1522 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1524 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1526 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1528 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1530 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1533 if (vtx_fmt & (0x7 << 15))
1534 vtx_size += (vtx_fmt >> 15) & 0x7;
1535 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1537 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1539 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1541 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1543 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1545 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1550 static int r100_packet0_check(struct radeon_cs_parser *p,
1551 struct radeon_cs_packet *pkt,
1552 unsigned idx, unsigned reg)
1554 struct radeon_cs_reloc *reloc;
1555 struct r100_cs_track *track;
1556 volatile uint32_t *ib;
1564 track = (struct r100_cs_track *)p->track;
1566 idx_value = radeon_get_ib_value(p, idx);
1569 case RADEON_CRTC_GUI_TRIG_VLINE:
1570 r = r100_cs_packet_parse_vline(p);
1572 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1574 radeon_cs_dump_packet(p, pkt);
1578 /* FIXME: only allow PACKET3 blit? easier to check for out of
1580 case RADEON_DST_PITCH_OFFSET:
1581 case RADEON_SRC_PITCH_OFFSET:
1582 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1586 case RADEON_RB3D_DEPTHOFFSET:
1587 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1589 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1591 radeon_cs_dump_packet(p, pkt);
1594 track->zb.robj = reloc->robj;
1595 track->zb.offset = idx_value;
1596 track->zb_dirty = true;
1597 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1599 case RADEON_RB3D_COLOROFFSET:
1600 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1602 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1604 radeon_cs_dump_packet(p, pkt);
1607 track->cb[0].robj = reloc->robj;
1608 track->cb[0].offset = idx_value;
1609 track->cb_dirty = true;
1610 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1612 case RADEON_PP_TXOFFSET_0:
1613 case RADEON_PP_TXOFFSET_1:
1614 case RADEON_PP_TXOFFSET_2:
1615 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1616 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1618 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1620 radeon_cs_dump_packet(p, pkt);
1623 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1624 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1625 tile_flags |= RADEON_TXO_MACRO_TILE;
1626 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1627 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1629 tmp = idx_value & ~(0x7 << 2);
1631 ib[idx] = tmp + ((u32)reloc->gpu_offset);
1633 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1634 track->textures[i].robj = reloc->robj;
1635 track->tex_dirty = true;
1637 case RADEON_PP_CUBIC_OFFSET_T0_0:
1638 case RADEON_PP_CUBIC_OFFSET_T0_1:
1639 case RADEON_PP_CUBIC_OFFSET_T0_2:
1640 case RADEON_PP_CUBIC_OFFSET_T0_3:
1641 case RADEON_PP_CUBIC_OFFSET_T0_4:
1642 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1643 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1645 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1647 radeon_cs_dump_packet(p, pkt);
1650 track->textures[0].cube_info[i].offset = idx_value;
1651 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1652 track->textures[0].cube_info[i].robj = reloc->robj;
1653 track->tex_dirty = true;
1655 case RADEON_PP_CUBIC_OFFSET_T1_0:
1656 case RADEON_PP_CUBIC_OFFSET_T1_1:
1657 case RADEON_PP_CUBIC_OFFSET_T1_2:
1658 case RADEON_PP_CUBIC_OFFSET_T1_3:
1659 case RADEON_PP_CUBIC_OFFSET_T1_4:
1660 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1661 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1663 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1665 radeon_cs_dump_packet(p, pkt);
1668 track->textures[1].cube_info[i].offset = idx_value;
1669 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1670 track->textures[1].cube_info[i].robj = reloc->robj;
1671 track->tex_dirty = true;
1673 case RADEON_PP_CUBIC_OFFSET_T2_0:
1674 case RADEON_PP_CUBIC_OFFSET_T2_1:
1675 case RADEON_PP_CUBIC_OFFSET_T2_2:
1676 case RADEON_PP_CUBIC_OFFSET_T2_3:
1677 case RADEON_PP_CUBIC_OFFSET_T2_4:
1678 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1679 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1681 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1683 radeon_cs_dump_packet(p, pkt);
1686 track->textures[2].cube_info[i].offset = idx_value;
1687 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1688 track->textures[2].cube_info[i].robj = reloc->robj;
1689 track->tex_dirty = true;
1691 case RADEON_RE_WIDTH_HEIGHT:
1692 track->maxy = ((idx_value >> 16) & 0x7FF);
1693 track->cb_dirty = true;
1694 track->zb_dirty = true;
1696 case RADEON_RB3D_COLORPITCH:
1697 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1699 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1701 radeon_cs_dump_packet(p, pkt);
1704 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1705 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1706 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1707 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1708 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1710 tmp = idx_value & ~(0x7 << 16);
1714 ib[idx] = idx_value;
1716 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1717 track->cb_dirty = true;
1719 case RADEON_RB3D_DEPTHPITCH:
1720 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1721 track->zb_dirty = true;
1723 case RADEON_RB3D_CNTL:
1724 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1730 track->cb[0].cpp = 1;
1735 track->cb[0].cpp = 2;
1738 track->cb[0].cpp = 4;
1741 DRM_ERROR("Invalid color buffer format (%d) !\n",
1742 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1745 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1746 track->cb_dirty = true;
1747 track->zb_dirty = true;
1749 case RADEON_RB3D_ZSTENCILCNTL:
1750 switch (idx_value & 0xf) {
1765 track->zb_dirty = true;
1767 case RADEON_RB3D_ZPASS_ADDR:
1768 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1770 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1772 radeon_cs_dump_packet(p, pkt);
1775 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1777 case RADEON_PP_CNTL:
1779 uint32_t temp = idx_value >> 4;
1780 for (i = 0; i < track->num_texture; i++)
1781 track->textures[i].enabled = !!(temp & (1 << i));
1782 track->tex_dirty = true;
1785 case RADEON_SE_VF_CNTL:
1786 track->vap_vf_cntl = idx_value;
1788 case RADEON_SE_VTX_FMT:
1789 track->vtx_size = r100_get_vtx_size(idx_value);
1791 case RADEON_PP_TEX_SIZE_0:
1792 case RADEON_PP_TEX_SIZE_1:
1793 case RADEON_PP_TEX_SIZE_2:
1794 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1795 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1796 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1797 track->tex_dirty = true;
1799 case RADEON_PP_TEX_PITCH_0:
1800 case RADEON_PP_TEX_PITCH_1:
1801 case RADEON_PP_TEX_PITCH_2:
1802 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1803 track->textures[i].pitch = idx_value + 32;
1804 track->tex_dirty = true;
1806 case RADEON_PP_TXFILTER_0:
1807 case RADEON_PP_TXFILTER_1:
1808 case RADEON_PP_TXFILTER_2:
1809 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1810 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1811 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1812 tmp = (idx_value >> 23) & 0x7;
1813 if (tmp == 2 || tmp == 6)
1814 track->textures[i].roundup_w = false;
1815 tmp = (idx_value >> 27) & 0x7;
1816 if (tmp == 2 || tmp == 6)
1817 track->textures[i].roundup_h = false;
1818 track->tex_dirty = true;
1820 case RADEON_PP_TXFORMAT_0:
1821 case RADEON_PP_TXFORMAT_1:
1822 case RADEON_PP_TXFORMAT_2:
1823 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1824 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1825 track->textures[i].use_pitch = 1;
1827 track->textures[i].use_pitch = 0;
1828 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1829 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1831 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1832 track->textures[i].tex_coord_type = 2;
1833 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1834 case RADEON_TXFORMAT_I8:
1835 case RADEON_TXFORMAT_RGB332:
1836 case RADEON_TXFORMAT_Y8:
1837 track->textures[i].cpp = 1;
1838 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1840 case RADEON_TXFORMAT_AI88:
1841 case RADEON_TXFORMAT_ARGB1555:
1842 case RADEON_TXFORMAT_RGB565:
1843 case RADEON_TXFORMAT_ARGB4444:
1844 case RADEON_TXFORMAT_VYUY422:
1845 case RADEON_TXFORMAT_YVYU422:
1846 case RADEON_TXFORMAT_SHADOW16:
1847 case RADEON_TXFORMAT_LDUDV655:
1848 case RADEON_TXFORMAT_DUDV88:
1849 track->textures[i].cpp = 2;
1850 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1852 case RADEON_TXFORMAT_ARGB8888:
1853 case RADEON_TXFORMAT_RGBA8888:
1854 case RADEON_TXFORMAT_SHADOW32:
1855 case RADEON_TXFORMAT_LDUDUV8888:
1856 track->textures[i].cpp = 4;
1857 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1859 case RADEON_TXFORMAT_DXT1:
1860 track->textures[i].cpp = 1;
1861 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1863 case RADEON_TXFORMAT_DXT23:
1864 case RADEON_TXFORMAT_DXT45:
1865 track->textures[i].cpp = 1;
1866 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1869 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1870 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1871 track->tex_dirty = true;
1873 case RADEON_PP_CUBIC_FACES_0:
1874 case RADEON_PP_CUBIC_FACES_1:
1875 case RADEON_PP_CUBIC_FACES_2:
1877 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1878 for (face = 0; face < 4; face++) {
1879 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1880 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1882 track->tex_dirty = true;
1885 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1892 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1893 struct radeon_cs_packet *pkt,
1894 struct radeon_bo *robj)
1899 value = radeon_get_ib_value(p, idx + 2);
1900 if ((value + 1) > radeon_bo_size(robj)) {
1901 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1902 "(need %u have %lu) !\n",
1904 radeon_bo_size(robj));
1910 static int r100_packet3_check(struct radeon_cs_parser *p,
1911 struct radeon_cs_packet *pkt)
1913 struct radeon_cs_reloc *reloc;
1914 struct r100_cs_track *track;
1916 volatile uint32_t *ib;
1921 track = (struct r100_cs_track *)p->track;
1922 switch (pkt->opcode) {
1923 case PACKET3_3D_LOAD_VBPNTR:
1924 r = r100_packet3_load_vbpntr(p, pkt, idx);
1928 case PACKET3_INDX_BUFFER:
1929 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1931 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1932 radeon_cs_dump_packet(p, pkt);
1935 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1936 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1942 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1943 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1945 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1946 radeon_cs_dump_packet(p, pkt);
1949 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1950 track->num_arrays = 1;
1951 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1953 track->arrays[0].robj = reloc->robj;
1954 track->arrays[0].esize = track->vtx_size;
1956 track->max_indx = radeon_get_ib_value(p, idx+1);
1958 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1959 track->immd_dwords = pkt->count - 1;
1960 r = r100_cs_track_check(p->rdev, track);
1964 case PACKET3_3D_DRAW_IMMD:
1965 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1966 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1969 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1970 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1971 track->immd_dwords = pkt->count - 1;
1972 r = r100_cs_track_check(p->rdev, track);
1976 /* triggers drawing using in-packet vertex data */
1977 case PACKET3_3D_DRAW_IMMD_2:
1978 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1979 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1982 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1983 track->immd_dwords = pkt->count;
1984 r = r100_cs_track_check(p->rdev, track);
1988 /* triggers drawing using in-packet vertex data */
1989 case PACKET3_3D_DRAW_VBUF_2:
1990 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1991 r = r100_cs_track_check(p->rdev, track);
1995 /* triggers drawing of vertex buffers setup elsewhere */
1996 case PACKET3_3D_DRAW_INDX_2:
1997 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1998 r = r100_cs_track_check(p->rdev, track);
2002 /* triggers drawing using indices to vertex buffer */
2003 case PACKET3_3D_DRAW_VBUF:
2004 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2005 r = r100_cs_track_check(p->rdev, track);
2009 /* triggers drawing of vertex buffers setup elsewhere */
2010 case PACKET3_3D_DRAW_INDX:
2011 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2012 r = r100_cs_track_check(p->rdev, track);
2016 /* triggers drawing using indices to vertex buffer */
2017 case PACKET3_3D_CLEAR_HIZ:
2018 case PACKET3_3D_CLEAR_ZMASK:
2019 if (p->rdev->hyperz_filp != p->filp)
2025 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2031 int r100_cs_parse(struct radeon_cs_parser *p)
2033 struct radeon_cs_packet pkt;
2034 struct r100_cs_track *track;
2037 track = kzalloc(sizeof(*track), GFP_KERNEL);
2040 r100_cs_track_clear(p->rdev, track);
2043 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2047 p->idx += pkt.count + 2;
2049 case RADEON_PACKET_TYPE0:
2050 if (p->rdev->family >= CHIP_R200)
2051 r = r100_cs_parse_packet0(p, &pkt,
2052 p->rdev->config.r100.reg_safe_bm,
2053 p->rdev->config.r100.reg_safe_bm_size,
2054 &r200_packet0_check);
2056 r = r100_cs_parse_packet0(p, &pkt,
2057 p->rdev->config.r100.reg_safe_bm,
2058 p->rdev->config.r100.reg_safe_bm_size,
2059 &r100_packet0_check);
2061 case RADEON_PACKET_TYPE2:
2063 case RADEON_PACKET_TYPE3:
2064 r = r100_packet3_check(p, &pkt);
2067 DRM_ERROR("Unknown packet type %d !\n",
2073 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2077 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2079 DRM_ERROR("pitch %d\n", t->pitch);
2080 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2081 DRM_ERROR("width %d\n", t->width);
2082 DRM_ERROR("width_11 %d\n", t->width_11);
2083 DRM_ERROR("height %d\n", t->height);
2084 DRM_ERROR("height_11 %d\n", t->height_11);
2085 DRM_ERROR("num levels %d\n", t->num_levels);
2086 DRM_ERROR("depth %d\n", t->txdepth);
2087 DRM_ERROR("bpp %d\n", t->cpp);
2088 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2089 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2090 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2091 DRM_ERROR("compress format %d\n", t->compress_format);
2094 static int r100_track_compress_size(int compress_format, int w, int h)
2096 int block_width, block_height, block_bytes;
2097 int wblocks, hblocks;
2104 switch (compress_format) {
2105 case R100_TRACK_COMP_DXT1:
2110 case R100_TRACK_COMP_DXT35:
2116 hblocks = (h + block_height - 1) / block_height;
2117 wblocks = (w + block_width - 1) / block_width;
2118 if (wblocks < min_wblocks)
2119 wblocks = min_wblocks;
2120 sz = wblocks * hblocks * block_bytes;
2124 static int r100_cs_track_cube(struct radeon_device *rdev,
2125 struct r100_cs_track *track, unsigned idx)
2127 unsigned face, w, h;
2128 struct radeon_bo *cube_robj;
2130 unsigned compress_format = track->textures[idx].compress_format;
2132 for (face = 0; face < 5; face++) {
2133 cube_robj = track->textures[idx].cube_info[face].robj;
2134 w = track->textures[idx].cube_info[face].width;
2135 h = track->textures[idx].cube_info[face].height;
2137 if (compress_format) {
2138 size = r100_track_compress_size(compress_format, w, h);
2141 size *= track->textures[idx].cpp;
2143 size += track->textures[idx].cube_info[face].offset;
2145 if (size > radeon_bo_size(cube_robj)) {
2146 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2147 size, radeon_bo_size(cube_robj));
2148 r100_cs_track_texture_print(&track->textures[idx]);
2155 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2156 struct r100_cs_track *track)
2158 struct radeon_bo *robj;
2160 unsigned u, i, w, h, d;
2163 for (u = 0; u < track->num_texture; u++) {
2164 if (!track->textures[u].enabled)
2166 if (track->textures[u].lookup_disable)
2168 robj = track->textures[u].robj;
2170 DRM_ERROR("No texture bound to unit %u\n", u);
2174 for (i = 0; i <= track->textures[u].num_levels; i++) {
2175 if (track->textures[u].use_pitch) {
2176 if (rdev->family < CHIP_R300)
2177 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2179 w = track->textures[u].pitch / (1 << i);
2181 w = track->textures[u].width;
2182 if (rdev->family >= CHIP_RV515)
2183 w |= track->textures[u].width_11;
2185 if (track->textures[u].roundup_w)
2186 w = roundup_pow_of_two(w);
2188 h = track->textures[u].height;
2189 if (rdev->family >= CHIP_RV515)
2190 h |= track->textures[u].height_11;
2192 if (track->textures[u].roundup_h)
2193 h = roundup_pow_of_two(h);
2194 if (track->textures[u].tex_coord_type == 1) {
2195 d = (1 << track->textures[u].txdepth) / (1 << i);
2201 if (track->textures[u].compress_format) {
2203 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2204 /* compressed textures are block based */
2208 size *= track->textures[u].cpp;
2210 switch (track->textures[u].tex_coord_type) {
2215 if (track->separate_cube) {
2216 ret = r100_cs_track_cube(rdev, track, u);
2223 DRM_ERROR("Invalid texture coordinate type %u for unit "
2224 "%u\n", track->textures[u].tex_coord_type, u);
2227 if (size > radeon_bo_size(robj)) {
2228 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2229 "%lu\n", u, size, radeon_bo_size(robj));
2230 r100_cs_track_texture_print(&track->textures[u]);
2237 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2243 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2245 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2246 !track->blend_read_enable)
2249 for (i = 0; i < num_cb; i++) {
2250 if (track->cb[i].robj == NULL) {
2251 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2254 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2255 size += track->cb[i].offset;
2256 if (size > radeon_bo_size(track->cb[i].robj)) {
2257 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2258 "(need %lu have %lu) !\n", i, size,
2259 radeon_bo_size(track->cb[i].robj));
2260 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2261 i, track->cb[i].pitch, track->cb[i].cpp,
2262 track->cb[i].offset, track->maxy);
2266 track->cb_dirty = false;
2268 if (track->zb_dirty && track->z_enabled) {
2269 if (track->zb.robj == NULL) {
2270 DRM_ERROR("[drm] No buffer for z buffer !\n");
2273 size = track->zb.pitch * track->zb.cpp * track->maxy;
2274 size += track->zb.offset;
2275 if (size > radeon_bo_size(track->zb.robj)) {
2276 DRM_ERROR("[drm] Buffer too small for z buffer "
2277 "(need %lu have %lu) !\n", size,
2278 radeon_bo_size(track->zb.robj));
2279 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2280 track->zb.pitch, track->zb.cpp,
2281 track->zb.offset, track->maxy);
2285 track->zb_dirty = false;
2287 if (track->aa_dirty && track->aaresolve) {
2288 if (track->aa.robj == NULL) {
2289 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2292 /* I believe the format comes from colorbuffer0. */
2293 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2294 size += track->aa.offset;
2295 if (size > radeon_bo_size(track->aa.robj)) {
2296 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2297 "(need %lu have %lu) !\n", i, size,
2298 radeon_bo_size(track->aa.robj));
2299 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2300 i, track->aa.pitch, track->cb[0].cpp,
2301 track->aa.offset, track->maxy);
2305 track->aa_dirty = false;
2307 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2308 if (track->vap_vf_cntl & (1 << 14)) {
2309 nverts = track->vap_alt_nverts;
2311 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2313 switch (prim_walk) {
2315 for (i = 0; i < track->num_arrays; i++) {
2316 size = track->arrays[i].esize * track->max_indx * 4;
2317 if (track->arrays[i].robj == NULL) {
2318 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2319 "bound\n", prim_walk, i);
2322 if (size > radeon_bo_size(track->arrays[i].robj)) {
2323 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2324 "need %lu dwords have %lu dwords\n",
2325 prim_walk, i, size >> 2,
2326 radeon_bo_size(track->arrays[i].robj)
2328 DRM_ERROR("Max indices %u\n", track->max_indx);
2334 for (i = 0; i < track->num_arrays; i++) {
2335 size = track->arrays[i].esize * (nverts - 1) * 4;
2336 if (track->arrays[i].robj == NULL) {
2337 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2338 "bound\n", prim_walk, i);
2341 if (size > radeon_bo_size(track->arrays[i].robj)) {
2342 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2343 "need %lu dwords have %lu dwords\n",
2344 prim_walk, i, size >> 2,
2345 radeon_bo_size(track->arrays[i].robj)
2352 size = track->vtx_size * nverts;
2353 if (size != track->immd_dwords) {
2354 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2355 track->immd_dwords, size);
2356 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2357 nverts, track->vtx_size);
2362 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2367 if (track->tex_dirty) {
2368 track->tex_dirty = false;
2369 return r100_cs_track_texture_check(rdev, track);
2374 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2378 track->cb_dirty = true;
2379 track->zb_dirty = true;
2380 track->tex_dirty = true;
2381 track->aa_dirty = true;
2383 if (rdev->family < CHIP_R300) {
2385 if (rdev->family <= CHIP_RS200)
2386 track->num_texture = 3;
2388 track->num_texture = 6;
2390 track->separate_cube = 1;
2393 track->num_texture = 16;
2395 track->separate_cube = 0;
2396 track->aaresolve = false;
2397 track->aa.robj = NULL;
2400 for (i = 0; i < track->num_cb; i++) {
2401 track->cb[i].robj = NULL;
2402 track->cb[i].pitch = 8192;
2403 track->cb[i].cpp = 16;
2404 track->cb[i].offset = 0;
2406 track->z_enabled = true;
2407 track->zb.robj = NULL;
2408 track->zb.pitch = 8192;
2410 track->zb.offset = 0;
2411 track->vtx_size = 0x7F;
2412 track->immd_dwords = 0xFFFFFFFFUL;
2413 track->num_arrays = 11;
2414 track->max_indx = 0x00FFFFFFUL;
2415 for (i = 0; i < track->num_arrays; i++) {
2416 track->arrays[i].robj = NULL;
2417 track->arrays[i].esize = 0x7F;
2419 for (i = 0; i < track->num_texture; i++) {
2420 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2421 track->textures[i].pitch = 16536;
2422 track->textures[i].width = 16536;
2423 track->textures[i].height = 16536;
2424 track->textures[i].width_11 = 1 << 11;
2425 track->textures[i].height_11 = 1 << 11;
2426 track->textures[i].num_levels = 12;
2427 if (rdev->family <= CHIP_RS200) {
2428 track->textures[i].tex_coord_type = 0;
2429 track->textures[i].txdepth = 0;
2431 track->textures[i].txdepth = 16;
2432 track->textures[i].tex_coord_type = 1;
2434 track->textures[i].cpp = 64;
2435 track->textures[i].robj = NULL;
2436 /* CS IB emission code makes sure texture unit are disabled */
2437 track->textures[i].enabled = false;
2438 track->textures[i].lookup_disable = false;
2439 track->textures[i].roundup_w = true;
2440 track->textures[i].roundup_h = true;
2441 if (track->separate_cube)
2442 for (face = 0; face < 5; face++) {
2443 track->textures[i].cube_info[face].robj = NULL;
2444 track->textures[i].cube_info[face].width = 16536;
2445 track->textures[i].cube_info[face].height = 16536;
2446 track->textures[i].cube_info[face].offset = 0;
2452 * Global GPU functions
2454 static void r100_errata(struct radeon_device *rdev)
2456 rdev->pll_errata = 0;
2458 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2459 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2462 if (rdev->family == CHIP_RV100 ||
2463 rdev->family == CHIP_RS100 ||
2464 rdev->family == CHIP_RS200) {
2465 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2469 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2474 for (i = 0; i < rdev->usec_timeout; i++) {
2475 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2484 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2489 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2490 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2491 " Bad things might happen.\n");
2493 for (i = 0; i < rdev->usec_timeout; i++) {
2494 tmp = RREG32(RADEON_RBBM_STATUS);
2495 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2503 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2508 for (i = 0; i < rdev->usec_timeout; i++) {
2509 /* read MC_STATUS */
2510 tmp = RREG32(RADEON_MC_STATUS);
2511 if (tmp & RADEON_MC_IDLE) {
2519 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2523 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2524 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2525 radeon_ring_lockup_update(rdev, ring);
2528 return radeon_ring_test_lockup(rdev, ring);
2531 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2532 void r100_enable_bm(struct radeon_device *rdev)
2535 /* Enable bus mastering */
2536 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2537 WREG32(RADEON_BUS_CNTL, tmp);
2540 void r100_bm_disable(struct radeon_device *rdev)
2544 /* disable bus mastering */
2545 tmp = RREG32(R_000030_BUS_CNTL);
2546 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2548 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2550 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2551 tmp = RREG32(RADEON_BUS_CNTL);
2553 pci_clear_master(rdev->pdev);
2557 int r100_asic_reset(struct radeon_device *rdev)
2559 struct r100_mc_save save;
2563 status = RREG32(R_000E40_RBBM_STATUS);
2564 if (!G_000E40_GUI_ACTIVE(status)) {
2567 r100_mc_stop(rdev, &save);
2568 status = RREG32(R_000E40_RBBM_STATUS);
2569 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2571 WREG32(RADEON_CP_CSQ_CNTL, 0);
2572 tmp = RREG32(RADEON_CP_RB_CNTL);
2573 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2574 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2575 WREG32(RADEON_CP_RB_WPTR, 0);
2576 WREG32(RADEON_CP_RB_CNTL, tmp);
2577 /* save PCI state */
2578 pci_save_state(rdev->pdev);
2579 /* disable bus mastering */
2580 r100_bm_disable(rdev);
2581 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2582 S_0000F0_SOFT_RESET_RE(1) |
2583 S_0000F0_SOFT_RESET_PP(1) |
2584 S_0000F0_SOFT_RESET_RB(1));
2585 RREG32(R_0000F0_RBBM_SOFT_RESET);
2587 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2589 status = RREG32(R_000E40_RBBM_STATUS);
2590 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2592 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2593 RREG32(R_0000F0_RBBM_SOFT_RESET);
2595 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2597 status = RREG32(R_000E40_RBBM_STATUS);
2598 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2599 /* restore PCI & busmastering */
2600 pci_restore_state(rdev->pdev);
2601 r100_enable_bm(rdev);
2602 /* Check if GPU is idle */
2603 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2604 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2605 dev_err(rdev->dev, "failed to reset GPU\n");
2608 dev_info(rdev->dev, "GPU reset succeed\n");
2609 r100_mc_resume(rdev, &save);
2613 void r100_set_common_regs(struct radeon_device *rdev)
2615 struct drm_device *dev = rdev->ddev;
2616 bool force_dac2 = false;
2619 /* set these so they don't interfere with anything */
2620 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2621 WREG32(RADEON_SUBPIC_CNTL, 0);
2622 WREG32(RADEON_VIPH_CONTROL, 0);
2623 WREG32(RADEON_I2C_CNTL_1, 0);
2624 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2625 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2626 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2628 /* always set up dac2 on rn50 and some rv100 as lots
2629 * of servers seem to wire it up to a VGA port but
2630 * don't report it in the bios connector
2633 switch (dev->pdev->device) {
2642 /* DELL triple head servers */
2643 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2644 ((dev->pdev->subsystem_device == 0x016c) ||
2645 (dev->pdev->subsystem_device == 0x016d) ||
2646 (dev->pdev->subsystem_device == 0x016e) ||
2647 (dev->pdev->subsystem_device == 0x016f) ||
2648 (dev->pdev->subsystem_device == 0x0170) ||
2649 (dev->pdev->subsystem_device == 0x017d) ||
2650 (dev->pdev->subsystem_device == 0x017e) ||
2651 (dev->pdev->subsystem_device == 0x0183) ||
2652 (dev->pdev->subsystem_device == 0x018a) ||
2653 (dev->pdev->subsystem_device == 0x019a)))
2659 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2660 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2661 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2663 /* For CRT on DAC2, don't turn it on if BIOS didn't
2664 enable it, even it's detected.
2667 /* force it to crtc0 */
2668 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2669 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2670 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2672 /* set up the TV DAC */
2673 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2674 RADEON_TV_DAC_STD_MASK |
2675 RADEON_TV_DAC_RDACPD |
2676 RADEON_TV_DAC_GDACPD |
2677 RADEON_TV_DAC_BDACPD |
2678 RADEON_TV_DAC_BGADJ_MASK |
2679 RADEON_TV_DAC_DACADJ_MASK);
2680 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2681 RADEON_TV_DAC_NHOLD |
2682 RADEON_TV_DAC_STD_PS2 |
2685 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2686 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2687 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2690 /* switch PM block to ACPI mode */
2691 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2692 tmp &= ~RADEON_PM_MODE_SEL;
2693 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2700 static void r100_vram_get_type(struct radeon_device *rdev)
2704 rdev->mc.vram_is_ddr = false;
2705 if (rdev->flags & RADEON_IS_IGP)
2706 rdev->mc.vram_is_ddr = true;
2707 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2708 rdev->mc.vram_is_ddr = true;
2709 if ((rdev->family == CHIP_RV100) ||
2710 (rdev->family == CHIP_RS100) ||
2711 (rdev->family == CHIP_RS200)) {
2712 tmp = RREG32(RADEON_MEM_CNTL);
2713 if (tmp & RV100_HALF_MODE) {
2714 rdev->mc.vram_width = 32;
2716 rdev->mc.vram_width = 64;
2718 if (rdev->flags & RADEON_SINGLE_CRTC) {
2719 rdev->mc.vram_width /= 4;
2720 rdev->mc.vram_is_ddr = true;
2722 } else if (rdev->family <= CHIP_RV280) {
2723 tmp = RREG32(RADEON_MEM_CNTL);
2724 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2725 rdev->mc.vram_width = 128;
2727 rdev->mc.vram_width = 64;
2731 rdev->mc.vram_width = 128;
2735 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2740 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2742 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2743 * that is has the 2nd generation multifunction PCI interface
2745 if (rdev->family == CHIP_RV280 ||
2746 rdev->family >= CHIP_RV350) {
2747 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2748 ~RADEON_HDP_APER_CNTL);
2749 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2750 return aper_size * 2;
2753 /* Older cards have all sorts of funny issues to deal with. First
2754 * check if it's a multifunction card by reading the PCI config
2755 * header type... Limit those to one aperture size
2757 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2759 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2760 DRM_INFO("Limiting VRAM to one aperture\n");
2764 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2765 * have set it up. We don't write this as it's broken on some ASICs but
2766 * we expect the BIOS to have done the right thing (might be too optimistic...)
2768 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2769 return aper_size * 2;
2773 void r100_vram_init_sizes(struct radeon_device *rdev)
2775 u64 config_aper_size;
2777 /* work out accessible VRAM */
2778 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2779 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2780 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2781 /* FIXME we don't use the second aperture yet when we could use it */
2782 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2783 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2784 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2785 if (rdev->flags & RADEON_IS_IGP) {
2787 /* read NB_TOM to get the amount of ram stolen for the GPU */
2788 tom = RREG32(RADEON_NB_TOM);
2789 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2790 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2791 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2793 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2794 /* Some production boards of m6 will report 0
2797 if (rdev->mc.real_vram_size == 0) {
2798 rdev->mc.real_vram_size = 8192 * 1024;
2799 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2801 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2802 * Novell bug 204882 + along with lots of ubuntu ones
2804 if (rdev->mc.aper_size > config_aper_size)
2805 config_aper_size = rdev->mc.aper_size;
2807 if (config_aper_size > rdev->mc.real_vram_size)
2808 rdev->mc.mc_vram_size = config_aper_size;
2810 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2814 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2818 temp = RREG32(RADEON_CONFIG_CNTL);
2819 if (state == false) {
2820 temp &= ~RADEON_CFG_VGA_RAM_EN;
2821 temp |= RADEON_CFG_VGA_IO_DIS;
2823 temp &= ~RADEON_CFG_VGA_IO_DIS;
2825 WREG32(RADEON_CONFIG_CNTL, temp);
2828 static void r100_mc_init(struct radeon_device *rdev)
2832 r100_vram_get_type(rdev);
2833 r100_vram_init_sizes(rdev);
2834 base = rdev->mc.aper_base;
2835 if (rdev->flags & RADEON_IS_IGP)
2836 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2837 radeon_vram_location(rdev, &rdev->mc, base);
2838 rdev->mc.gtt_base_align = 0;
2839 if (!(rdev->flags & RADEON_IS_AGP))
2840 radeon_gtt_location(rdev, &rdev->mc);
2841 radeon_update_bandwidth_info(rdev);
2846 * Indirect registers accessor
2848 void r100_pll_errata_after_index(struct radeon_device *rdev)
2850 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2851 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2852 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2856 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2858 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2859 * or the chip could hang on a subsequent access
2861 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2865 /* This function is required to workaround a hardware bug in some (all?)
2866 * revisions of the R300. This workaround should be called after every
2867 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2868 * may not be correct.
2870 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2873 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2874 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2875 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2876 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2877 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2881 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2883 unsigned long flags;
2886 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2887 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2888 r100_pll_errata_after_index(rdev);
2889 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2890 r100_pll_errata_after_data(rdev);
2891 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2895 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2897 unsigned long flags;
2899 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2900 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2901 r100_pll_errata_after_index(rdev);
2902 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2903 r100_pll_errata_after_data(rdev);
2904 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2907 static void r100_set_safe_registers(struct radeon_device *rdev)
2909 if (ASIC_IS_RN50(rdev)) {
2910 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2911 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2912 } else if (rdev->family < CHIP_R200) {
2913 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2914 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2916 r200_set_safe_registers(rdev);
2923 #if defined(CONFIG_DEBUG_FS)
2924 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2926 struct drm_info_node *node = (struct drm_info_node *) m->private;
2927 struct drm_device *dev = node->minor->dev;
2928 struct radeon_device *rdev = dev->dev_private;
2929 uint32_t reg, value;
2932 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2933 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2934 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2935 for (i = 0; i < 64; i++) {
2936 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2937 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2938 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2939 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2940 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2945 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2947 struct drm_info_node *node = (struct drm_info_node *) m->private;
2948 struct drm_device *dev = node->minor->dev;
2949 struct radeon_device *rdev = dev->dev_private;
2950 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2952 unsigned count, i, j;
2954 radeon_ring_free_size(rdev, ring);
2955 rdp = RREG32(RADEON_CP_RB_RPTR);
2956 wdp = RREG32(RADEON_CP_RB_WPTR);
2957 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2958 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2959 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2960 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2961 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2962 seq_printf(m, "%u dwords in ring\n", count);
2964 for (j = 0; j <= count; j++) {
2965 i = (rdp + j) & ring->ptr_mask;
2966 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2973 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2975 struct drm_info_node *node = (struct drm_info_node *) m->private;
2976 struct drm_device *dev = node->minor->dev;
2977 struct radeon_device *rdev = dev->dev_private;
2978 uint32_t csq_stat, csq2_stat, tmp;
2979 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2982 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2983 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2984 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2985 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2986 r_rptr = (csq_stat >> 0) & 0x3ff;
2987 r_wptr = (csq_stat >> 10) & 0x3ff;
2988 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2989 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2990 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2991 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2992 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2993 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2994 seq_printf(m, "Ring rptr %u\n", r_rptr);
2995 seq_printf(m, "Ring wptr %u\n", r_wptr);
2996 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2997 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2998 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2999 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3000 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3001 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3002 seq_printf(m, "Ring fifo:\n");
3003 for (i = 0; i < 256; i++) {
3004 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3005 tmp = RREG32(RADEON_CP_CSQ_DATA);
3006 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3008 seq_printf(m, "Indirect1 fifo:\n");
3009 for (i = 256; i <= 512; i++) {
3010 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3011 tmp = RREG32(RADEON_CP_CSQ_DATA);
3012 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3014 seq_printf(m, "Indirect2 fifo:\n");
3015 for (i = 640; i < ib1_wptr; i++) {
3016 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3017 tmp = RREG32(RADEON_CP_CSQ_DATA);
3018 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3023 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3025 struct drm_info_node *node = (struct drm_info_node *) m->private;
3026 struct drm_device *dev = node->minor->dev;
3027 struct radeon_device *rdev = dev->dev_private;
3030 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3031 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3032 tmp = RREG32(RADEON_MC_FB_LOCATION);
3033 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3034 tmp = RREG32(RADEON_BUS_CNTL);
3035 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3036 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3037 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3038 tmp = RREG32(RADEON_AGP_BASE);
3039 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3040 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3041 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3042 tmp = RREG32(0x01D0);
3043 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3044 tmp = RREG32(RADEON_AIC_LO_ADDR);
3045 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3046 tmp = RREG32(RADEON_AIC_HI_ADDR);
3047 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3048 tmp = RREG32(0x01E4);
3049 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3053 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3054 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3057 static struct drm_info_list r100_debugfs_cp_list[] = {
3058 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3059 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3062 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3063 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3067 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3069 #if defined(CONFIG_DEBUG_FS)
3070 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3076 int r100_debugfs_cp_init(struct radeon_device *rdev)
3078 #if defined(CONFIG_DEBUG_FS)
3079 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3085 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3087 #if defined(CONFIG_DEBUG_FS)
3088 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3094 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3095 uint32_t tiling_flags, uint32_t pitch,
3096 uint32_t offset, uint32_t obj_size)
3098 int surf_index = reg * 16;
3101 if (rdev->family <= CHIP_RS200) {
3102 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3103 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3104 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3105 if (tiling_flags & RADEON_TILING_MACRO)
3106 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3107 /* setting pitch to 0 disables tiling */
3108 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3111 } else if (rdev->family <= CHIP_RV280) {
3112 if (tiling_flags & (RADEON_TILING_MACRO))
3113 flags |= R200_SURF_TILE_COLOR_MACRO;
3114 if (tiling_flags & RADEON_TILING_MICRO)
3115 flags |= R200_SURF_TILE_COLOR_MICRO;
3117 if (tiling_flags & RADEON_TILING_MACRO)
3118 flags |= R300_SURF_TILE_MACRO;
3119 if (tiling_flags & RADEON_TILING_MICRO)
3120 flags |= R300_SURF_TILE_MICRO;
3123 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3124 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3125 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3126 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3128 /* r100/r200 divide by 16 */
3129 if (rdev->family < CHIP_R300)
3130 flags |= pitch / 16;
3135 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3136 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3137 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3138 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3142 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3144 int surf_index = reg * 16;
3145 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3148 void r100_bandwidth_update(struct radeon_device *rdev)
3150 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3151 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3152 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3153 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3154 fixed20_12 memtcas_ff[8] = {
3159 dfixed_init_half(1),
3160 dfixed_init_half(2),
3163 fixed20_12 memtcas_rs480_ff[8] = {
3169 dfixed_init_half(1),
3170 dfixed_init_half(2),
3171 dfixed_init_half(3),
3173 fixed20_12 memtcas2_ff[8] = {
3183 fixed20_12 memtrbs[8] = {
3185 dfixed_init_half(1),
3187 dfixed_init_half(2),
3189 dfixed_init_half(3),
3193 fixed20_12 memtrbs_r4xx[8] = {
3203 fixed20_12 min_mem_eff;
3204 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3205 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3206 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3207 disp_drain_rate2, read_return_rate;
3208 fixed20_12 time_disp1_drop_priority;
3210 int cur_size = 16; /* in octawords */
3211 int critical_point = 0, critical_point2;
3212 /* uint32_t read_return_rate, time_disp1_drop_priority; */
3213 int stop_req, max_stop_req;
3214 struct drm_display_mode *mode1 = NULL;
3215 struct drm_display_mode *mode2 = NULL;
3216 uint32_t pixel_bytes1 = 0;
3217 uint32_t pixel_bytes2 = 0;
3219 radeon_update_display_priority(rdev);
3221 if (rdev->mode_info.crtcs[0]->base.enabled) {
3222 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3223 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
3225 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3226 if (rdev->mode_info.crtcs[1]->base.enabled) {
3227 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3228 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
3232 min_mem_eff.full = dfixed_const_8(0);
3234 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3235 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3236 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3237 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3238 /* check crtc enables */
3240 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3242 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3243 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3247 * determine is there is enough bw for current mode
3249 sclk_ff = rdev->pm.sclk;
3250 mclk_ff = rdev->pm.mclk;
3252 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3253 temp_ff.full = dfixed_const(temp);
3254 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3258 peak_disp_bw.full = 0;
3260 temp_ff.full = dfixed_const(1000);
3261 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3262 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3263 temp_ff.full = dfixed_const(pixel_bytes1);
3264 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3267 temp_ff.full = dfixed_const(1000);
3268 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3269 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3270 temp_ff.full = dfixed_const(pixel_bytes2);
3271 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3274 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3275 if (peak_disp_bw.full >= mem_bw.full) {
3276 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3277 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3280 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3281 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3282 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3283 mem_trcd = ((temp >> 2) & 0x3) + 1;
3284 mem_trp = ((temp & 0x3)) + 1;
3285 mem_tras = ((temp & 0x70) >> 4) + 1;
3286 } else if (rdev->family == CHIP_R300 ||
3287 rdev->family == CHIP_R350) { /* r300, r350 */
3288 mem_trcd = (temp & 0x7) + 1;
3289 mem_trp = ((temp >> 8) & 0x7) + 1;
3290 mem_tras = ((temp >> 11) & 0xf) + 4;
3291 } else if (rdev->family == CHIP_RV350 ||
3292 rdev->family <= CHIP_RV380) {
3294 mem_trcd = (temp & 0x7) + 3;
3295 mem_trp = ((temp >> 8) & 0x7) + 3;
3296 mem_tras = ((temp >> 11) & 0xf) + 6;
3297 } else if (rdev->family == CHIP_R420 ||
3298 rdev->family == CHIP_R423 ||
3299 rdev->family == CHIP_RV410) {
3301 mem_trcd = (temp & 0xf) + 3;
3304 mem_trp = ((temp >> 8) & 0xf) + 3;
3307 mem_tras = ((temp >> 12) & 0x1f) + 6;
3310 } else { /* RV200, R200 */
3311 mem_trcd = (temp & 0x7) + 1;
3312 mem_trp = ((temp >> 8) & 0x7) + 1;
3313 mem_tras = ((temp >> 12) & 0xf) + 4;
3316 trcd_ff.full = dfixed_const(mem_trcd);
3317 trp_ff.full = dfixed_const(mem_trp);
3318 tras_ff.full = dfixed_const(mem_tras);
3320 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3321 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3322 data = (temp & (7 << 20)) >> 20;
3323 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3324 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3325 tcas_ff = memtcas_rs480_ff[data];
3327 tcas_ff = memtcas_ff[data];
3329 tcas_ff = memtcas2_ff[data];
3331 if (rdev->family == CHIP_RS400 ||
3332 rdev->family == CHIP_RS480) {
3333 /* extra cas latency stored in bits 23-25 0-4 clocks */
3334 data = (temp >> 23) & 0x7;
3336 tcas_ff.full += dfixed_const(data);
3339 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3340 /* on the R300, Tcas is included in Trbs.
3342 temp = RREG32(RADEON_MEM_CNTL);
3343 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3345 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3346 temp = RREG32(R300_MC_IND_INDEX);
3347 temp &= ~R300_MC_IND_ADDR_MASK;
3348 temp |= R300_MC_READ_CNTL_CD_mcind;
3349 WREG32(R300_MC_IND_INDEX, temp);
3350 temp = RREG32(R300_MC_IND_DATA);
3351 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3353 temp = RREG32(R300_MC_READ_CNTL_AB);
3354 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3357 temp = RREG32(R300_MC_READ_CNTL_AB);
3358 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3360 if (rdev->family == CHIP_RV410 ||
3361 rdev->family == CHIP_R420 ||
3362 rdev->family == CHIP_R423)
3363 trbs_ff = memtrbs_r4xx[data];
3365 trbs_ff = memtrbs[data];
3366 tcas_ff.full += trbs_ff.full;
3369 sclk_eff_ff.full = sclk_ff.full;
3371 if (rdev->flags & RADEON_IS_AGP) {
3372 fixed20_12 agpmode_ff;
3373 agpmode_ff.full = dfixed_const(radeon_agpmode);
3374 temp_ff.full = dfixed_const_666(16);
3375 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3377 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3379 if (ASIC_IS_R300(rdev)) {
3380 sclk_delay_ff.full = dfixed_const(250);
3382 if ((rdev->family == CHIP_RV100) ||
3383 rdev->flags & RADEON_IS_IGP) {
3384 if (rdev->mc.vram_is_ddr)
3385 sclk_delay_ff.full = dfixed_const(41);
3387 sclk_delay_ff.full = dfixed_const(33);
3389 if (rdev->mc.vram_width == 128)
3390 sclk_delay_ff.full = dfixed_const(57);
3392 sclk_delay_ff.full = dfixed_const(41);
3396 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3398 if (rdev->mc.vram_is_ddr) {
3399 if (rdev->mc.vram_width == 32) {
3400 k1.full = dfixed_const(40);
3403 k1.full = dfixed_const(20);
3407 k1.full = dfixed_const(40);
3411 temp_ff.full = dfixed_const(2);
3412 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3413 temp_ff.full = dfixed_const(c);
3414 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3415 temp_ff.full = dfixed_const(4);
3416 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3417 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3418 mc_latency_mclk.full += k1.full;
3420 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3421 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3424 HW cursor time assuming worst case of full size colour cursor.
3426 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3427 temp_ff.full += trcd_ff.full;
3428 if (temp_ff.full < tras_ff.full)
3429 temp_ff.full = tras_ff.full;
3430 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3432 temp_ff.full = dfixed_const(cur_size);
3433 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3435 Find the total latency for the display data.
3437 disp_latency_overhead.full = dfixed_const(8);
3438 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3439 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3440 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3442 if (mc_latency_mclk.full > mc_latency_sclk.full)
3443 disp_latency.full = mc_latency_mclk.full;
3445 disp_latency.full = mc_latency_sclk.full;
3447 /* setup Max GRPH_STOP_REQ default value */
3448 if (ASIC_IS_RV100(rdev))
3449 max_stop_req = 0x5c;
3451 max_stop_req = 0x7c;
3455 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3456 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3458 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3460 if (stop_req > max_stop_req)
3461 stop_req = max_stop_req;
3464 Find the drain rate of the display buffer.
3466 temp_ff.full = dfixed_const((16/pixel_bytes1));
3467 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3470 Find the critical point of the display buffer.
3472 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3473 crit_point_ff.full += dfixed_const_half(0);
3475 critical_point = dfixed_trunc(crit_point_ff);
3477 if (rdev->disp_priority == 2) {
3482 The critical point should never be above max_stop_req-4. Setting
3483 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3485 if (max_stop_req - critical_point < 4)
3488 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3489 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3490 critical_point = 0x10;
3493 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3494 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3495 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3496 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3497 if ((rdev->family == CHIP_R350) &&
3498 (stop_req > 0x15)) {
3501 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3502 temp |= RADEON_GRPH_BUFFER_SIZE;
3503 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3504 RADEON_GRPH_CRITICAL_AT_SOF |
3505 RADEON_GRPH_STOP_CNTL);
3507 Write the result into the register.
3509 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3510 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3513 if ((rdev->family == CHIP_RS400) ||
3514 (rdev->family == CHIP_RS480)) {
3515 /* attempt to program RS400 disp regs correctly ??? */
3516 temp = RREG32(RS400_DISP1_REG_CNTL);
3517 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3518 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3519 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3520 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3521 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3522 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3523 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3524 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3525 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3526 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3527 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3531 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3532 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3533 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3538 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3540 if (stop_req > max_stop_req)
3541 stop_req = max_stop_req;
3544 Find the drain rate of the display buffer.
3546 temp_ff.full = dfixed_const((16/pixel_bytes2));
3547 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3549 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3550 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3551 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3552 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3553 if ((rdev->family == CHIP_R350) &&
3554 (stop_req > 0x15)) {
3557 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3558 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3559 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3560 RADEON_GRPH_CRITICAL_AT_SOF |
3561 RADEON_GRPH_STOP_CNTL);
3563 if ((rdev->family == CHIP_RS100) ||
3564 (rdev->family == CHIP_RS200))
3565 critical_point2 = 0;
3567 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3568 temp_ff.full = dfixed_const(temp);
3569 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3570 if (sclk_ff.full < temp_ff.full)
3571 temp_ff.full = sclk_ff.full;
3573 read_return_rate.full = temp_ff.full;
3576 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3577 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3579 time_disp1_drop_priority.full = 0;
3581 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3582 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3583 crit_point_ff.full += dfixed_const_half(0);
3585 critical_point2 = dfixed_trunc(crit_point_ff);
3587 if (rdev->disp_priority == 2) {
3588 critical_point2 = 0;
3591 if (max_stop_req - critical_point2 < 4)
3592 critical_point2 = 0;
3596 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3597 /* some R300 cards have problem with this set to 0 */
3598 critical_point2 = 0x10;
3601 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3602 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3604 if ((rdev->family == CHIP_RS400) ||
3605 (rdev->family == CHIP_RS480)) {
3607 /* attempt to program RS400 disp2 regs correctly ??? */
3608 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3609 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3610 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3611 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3612 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3613 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3614 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3615 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3616 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3617 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3618 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3619 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3621 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3622 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3623 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3624 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3627 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3628 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3632 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3639 r = radeon_scratch_get(rdev, &scratch);
3641 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3644 WREG32(scratch, 0xCAFEDEAD);
3645 r = radeon_ring_lock(rdev, ring, 2);
3647 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3648 radeon_scratch_free(rdev, scratch);
3651 radeon_ring_write(ring, PACKET0(scratch, 0));
3652 radeon_ring_write(ring, 0xDEADBEEF);
3653 radeon_ring_unlock_commit(rdev, ring);
3654 for (i = 0; i < rdev->usec_timeout; i++) {
3655 tmp = RREG32(scratch);
3656 if (tmp == 0xDEADBEEF) {
3661 if (i < rdev->usec_timeout) {
3662 DRM_INFO("ring test succeeded in %d usecs\n", i);
3664 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3668 radeon_scratch_free(rdev, scratch);
3672 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3674 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3676 if (ring->rptr_save_reg) {
3677 u32 next_rptr = ring->wptr + 2 + 3;
3678 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3679 radeon_ring_write(ring, next_rptr);
3682 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3683 radeon_ring_write(ring, ib->gpu_addr);
3684 radeon_ring_write(ring, ib->length_dw);
3687 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3689 struct radeon_ib ib;
3695 r = radeon_scratch_get(rdev, &scratch);
3697 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3700 WREG32(scratch, 0xCAFEDEAD);
3701 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3703 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3706 ib.ptr[0] = PACKET0(scratch, 0);
3707 ib.ptr[1] = 0xDEADBEEF;
3708 ib.ptr[2] = PACKET2(0);
3709 ib.ptr[3] = PACKET2(0);
3710 ib.ptr[4] = PACKET2(0);
3711 ib.ptr[5] = PACKET2(0);
3712 ib.ptr[6] = PACKET2(0);
3713 ib.ptr[7] = PACKET2(0);
3715 r = radeon_ib_schedule(rdev, &ib, NULL);
3717 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3720 r = radeon_fence_wait(ib.fence, false);
3722 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3725 for (i = 0; i < rdev->usec_timeout; i++) {
3726 tmp = RREG32(scratch);
3727 if (tmp == 0xDEADBEEF) {
3732 if (i < rdev->usec_timeout) {
3733 DRM_INFO("ib test succeeded in %u usecs\n", i);
3735 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3740 radeon_ib_free(rdev, &ib);
3742 radeon_scratch_free(rdev, scratch);
3746 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3748 /* Shutdown CP we shouldn't need to do that but better be safe than
3751 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3752 WREG32(R_000740_CP_CSQ_CNTL, 0);
3754 /* Save few CRTC registers */
3755 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3756 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3757 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3758 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3759 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3760 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3761 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3764 /* Disable VGA aperture access */
3765 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3766 /* Disable cursor, overlay, crtc */
3767 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3768 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3769 S_000054_CRTC_DISPLAY_DIS(1));
3770 WREG32(R_000050_CRTC_GEN_CNTL,
3771 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3772 S_000050_CRTC_DISP_REQ_EN_B(1));
3773 WREG32(R_000420_OV0_SCALE_CNTL,
3774 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3775 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3776 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3777 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3778 S_000360_CUR2_LOCK(1));
3779 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3780 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3781 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3782 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3783 WREG32(R_000360_CUR2_OFFSET,
3784 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3788 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3790 /* Update base address for crtc */
3791 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3792 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3793 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3795 /* Restore CRTC registers */
3796 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3797 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3798 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3799 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3800 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3804 void r100_vga_render_disable(struct radeon_device *rdev)
3808 tmp = RREG8(R_0003C2_GENMO_WT);
3809 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3812 static void r100_debugfs(struct radeon_device *rdev)
3816 r = r100_debugfs_mc_info_init(rdev);
3818 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3821 static void r100_mc_program(struct radeon_device *rdev)
3823 struct r100_mc_save save;
3825 /* Stops all mc clients */
3826 r100_mc_stop(rdev, &save);
3827 if (rdev->flags & RADEON_IS_AGP) {
3828 WREG32(R_00014C_MC_AGP_LOCATION,
3829 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3830 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3831 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3832 if (rdev->family > CHIP_RV200)
3833 WREG32(R_00015C_AGP_BASE_2,
3834 upper_32_bits(rdev->mc.agp_base) & 0xff);
3836 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3837 WREG32(R_000170_AGP_BASE, 0);
3838 if (rdev->family > CHIP_RV200)
3839 WREG32(R_00015C_AGP_BASE_2, 0);
3841 /* Wait for mc idle */
3842 if (r100_mc_wait_for_idle(rdev))
3843 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3844 /* Program MC, should be a 32bits limited address space */
3845 WREG32(R_000148_MC_FB_LOCATION,
3846 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3847 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3848 r100_mc_resume(rdev, &save);
3851 static void r100_clock_startup(struct radeon_device *rdev)
3855 if (radeon_dynclks != -1 && radeon_dynclks)
3856 radeon_legacy_set_clock_gating(rdev, 1);
3857 /* We need to force on some of the block */
3858 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3859 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3860 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3861 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3862 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3865 static int r100_startup(struct radeon_device *rdev)
3869 /* set common regs */
3870 r100_set_common_regs(rdev);
3872 r100_mc_program(rdev);
3874 r100_clock_startup(rdev);
3875 /* Initialize GART (initialize after TTM so we can allocate
3876 * memory through TTM but finalize after TTM) */
3877 r100_enable_bm(rdev);
3878 if (rdev->flags & RADEON_IS_PCI) {
3879 r = r100_pci_gart_enable(rdev);
3884 /* allocate wb buffer */
3885 r = radeon_wb_init(rdev);
3889 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3891 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3896 if (!rdev->irq.installed) {
3897 r = radeon_irq_kms_init(rdev);
3903 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3904 /* 1M ring buffer */
3905 r = r100_cp_init(rdev, 1024 * 1024);
3907 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3911 r = radeon_ib_pool_init(rdev);
3913 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3920 int r100_resume(struct radeon_device *rdev)
3924 /* Make sur GART are not working */
3925 if (rdev->flags & RADEON_IS_PCI)
3926 r100_pci_gart_disable(rdev);
3927 /* Resume clock before doing reset */
3928 r100_clock_startup(rdev);
3929 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3930 if (radeon_asic_reset(rdev)) {
3931 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3932 RREG32(R_000E40_RBBM_STATUS),
3933 RREG32(R_0007C0_CP_STAT));
3936 radeon_combios_asic_init(rdev->ddev);
3937 /* Resume clock after posting */
3938 r100_clock_startup(rdev);
3939 /* Initialize surface registers */
3940 radeon_surface_init(rdev);
3942 rdev->accel_working = true;
3943 r = r100_startup(rdev);
3945 rdev->accel_working = false;
3950 int r100_suspend(struct radeon_device *rdev)
3952 radeon_pm_suspend(rdev);
3953 r100_cp_disable(rdev);
3954 radeon_wb_disable(rdev);
3955 r100_irq_disable(rdev);
3956 if (rdev->flags & RADEON_IS_PCI)
3957 r100_pci_gart_disable(rdev);
3961 void r100_fini(struct radeon_device *rdev)
3963 radeon_pm_fini(rdev);
3965 radeon_wb_fini(rdev);
3966 radeon_ib_pool_fini(rdev);
3967 radeon_gem_fini(rdev);
3968 if (rdev->flags & RADEON_IS_PCI)
3969 r100_pci_gart_fini(rdev);
3970 radeon_agp_fini(rdev);
3971 radeon_irq_kms_fini(rdev);
3972 radeon_fence_driver_fini(rdev);
3973 radeon_bo_fini(rdev);
3974 radeon_atombios_fini(rdev);
3980 * Due to how kexec works, it can leave the hw fully initialised when it
3981 * boots the new kernel. However doing our init sequence with the CP and
3982 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3983 * do some quick sanity checks and restore sane values to avoid this
3986 void r100_restore_sanity(struct radeon_device *rdev)
3990 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3992 WREG32(RADEON_CP_CSQ_CNTL, 0);
3994 tmp = RREG32(RADEON_CP_RB_CNTL);
3996 WREG32(RADEON_CP_RB_CNTL, 0);
3998 tmp = RREG32(RADEON_SCRATCH_UMSK);
4000 WREG32(RADEON_SCRATCH_UMSK, 0);
4004 int r100_init(struct radeon_device *rdev)
4008 /* Register debugfs file specific to this group of asics */
4011 r100_vga_render_disable(rdev);
4012 /* Initialize scratch registers */
4013 radeon_scratch_init(rdev);
4014 /* Initialize surface registers */
4015 radeon_surface_init(rdev);
4016 /* sanity check some register to avoid hangs like after kexec */
4017 r100_restore_sanity(rdev);
4018 /* TODO: disable VGA need to use VGA request */
4020 if (!radeon_get_bios(rdev)) {
4021 if (ASIC_IS_AVIVO(rdev))
4024 if (rdev->is_atom_bios) {
4025 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4028 r = radeon_combios_init(rdev);
4032 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4033 if (radeon_asic_reset(rdev)) {
4035 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4036 RREG32(R_000E40_RBBM_STATUS),
4037 RREG32(R_0007C0_CP_STAT));
4039 /* check if cards are posted or not */
4040 if (radeon_boot_test_post_card(rdev) == false)
4042 /* Set asic errata */
4044 /* Initialize clocks */
4045 radeon_get_clock_info(rdev->ddev);
4046 /* initialize AGP */
4047 if (rdev->flags & RADEON_IS_AGP) {
4048 r = radeon_agp_init(rdev);
4050 radeon_agp_disable(rdev);
4053 /* initialize VRAM */
4056 r = radeon_fence_driver_init(rdev);
4059 /* Memory manager */
4060 r = radeon_bo_init(rdev);
4063 if (rdev->flags & RADEON_IS_PCI) {
4064 r = r100_pci_gart_init(rdev);
4068 r100_set_safe_registers(rdev);
4070 /* Initialize power management */
4071 radeon_pm_init(rdev);
4073 rdev->accel_working = true;
4074 r = r100_startup(rdev);
4076 /* Somethings want wront with the accel init stop accel */
4077 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4079 radeon_wb_fini(rdev);
4080 radeon_ib_pool_fini(rdev);
4081 radeon_irq_kms_fini(rdev);
4082 if (rdev->flags & RADEON_IS_PCI)
4083 r100_pci_gart_fini(rdev);
4084 rdev->accel_working = false;
4089 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
4090 bool always_indirect)
4092 if (reg < rdev->rmmio_size && !always_indirect)
4093 return readl(((void __iomem *)rdev->rmmio) + reg);
4095 unsigned long flags;
4098 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4099 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4100 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4101 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4107 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
4108 bool always_indirect)
4110 if (reg < rdev->rmmio_size && !always_indirect)
4111 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4113 unsigned long flags;
4115 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4116 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4117 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4118 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4122 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4124 if (reg < rdev->rio_mem_size)
4125 return ioread32(rdev->rio_mem + reg);
4127 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4128 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4132 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4134 if (reg < rdev->rio_mem_size)
4135 iowrite32(v, rdev->rio_mem + reg);
4137 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4138 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);