2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
29 #include "radeon_asic.h"
30 #include <drm/radeon_drm.h>
34 #include "cayman_blit_shaders.h"
35 #include "radeon_ucode.h"
36 #include "clearstate_cayman.h"
38 static const u32 tn_rlc_save_restore_register_list[] =
164 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
165 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
166 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
167 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
168 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
169 extern void evergreen_mc_program(struct radeon_device *rdev);
170 extern void evergreen_irq_suspend(struct radeon_device *rdev);
171 extern int evergreen_mc_init(struct radeon_device *rdev);
172 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
173 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
174 extern void evergreen_program_aspm(struct radeon_device *rdev);
175 extern void sumo_rlc_fini(struct radeon_device *rdev);
176 extern int sumo_rlc_init(struct radeon_device *rdev);
179 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
180 MODULE_FIRMWARE("radeon/BARTS_me.bin");
181 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
182 MODULE_FIRMWARE("radeon/BARTS_smc.bin");
183 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
184 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
185 MODULE_FIRMWARE("radeon/TURKS_me.bin");
186 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
187 MODULE_FIRMWARE("radeon/TURKS_smc.bin");
188 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
189 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
190 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
191 MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
192 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
193 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
194 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
195 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
196 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
197 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
198 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
199 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
202 static const u32 cayman_golden_registers2[] =
204 0x3e5c, 0xffffffff, 0x00000000,
205 0x3e48, 0xffffffff, 0x00000000,
206 0x3e4c, 0xffffffff, 0x00000000,
207 0x3e64, 0xffffffff, 0x00000000,
208 0x3e50, 0xffffffff, 0x00000000,
209 0x3e60, 0xffffffff, 0x00000000
212 static const u32 cayman_golden_registers[] =
214 0x5eb4, 0xffffffff, 0x00000002,
215 0x5e78, 0x8f311ff1, 0x001000f0,
216 0x3f90, 0xffff0000, 0xff000000,
217 0x9148, 0xffff0000, 0xff000000,
218 0x3f94, 0xffff0000, 0xff000000,
219 0x914c, 0xffff0000, 0xff000000,
220 0xc78, 0x00000080, 0x00000080,
221 0xbd4, 0x70073777, 0x00011003,
222 0xd02c, 0xbfffff1f, 0x08421000,
223 0xd0b8, 0x73773777, 0x02011003,
224 0x5bc0, 0x00200000, 0x50100000,
225 0x98f8, 0x33773777, 0x02011003,
226 0x98fc, 0xffffffff, 0x76541032,
227 0x7030, 0x31000311, 0x00000011,
228 0x2f48, 0x33773777, 0x42010001,
229 0x6b28, 0x00000010, 0x00000012,
230 0x7728, 0x00000010, 0x00000012,
231 0x10328, 0x00000010, 0x00000012,
232 0x10f28, 0x00000010, 0x00000012,
233 0x11b28, 0x00000010, 0x00000012,
234 0x12728, 0x00000010, 0x00000012,
235 0x240c, 0x000007ff, 0x00000000,
236 0x8a14, 0xf000001f, 0x00000007,
237 0x8b24, 0x3fff3fff, 0x00ff0fff,
238 0x8b10, 0x0000ff0f, 0x00000000,
239 0x28a4c, 0x07ffffff, 0x06000000,
240 0x10c, 0x00000001, 0x00010003,
241 0xa02c, 0xffffffff, 0x0000009b,
242 0x913c, 0x0000010f, 0x01000100,
243 0x8c04, 0xf8ff00ff, 0x40600060,
244 0x28350, 0x00000f01, 0x00000000,
245 0x9508, 0x3700001f, 0x00000002,
246 0x960c, 0xffffffff, 0x54763210,
247 0x88c4, 0x001f3ae3, 0x00000082,
248 0x88d0, 0xffffffff, 0x0f40df40,
249 0x88d4, 0x0000001f, 0x00000010,
250 0x8974, 0xffffffff, 0x00000000
253 static const u32 dvst_golden_registers2[] =
255 0x8f8, 0xffffffff, 0,
256 0x8fc, 0x00380000, 0,
257 0x8f8, 0xffffffff, 1,
261 static const u32 dvst_golden_registers[] =
263 0x690, 0x3fff3fff, 0x20c00033,
264 0x918c, 0x0fff0fff, 0x00010006,
265 0x91a8, 0x0fff0fff, 0x00010006,
266 0x9150, 0xffffdfff, 0x6e944040,
267 0x917c, 0x0fff0fff, 0x00030002,
268 0x9198, 0x0fff0fff, 0x00030002,
269 0x915c, 0x0fff0fff, 0x00010000,
270 0x3f90, 0xffff0001, 0xff000000,
271 0x9178, 0x0fff0fff, 0x00070000,
272 0x9194, 0x0fff0fff, 0x00070000,
273 0x9148, 0xffff0001, 0xff000000,
274 0x9190, 0x0fff0fff, 0x00090008,
275 0x91ac, 0x0fff0fff, 0x00090008,
276 0x3f94, 0xffff0000, 0xff000000,
277 0x914c, 0xffff0000, 0xff000000,
278 0x929c, 0x00000fff, 0x00000001,
279 0x55e4, 0xff607fff, 0xfc000100,
280 0x8a18, 0xff000fff, 0x00000100,
281 0x8b28, 0xff000fff, 0x00000100,
282 0x9144, 0xfffc0fff, 0x00000100,
283 0x6ed8, 0x00010101, 0x00010000,
284 0x9830, 0xffffffff, 0x00000000,
285 0x9834, 0xf00fffff, 0x00000400,
286 0x9838, 0xfffffffe, 0x00000000,
287 0xd0c0, 0xff000fff, 0x00000100,
288 0xd02c, 0xbfffff1f, 0x08421000,
289 0xd0b8, 0x73773777, 0x12010001,
290 0x5bb0, 0x000000f0, 0x00000070,
291 0x98f8, 0x73773777, 0x12010001,
292 0x98fc, 0xffffffff, 0x00000010,
293 0x9b7c, 0x00ff0000, 0x00fc0000,
294 0x8030, 0x00001f0f, 0x0000100a,
295 0x2f48, 0x73773777, 0x12010001,
296 0x2408, 0x00030000, 0x000c007f,
297 0x8a14, 0xf000003f, 0x00000007,
298 0x8b24, 0x3fff3fff, 0x00ff0fff,
299 0x8b10, 0x0000ff0f, 0x00000000,
300 0x28a4c, 0x07ffffff, 0x06000000,
301 0x4d8, 0x00000fff, 0x00000100,
302 0xa008, 0xffffffff, 0x00010000,
303 0x913c, 0xffff03ff, 0x01000100,
304 0x8c00, 0x000000ff, 0x00000003,
305 0x8c04, 0xf8ff00ff, 0x40600060,
306 0x8cf0, 0x1fff1fff, 0x08e00410,
307 0x28350, 0x00000f01, 0x00000000,
308 0x9508, 0xf700071f, 0x00000002,
309 0x960c, 0xffffffff, 0x54763210,
310 0x20ef8, 0x01ff01ff, 0x00000002,
311 0x20e98, 0xfffffbff, 0x00200000,
312 0x2015c, 0xffffffff, 0x00000f40,
313 0x88c4, 0x001f3ae3, 0x00000082,
314 0x8978, 0x3fffffff, 0x04050140,
315 0x88d4, 0x0000001f, 0x00000010,
316 0x8974, 0xffffffff, 0x00000000
319 static const u32 scrapper_golden_registers[] =
321 0x690, 0x3fff3fff, 0x20c00033,
322 0x918c, 0x0fff0fff, 0x00010006,
323 0x918c, 0x0fff0fff, 0x00010006,
324 0x91a8, 0x0fff0fff, 0x00010006,
325 0x91a8, 0x0fff0fff, 0x00010006,
326 0x9150, 0xffffdfff, 0x6e944040,
327 0x9150, 0xffffdfff, 0x6e944040,
328 0x917c, 0x0fff0fff, 0x00030002,
329 0x917c, 0x0fff0fff, 0x00030002,
330 0x9198, 0x0fff0fff, 0x00030002,
331 0x9198, 0x0fff0fff, 0x00030002,
332 0x915c, 0x0fff0fff, 0x00010000,
333 0x915c, 0x0fff0fff, 0x00010000,
334 0x3f90, 0xffff0001, 0xff000000,
335 0x3f90, 0xffff0001, 0xff000000,
336 0x9178, 0x0fff0fff, 0x00070000,
337 0x9178, 0x0fff0fff, 0x00070000,
338 0x9194, 0x0fff0fff, 0x00070000,
339 0x9194, 0x0fff0fff, 0x00070000,
340 0x9148, 0xffff0001, 0xff000000,
341 0x9148, 0xffff0001, 0xff000000,
342 0x9190, 0x0fff0fff, 0x00090008,
343 0x9190, 0x0fff0fff, 0x00090008,
344 0x91ac, 0x0fff0fff, 0x00090008,
345 0x91ac, 0x0fff0fff, 0x00090008,
346 0x3f94, 0xffff0000, 0xff000000,
347 0x3f94, 0xffff0000, 0xff000000,
348 0x914c, 0xffff0000, 0xff000000,
349 0x914c, 0xffff0000, 0xff000000,
350 0x929c, 0x00000fff, 0x00000001,
351 0x929c, 0x00000fff, 0x00000001,
352 0x55e4, 0xff607fff, 0xfc000100,
353 0x8a18, 0xff000fff, 0x00000100,
354 0x8a18, 0xff000fff, 0x00000100,
355 0x8b28, 0xff000fff, 0x00000100,
356 0x8b28, 0xff000fff, 0x00000100,
357 0x9144, 0xfffc0fff, 0x00000100,
358 0x9144, 0xfffc0fff, 0x00000100,
359 0x6ed8, 0x00010101, 0x00010000,
360 0x9830, 0xffffffff, 0x00000000,
361 0x9830, 0xffffffff, 0x00000000,
362 0x9834, 0xf00fffff, 0x00000400,
363 0x9834, 0xf00fffff, 0x00000400,
364 0x9838, 0xfffffffe, 0x00000000,
365 0x9838, 0xfffffffe, 0x00000000,
366 0xd0c0, 0xff000fff, 0x00000100,
367 0xd02c, 0xbfffff1f, 0x08421000,
368 0xd02c, 0xbfffff1f, 0x08421000,
369 0xd0b8, 0x73773777, 0x12010001,
370 0xd0b8, 0x73773777, 0x12010001,
371 0x5bb0, 0x000000f0, 0x00000070,
372 0x98f8, 0x73773777, 0x12010001,
373 0x98f8, 0x73773777, 0x12010001,
374 0x98fc, 0xffffffff, 0x00000010,
375 0x98fc, 0xffffffff, 0x00000010,
376 0x9b7c, 0x00ff0000, 0x00fc0000,
377 0x9b7c, 0x00ff0000, 0x00fc0000,
378 0x8030, 0x00001f0f, 0x0000100a,
379 0x8030, 0x00001f0f, 0x0000100a,
380 0x2f48, 0x73773777, 0x12010001,
381 0x2f48, 0x73773777, 0x12010001,
382 0x2408, 0x00030000, 0x000c007f,
383 0x8a14, 0xf000003f, 0x00000007,
384 0x8a14, 0xf000003f, 0x00000007,
385 0x8b24, 0x3fff3fff, 0x00ff0fff,
386 0x8b24, 0x3fff3fff, 0x00ff0fff,
387 0x8b10, 0x0000ff0f, 0x00000000,
388 0x8b10, 0x0000ff0f, 0x00000000,
389 0x28a4c, 0x07ffffff, 0x06000000,
390 0x28a4c, 0x07ffffff, 0x06000000,
391 0x4d8, 0x00000fff, 0x00000100,
392 0x4d8, 0x00000fff, 0x00000100,
393 0xa008, 0xffffffff, 0x00010000,
394 0xa008, 0xffffffff, 0x00010000,
395 0x913c, 0xffff03ff, 0x01000100,
396 0x913c, 0xffff03ff, 0x01000100,
397 0x90e8, 0x001fffff, 0x010400c0,
398 0x8c00, 0x000000ff, 0x00000003,
399 0x8c00, 0x000000ff, 0x00000003,
400 0x8c04, 0xf8ff00ff, 0x40600060,
401 0x8c04, 0xf8ff00ff, 0x40600060,
402 0x8c30, 0x0000000f, 0x00040005,
403 0x8cf0, 0x1fff1fff, 0x08e00410,
404 0x8cf0, 0x1fff1fff, 0x08e00410,
405 0x900c, 0x00ffffff, 0x0017071f,
406 0x28350, 0x00000f01, 0x00000000,
407 0x28350, 0x00000f01, 0x00000000,
408 0x9508, 0xf700071f, 0x00000002,
409 0x9508, 0xf700071f, 0x00000002,
410 0x9688, 0x00300000, 0x0017000f,
411 0x960c, 0xffffffff, 0x54763210,
412 0x960c, 0xffffffff, 0x54763210,
413 0x20ef8, 0x01ff01ff, 0x00000002,
414 0x20e98, 0xfffffbff, 0x00200000,
415 0x2015c, 0xffffffff, 0x00000f40,
416 0x88c4, 0x001f3ae3, 0x00000082,
417 0x88c4, 0x001f3ae3, 0x00000082,
418 0x8978, 0x3fffffff, 0x04050140,
419 0x8978, 0x3fffffff, 0x04050140,
420 0x88d4, 0x0000001f, 0x00000010,
421 0x88d4, 0x0000001f, 0x00000010,
422 0x8974, 0xffffffff, 0x00000000,
423 0x8974, 0xffffffff, 0x00000000
426 static void ni_init_golden_registers(struct radeon_device *rdev)
428 switch (rdev->family) {
430 radeon_program_register_sequence(rdev,
431 cayman_golden_registers,
432 (const u32)ARRAY_SIZE(cayman_golden_registers));
433 radeon_program_register_sequence(rdev,
434 cayman_golden_registers2,
435 (const u32)ARRAY_SIZE(cayman_golden_registers2));
438 if ((rdev->pdev->device == 0x9900) ||
439 (rdev->pdev->device == 0x9901) ||
440 (rdev->pdev->device == 0x9903) ||
441 (rdev->pdev->device == 0x9904) ||
442 (rdev->pdev->device == 0x9905) ||
443 (rdev->pdev->device == 0x9906) ||
444 (rdev->pdev->device == 0x9907) ||
445 (rdev->pdev->device == 0x9908) ||
446 (rdev->pdev->device == 0x9909) ||
447 (rdev->pdev->device == 0x990A) ||
448 (rdev->pdev->device == 0x990B) ||
449 (rdev->pdev->device == 0x990C) ||
450 (rdev->pdev->device == 0x990D) ||
451 (rdev->pdev->device == 0x990E) ||
452 (rdev->pdev->device == 0x990F) ||
453 (rdev->pdev->device == 0x9910) ||
454 (rdev->pdev->device == 0x9913) ||
455 (rdev->pdev->device == 0x9917) ||
456 (rdev->pdev->device == 0x9918)) {
457 radeon_program_register_sequence(rdev,
458 dvst_golden_registers,
459 (const u32)ARRAY_SIZE(dvst_golden_registers));
460 radeon_program_register_sequence(rdev,
461 dvst_golden_registers2,
462 (const u32)ARRAY_SIZE(dvst_golden_registers2));
464 radeon_program_register_sequence(rdev,
465 scrapper_golden_registers,
466 (const u32)ARRAY_SIZE(scrapper_golden_registers));
467 radeon_program_register_sequence(rdev,
468 dvst_golden_registers2,
469 (const u32)ARRAY_SIZE(dvst_golden_registers2));
477 #define BTC_IO_MC_REGS_SIZE 29
479 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
480 {0x00000077, 0xff010100},
481 {0x00000078, 0x00000000},
482 {0x00000079, 0x00001434},
483 {0x0000007a, 0xcc08ec08},
484 {0x0000007b, 0x00040000},
485 {0x0000007c, 0x000080c0},
486 {0x0000007d, 0x09000000},
487 {0x0000007e, 0x00210404},
488 {0x00000081, 0x08a8e800},
489 {0x00000082, 0x00030444},
490 {0x00000083, 0x00000000},
491 {0x00000085, 0x00000001},
492 {0x00000086, 0x00000002},
493 {0x00000087, 0x48490000},
494 {0x00000088, 0x20244647},
495 {0x00000089, 0x00000005},
496 {0x0000008b, 0x66030000},
497 {0x0000008c, 0x00006603},
498 {0x0000008d, 0x00000100},
499 {0x0000008f, 0x00001c0a},
500 {0x00000090, 0xff000001},
501 {0x00000094, 0x00101101},
502 {0x00000095, 0x00000fff},
503 {0x00000096, 0x00116fff},
504 {0x00000097, 0x60010000},
505 {0x00000098, 0x10010000},
506 {0x00000099, 0x00006000},
507 {0x0000009a, 0x00001000},
508 {0x0000009f, 0x00946a00}
511 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
512 {0x00000077, 0xff010100},
513 {0x00000078, 0x00000000},
514 {0x00000079, 0x00001434},
515 {0x0000007a, 0xcc08ec08},
516 {0x0000007b, 0x00040000},
517 {0x0000007c, 0x000080c0},
518 {0x0000007d, 0x09000000},
519 {0x0000007e, 0x00210404},
520 {0x00000081, 0x08a8e800},
521 {0x00000082, 0x00030444},
522 {0x00000083, 0x00000000},
523 {0x00000085, 0x00000001},
524 {0x00000086, 0x00000002},
525 {0x00000087, 0x48490000},
526 {0x00000088, 0x20244647},
527 {0x00000089, 0x00000005},
528 {0x0000008b, 0x66030000},
529 {0x0000008c, 0x00006603},
530 {0x0000008d, 0x00000100},
531 {0x0000008f, 0x00001c0a},
532 {0x00000090, 0xff000001},
533 {0x00000094, 0x00101101},
534 {0x00000095, 0x00000fff},
535 {0x00000096, 0x00116fff},
536 {0x00000097, 0x60010000},
537 {0x00000098, 0x10010000},
538 {0x00000099, 0x00006000},
539 {0x0000009a, 0x00001000},
540 {0x0000009f, 0x00936a00}
543 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
544 {0x00000077, 0xff010100},
545 {0x00000078, 0x00000000},
546 {0x00000079, 0x00001434},
547 {0x0000007a, 0xcc08ec08},
548 {0x0000007b, 0x00040000},
549 {0x0000007c, 0x000080c0},
550 {0x0000007d, 0x09000000},
551 {0x0000007e, 0x00210404},
552 {0x00000081, 0x08a8e800},
553 {0x00000082, 0x00030444},
554 {0x00000083, 0x00000000},
555 {0x00000085, 0x00000001},
556 {0x00000086, 0x00000002},
557 {0x00000087, 0x48490000},
558 {0x00000088, 0x20244647},
559 {0x00000089, 0x00000005},
560 {0x0000008b, 0x66030000},
561 {0x0000008c, 0x00006603},
562 {0x0000008d, 0x00000100},
563 {0x0000008f, 0x00001c0a},
564 {0x00000090, 0xff000001},
565 {0x00000094, 0x00101101},
566 {0x00000095, 0x00000fff},
567 {0x00000096, 0x00116fff},
568 {0x00000097, 0x60010000},
569 {0x00000098, 0x10010000},
570 {0x00000099, 0x00006000},
571 {0x0000009a, 0x00001000},
572 {0x0000009f, 0x00916a00}
575 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
576 {0x00000077, 0xff010100},
577 {0x00000078, 0x00000000},
578 {0x00000079, 0x00001434},
579 {0x0000007a, 0xcc08ec08},
580 {0x0000007b, 0x00040000},
581 {0x0000007c, 0x000080c0},
582 {0x0000007d, 0x09000000},
583 {0x0000007e, 0x00210404},
584 {0x00000081, 0x08a8e800},
585 {0x00000082, 0x00030444},
586 {0x00000083, 0x00000000},
587 {0x00000085, 0x00000001},
588 {0x00000086, 0x00000002},
589 {0x00000087, 0x48490000},
590 {0x00000088, 0x20244647},
591 {0x00000089, 0x00000005},
592 {0x0000008b, 0x66030000},
593 {0x0000008c, 0x00006603},
594 {0x0000008d, 0x00000100},
595 {0x0000008f, 0x00001c0a},
596 {0x00000090, 0xff000001},
597 {0x00000094, 0x00101101},
598 {0x00000095, 0x00000fff},
599 {0x00000096, 0x00116fff},
600 {0x00000097, 0x60010000},
601 {0x00000098, 0x10010000},
602 {0x00000099, 0x00006000},
603 {0x0000009a, 0x00001000},
604 {0x0000009f, 0x00976b00}
607 int ni_mc_load_microcode(struct radeon_device *rdev)
609 const __be32 *fw_data;
610 u32 mem_type, running, blackout = 0;
612 int i, ucode_size, regs_size;
617 switch (rdev->family) {
619 io_mc_regs = (u32 *)&barts_io_mc_regs;
620 ucode_size = BTC_MC_UCODE_SIZE;
621 regs_size = BTC_IO_MC_REGS_SIZE;
624 io_mc_regs = (u32 *)&turks_io_mc_regs;
625 ucode_size = BTC_MC_UCODE_SIZE;
626 regs_size = BTC_IO_MC_REGS_SIZE;
630 io_mc_regs = (u32 *)&caicos_io_mc_regs;
631 ucode_size = BTC_MC_UCODE_SIZE;
632 regs_size = BTC_IO_MC_REGS_SIZE;
635 io_mc_regs = (u32 *)&cayman_io_mc_regs;
636 ucode_size = CAYMAN_MC_UCODE_SIZE;
637 regs_size = BTC_IO_MC_REGS_SIZE;
641 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
642 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
644 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
646 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
647 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
650 /* reset the engine and set to writable */
651 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
652 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
654 /* load mc io regs */
655 for (i = 0; i < regs_size; i++) {
656 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
657 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
659 /* load the MC ucode */
660 fw_data = (const __be32 *)rdev->mc_fw->data;
661 for (i = 0; i < ucode_size; i++)
662 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
664 /* put the engine back into the active state */
665 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
666 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
667 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
669 /* wait for training to complete */
670 for (i = 0; i < rdev->usec_timeout; i++) {
671 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
677 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
683 int ni_init_microcode(struct radeon_device *rdev)
685 const char *chip_name;
686 const char *rlc_chip_name;
687 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
688 size_t smc_req_size = 0;
694 switch (rdev->family) {
697 rlc_chip_name = "BTC";
698 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
699 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
700 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
701 mc_req_size = BTC_MC_UCODE_SIZE * 4;
702 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
706 rlc_chip_name = "BTC";
707 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
708 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
709 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
710 mc_req_size = BTC_MC_UCODE_SIZE * 4;
711 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
714 chip_name = "CAICOS";
715 rlc_chip_name = "BTC";
716 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
717 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
718 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
719 mc_req_size = BTC_MC_UCODE_SIZE * 4;
720 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
723 chip_name = "CAYMAN";
724 rlc_chip_name = "CAYMAN";
725 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
726 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
727 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
728 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
729 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
733 rlc_chip_name = "ARUBA";
734 /* pfp/me same size as CAYMAN */
735 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
736 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
737 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
743 DRM_INFO("Loading %s Microcode\n", chip_name);
745 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
746 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
749 if (rdev->pfp_fw->size != pfp_req_size) {
751 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
752 rdev->pfp_fw->size, fw_name);
757 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
758 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
761 if (rdev->me_fw->size != me_req_size) {
763 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
764 rdev->me_fw->size, fw_name);
768 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
769 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
772 if (rdev->rlc_fw->size != rlc_req_size) {
774 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
775 rdev->rlc_fw->size, fw_name);
779 /* no MC ucode on TN */
780 if (!(rdev->flags & RADEON_IS_IGP)) {
781 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
782 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
785 if (rdev->mc_fw->size != mc_req_size) {
787 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
788 rdev->mc_fw->size, fw_name);
793 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
794 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
795 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
798 "smc: error loading firmware \"%s\"\n",
800 release_firmware(rdev->smc_fw);
803 } else if (rdev->smc_fw->size != smc_req_size) {
805 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
806 rdev->mc_fw->size, fw_name);
815 "ni_cp: Failed to load firmware \"%s\"\n",
817 release_firmware(rdev->pfp_fw);
819 release_firmware(rdev->me_fw);
821 release_firmware(rdev->rlc_fw);
823 release_firmware(rdev->mc_fw);
829 int tn_get_temp(struct radeon_device *rdev)
831 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
832 int actual_temp = (temp / 8) - 49;
834 return actual_temp * 1000;
840 static void cayman_gpu_init(struct radeon_device *rdev)
842 u32 gb_addr_config = 0;
843 u32 mc_shared_chmap, mc_arb_ramcfg;
844 u32 cgts_tcc_disable;
847 u32 cgts_sm_ctrl_reg;
848 u32 hdp_host_path_cntl;
850 u32 disabled_rb_mask;
853 switch (rdev->family) {
855 rdev->config.cayman.max_shader_engines = 2;
856 rdev->config.cayman.max_pipes_per_simd = 4;
857 rdev->config.cayman.max_tile_pipes = 8;
858 rdev->config.cayman.max_simds_per_se = 12;
859 rdev->config.cayman.max_backends_per_se = 4;
860 rdev->config.cayman.max_texture_channel_caches = 8;
861 rdev->config.cayman.max_gprs = 256;
862 rdev->config.cayman.max_threads = 256;
863 rdev->config.cayman.max_gs_threads = 32;
864 rdev->config.cayman.max_stack_entries = 512;
865 rdev->config.cayman.sx_num_of_sets = 8;
866 rdev->config.cayman.sx_max_export_size = 256;
867 rdev->config.cayman.sx_max_export_pos_size = 64;
868 rdev->config.cayman.sx_max_export_smx_size = 192;
869 rdev->config.cayman.max_hw_contexts = 8;
870 rdev->config.cayman.sq_num_cf_insts = 2;
872 rdev->config.cayman.sc_prim_fifo_size = 0x100;
873 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
874 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
875 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
879 rdev->config.cayman.max_shader_engines = 1;
880 rdev->config.cayman.max_pipes_per_simd = 4;
881 rdev->config.cayman.max_tile_pipes = 2;
882 if ((rdev->pdev->device == 0x9900) ||
883 (rdev->pdev->device == 0x9901) ||
884 (rdev->pdev->device == 0x9905) ||
885 (rdev->pdev->device == 0x9906) ||
886 (rdev->pdev->device == 0x9907) ||
887 (rdev->pdev->device == 0x9908) ||
888 (rdev->pdev->device == 0x9909) ||
889 (rdev->pdev->device == 0x990B) ||
890 (rdev->pdev->device == 0x990C) ||
891 (rdev->pdev->device == 0x990F) ||
892 (rdev->pdev->device == 0x9910) ||
893 (rdev->pdev->device == 0x9917) ||
894 (rdev->pdev->device == 0x9999) ||
895 (rdev->pdev->device == 0x999C)) {
896 rdev->config.cayman.max_simds_per_se = 6;
897 rdev->config.cayman.max_backends_per_se = 2;
898 } else if ((rdev->pdev->device == 0x9903) ||
899 (rdev->pdev->device == 0x9904) ||
900 (rdev->pdev->device == 0x990A) ||
901 (rdev->pdev->device == 0x990D) ||
902 (rdev->pdev->device == 0x990E) ||
903 (rdev->pdev->device == 0x9913) ||
904 (rdev->pdev->device == 0x9918) ||
905 (rdev->pdev->device == 0x999D)) {
906 rdev->config.cayman.max_simds_per_se = 4;
907 rdev->config.cayman.max_backends_per_se = 2;
908 } else if ((rdev->pdev->device == 0x9919) ||
909 (rdev->pdev->device == 0x9990) ||
910 (rdev->pdev->device == 0x9991) ||
911 (rdev->pdev->device == 0x9994) ||
912 (rdev->pdev->device == 0x9995) ||
913 (rdev->pdev->device == 0x9996) ||
914 (rdev->pdev->device == 0x999A) ||
915 (rdev->pdev->device == 0x99A0)) {
916 rdev->config.cayman.max_simds_per_se = 3;
917 rdev->config.cayman.max_backends_per_se = 1;
919 rdev->config.cayman.max_simds_per_se = 2;
920 rdev->config.cayman.max_backends_per_se = 1;
922 rdev->config.cayman.max_texture_channel_caches = 2;
923 rdev->config.cayman.max_gprs = 256;
924 rdev->config.cayman.max_threads = 256;
925 rdev->config.cayman.max_gs_threads = 32;
926 rdev->config.cayman.max_stack_entries = 512;
927 rdev->config.cayman.sx_num_of_sets = 8;
928 rdev->config.cayman.sx_max_export_size = 256;
929 rdev->config.cayman.sx_max_export_pos_size = 64;
930 rdev->config.cayman.sx_max_export_smx_size = 192;
931 rdev->config.cayman.max_hw_contexts = 8;
932 rdev->config.cayman.sq_num_cf_insts = 2;
934 rdev->config.cayman.sc_prim_fifo_size = 0x40;
935 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
936 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
937 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
942 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
943 WREG32((0x2c14 + j), 0x00000000);
944 WREG32((0x2c18 + j), 0x00000000);
945 WREG32((0x2c1c + j), 0x00000000);
946 WREG32((0x2c20 + j), 0x00000000);
947 WREG32((0x2c24 + j), 0x00000000);
950 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
952 evergreen_fix_pci_max_read_req_size(rdev);
954 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
955 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
957 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
958 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
959 if (rdev->config.cayman.mem_row_size_in_kb > 4)
960 rdev->config.cayman.mem_row_size_in_kb = 4;
961 /* XXX use MC settings? */
962 rdev->config.cayman.shader_engine_tile_size = 32;
963 rdev->config.cayman.num_gpus = 1;
964 rdev->config.cayman.multi_gpu_tile_size = 64;
966 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
967 rdev->config.cayman.num_tile_pipes = (1 << tmp);
968 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
969 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
970 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
971 rdev->config.cayman.num_shader_engines = tmp + 1;
972 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
973 rdev->config.cayman.num_gpus = tmp + 1;
974 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
975 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
976 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
977 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
980 /* setup tiling info dword. gb_addr_config is not adequate since it does
981 * not have bank info, so create a custom tiling dword.
984 * bits 11:8 group_size
985 * bits 15:12 row_size
987 rdev->config.cayman.tile_config = 0;
988 switch (rdev->config.cayman.num_tile_pipes) {
991 rdev->config.cayman.tile_config |= (0 << 0);
994 rdev->config.cayman.tile_config |= (1 << 0);
997 rdev->config.cayman.tile_config |= (2 << 0);
1000 rdev->config.cayman.tile_config |= (3 << 0);
1004 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1005 if (rdev->flags & RADEON_IS_IGP)
1006 rdev->config.cayman.tile_config |= 1 << 4;
1008 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1009 case 0: /* four banks */
1010 rdev->config.cayman.tile_config |= 0 << 4;
1012 case 1: /* eight banks */
1013 rdev->config.cayman.tile_config |= 1 << 4;
1015 case 2: /* sixteen banks */
1017 rdev->config.cayman.tile_config |= 2 << 4;
1021 rdev->config.cayman.tile_config |=
1022 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1023 rdev->config.cayman.tile_config |=
1024 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1027 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1028 u32 rb_disable_bitmap;
1030 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1031 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1032 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1034 tmp |= rb_disable_bitmap;
1036 /* enabled rb are just the one not disabled :) */
1037 disabled_rb_mask = tmp;
1039 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1041 /* if all the backends are disabled, fix it up here */
1042 if ((disabled_rb_mask & tmp) == tmp) {
1043 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1044 disabled_rb_mask &= ~(1 << i);
1047 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1048 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1050 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1051 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1052 if (ASIC_IS_DCE6(rdev))
1053 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1054 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1055 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1056 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1057 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1058 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1059 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1061 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1062 (rdev->flags & RADEON_IS_IGP)) {
1063 if ((disabled_rb_mask & 3) == 1) {
1064 /* RB0 disabled, RB1 enabled */
1067 /* RB1 disabled, RB0 enabled */
1071 tmp = gb_addr_config & NUM_PIPES_MASK;
1072 tmp = r6xx_remap_render_backend(rdev, tmp,
1073 rdev->config.cayman.max_backends_per_se *
1074 rdev->config.cayman.max_shader_engines,
1075 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1077 WREG32(GB_BACKEND_MAP, tmp);
1079 cgts_tcc_disable = 0xffff0000;
1080 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1081 cgts_tcc_disable &= ~(1 << (16 + i));
1082 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1083 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1084 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1085 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1087 /* reprogram the shader complex */
1088 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1089 for (i = 0; i < 16; i++)
1090 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1091 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1093 /* set HW defaults for 3D engine */
1094 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1096 sx_debug_1 = RREG32(SX_DEBUG_1);
1097 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1098 WREG32(SX_DEBUG_1, sx_debug_1);
1100 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1101 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1102 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
1103 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1105 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1107 /* need to be explicitly zero-ed */
1108 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1109 WREG32(SQ_LSTMP_RING_BASE, 0);
1110 WREG32(SQ_HSTMP_RING_BASE, 0);
1111 WREG32(SQ_ESTMP_RING_BASE, 0);
1112 WREG32(SQ_GSTMP_RING_BASE, 0);
1113 WREG32(SQ_VSTMP_RING_BASE, 0);
1114 WREG32(SQ_PSTMP_RING_BASE, 0);
1116 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1118 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1119 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1120 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
1122 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1123 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1124 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
1127 WREG32(VGT_NUM_INSTANCES, 1);
1129 WREG32(CP_PERFMON_CNTL, 0);
1131 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1132 FETCH_FIFO_HIWATER(0x4) |
1133 DONE_FIFO_HIWATER(0xe0) |
1134 ALU_UPDATE_FIFO_HIWATER(0x8)));
1136 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1137 WREG32(SQ_CONFIG, (VC_ENABLE |
1142 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1144 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1145 FORCE_EOV_MAX_REZ_CNT(255)));
1147 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1148 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1150 WREG32(VGT_GS_VERTEX_REUSE, 16);
1151 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1153 WREG32(CB_PERF_CTR0_SEL_0, 0);
1154 WREG32(CB_PERF_CTR0_SEL_1, 0);
1155 WREG32(CB_PERF_CTR1_SEL_0, 0);
1156 WREG32(CB_PERF_CTR1_SEL_1, 0);
1157 WREG32(CB_PERF_CTR2_SEL_0, 0);
1158 WREG32(CB_PERF_CTR2_SEL_1, 0);
1159 WREG32(CB_PERF_CTR3_SEL_0, 0);
1160 WREG32(CB_PERF_CTR3_SEL_1, 0);
1162 tmp = RREG32(HDP_MISC_CNTL);
1163 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1164 WREG32(HDP_MISC_CNTL, tmp);
1166 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1167 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1169 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1173 /* set clockgating golden values on TN */
1174 if (rdev->family == CHIP_ARUBA) {
1175 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1177 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1178 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1180 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1187 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1189 /* flush hdp cache */
1190 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1192 /* bits 0-7 are the VM contexts0-7 */
1193 WREG32(VM_INVALIDATE_REQUEST, 1);
1196 static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1200 if (rdev->gart.robj == NULL) {
1201 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1204 r = radeon_gart_table_vram_pin(rdev);
1207 radeon_gart_restore(rdev);
1208 /* Setup TLB control */
1209 WREG32(MC_VM_MX_L1_TLB_CNTL,
1212 ENABLE_L1_FRAGMENT_PROCESSING |
1213 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1214 ENABLE_ADVANCED_DRIVER_MODEL |
1215 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1216 /* Setup L2 cache */
1217 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1218 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1219 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1220 EFFECTIVE_L2_QUEUE_SIZE(7) |
1221 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1222 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1223 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1224 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1225 /* setup context0 */
1226 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1227 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1228 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1229 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1230 (u32)(rdev->dummy_page.addr >> 12));
1231 WREG32(VM_CONTEXT0_CNTL2, 0);
1232 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1233 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1239 /* empty context1-7 */
1240 /* Assign the pt base to something valid for now; the pts used for
1241 * the VMs are determined by the application and setup and assigned
1242 * on the fly in the vm part of radeon_gart.c
1244 for (i = 1; i < 8; i++) {
1245 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1246 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
1247 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1248 rdev->gart.table_addr >> 12);
1251 /* enable context1-7 */
1252 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1253 (u32)(rdev->dummy_page.addr >> 12));
1254 WREG32(VM_CONTEXT1_CNTL2, 4);
1255 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1256 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1257 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1258 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1259 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1260 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1261 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1262 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1263 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1264 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1265 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1266 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1267 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1269 cayman_pcie_gart_tlb_flush(rdev);
1270 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1271 (unsigned)(rdev->mc.gtt_size >> 20),
1272 (unsigned long long)rdev->gart.table_addr);
1273 rdev->gart.ready = true;
1277 static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1279 /* Disable all tables */
1280 WREG32(VM_CONTEXT0_CNTL, 0);
1281 WREG32(VM_CONTEXT1_CNTL, 0);
1282 /* Setup TLB control */
1283 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1284 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1285 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1286 /* Setup L2 cache */
1287 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1288 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1289 EFFECTIVE_L2_QUEUE_SIZE(7) |
1290 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1291 WREG32(VM_L2_CNTL2, 0);
1292 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1293 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1294 radeon_gart_table_vram_unpin(rdev);
1297 static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1299 cayman_pcie_gart_disable(rdev);
1300 radeon_gart_table_vram_free(rdev);
1301 radeon_gart_fini(rdev);
1304 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1305 int ring, u32 cp_int_cntl)
1307 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1309 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1310 WREG32(CP_INT_CNTL, cp_int_cntl);
1316 void cayman_fence_ring_emit(struct radeon_device *rdev,
1317 struct radeon_fence *fence)
1319 struct radeon_ring *ring = &rdev->ring[fence->ring];
1320 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1322 /* flush read cache over gart for this vmid */
1323 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1324 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1325 radeon_ring_write(ring, 0);
1326 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1327 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1328 radeon_ring_write(ring, 0xFFFFFFFF);
1329 radeon_ring_write(ring, 0);
1330 radeon_ring_write(ring, 10); /* poll interval */
1331 /* EVENT_WRITE_EOP - flush caches, send int */
1332 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1333 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1334 radeon_ring_write(ring, addr & 0xffffffff);
1335 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1336 radeon_ring_write(ring, fence->seq);
1337 radeon_ring_write(ring, 0);
1340 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1342 struct radeon_ring *ring = &rdev->ring[ib->ring];
1344 /* set to DX10/11 mode */
1345 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1346 radeon_ring_write(ring, 1);
1348 if (ring->rptr_save_reg) {
1349 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1350 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1351 radeon_ring_write(ring, ((ring->rptr_save_reg -
1352 PACKET3_SET_CONFIG_REG_START) >> 2));
1353 radeon_ring_write(ring, next_rptr);
1356 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1357 radeon_ring_write(ring,
1361 (ib->gpu_addr & 0xFFFFFFFC));
1362 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1363 radeon_ring_write(ring, ib->length_dw |
1364 (ib->vm ? (ib->vm->id << 24) : 0));
1366 /* flush read cache over gart for this vmid */
1367 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1368 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1369 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
1370 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1371 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1372 radeon_ring_write(ring, 0xFFFFFFFF);
1373 radeon_ring_write(ring, 0);
1374 radeon_ring_write(ring, 10); /* poll interval */
1377 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1380 WREG32(CP_ME_CNTL, 0);
1382 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1383 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1384 WREG32(SCRATCH_UMSK, 0);
1385 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1389 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1391 const __be32 *fw_data;
1394 if (!rdev->me_fw || !rdev->pfp_fw)
1397 cayman_cp_enable(rdev, false);
1399 fw_data = (const __be32 *)rdev->pfp_fw->data;
1400 WREG32(CP_PFP_UCODE_ADDR, 0);
1401 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1402 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1403 WREG32(CP_PFP_UCODE_ADDR, 0);
1405 fw_data = (const __be32 *)rdev->me_fw->data;
1406 WREG32(CP_ME_RAM_WADDR, 0);
1407 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1408 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1410 WREG32(CP_PFP_UCODE_ADDR, 0);
1411 WREG32(CP_ME_RAM_WADDR, 0);
1412 WREG32(CP_ME_RAM_RADDR, 0);
1416 static int cayman_cp_start(struct radeon_device *rdev)
1418 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1421 r = radeon_ring_lock(rdev, ring, 7);
1423 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1426 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1427 radeon_ring_write(ring, 0x1);
1428 radeon_ring_write(ring, 0x0);
1429 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1430 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1431 radeon_ring_write(ring, 0);
1432 radeon_ring_write(ring, 0);
1433 radeon_ring_unlock_commit(rdev, ring);
1435 cayman_cp_enable(rdev, true);
1437 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1439 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1443 /* setup clear context state */
1444 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1445 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1447 for (i = 0; i < cayman_default_size; i++)
1448 radeon_ring_write(ring, cayman_default_state[i]);
1450 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1451 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1453 /* set clear context state */
1454 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1455 radeon_ring_write(ring, 0);
1457 /* SQ_VTX_BASE_VTX_LOC */
1458 radeon_ring_write(ring, 0xc0026f00);
1459 radeon_ring_write(ring, 0x00000000);
1460 radeon_ring_write(ring, 0x00000000);
1461 radeon_ring_write(ring, 0x00000000);
1464 radeon_ring_write(ring, 0xc0036f00);
1465 radeon_ring_write(ring, 0x00000bc4);
1466 radeon_ring_write(ring, 0xffffffff);
1467 radeon_ring_write(ring, 0xffffffff);
1468 radeon_ring_write(ring, 0xffffffff);
1470 radeon_ring_write(ring, 0xc0026900);
1471 radeon_ring_write(ring, 0x00000316);
1472 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1473 radeon_ring_write(ring, 0x00000010); /* */
1475 radeon_ring_unlock_commit(rdev, ring);
1477 /* XXX init other rings */
1482 static void cayman_cp_fini(struct radeon_device *rdev)
1484 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1485 cayman_cp_enable(rdev, false);
1486 radeon_ring_fini(rdev, ring);
1487 radeon_scratch_free(rdev, ring->rptr_save_reg);
1490 static int cayman_cp_resume(struct radeon_device *rdev)
1492 static const int ridx[] = {
1493 RADEON_RING_TYPE_GFX_INDEX,
1494 CAYMAN_RING_TYPE_CP1_INDEX,
1495 CAYMAN_RING_TYPE_CP2_INDEX
1497 static const unsigned cp_rb_cntl[] = {
1502 static const unsigned cp_rb_rptr_addr[] = {
1507 static const unsigned cp_rb_rptr_addr_hi[] = {
1508 CP_RB0_RPTR_ADDR_HI,
1509 CP_RB1_RPTR_ADDR_HI,
1512 static const unsigned cp_rb_base[] = {
1517 struct radeon_ring *ring;
1520 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1521 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1527 RREG32(GRBM_SOFT_RESET);
1529 WREG32(GRBM_SOFT_RESET, 0);
1530 RREG32(GRBM_SOFT_RESET);
1532 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1533 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1535 /* Set the write pointer delay */
1536 WREG32(CP_RB_WPTR_DELAY, 0);
1538 WREG32(CP_DEBUG, (1 << 27));
1540 /* set the wb address whether it's enabled or not */
1541 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1542 WREG32(SCRATCH_UMSK, 0xff);
1544 for (i = 0; i < 3; ++i) {
1548 /* Set ring buffer size */
1549 ring = &rdev->ring[ridx[i]];
1550 rb_cntl = order_base_2(ring->ring_size / 8);
1551 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1553 rb_cntl |= BUF_SWAP_32BIT;
1555 WREG32(cp_rb_cntl[i], rb_cntl);
1557 /* set the wb address whether it's enabled or not */
1558 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1559 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1560 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1563 /* set the rb base addr, this causes an internal reset of ALL rings */
1564 for (i = 0; i < 3; ++i) {
1565 ring = &rdev->ring[ridx[i]];
1566 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1569 for (i = 0; i < 3; ++i) {
1570 /* Initialize the ring buffer's read and write pointers */
1571 ring = &rdev->ring[ridx[i]];
1572 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1574 ring->rptr = ring->wptr = 0;
1575 WREG32(ring->rptr_reg, ring->rptr);
1576 WREG32(ring->wptr_reg, ring->wptr);
1579 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1582 /* start the rings */
1583 cayman_cp_start(rdev);
1584 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1585 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1586 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1587 /* this only test cp0 */
1588 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1590 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1591 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1592 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1599 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1605 tmp = RREG32(GRBM_STATUS);
1606 if (tmp & (PA_BUSY | SC_BUSY |
1608 TA_BUSY | VGT_BUSY |
1610 GDS_BUSY | SPI_BUSY |
1611 IA_BUSY | IA_BUSY_NO_DMA))
1612 reset_mask |= RADEON_RESET_GFX;
1614 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1615 CP_BUSY | CP_COHERENCY_BUSY))
1616 reset_mask |= RADEON_RESET_CP;
1618 if (tmp & GRBM_EE_BUSY)
1619 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1621 /* DMA_STATUS_REG 0 */
1622 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1623 if (!(tmp & DMA_IDLE))
1624 reset_mask |= RADEON_RESET_DMA;
1626 /* DMA_STATUS_REG 1 */
1627 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1628 if (!(tmp & DMA_IDLE))
1629 reset_mask |= RADEON_RESET_DMA1;
1632 tmp = RREG32(SRBM_STATUS2);
1634 reset_mask |= RADEON_RESET_DMA;
1636 if (tmp & DMA1_BUSY)
1637 reset_mask |= RADEON_RESET_DMA1;
1640 tmp = RREG32(SRBM_STATUS);
1641 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1642 reset_mask |= RADEON_RESET_RLC;
1645 reset_mask |= RADEON_RESET_IH;
1648 reset_mask |= RADEON_RESET_SEM;
1650 if (tmp & GRBM_RQ_PENDING)
1651 reset_mask |= RADEON_RESET_GRBM;
1654 reset_mask |= RADEON_RESET_VMC;
1656 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1657 MCC_BUSY | MCD_BUSY))
1658 reset_mask |= RADEON_RESET_MC;
1660 if (evergreen_is_display_hung(rdev))
1661 reset_mask |= RADEON_RESET_DISPLAY;
1664 tmp = RREG32(VM_L2_STATUS);
1666 reset_mask |= RADEON_RESET_VMC;
1668 /* Skip MC reset as it's mostly likely not hung, just busy */
1669 if (reset_mask & RADEON_RESET_MC) {
1670 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1671 reset_mask &= ~RADEON_RESET_MC;
1677 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1679 struct evergreen_mc_save save;
1680 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1683 if (reset_mask == 0)
1686 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1688 evergreen_print_gpu_status_regs(rdev);
1689 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1691 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1693 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1695 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1698 /* Disable CP parsing/prefetching */
1699 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1701 if (reset_mask & RADEON_RESET_DMA) {
1703 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1704 tmp &= ~DMA_RB_ENABLE;
1705 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1708 if (reset_mask & RADEON_RESET_DMA1) {
1710 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1711 tmp &= ~DMA_RB_ENABLE;
1712 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1717 evergreen_mc_stop(rdev, &save);
1718 if (evergreen_mc_wait_for_idle(rdev)) {
1719 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1722 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1723 grbm_soft_reset = SOFT_RESET_CB |
1737 if (reset_mask & RADEON_RESET_CP) {
1738 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1740 srbm_soft_reset |= SOFT_RESET_GRBM;
1743 if (reset_mask & RADEON_RESET_DMA)
1744 srbm_soft_reset |= SOFT_RESET_DMA;
1746 if (reset_mask & RADEON_RESET_DMA1)
1747 srbm_soft_reset |= SOFT_RESET_DMA1;
1749 if (reset_mask & RADEON_RESET_DISPLAY)
1750 srbm_soft_reset |= SOFT_RESET_DC;
1752 if (reset_mask & RADEON_RESET_RLC)
1753 srbm_soft_reset |= SOFT_RESET_RLC;
1755 if (reset_mask & RADEON_RESET_SEM)
1756 srbm_soft_reset |= SOFT_RESET_SEM;
1758 if (reset_mask & RADEON_RESET_IH)
1759 srbm_soft_reset |= SOFT_RESET_IH;
1761 if (reset_mask & RADEON_RESET_GRBM)
1762 srbm_soft_reset |= SOFT_RESET_GRBM;
1764 if (reset_mask & RADEON_RESET_VMC)
1765 srbm_soft_reset |= SOFT_RESET_VMC;
1767 if (!(rdev->flags & RADEON_IS_IGP)) {
1768 if (reset_mask & RADEON_RESET_MC)
1769 srbm_soft_reset |= SOFT_RESET_MC;
1772 if (grbm_soft_reset) {
1773 tmp = RREG32(GRBM_SOFT_RESET);
1774 tmp |= grbm_soft_reset;
1775 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1776 WREG32(GRBM_SOFT_RESET, tmp);
1777 tmp = RREG32(GRBM_SOFT_RESET);
1781 tmp &= ~grbm_soft_reset;
1782 WREG32(GRBM_SOFT_RESET, tmp);
1783 tmp = RREG32(GRBM_SOFT_RESET);
1786 if (srbm_soft_reset) {
1787 tmp = RREG32(SRBM_SOFT_RESET);
1788 tmp |= srbm_soft_reset;
1789 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1790 WREG32(SRBM_SOFT_RESET, tmp);
1791 tmp = RREG32(SRBM_SOFT_RESET);
1795 tmp &= ~srbm_soft_reset;
1796 WREG32(SRBM_SOFT_RESET, tmp);
1797 tmp = RREG32(SRBM_SOFT_RESET);
1800 /* Wait a little for things to settle down */
1803 evergreen_mc_resume(rdev, &save);
1806 evergreen_print_gpu_status_regs(rdev);
1809 int cayman_asic_reset(struct radeon_device *rdev)
1813 reset_mask = cayman_gpu_check_soft_reset(rdev);
1816 r600_set_bios_scratch_engine_hung(rdev, true);
1818 cayman_gpu_soft_reset(rdev, reset_mask);
1820 reset_mask = cayman_gpu_check_soft_reset(rdev);
1823 r600_set_bios_scratch_engine_hung(rdev, false);
1829 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1831 * @rdev: radeon_device pointer
1832 * @ring: radeon_ring structure holding ring information
1834 * Check if the GFX engine is locked up.
1835 * Returns true if the engine appears to be locked up, false if not.
1837 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1839 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1841 if (!(reset_mask & (RADEON_RESET_GFX |
1842 RADEON_RESET_COMPUTE |
1843 RADEON_RESET_CP))) {
1844 radeon_ring_lockup_update(ring);
1847 /* force CP activities */
1848 radeon_ring_force_activity(rdev, ring);
1849 return radeon_ring_test_lockup(rdev, ring);
1852 static int cayman_startup(struct radeon_device *rdev)
1854 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1857 /* enable pcie gen2 link */
1858 evergreen_pcie_gen2_enable(rdev);
1860 evergreen_program_aspm(rdev);
1862 /* scratch needs to be initialized before MC */
1863 r = r600_vram_scratch_init(rdev);
1867 evergreen_mc_program(rdev);
1869 if (rdev->flags & RADEON_IS_IGP) {
1870 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1871 r = ni_init_microcode(rdev);
1873 DRM_ERROR("Failed to load firmware!\n");
1878 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1879 r = ni_init_microcode(rdev);
1881 DRM_ERROR("Failed to load firmware!\n");
1886 r = ni_mc_load_microcode(rdev);
1888 DRM_ERROR("Failed to load MC firmware!\n");
1893 r = cayman_pcie_gart_enable(rdev);
1896 cayman_gpu_init(rdev);
1898 /* allocate rlc buffers */
1899 if (rdev->flags & RADEON_IS_IGP) {
1900 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
1901 rdev->rlc.reg_list_size =
1902 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
1903 rdev->rlc.cs_data = cayman_cs_data;
1904 r = sumo_rlc_init(rdev);
1906 DRM_ERROR("Failed to init rlc BOs!\n");
1911 /* allocate wb buffer */
1912 r = radeon_wb_init(rdev);
1916 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1918 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1922 r = uvd_v2_2_resume(rdev);
1924 r = radeon_fence_driver_start_ring(rdev,
1925 R600_RING_TYPE_UVD_INDEX);
1927 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1930 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1932 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1934 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1938 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1940 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1944 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1946 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1950 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
1952 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1957 if (!rdev->irq.installed) {
1958 r = radeon_irq_kms_init(rdev);
1963 r = r600_irq_init(rdev);
1965 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1966 radeon_irq_kms_fini(rdev);
1969 evergreen_irq_set(rdev);
1971 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1972 CP_RB0_RPTR, CP_RB0_WPTR,
1977 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1978 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1979 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
1980 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
1981 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1985 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1986 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
1987 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
1988 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
1989 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1993 r = cayman_cp_load_microcode(rdev);
1996 r = cayman_cp_resume(rdev);
2000 r = cayman_dma_resume(rdev);
2004 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2005 if (ring->ring_size) {
2006 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
2007 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
2010 r = uvd_v1_0_init(rdev);
2012 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
2015 r = radeon_ib_pool_init(rdev);
2017 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2021 r = radeon_vm_manager_init(rdev);
2023 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
2027 if (ASIC_IS_DCE6(rdev)) {
2028 r = dce6_audio_init(rdev);
2032 r = r600_audio_init(rdev);
2040 int cayman_resume(struct radeon_device *rdev)
2044 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2045 * posting will perform necessary task to bring back GPU into good
2049 atom_asic_init(rdev->mode_info.atom_context);
2051 /* init golden registers */
2052 ni_init_golden_registers(rdev);
2054 rdev->accel_working = true;
2055 r = cayman_startup(rdev);
2057 DRM_ERROR("cayman startup failed on resume\n");
2058 rdev->accel_working = false;
2064 int cayman_suspend(struct radeon_device *rdev)
2066 if (ASIC_IS_DCE6(rdev))
2067 dce6_audio_fini(rdev);
2069 r600_audio_fini(rdev);
2070 radeon_vm_manager_fini(rdev);
2071 cayman_cp_enable(rdev, false);
2072 cayman_dma_stop(rdev);
2073 uvd_v1_0_fini(rdev);
2074 radeon_uvd_suspend(rdev);
2075 evergreen_irq_suspend(rdev);
2076 radeon_wb_disable(rdev);
2077 cayman_pcie_gart_disable(rdev);
2081 /* Plan is to move initialization in that function and use
2082 * helper function so that radeon_device_init pretty much
2083 * do nothing more than calling asic specific function. This
2084 * should also allow to remove a bunch of callback function
2087 int cayman_init(struct radeon_device *rdev)
2089 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2093 if (!radeon_get_bios(rdev)) {
2094 if (ASIC_IS_AVIVO(rdev))
2097 /* Must be an ATOMBIOS */
2098 if (!rdev->is_atom_bios) {
2099 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2102 r = radeon_atombios_init(rdev);
2106 /* Post card if necessary */
2107 if (!radeon_card_posted(rdev)) {
2109 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2112 DRM_INFO("GPU not posted. posting now...\n");
2113 atom_asic_init(rdev->mode_info.atom_context);
2115 /* init golden registers */
2116 ni_init_golden_registers(rdev);
2117 /* Initialize scratch registers */
2118 r600_scratch_init(rdev);
2119 /* Initialize surface registers */
2120 radeon_surface_init(rdev);
2121 /* Initialize clocks */
2122 radeon_get_clock_info(rdev->ddev);
2124 r = radeon_fence_driver_init(rdev);
2127 /* initialize memory controller */
2128 r = evergreen_mc_init(rdev);
2131 /* Memory manager */
2132 r = radeon_bo_init(rdev);
2136 ring->ring_obj = NULL;
2137 r600_ring_init(rdev, ring, 1024 * 1024);
2139 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2140 ring->ring_obj = NULL;
2141 r600_ring_init(rdev, ring, 64 * 1024);
2143 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2144 ring->ring_obj = NULL;
2145 r600_ring_init(rdev, ring, 64 * 1024);
2147 r = radeon_uvd_init(rdev);
2149 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2150 ring->ring_obj = NULL;
2151 r600_ring_init(rdev, ring, 4096);
2154 rdev->ih.ring_obj = NULL;
2155 r600_ih_ring_init(rdev, 64 * 1024);
2157 r = r600_pcie_gart_init(rdev);
2161 rdev->accel_working = true;
2162 r = cayman_startup(rdev);
2164 dev_err(rdev->dev, "disabling GPU acceleration\n");
2165 cayman_cp_fini(rdev);
2166 cayman_dma_fini(rdev);
2167 r600_irq_fini(rdev);
2168 if (rdev->flags & RADEON_IS_IGP)
2169 sumo_rlc_fini(rdev);
2170 radeon_wb_fini(rdev);
2171 radeon_ib_pool_fini(rdev);
2172 radeon_vm_manager_fini(rdev);
2173 radeon_irq_kms_fini(rdev);
2174 cayman_pcie_gart_fini(rdev);
2175 rdev->accel_working = false;
2178 /* Don't start up if the MC ucode is missing.
2179 * The default clocks and voltages before the MC ucode
2180 * is loaded are not suffient for advanced operations.
2182 * We can skip this check for TN, because there is no MC
2185 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
2186 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2193 void cayman_fini(struct radeon_device *rdev)
2195 cayman_cp_fini(rdev);
2196 cayman_dma_fini(rdev);
2197 r600_irq_fini(rdev);
2198 if (rdev->flags & RADEON_IS_IGP)
2199 sumo_rlc_fini(rdev);
2200 radeon_wb_fini(rdev);
2201 radeon_vm_manager_fini(rdev);
2202 radeon_ib_pool_fini(rdev);
2203 radeon_irq_kms_fini(rdev);
2204 uvd_v1_0_fini(rdev);
2205 radeon_uvd_fini(rdev);
2206 cayman_pcie_gart_fini(rdev);
2207 r600_vram_scratch_fini(rdev);
2208 radeon_gem_fini(rdev);
2209 radeon_fence_driver_fini(rdev);
2210 radeon_bo_fini(rdev);
2211 radeon_atombios_fini(rdev);
2219 int cayman_vm_init(struct radeon_device *rdev)
2222 rdev->vm_manager.nvm = 8;
2223 /* base offset of vram pages */
2224 if (rdev->flags & RADEON_IS_IGP) {
2225 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2227 rdev->vm_manager.vram_base_offset = tmp;
2229 rdev->vm_manager.vram_base_offset = 0;
2233 void cayman_vm_fini(struct radeon_device *rdev)
2238 * cayman_vm_decode_fault - print human readable fault info
2240 * @rdev: radeon_device pointer
2241 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2242 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2244 * Print human readable fault information (cayman/TN).
2246 void cayman_vm_decode_fault(struct radeon_device *rdev,
2247 u32 status, u32 addr)
2249 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2250 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2251 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2343 block = "TC_TFETCH";
2353 block = "TC_VFETCH";
2392 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2393 protections, vmid, addr,
2394 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2399 * cayman_vm_flush - vm flush using the CP
2401 * @rdev: radeon_device pointer
2403 * Update the page table base and flush the VM TLB
2404 * using the CP (cayman-si).
2406 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2408 struct radeon_ring *ring = &rdev->ring[ridx];
2413 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
2414 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2416 /* flush hdp cache */
2417 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2418 radeon_ring_write(ring, 0x1);
2420 /* bits 0-7 are the VM contexts0-7 */
2421 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2422 radeon_ring_write(ring, 1 << vm->id);
2424 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2425 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2426 radeon_ring_write(ring, 0x0);