drivers/gpu/drm/radeon/ni.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "radeon_drm.h"
  32 #include "nid.h"
  33 #include "atom.h"
  34 #include "ni_reg.h"
  35 #include "cayman_blit_shaders.h"
  36
  37 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  38 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  39 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
  40 extern void evergreen_mc_program(struct radeon_device *rdev);
  41 extern void evergreen_irq_suspend(struct radeon_device *rdev);
  42 extern int evergreen_mc_init(struct radeon_device *rdev);
  43 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  44 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  45 extern void si_rlc_fini(struct radeon_device *rdev);
  46 extern int si_rlc_init(struct radeon_device *rdev);
  47
  48 #define EVERGREEN_PFP_UCODE_SIZE 1120
  49 #define EVERGREEN_PM4_UCODE_SIZE 1376
  50 #define EVERGREEN_RLC_UCODE_SIZE 768
  51 #define BTC_MC_UCODE_SIZE 6024
  52
  53 #define CAYMAN_PFP_UCODE_SIZE 2176
  54 #define CAYMAN_PM4_UCODE_SIZE 2176
  55 #define CAYMAN_RLC_UCODE_SIZE 1024
  56 #define CAYMAN_MC_UCODE_SIZE 6037
  57
  58 #define ARUBA_RLC_UCODE_SIZE 1536
  59
  60 /* Firmware Names */
  61 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
  62 MODULE_FIRMWARE("radeon/BARTS_me.bin");
  63 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
  64 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
  65 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
  66 MODULE_FIRMWARE("radeon/TURKS_me.bin");
  67 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
  68 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
  69 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
  70 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
  71 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
  72 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
  73 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
  74 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
  75 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
  76 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
  77 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
  78
  79 #define BTC_IO_MC_REGS_SIZE 29
  80
  81 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  82         {0x00000077, 0xff010100},
  83         {0x00000078, 0x00000000},
  84         {0x00000079, 0x00001434},
  85         {0x0000007a, 0xcc08ec08},
  86         {0x0000007b, 0x00040000},
  87         {0x0000007c, 0x000080c0},
  88         {0x0000007d, 0x09000000},
  89         {0x0000007e, 0x00210404},
  90         {0x00000081, 0x08a8e800},
  91         {0x00000082, 0x00030444},
  92         {0x00000083, 0x00000000},
  93         {0x00000085, 0x00000001},
  94         {0x00000086, 0x00000002},
  95         {0x00000087, 0x48490000},
  96         {0x00000088, 0x20244647},
  97         {0x00000089, 0x00000005},
  98         {0x0000008b, 0x66030000},
  99         {0x0000008c, 0x00006603},
 100         {0x0000008d, 0x00000100},
 101         {0x0000008f, 0x00001c0a},
 102         {0x00000090, 0xff000001},
 103         {0x00000094, 0x00101101},
 104         {0x00000095, 0x00000fff},
 105         {0x00000096, 0x00116fff},
 106         {0x00000097, 0x60010000},
 107         {0x00000098, 0x10010000},
 108         {0x00000099, 0x00006000},
 109         {0x0000009a, 0x00001000},
 110         {0x0000009f, 0x00946a00}
 111 };
 112
 113 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 114         {0x00000077, 0xff010100},
 115         {0x00000078, 0x00000000},
 116         {0x00000079, 0x00001434},
 117         {0x0000007a, 0xcc08ec08},
 118         {0x0000007b, 0x00040000},
 119         {0x0000007c, 0x000080c0},
 120         {0x0000007d, 0x09000000},
 121         {0x0000007e, 0x00210404},
 122         {0x00000081, 0x08a8e800},
 123         {0x00000082, 0x00030444},
 124         {0x00000083, 0x00000000},
 125         {0x00000085, 0x00000001},
 126         {0x00000086, 0x00000002},
 127         {0x00000087, 0x48490000},
 128         {0x00000088, 0x20244647},
 129         {0x00000089, 0x00000005},
 130         {0x0000008b, 0x66030000},
 131         {0x0000008c, 0x00006603},
 132         {0x0000008d, 0x00000100},
 133         {0x0000008f, 0x00001c0a},
 134         {0x00000090, 0xff000001},
 135         {0x00000094, 0x00101101},
 136         {0x00000095, 0x00000fff},
 137         {0x00000096, 0x00116fff},
 138         {0x00000097, 0x60010000},
 139         {0x00000098, 0x10010000},
 140         {0x00000099, 0x00006000},
 141         {0x0000009a, 0x00001000},
 142         {0x0000009f, 0x00936a00}
 143 };
 144
 145 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 146         {0x00000077, 0xff010100},
 147         {0x00000078, 0x00000000},
 148         {0x00000079, 0x00001434},
 149         {0x0000007a, 0xcc08ec08},
 150         {0x0000007b, 0x00040000},
 151         {0x0000007c, 0x000080c0},
 152         {0x0000007d, 0x09000000},
 153         {0x0000007e, 0x00210404},
 154         {0x00000081, 0x08a8e800},
 155         {0x00000082, 0x00030444},
 156         {0x00000083, 0x00000000},
 157         {0x00000085, 0x00000001},
 158         {0x00000086, 0x00000002},
 159         {0x00000087, 0x48490000},
 160         {0x00000088, 0x20244647},
 161         {0x00000089, 0x00000005},
 162         {0x0000008b, 0x66030000},
 163         {0x0000008c, 0x00006603},
 164         {0x0000008d, 0x00000100},
 165         {0x0000008f, 0x00001c0a},
 166         {0x00000090, 0xff000001},
 167         {0x00000094, 0x00101101},
 168         {0x00000095, 0x00000fff},
 169         {0x00000096, 0x00116fff},
 170         {0x00000097, 0x60010000},
 171         {0x00000098, 0x10010000},
 172         {0x00000099, 0x00006000},
 173         {0x0000009a, 0x00001000},
 174         {0x0000009f, 0x00916a00}
 175 };
 176
 177 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 178         {0x00000077, 0xff010100},
 179         {0x00000078, 0x00000000},
 180         {0x00000079, 0x00001434},
 181         {0x0000007a, 0xcc08ec08},
 182         {0x0000007b, 0x00040000},
 183         {0x0000007c, 0x000080c0},
 184         {0x0000007d, 0x09000000},
 185         {0x0000007e, 0x00210404},
 186         {0x00000081, 0x08a8e800},
 187         {0x00000082, 0x00030444},
 188         {0x00000083, 0x00000000},
 189         {0x00000085, 0x00000001},
 190         {0x00000086, 0x00000002},
 191         {0x00000087, 0x48490000},
 192         {0x00000088, 0x20244647},
 193         {0x00000089, 0x00000005},
 194         {0x0000008b, 0x66030000},
 195         {0x0000008c, 0x00006603},
 196         {0x0000008d, 0x00000100},
 197         {0x0000008f, 0x00001c0a},
 198         {0x00000090, 0xff000001},
 199         {0x00000094, 0x00101101},
 200         {0x00000095, 0x00000fff},
 201         {0x00000096, 0x00116fff},
 202         {0x00000097, 0x60010000},
 203         {0x00000098, 0x10010000},
 204         {0x00000099, 0x00006000},
 205         {0x0000009a, 0x00001000},
 206         {0x0000009f, 0x00976b00}
 207 };
 208
 209 int ni_mc_load_microcode(struct radeon_device *rdev)
 210 {
 211         const __be32 *fw_data;
 212         u32 mem_type, running, blackout = 0;
 213         u32 *io_mc_regs;
 214         int i, ucode_size, regs_size;
 215
 216         if (!rdev->mc_fw)
 217                 return -EINVAL;
 218
 219         switch (rdev->family) {
 220         case CHIP_BARTS:
 221                 io_mc_regs = (u32 *)&barts_io_mc_regs;
 222                 ucode_size = BTC_MC_UCODE_SIZE;
 223                 regs_size = BTC_IO_MC_REGS_SIZE;
 224                 break;
 225         case CHIP_TURKS:
 226                 io_mc_regs = (u32 *)&turks_io_mc_regs;
 227                 ucode_size = BTC_MC_UCODE_SIZE;
 228                 regs_size = BTC_IO_MC_REGS_SIZE;
 229                 break;
 230         case CHIP_CAICOS:
 231         default:
 232                 io_mc_regs = (u32 *)&caicos_io_mc_regs;
 233                 ucode_size = BTC_MC_UCODE_SIZE;
 234                 regs_size = BTC_IO_MC_REGS_SIZE;
 235                 break;
 236         case CHIP_CAYMAN:
 237                 io_mc_regs = (u32 *)&cayman_io_mc_regs;
 238                 ucode_size = CAYMAN_MC_UCODE_SIZE;
 239                 regs_size = BTC_IO_MC_REGS_SIZE;
 240                 break;
 241         }
 242
 243         mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
 244         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 245
 246         if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
 247                 if (running) {
 248                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 249                         WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
 250                 }
 251
 252                 /* reset the engine and set to writable */
 253                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 254                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 255
 256                 /* load mc io regs */
 257                 for (i = 0; i < regs_size; i++) {
 258                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 259                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 260                 }
 261                 /* load the MC ucode */
 262                 fw_data = (const __be32 *)rdev->mc_fw->data;
 263                 for (i = 0; i < ucode_size; i++)
 264                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 265
 266                 /* put the engine back into the active state */
 267                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 268                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 269                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 270
 271                 /* wait for training to complete */
 272                 for (i = 0; i < rdev->usec_timeout; i++) {
 273                         if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
 274                                 break;
 275                         udelay(1);
 276                 }
 277
 278                 if (running)
 279                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 280         }
 281
 282         return 0;
 283 }
 284
 285 int ni_init_microcode(struct radeon_device *rdev)
 286 {
 287         struct platform_device *pdev;
 288         const char *chip_name;
 289         const char *rlc_chip_name;
 290         size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
 291         char fw_name[30];
 292         int err;
 293
 294         DRM_DEBUG("\n");
 295
 296         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 297         err = IS_ERR(pdev);
 298         if (err) {
 299                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 300                 return -EINVAL;
 301         }
 302
 303         switch (rdev->family) {
 304         case CHIP_BARTS:
 305                 chip_name = "BARTS";
 306                 rlc_chip_name = "BTC";
 307                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 308                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 309                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 310                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 311                 break;
 312         case CHIP_TURKS:
 313                 chip_name = "TURKS";
 314                 rlc_chip_name = "BTC";
 315                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 316                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 317                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 318                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 319                 break;
 320         case CHIP_CAICOS:
 321                 chip_name = "CAICOS";
 322                 rlc_chip_name = "BTC";
 323                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 324                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 325                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 326                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 327                 break;
 328         case CHIP_CAYMAN:
 329                 chip_name = "CAYMAN";
 330                 rlc_chip_name = "CAYMAN";
 331                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 332                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 333                 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
 334                 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
 335                 break;
 336         case CHIP_ARUBA:
 337                 chip_name = "ARUBA";
 338                 rlc_chip_name = "ARUBA";
 339                 /* pfp/me same size as CAYMAN */
 340                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 341                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 342                 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
 343                 mc_req_size = 0;
 344                 break;
 345         default: BUG();
 346         }
 347
 348         DRM_INFO("Loading %s Microcode\n", chip_name);
 349
 350         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 351         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 352         if (err)
 353                 goto out;
 354         if (rdev->pfp_fw->size != pfp_req_size) {
 355                 printk(KERN_ERR
 356                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 357                        rdev->pfp_fw->size, fw_name);
 358                 err = -EINVAL;
 359                 goto out;
 360         }
 361
 362         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 363         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 364         if (err)
 365                 goto out;
 366         if (rdev->me_fw->size != me_req_size) {
 367                 printk(KERN_ERR
 368                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 369                        rdev->me_fw->size, fw_name);
 370                 err = -EINVAL;
 371         }
 372
 373         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 374         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 375         if (err)
 376                 goto out;
 377         if (rdev->rlc_fw->size != rlc_req_size) {
 378                 printk(KERN_ERR
 379                        "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
 380                        rdev->rlc_fw->size, fw_name);
 381                 err = -EINVAL;
 382         }
 383
 384         /* no MC ucode on TN */
 385         if (!(rdev->flags & RADEON_IS_IGP)) {
 386                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 387                 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 388                 if (err)
 389                         goto out;
 390                 if (rdev->mc_fw->size != mc_req_size) {
 391                         printk(KERN_ERR
 392                                "ni_mc: Bogus length %zu in firmware \"%s\"\n",
 393                                rdev->mc_fw->size, fw_name);
 394                         err = -EINVAL;
 395                 }
 396         }
 397 out:
 398         platform_device_unregister(pdev);
 399
 400         if (err) {
 401                 if (err != -EINVAL)
 402                         printk(KERN_ERR
 403                                "ni_cp: Failed to load firmware \"%s\"\n",
 404                                fw_name);
 405                 release_firmware(rdev->pfp_fw);
 406                 rdev->pfp_fw = NULL;
 407                 release_firmware(rdev->me_fw);
 408                 rdev->me_fw = NULL;
 409                 release_firmware(rdev->rlc_fw);
 410                 rdev->rlc_fw = NULL;
 411                 release_firmware(rdev->mc_fw);
 412                 rdev->mc_fw = NULL;
 413         }
 414         return err;
 415 }
 416
 417 /*
 418  * Core functions
 419  */
 420 static void cayman_gpu_init(struct radeon_device *rdev)
 421 {
 422         u32 gb_addr_config = 0;
 423         u32 mc_shared_chmap, mc_arb_ramcfg;
 424         u32 cgts_tcc_disable;
 425         u32 sx_debug_1;
 426         u32 smx_dc_ctl0;
 427         u32 cgts_sm_ctrl_reg;
 428         u32 hdp_host_path_cntl;
 429         u32 tmp;
 430         u32 disabled_rb_mask;
 431         int i, j;
 432
 433         switch (rdev->family) {
 434         case CHIP_CAYMAN:
 435                 rdev->config.cayman.max_shader_engines = 2;
 436                 rdev->config.cayman.max_pipes_per_simd = 4;
 437                 rdev->config.cayman.max_tile_pipes = 8;
 438                 rdev->config.cayman.max_simds_per_se = 12;
 439                 rdev->config.cayman.max_backends_per_se = 4;
 440                 rdev->config.cayman.max_texture_channel_caches = 8;
 441                 rdev->config.cayman.max_gprs = 256;
 442                 rdev->config.cayman.max_threads = 256;
 443                 rdev->config.cayman.max_gs_threads = 32;
 444                 rdev->config.cayman.max_stack_entries = 512;
 445                 rdev->config.cayman.sx_num_of_sets = 8;
 446                 rdev->config.cayman.sx_max_export_size = 256;
 447                 rdev->config.cayman.sx_max_export_pos_size = 64;
 448                 rdev->config.cayman.sx_max_export_smx_size = 192;
 449                 rdev->config.cayman.max_hw_contexts = 8;
 450                 rdev->config.cayman.sq_num_cf_insts = 2;
 451
 452                 rdev->config.cayman.sc_prim_fifo_size = 0x100;
 453                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 454                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 455                 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
 456                 break;
 457         case CHIP_ARUBA:
 458         default:
 459                 rdev->config.cayman.max_shader_engines = 1;
 460                 rdev->config.cayman.max_pipes_per_simd = 4;
 461                 rdev->config.cayman.max_tile_pipes = 2;
 462                 if ((rdev->pdev->device == 0x9900) ||
 463                     (rdev->pdev->device == 0x9901) ||
 464                     (rdev->pdev->device == 0x9905) ||
 465                     (rdev->pdev->device == 0x9906) ||
 466                     (rdev->pdev->device == 0x9907) ||
 467                     (rdev->pdev->device == 0x9908) ||
 468                     (rdev->pdev->device == 0x9909) ||
 469                     (rdev->pdev->device == 0x9910) ||
 470                     (rdev->pdev->device == 0x9917)) {
 471                         rdev->config.cayman.max_simds_per_se = 6;
 472                         rdev->config.cayman.max_backends_per_se = 2;
 473                 } else if ((rdev->pdev->device == 0x9903) ||
 474                            (rdev->pdev->device == 0x9904) ||
 475                            (rdev->pdev->device == 0x990A) ||
 476                            (rdev->pdev->device == 0x9913) ||
 477                            (rdev->pdev->device == 0x9918)) {
 478                         rdev->config.cayman.max_simds_per_se = 4;
 479                         rdev->config.cayman.max_backends_per_se = 2;
 480                 } else if ((rdev->pdev->device == 0x9919) ||
 481                            (rdev->pdev->device == 0x9990) ||
 482                            (rdev->pdev->device == 0x9991) ||
 483                            (rdev->pdev->device == 0x9994) ||
 484                            (rdev->pdev->device == 0x99A0)) {
 485                         rdev->config.cayman.max_simds_per_se = 3;
 486                         rdev->config.cayman.max_backends_per_se = 1;
 487                 } else {
 488                         rdev->config.cayman.max_simds_per_se = 2;
 489                         rdev->config.cayman.max_backends_per_se = 1;
 490                 }
 491                 rdev->config.cayman.max_texture_channel_caches = 2;
 492                 rdev->config.cayman.max_gprs = 256;
 493                 rdev->config.cayman.max_threads = 256;
 494                 rdev->config.cayman.max_gs_threads = 32;
 495                 rdev->config.cayman.max_stack_entries = 512;
 496                 rdev->config.cayman.sx_num_of_sets = 8;
 497                 rdev->config.cayman.sx_max_export_size = 256;
 498                 rdev->config.cayman.sx_max_export_pos_size = 64;
 499                 rdev->config.cayman.sx_max_export_smx_size = 192;
 500                 rdev->config.cayman.max_hw_contexts = 8;
 501                 rdev->config.cayman.sq_num_cf_insts = 2;
 502
 503                 rdev->config.cayman.sc_prim_fifo_size = 0x40;
 504                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 505                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 506                 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
 507                 break;
 508         }
 509
 510         /* Initialize HDP */
 511         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 512                 WREG32((0x2c14 + j), 0x00000000);
 513                 WREG32((0x2c18 + j), 0x00000000);
 514                 WREG32((0x2c1c + j), 0x00000000);
 515                 WREG32((0x2c20 + j), 0x00000000);
 516                 WREG32((0x2c24 + j), 0x00000000);
 517         }
 518
 519         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 520
 521         evergreen_fix_pci_max_read_req_size(rdev);
 522
 523         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
 524         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 525
 526         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
 527         rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
 528         if (rdev->config.cayman.mem_row_size_in_kb > 4)
 529                 rdev->config.cayman.mem_row_size_in_kb = 4;
 530         /* XXX use MC settings? */
 531         rdev->config.cayman.shader_engine_tile_size = 32;
 532         rdev->config.cayman.num_gpus = 1;
 533         rdev->config.cayman.multi_gpu_tile_size = 64;
 534
 535         tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
 536         rdev->config.cayman.num_tile_pipes = (1 << tmp);
 537         tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
 538         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 539         tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
 540         rdev->config.cayman.num_shader_engines = tmp + 1;
 541         tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
 542         rdev->config.cayman.num_gpus = tmp + 1;
 543         tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
 544         rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
 545         tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
 546         rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
 547
 548
 549         /* setup tiling info dword.  gb_addr_config is not adequate since it does
 550          * not have bank info, so create a custom tiling dword.
 551          * bits 3:0   num_pipes
 552          * bits 7:4   num_banks
 553          * bits 11:8  group_size
 554          * bits 15:12 row_size
 555          */
 556         rdev->config.cayman.tile_config = 0;
 557         switch (rdev->config.cayman.num_tile_pipes) {
 558         case 1:
 559         default:
 560                 rdev->config.cayman.tile_config |= (0 << 0);
 561                 break;
 562         case 2:
 563                 rdev->config.cayman.tile_config |= (1 << 0);
 564                 break;
 565         case 4:
 566                 rdev->config.cayman.tile_config |= (2 << 0);
 567                 break;
 568         case 8:
 569                 rdev->config.cayman.tile_config |= (3 << 0);
 570                 break;
 571         }
 572
 573         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
 574         if (rdev->flags & RADEON_IS_IGP)
 575                 rdev->config.cayman.tile_config |= 1 << 4;
 576         else {
 577                 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
 578                         rdev->config.cayman.tile_config |= 1 << 4;
 579                 else
 580                         rdev->config.cayman.tile_config |= 0 << 4;
 581         }
 582         rdev->config.cayman.tile_config |=
 583                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
 584         rdev->config.cayman.tile_config |=
 585                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
 586
 587         tmp = 0;
 588         for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
 589                 u32 rb_disable_bitmap;
 590
 591                 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
 592                 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
 593                 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
 594                 tmp <<= 4;
 595                 tmp |= rb_disable_bitmap;
 596         }
 597         /* enabled rb are just the one not disabled :) */
 598         disabled_rb_mask = tmp;
 599
 600         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
 601         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
 602
 603         WREG32(GB_ADDR_CONFIG, gb_addr_config);
 604         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
 605         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 606
 607         tmp = gb_addr_config & NUM_PIPES_MASK;
 608         tmp = r6xx_remap_render_backend(rdev, tmp,
 609                                         rdev->config.cayman.max_backends_per_se *
 610                                         rdev->config.cayman.max_shader_engines,
 611                                         CAYMAN_MAX_BACKENDS, disabled_rb_mask);
 612         WREG32(GB_BACKEND_MAP, tmp);
 613
 614         cgts_tcc_disable = 0xffff0000;
 615         for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
 616                 cgts_tcc_disable &= ~(1 << (16 + i));
 617         WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
 618         WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
 619         WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
 620         WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
 621
 622         /* reprogram the shader complex */
 623         cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
 624         for (i = 0; i < 16; i++)
 625                 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
 626         WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
 627
 628         /* set HW defaults for 3D engine */
 629         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
 630
 631         sx_debug_1 = RREG32(SX_DEBUG_1);
 632         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 633         WREG32(SX_DEBUG_1, sx_debug_1);
 634
 635         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 636         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
 637         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
 638         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 639
 640         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
 641
 642         /* need to be explicitly zero-ed */
 643         WREG32(VGT_OFFCHIP_LDS_BASE, 0);
 644         WREG32(SQ_LSTMP_RING_BASE, 0);
 645         WREG32(SQ_HSTMP_RING_BASE, 0);
 646         WREG32(SQ_ESTMP_RING_BASE, 0);
 647         WREG32(SQ_GSTMP_RING_BASE, 0);
 648         WREG32(SQ_VSTMP_RING_BASE, 0);
 649         WREG32(SQ_PSTMP_RING_BASE, 0);
 650
 651         WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
 652
 653         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
 654                                         POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
 655                                         SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
 656
 657         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
 658                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
 659                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
 660
 661
 662         WREG32(VGT_NUM_INSTANCES, 1);
 663
 664         WREG32(CP_PERFMON_CNTL, 0);
 665
 666         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
 667                                   FETCH_FIFO_HIWATER(0x4) |
 668                                   DONE_FIFO_HIWATER(0xe0) |
 669                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
 670
 671         WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
 672         WREG32(SQ_CONFIG, (VC_ENABLE |
 673                            EXPORT_SRC_C |
 674                            GFX_PRIO(0) |
 675                            CS1_PRIO(0) |
 676                            CS2_PRIO(1)));
 677         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
 678
 679         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 680                                           FORCE_EOV_MAX_REZ_CNT(255)));
 681
 682         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
 683                AUTO_INVLD_EN(ES_AND_GS_AUTO));
 684
 685         WREG32(VGT_GS_VERTEX_REUSE, 16);
 686         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 687
 688         WREG32(CB_PERF_CTR0_SEL_0, 0);
 689         WREG32(CB_PERF_CTR0_SEL_1, 0);
 690         WREG32(CB_PERF_CTR1_SEL_0, 0);
 691         WREG32(CB_PERF_CTR1_SEL_1, 0);
 692         WREG32(CB_PERF_CTR2_SEL_0, 0);
 693         WREG32(CB_PERF_CTR2_SEL_1, 0);
 694         WREG32(CB_PERF_CTR3_SEL_0, 0);
 695         WREG32(CB_PERF_CTR3_SEL_1, 0);
 696
 697         tmp = RREG32(HDP_MISC_CNTL);
 698         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
 699         WREG32(HDP_MISC_CNTL, tmp);
 700
 701         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 702         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 703
 704         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
 705
 706         udelay(50);
 707 }
 708
 709 /*
 710  * GART
 711  */
 712 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
 713 {
 714         /* flush hdp cache */
 715         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 716
 717         /* bits 0-7 are the VM contexts0-7 */
 718         WREG32(VM_INVALIDATE_REQUEST, 1);
 719 }
 720
 721 int cayman_pcie_gart_enable(struct radeon_device *rdev)
 722 {
 723         int i, r;
 724
 725         if (rdev->gart.robj == NULL) {
 726                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 727                 return -EINVAL;
 728         }
 729         r = radeon_gart_table_vram_pin(rdev);
 730         if (r)
 731                 return r;
 732         radeon_gart_restore(rdev);
 733         /* Setup TLB control */
 734         WREG32(MC_VM_MX_L1_TLB_CNTL,
 735                (0xA << 7) |
 736                ENABLE_L1_TLB |
 737                ENABLE_L1_FRAGMENT_PROCESSING |
 738                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 739                ENABLE_ADVANCED_DRIVER_MODEL |
 740                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
 741         /* Setup L2 cache */
 742         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
 743                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 744                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
 745                EFFECTIVE_L2_QUEUE_SIZE(7) |
 746                CONTEXT1_IDENTITY_ACCESS_MODE(1));
 747         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
 748         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
 749                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
 750         /* setup context0 */
 751         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 752         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 753         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 754         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 755                         (u32)(rdev->dummy_page.addr >> 12));
 756         WREG32(VM_CONTEXT0_CNTL2, 0);
 757         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 758                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 759
 760         WREG32(0x15D4, 0);
 761         WREG32(0x15D8, 0);
 762         WREG32(0x15DC, 0);
 763
 764         /* empty context1-7 */
 765         for (i = 1; i < 8; i++) {
 766                 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
 767                 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);
 768                 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
 769                         rdev->gart.table_addr >> 12);
 770         }
 771
 772         /* enable context1-7 */
 773         WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 774                (u32)(rdev->dummy_page.addr >> 12));
 775         WREG32(VM_CONTEXT1_CNTL2, 0);
 776         WREG32(VM_CONTEXT1_CNTL, 0);
 777         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 778                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 779
 780         cayman_pcie_gart_tlb_flush(rdev);
 781         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 782                  (unsigned)(rdev->mc.gtt_size >> 20),
 783                  (unsigned long long)rdev->gart.table_addr);
 784         rdev->gart.ready = true;
 785         return 0;
 786 }
 787
 788 void cayman_pcie_gart_disable(struct radeon_device *rdev)
 789 {
 790         /* Disable all tables */
 791         WREG32(VM_CONTEXT0_CNTL, 0);
 792         WREG32(VM_CONTEXT1_CNTL, 0);
 793         /* Setup TLB control */
 794         WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
 795                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 796                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
 797         /* Setup L2 cache */
 798         WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 799                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
 800                EFFECTIVE_L2_QUEUE_SIZE(7) |
 801                CONTEXT1_IDENTITY_ACCESS_MODE(1));
 802         WREG32(VM_L2_CNTL2, 0);
 803         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
 804                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
 805         radeon_gart_table_vram_unpin(rdev);
 806 }
 807
 808 void cayman_pcie_gart_fini(struct radeon_device *rdev)
 809 {
 810         cayman_pcie_gart_disable(rdev);
 811         radeon_gart_table_vram_free(rdev);
 812         radeon_gart_fini(rdev);
 813 }
 814
 815 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
 816                               int ring, u32 cp_int_cntl)
 817 {
 818         u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
 819
 820         WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
 821         WREG32(CP_INT_CNTL, cp_int_cntl);
 822 }
 823
 824 /*
 825  * CP.
 826  */
 827 void cayman_fence_ring_emit(struct radeon_device *rdev,
 828                             struct radeon_fence *fence)
 829 {
 830         struct radeon_ring *ring = &rdev->ring[fence->ring];
 831         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
 832
 833         /* flush read cache over gart for this vmid */
 834         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 835         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
 836         radeon_ring_write(ring, 0);
 837         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
 838         radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
 839         radeon_ring_write(ring, 0xFFFFFFFF);
 840         radeon_ring_write(ring, 0);
 841         radeon_ring_write(ring, 10); /* poll interval */
 842         /* EVENT_WRITE_EOP - flush caches, send int */
 843         radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
 844         radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
 845         radeon_ring_write(ring, addr & 0xffffffff);
 846         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
 847         radeon_ring_write(ring, fence->seq);
 848         radeon_ring_write(ring, 0);
 849 }
 850
 851 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 852 {
 853         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
 854
 855         /* set to DX10/11 mode */
 856         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
 857         radeon_ring_write(ring, 1);
 858         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 859         radeon_ring_write(ring,
 860 #ifdef __BIG_ENDIAN
 861                           (2 << 0) |
 862 #endif
 863                           (ib->gpu_addr & 0xFFFFFFFC));
 864         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
 865         radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
 866
 867         /* flush read cache over gart for this vmid */
 868         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 869         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
 870         radeon_ring_write(ring, ib->vm_id);
 871         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
 872         radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
 873         radeon_ring_write(ring, 0xFFFFFFFF);
 874         radeon_ring_write(ring, 0);
 875         radeon_ring_write(ring, 10); /* poll interval */
 876 }
 877
 878 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
 879 {
 880         if (enable)
 881                 WREG32(CP_ME_CNTL, 0);
 882         else {
 883                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 884                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 885                 WREG32(SCRATCH_UMSK, 0);
 886         }
 887 }
 888
 889 static int cayman_cp_load_microcode(struct radeon_device *rdev)
 890 {
 891         const __be32 *fw_data;
 892         int i;
 893
 894         if (!rdev->me_fw || !rdev->pfp_fw)
 895                 return -EINVAL;
 896
 897         cayman_cp_enable(rdev, false);
 898
 899         fw_data = (const __be32 *)rdev->pfp_fw->data;
 900         WREG32(CP_PFP_UCODE_ADDR, 0);
 901         for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
 902                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 903         WREG32(CP_PFP_UCODE_ADDR, 0);
 904
 905         fw_data = (const __be32 *)rdev->me_fw->data;
 906         WREG32(CP_ME_RAM_WADDR, 0);
 907         for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
 908                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 909
 910         WREG32(CP_PFP_UCODE_ADDR, 0);
 911         WREG32(CP_ME_RAM_WADDR, 0);
 912         WREG32(CP_ME_RAM_RADDR, 0);
 913         return 0;
 914 }
 915
 916 static int cayman_cp_start(struct radeon_device *rdev)
 917 {
 918         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 919         int r, i;
 920
 921         r = radeon_ring_lock(rdev, ring, 7);
 922         if (r) {
 923                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
 924                 return r;
 925         }
 926         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
 927         radeon_ring_write(ring, 0x1);
 928         radeon_ring_write(ring, 0x0);
 929         radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
 930         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
 931         radeon_ring_write(ring, 0);
 932         radeon_ring_write(ring, 0);
 933         radeon_ring_unlock_commit(rdev, ring);
 934
 935         cayman_cp_enable(rdev, true);
 936
 937         r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
 938         if (r) {
 939                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
 940                 return r;
 941         }
 942
 943         /* setup clear context state */
 944         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 945         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 946
 947         for (i = 0; i < cayman_default_size; i++)
 948                 radeon_ring_write(ring, cayman_default_state[i]);
 949
 950         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 951         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
 952
 953         /* set clear context state */
 954         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
 955         radeon_ring_write(ring, 0);
 956
 957         /* SQ_VTX_BASE_VTX_LOC */
 958         radeon_ring_write(ring, 0xc0026f00);
 959         radeon_ring_write(ring, 0x00000000);
 960         radeon_ring_write(ring, 0x00000000);
 961         radeon_ring_write(ring, 0x00000000);
 962
 963         /* Clear consts */
 964         radeon_ring_write(ring, 0xc0036f00);
 965         radeon_ring_write(ring, 0x00000bc4);
 966         radeon_ring_write(ring, 0xffffffff);
 967         radeon_ring_write(ring, 0xffffffff);
 968         radeon_ring_write(ring, 0xffffffff);
 969
 970         radeon_ring_write(ring, 0xc0026900);
 971         radeon_ring_write(ring, 0x00000316);
 972         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
 973         radeon_ring_write(ring, 0x00000010); /*  */
 974
 975         radeon_ring_unlock_commit(rdev, ring);
 976
 977         /* XXX init other rings */
 978
 979         return 0;
 980 }
 981
 982 static void cayman_cp_fini(struct radeon_device *rdev)
 983 {
 984         cayman_cp_enable(rdev, false);
 985         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
 986 }
 987
 988 int cayman_cp_resume(struct radeon_device *rdev)
 989 {
 990         struct radeon_ring *ring;
 991         u32 tmp;
 992         u32 rb_bufsz;
 993         int r;
 994
 995         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
 996         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
 997                                  SOFT_RESET_PA |
 998                                  SOFT_RESET_SH |
 999                                  SOFT_RESET_VGT |
1000                                  SOFT_RESET_SPI |
1001                                  SOFT_RESET_SX));
1002         RREG32(GRBM_SOFT_RESET);
1003         mdelay(15);
1004         WREG32(GRBM_SOFT_RESET, 0);
1005         RREG32(GRBM_SOFT_RESET);
1006
1007         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1008         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1009
1010         /* Set the write pointer delay */
1011         WREG32(CP_RB_WPTR_DELAY, 0);
1012
1013         WREG32(CP_DEBUG, (1 << 27));
1014
1015         /* ring 0 - compute and gfx */
1016         /* Set ring buffer size */
1017         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1018         rb_bufsz = drm_order(ring->ring_size / 8);
1019         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1020 #ifdef __BIG_ENDIAN
1021         tmp |= BUF_SWAP_32BIT;
1022 #endif
1023         WREG32(CP_RB0_CNTL, tmp);
1024
1025         /* Initialize the ring buffer's read and write pointers */
1026         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1027         ring->wptr = 0;
1028         WREG32(CP_RB0_WPTR, ring->wptr);
1029
1030         /* set the wb address wether it's enabled or not */
1031         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1032         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1033         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1034
1035         if (rdev->wb.enabled)
1036                 WREG32(SCRATCH_UMSK, 0xff);
1037         else {
1038                 tmp |= RB_NO_UPDATE;
1039                 WREG32(SCRATCH_UMSK, 0);
1040         }
1041
1042         mdelay(1);
1043         WREG32(CP_RB0_CNTL, tmp);
1044
1045         WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1046
1047         ring->rptr = RREG32(CP_RB0_RPTR);
1048
1049         /* ring1  - compute only */
1050         /* Set ring buffer size */
1051         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1052         rb_bufsz = drm_order(ring->ring_size / 8);
1053         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1054 #ifdef __BIG_ENDIAN
1055         tmp |= BUF_SWAP_32BIT;
1056 #endif
1057         WREG32(CP_RB1_CNTL, tmp);
1058
1059         /* Initialize the ring buffer's read and write pointers */
1060         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1061         ring->wptr = 0;
1062         WREG32(CP_RB1_WPTR, ring->wptr);
1063
1064         /* set the wb address wether it's enabled or not */
1065         WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1066         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1067
1068         mdelay(1);
1069         WREG32(CP_RB1_CNTL, tmp);
1070
1071         WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1072
1073         ring->rptr = RREG32(CP_RB1_RPTR);
1074
1075         /* ring2 - compute only */
1076         /* Set ring buffer size */
1077         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1078         rb_bufsz = drm_order(ring->ring_size / 8);
1079         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1080 #ifdef __BIG_ENDIAN
1081         tmp |= BUF_SWAP_32BIT;
1082 #endif
1083         WREG32(CP_RB2_CNTL, tmp);
1084
1085         /* Initialize the ring buffer's read and write pointers */
1086         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1087         ring->wptr = 0;
1088         WREG32(CP_RB2_WPTR, ring->wptr);
1089
1090         /* set the wb address wether it's enabled or not */
1091         WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1092         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1093
1094         mdelay(1);
1095         WREG32(CP_RB2_CNTL, tmp);
1096
1097         WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1098
1099         ring->rptr = RREG32(CP_RB2_RPTR);
1100
1101         /* start the rings */
1102         cayman_cp_start(rdev);
1103         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1104         rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1105         rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1106         /* this only test cp0 */
1107         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1108         if (r) {
1109                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1110                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1111                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1112                 return r;
1113         }
1114
1115         return 0;
1116 }
1117
1118 static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1119 {
1120         struct evergreen_mc_save save;
1121         u32 grbm_reset = 0;
1122
1123         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1124                 return 0;
1125
1126         dev_info(rdev->dev, "GPU softreset \n");
1127         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1128                 RREG32(GRBM_STATUS));
1129         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1130                 RREG32(GRBM_STATUS_SE0));
1131         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1132                 RREG32(GRBM_STATUS_SE1));
1133         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1134                 RREG32(SRBM_STATUS));
1135         dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",
1136                  RREG32(0x14F8));
1137         dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1138                  RREG32(0x14D8));
1139         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1140                  RREG32(0x14FC));
1141         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1142                  RREG32(0x14DC));
1143
1144         evergreen_mc_stop(rdev, &save);
1145         if (evergreen_mc_wait_for_idle(rdev)) {
1146                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1147         }
1148         /* Disable CP parsing/prefetching */
1149         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1150
1151         /* reset all the gfx blocks */
1152         grbm_reset = (SOFT_RESET_CP |
1153                       SOFT_RESET_CB |
1154                       SOFT_RESET_DB |
1155                       SOFT_RESET_GDS |
1156                       SOFT_RESET_PA |
1157                       SOFT_RESET_SC |
1158                       SOFT_RESET_SPI |
1159                       SOFT_RESET_SH |
1160                       SOFT_RESET_SX |
1161                       SOFT_RESET_TC |
1162                       SOFT_RESET_TA |
1163                       SOFT_RESET_VGT |
1164                       SOFT_RESET_IA);
1165
1166         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1167         WREG32(GRBM_SOFT_RESET, grbm_reset);
1168         (void)RREG32(GRBM_SOFT_RESET);
1169         udelay(50);
1170         WREG32(GRBM_SOFT_RESET, 0);
1171         (void)RREG32(GRBM_SOFT_RESET);
1172         /* Wait a little for things to settle down */
1173         udelay(50);
1174
1175         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1176                 RREG32(GRBM_STATUS));
1177         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1178                 RREG32(GRBM_STATUS_SE0));
1179         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1180                 RREG32(GRBM_STATUS_SE1));
1181         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1182                 RREG32(SRBM_STATUS));
1183         evergreen_mc_resume(rdev, &save);
1184         return 0;
1185 }
1186
1187 int cayman_asic_reset(struct radeon_device *rdev)
1188 {
1189         return cayman_gpu_soft_reset(rdev);
1190 }
1191
1192 static int cayman_startup(struct radeon_device *rdev)
1193 {
1194         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1195         int r;
1196
1197         /* enable pcie gen2 link */
1198         evergreen_pcie_gen2_enable(rdev);
1199
1200         if (rdev->flags & RADEON_IS_IGP) {
1201                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1202                         r = ni_init_microcode(rdev);
1203                         if (r) {
1204                                 DRM_ERROR("Failed to load firmware!\n");
1205                                 return r;
1206                         }
1207                 }
1208         } else {
1209                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1210                         r = ni_init_microcode(rdev);
1211                         if (r) {
1212                                 DRM_ERROR("Failed to load firmware!\n");
1213                                 return r;
1214                         }
1215                 }
1216
1217                 r = ni_mc_load_microcode(rdev);
1218                 if (r) {
1219                         DRM_ERROR("Failed to load MC firmware!\n");
1220                         return r;
1221                 }
1222         }
1223
1224         r = r600_vram_scratch_init(rdev);
1225         if (r)
1226                 return r;
1227
1228         evergreen_mc_program(rdev);
1229         r = cayman_pcie_gart_enable(rdev);
1230         if (r)
1231                 return r;
1232         cayman_gpu_init(rdev);
1233
1234         r = evergreen_blit_init(rdev);
1235         if (r) {
1236                 r600_blit_fini(rdev);
1237                 rdev->asic->copy.copy = NULL;
1238                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1239         }
1240
1241         /* allocate rlc buffers */
1242         if (rdev->flags & RADEON_IS_IGP) {
1243                 r = si_rlc_init(rdev);
1244                 if (r) {
1245                         DRM_ERROR("Failed to init rlc BOs!\n");
1246                         return r;
1247                 }
1248         }
1249
1250         /* allocate wb buffer */
1251         r = radeon_wb_init(rdev);
1252         if (r)
1253                 return r;
1254
1255         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1256         if (r) {
1257                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1258                 return r;
1259         }
1260
1261         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1262         if (r) {
1263                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1264                 return r;
1265         }
1266
1267         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1268         if (r) {
1269                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1270                 return r;
1271         }
1272
1273         /* Enable IRQ */
1274         r = r600_irq_init(rdev);
1275         if (r) {
1276                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1277                 radeon_irq_kms_fini(rdev);
1278                 return r;
1279         }
1280         evergreen_irq_set(rdev);
1281
1282         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1283                              CP_RB0_RPTR, CP_RB0_WPTR,
1284                              0, 0xfffff, RADEON_CP_PACKET2);
1285         if (r)
1286                 return r;
1287         r = cayman_cp_load_microcode(rdev);
1288         if (r)
1289                 return r;
1290         r = cayman_cp_resume(rdev);
1291         if (r)
1292                 return r;
1293
1294         r = radeon_ib_pool_start(rdev);
1295         if (r)
1296                 return r;
1297
1298         r = radeon_ib_ring_tests(rdev);
1299         if (r)
1300                 return r;
1301
1302         r = radeon_vm_manager_start(rdev);
1303         if (r)
1304                 return r;
1305
1306         return 0;
1307 }
1308
1309 int cayman_resume(struct radeon_device *rdev)
1310 {
1311         int r;
1312
1313         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1314          * posting will perform necessary task to bring back GPU into good
1315          * shape.
1316          */
1317         /* post card */
1318         atom_asic_init(rdev->mode_info.atom_context);
1319
1320         rdev->accel_working = true;
1321         r = cayman_startup(rdev);
1322         if (r) {
1323                 DRM_ERROR("cayman startup failed on resume\n");
1324                 rdev->accel_working = false;
1325                 return r;
1326         }
1327         return r;
1328 }
1329
1330 int cayman_suspend(struct radeon_device *rdev)
1331 {
1332         /* FIXME: we should wait for ring to be empty */
1333         radeon_ib_pool_suspend(rdev);
1334         radeon_vm_manager_suspend(rdev);
1335         r600_blit_suspend(rdev);
1336         cayman_cp_enable(rdev, false);
1337         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1338         evergreen_irq_suspend(rdev);
1339         radeon_wb_disable(rdev);
1340         cayman_pcie_gart_disable(rdev);
1341         return 0;
1342 }
1343
1344 /* Plan is to move initialization in that function and use
1345  * helper function so that radeon_device_init pretty much
1346  * do nothing more than calling asic specific function. This
1347  * should also allow to remove a bunch of callback function
1348  * like vram_info.
1349  */
1350 int cayman_init(struct radeon_device *rdev)
1351 {
1352         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1353         int r;
1354
1355         /* Read BIOS */
1356         if (!radeon_get_bios(rdev)) {
1357                 if (ASIC_IS_AVIVO(rdev))
1358                         return -EINVAL;
1359         }
1360         /* Must be an ATOMBIOS */
1361         if (!rdev->is_atom_bios) {
1362                 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1363                 return -EINVAL;
1364         }
1365         r = radeon_atombios_init(rdev);
1366         if (r)
1367                 return r;
1368
1369         /* Post card if necessary */
1370         if (!radeon_card_posted(rdev)) {
1371                 if (!rdev->bios) {
1372                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1373                         return -EINVAL;
1374                 }
1375                 DRM_INFO("GPU not posted. posting now...\n");
1376                 atom_asic_init(rdev->mode_info.atom_context);
1377         }
1378         /* Initialize scratch registers */
1379         r600_scratch_init(rdev);
1380         /* Initialize surface registers */
1381         radeon_surface_init(rdev);
1382         /* Initialize clocks */
1383         radeon_get_clock_info(rdev->ddev);
1384         /* Fence driver */
1385         r = radeon_fence_driver_init(rdev);
1386         if (r)
1387                 return r;
1388         /* initialize memory controller */
1389         r = evergreen_mc_init(rdev);
1390         if (r)
1391                 return r;
1392         /* Memory manager */
1393         r = radeon_bo_init(rdev);
1394         if (r)
1395                 return r;
1396
1397         r = radeon_irq_kms_init(rdev);
1398         if (r)
1399                 return r;
1400
1401         ring->ring_obj = NULL;
1402         r600_ring_init(rdev, ring, 1024 * 1024);
1403
1404         rdev->ih.ring_obj = NULL;
1405         r600_ih_ring_init(rdev, 64 * 1024);
1406
1407         r = r600_pcie_gart_init(rdev);
1408         if (r)
1409                 return r;
1410
1411         r = radeon_ib_pool_init(rdev);
1412         rdev->accel_working = true;
1413         if (r) {
1414                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1415                 rdev->accel_working = false;
1416         }
1417         r = radeon_vm_manager_init(rdev);
1418         if (r) {
1419                 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
1420         }
1421
1422         r = cayman_startup(rdev);
1423         if (r) {
1424                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1425                 cayman_cp_fini(rdev);
1426                 r600_irq_fini(rdev);
1427                 if (rdev->flags & RADEON_IS_IGP)
1428                         si_rlc_fini(rdev);
1429                 radeon_wb_fini(rdev);
1430                 r100_ib_fini(rdev);
1431                 radeon_vm_manager_fini(rdev);
1432                 radeon_irq_kms_fini(rdev);
1433                 cayman_pcie_gart_fini(rdev);
1434                 rdev->accel_working = false;
1435         }
1436
1437         /* Don't start up if the MC ucode is missing.
1438          * The default clocks and voltages before the MC ucode
1439          * is loaded are not suffient for advanced operations.
1440          *
1441          * We can skip this check for TN, because there is no MC
1442          * ucode.
1443          */
1444         if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
1445                 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1446                 return -EINVAL;
1447         }
1448
1449         return 0;
1450 }
1451
1452 void cayman_fini(struct radeon_device *rdev)
1453 {
1454         r600_blit_fini(rdev);
1455         cayman_cp_fini(rdev);
1456         r600_irq_fini(rdev);
1457         if (rdev->flags & RADEON_IS_IGP)
1458                 si_rlc_fini(rdev);
1459         radeon_wb_fini(rdev);
1460         radeon_vm_manager_fini(rdev);
1461         r100_ib_fini(rdev);
1462         radeon_irq_kms_fini(rdev);
1463         cayman_pcie_gart_fini(rdev);
1464         r600_vram_scratch_fini(rdev);
1465         radeon_gem_fini(rdev);
1466         radeon_fence_driver_fini(rdev);
1467         radeon_bo_fini(rdev);
1468         radeon_atombios_fini(rdev);
1469         kfree(rdev->bios);
1470         rdev->bios = NULL;
1471 }
1472
1473 /*
1474  * vm
1475  */
1476 int cayman_vm_init(struct radeon_device *rdev)
1477 {
1478         /* number of VMs */
1479         rdev->vm_manager.nvm = 8;
1480         /* base offset of vram pages */
1481         if (rdev->flags & RADEON_IS_IGP) {
1482                 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1483                 tmp <<= 22;
1484                 rdev->vm_manager.vram_base_offset = tmp;
1485         } else
1486                 rdev->vm_manager.vram_base_offset = 0;
1487         return 0;
1488 }
1489
1490 void cayman_vm_fini(struct radeon_device *rdev)
1491 {
1492 }
1493
1494 int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
1495 {
1496         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (id << 2), 0);
1497         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (id << 2), vm->last_pfn);
1498         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
1499         /* flush hdp cache */
1500         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1501         /* bits 0-7 are the VM contexts0-7 */
1502         WREG32(VM_INVALIDATE_REQUEST, 1 << id);
1503         return 0;
1504 }
1505
1506 void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
1507 {
1508         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0);
1509         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0);
1510         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
1511         /* flush hdp cache */
1512         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1513         /* bits 0-7 are the VM contexts0-7 */
1514         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1515 }
1516
1517 void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
1518 {
1519         if (vm->id == -1)
1520                 return;
1521
1522         /* flush hdp cache */
1523         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1524         /* bits 0-7 are the VM contexts0-7 */
1525         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1526 }
1527
1528 #define R600_PTE_VALID     (1 << 0)
1529 #define R600_PTE_SYSTEM    (1 << 1)
1530 #define R600_PTE_SNOOPED   (1 << 2)
1531 #define R600_PTE_READABLE  (1 << 5)
1532 #define R600_PTE_WRITEABLE (1 << 6)
1533
1534 uint32_t cayman_vm_page_flags(struct radeon_device *rdev,
1535                               struct radeon_vm *vm,
1536                               uint32_t flags)
1537 {
1538         uint32_t r600_flags = 0;
1539
1540         r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
1541         r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1542         r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1543         if (flags & RADEON_VM_PAGE_SYSTEM) {
1544                 r600_flags |= R600_PTE_SYSTEM;
1545                 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1546         }
1547         return r600_flags;
1548 }
1549
1550 void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
1551                         unsigned pfn, uint64_t addr, uint32_t flags)
1552 {
1553         void __iomem *ptr = (void *)vm->pt;
1554
1555         addr = addr & 0xFFFFFFFFFFFFF000ULL;
1556         addr |= flags;
1557         writeq(addr, ptr + (pfn * 8));
1558 }